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V4L/DVB (4550): Make saa7115 to report the complete chipset name
[linux-2.6-block.git] / drivers / media / video / saa7115.c
CommitLineData
f5762e44 1/* saa7115 - Philips SAA7113/SAA7114/SAA7115 video decoder driver
e19b2fcc
HV		 2 *
3 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
4 * the saa7111 driver by Dave Perks.
5 *
6 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
7 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
8 *
9 * Slight changes for video timing and attachment output by
10 * Wolfgang Scherr <scherr@net4you.net>
11 *
12 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
13 * by Ronald Bultje <rbultje@ronald.bitfreak.net>
14 *
15 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
16 * (2/17/2003)
17 *
18 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
f5762e44 19 * SAA7113 support by Mauro Carvalho Chehab <mchehab@infradead.org>
e19b2fcc
HV		 20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version 2
24 * of the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
34 */
35
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/i2c.h>
41#include <linux/videodev2.h>
e19b2fcc 42#include <media/v4l2-common.h>
1f8f5fa9 43#include <media/saa7115.h>
3578d3dd 44#include <asm/div64.h>
e19b2fcc 45
f5762e44
MCC		 46MODULE_DESCRIPTION("Philips SAA7113/SAA7114/SAA7115 video decoder driver");
47MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
48 "Hans Verkuil, Mauro Carvalho Chehab");
e19b2fcc
HV		 49MODULE_LICENSE("GPL");
50
51static int debug = 0;
fac9e899 52module_param(debug, bool, 0644);
e19b2fcc
HV		 53
54MODULE_PARM_DESC(debug, "Debug level (0-1)");
55
f5762e44 56static unsigned short normal_i2c[] = {
01342358 57 0x4a >> 1, 0x48 >> 1, /* SAA7113 */
f5762e44
MCC		 58 0x42 >> 1, 0x40 >> 1, /* SAA7114 and SAA7115 */
59 I2C_CLIENT_END };
e19b2fcc
HV		 60
61
62I2C_CLIENT_INSMOD;
63
64struct saa7115_state {
65 v4l2_std_id std;
66 int input;
67 int enable;
3faeeae4 68 int radio;
e19b2fcc
HV		 69 int bright;
70 int contrast;
71 int hue;
72 int sat;
73 enum v4l2_chip_ident ident;
3578d3dd 74 u32 audclk_freq;
b7f8292c
HV		 75 u32 crystal_freq;
76 u8 ucgc;
77 u8 cgcdiv;
78 u8 apll;
e19b2fcc
HV		 79};
80
81/* ----------------------------------------------------------------------- */
82
83static inline int saa7115_write(struct i2c_client *client, u8 reg, u8 value)
84{
85 return i2c_smbus_write_byte_data(client, reg, value);
86}
87
88static int saa7115_writeregs(struct i2c_client *client, const unsigned char *regs)
89{
90 unsigned char reg, data;
91
92 while (*regs != 0x00) {
93 reg = *(regs++);
94 data = *(regs++);
95 if (saa7115_write(client, reg, data) < 0)
96 return -1;
97 }
98 return 0;
99}
100
101static inline int saa7115_read(struct i2c_client *client, u8 reg)
102{
103 return i2c_smbus_read_byte_data(client, reg);
104}
105
106/* ----------------------------------------------------------------------- */
107
108/* If a value differs from the Hauppauge driver values, then the comment starts with
109 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
110 Hauppauge driver sets. */
111
112static const unsigned char saa7115_init_auto_input[] = {
f5762e44 113 /* Front-End Part */
e19b2fcc
HV		 114 0x01, 0x48, /* white peak control disabled */
115 0x03, 0x20, /* was 0x30. 0x20: long vertical blanking */
116 0x04, 0x90, /* analog gain set to 0 */
117 0x05, 0x90, /* analog gain set to 0 */
f5762e44 118 /* Decoder Part */
e19b2fcc
HV		 119 0x06, 0xeb, /* horiz sync begin = -21 */
120 0x07, 0xe0, /* horiz sync stop = -17 */
121 0x0a, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
122 0x0b, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
123 0x0c, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
124 0x0d, 0x00, /* chrominance hue control */
125 0x0f, 0x00, /* chrominance gain control: use automicatic mode */
126 0x10, 0x06, /* chrominance/luminance control: active adaptive combfilter */
127 0x11, 0x00, /* delay control */
128 0x12, 0x9d, /* RTS0 output control: VGATE */
129 0x13, 0x80, /* X-port output control: ITU656 standard mode, RTCO output enable RTCE */
130 0x14, 0x00, /* analog/ADC/auto compatibility control */
131 0x18, 0x40, /* raw data gain 0x00 = nominal */
132 0x19, 0x80, /* raw data offset 0x80 = 0 LSB */
133 0x1a, 0x77, /* color killer level control 0x77 = recommended */
134 0x1b, 0x42, /* misc chroma control 0x42 = recommended */
135 0x1c, 0xa9, /* combfilter control 0xA9 = recommended */
136 0x1d, 0x01, /* combfilter control 0x01 = recommended */
f5762e44
MCC		 137
138 /* Power Device Control */
e19b2fcc
HV		 139 0x88, 0xd0, /* reset device */
140 0x88, 0xf0, /* set device programmed, all in operational mode */
141 0x00, 0x00
142};
143
144static const unsigned char saa7115_cfg_reset_scaler[] = {
145 0x87, 0x00, /* disable I-port output */
146 0x88, 0xd0, /* reset scaler */
147 0x88, 0xf0, /* activate scaler */
148 0x87, 0x01, /* enable I-port output */
149 0x00, 0x00
150};
151
152/* ============== SAA7715 VIDEO templates ============= */
153
154static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
155 0xcc, 0xd0, /* hsize low (output), hor. output window size = 0x2d0 = 720 */
156 0xcd, 0x02, /* hsize hi (output) */
157
158 /* Why not in 60hz-Land, too? */
159 0xd0, 0x01, /* downscale = 1 */
160 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */
161 0xd9, 0x04,
162 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
163 0xdd, 0x02, /* H-scaling incr chroma */
164
165 0x00, 0x00
166};
167static const unsigned char saa7115_cfg_60hz_fullres_y[] = {
168 0xce, 0xf8, /* vsize low (output), ver. output window size = 248 (but 60hz is 240?) */
169 0xcf, 0x00, /* vsize hi (output) */
170
171 /* Why not in 60hz-Land, too? */
172 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */
173 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */
174
175 0xe0, 0x00, /* V-scaling incr luma low */
176 0xe1, 0x04, /* " hi */
177 0xe2, 0x00, /* V-scaling incr chroma low */
178 0xe3, 0x04, /* " hi */
179
180 0x00, 0x00
181};
182
183static const unsigned char saa7115_cfg_60hz_video[] = {
184 0x80, 0x00, /* reset tasks */
185 0x88, 0xd0, /* reset scaler */
186
187 0x15, 0x03, /* VGATE pulse start */
188 0x16, 0x11, /* VGATE pulse stop */
189 0x17, 0x9c, /* VGATE MSB and other values */
190
191 0x08, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
192 0x0e, 0x07, /* lots of different stuff... video autodetection is on */
193
194 0x5a, 0x06, /* Vertical offset, standard 60hz value for ITU656 line counting */
195
196 /* Task A */
197 0x90, 0x80, /* Task Handling Control */
198 0x91, 0x48, /* X-port formats/config */
199 0x92, 0x40, /* Input Ref. signal Def. */
200 0x93, 0x84, /* I-port config */
201 0x94, 0x01, /* hoffset low (input), 0x0002 is minimum */
202 0x95, 0x00, /* hoffset hi (input) */
203 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */
204 0x97, 0x02, /* hsize hi (input) */
205 0x98, 0x05, /* voffset low (input) */
206 0x99, 0x00, /* voffset hi (input) */
207 0x9a, 0x0c, /* vsize low (input), 0x0c = 12 */
208 0x9b, 0x00, /* vsize hi (input) */
209 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */
210 0x9d, 0x05, /* hsize hi (output) */
211 0x9e, 0x0c, /* vsize low (output), 0x0c = 12 */
212 0x9f, 0x00, /* vsize hi (output) */
213
214 /* Task B */
215 0xc0, 0x00, /* Task Handling Control */
216 0xc1, 0x08, /* X-port formats/config */
217 0xc2, 0x00, /* Input Ref. signal Def. */
218 0xc3, 0x80, /* I-port config */
219 0xc4, 0x02, /* hoffset low (input), 0x0002 is minimum */
220 0xc5, 0x00, /* hoffset hi (input) */
221 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */
222 0xc7, 0x02, /* hsize hi (input) */
223 0xc8, 0x12, /* voffset low (input), 0x12 = 18 */
224 0xc9, 0x00, /* voffset hi (input) */
225 0xca, 0xf8, /* vsize low (input), 0xf8 = 248 */
226 0xcb, 0x00, /* vsize hi (input) */
227 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */
228 0xcd, 0x02, /* hsize hi (output) */
229
230 0xf0, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
231 0xf1, 0x05, /* low bit with 0xF0 */
232 0xf5, 0xad, /* Set pulse generator register */
233 0xf6, 0x01,
234
235 0x87, 0x00, /* Disable I-port output */
236 0x88, 0xd0, /* reset scaler */
237 0x80, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */
238 0x88, 0xf0, /* activate scaler */
239 0x87, 0x01, /* Enable I-port output */
240 0x00, 0x00
241};
242
243static const unsigned char saa7115_cfg_50hz_fullres_x[] = {
244 0xcc, 0xd0, /* hsize low (output), 720 same as 60hz */
245 0xcd, 0x02, /* hsize hi (output) */
246
247 0xd0, 0x01, /* down scale = 1 */
248 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */
249 0xd9, 0x04,
250 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
251 0xdd, 0x02, /* H-scaling incr chroma */
252
253 0x00, 0x00
254};
255static const unsigned char saa7115_cfg_50hz_fullres_y[] = {
256 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */
257 0xcf, 0x01, /* vsize hi (output) */
258
259 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */
260 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */
261
262 0xe0, 0x00, /* V-scaling incr luma low */
263 0xe1, 0x04, /* " hi */
264 0xe2, 0x00, /* V-scaling incr chroma low */
265 0xe3, 0x04, /* " hi */
266
267 0x00, 0x00
268};
269
270static const unsigned char saa7115_cfg_50hz_video[] = {
271 0x80, 0x00, /* reset tasks */
272 0x88, 0xd0, /* reset scaler */
273
274 0x15, 0x37, /* VGATE start */
275 0x16, 0x16, /* VGATE stop */
276 0x17, 0x99, /* VGATE MSB and other values */
277
278 0x08, 0x28, /* 0x28 = PAL */
279 0x0e, 0x07, /* chrominance control 1 */
280
281 0x5a, 0x03, /* Vertical offset, standard 50hz value */
282
283 /* Task A */
284 0x90, 0x81, /* Task Handling Control */
285 0x91, 0x48, /* X-port formats/config */
286 0x92, 0x40, /* Input Ref. signal Def. */
287 0x93, 0x84, /* I-port config */
288 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
289 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
290 0x94, 0x00, /* hoffset low (input), 0x0002 is minimum */
291 0x95, 0x00, /* hoffset hi (input) */
292 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */
293 0x97, 0x02, /* hsize hi (input) */
294 0x98, 0x03, /* voffset low (input) */
295 0x99, 0x00, /* voffset hi (input) */
296 0x9a, 0x12, /* vsize low (input), 0x12 = 18 */
297 0x9b, 0x00, /* vsize hi (input) */
298 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */
299 0x9d, 0x05, /* hsize hi (output) */
300 0x9e, 0x12, /* vsize low (output), 0x12 = 18 */
301 0x9f, 0x00, /* vsize hi (output) */
302
303 /* Task B */
304 0xc0, 0x00, /* Task Handling Control */
305 0xc1, 0x08, /* X-port formats/config */
306 0xc2, 0x00, /* Input Ref. signal Def. */
307 0xc3, 0x80, /* I-port config */
308 0xc4, 0x00, /* hoffset low (input), 0x0002 is minimum. See comment at 0x94 above. */
309 0xc5, 0x00, /* hoffset hi (input) */
310 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */
311 0xc7, 0x02, /* hsize hi (input) */
312 0xc8, 0x16, /* voffset low (input), 0x16 = 22 */
313 0xc9, 0x00, /* voffset hi (input) */
314 0xca, 0x20, /* vsize low (input), 0x0120 = 288 */
315 0xcb, 0x01, /* vsize hi (input) */
316 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */
317 0xcd, 0x02, /* hsize hi (output) */
318 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */
319 0xcf, 0x01, /* vsize hi (output) */
320
321 0xf0, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
322 0xf1, 0x05, /* low bit with 0xF0, (was 0x05) */
323 0xf5, 0xb0, /* Set pulse generator register */
324 0xf6, 0x01,
325
326 0x87, 0x00, /* Disable I-port output */
327 0x88, 0xd0, /* reset scaler (was 0xD0) */
328 0x80, 0x20, /* Activate only task "B" */
329 0x88, 0xf0, /* activate scaler */
330 0x87, 0x01, /* Enable I-port output */
331 0x00, 0x00
332};
333
334/* ============== SAA7715 VIDEO templates (end) ======= */
335
336static const unsigned char saa7115_cfg_vbi_on[] = {
337 0x80, 0x00, /* reset tasks */
338 0x88, 0xd0, /* reset scaler */
339 0x80, 0x30, /* Activate both tasks */
340 0x88, 0xf0, /* activate scaler */
341 0x87, 0x01, /* Enable I-port output */
342 0x00, 0x00
343};
344
345static const unsigned char saa7115_cfg_vbi_off[] = {
346 0x80, 0x00, /* reset tasks */
347 0x88, 0xd0, /* reset scaler */
348 0x80, 0x20, /* Activate only task "B" */
349 0x88, 0xf0, /* activate scaler */
350 0x87, 0x01, /* Enable I-port output */
351 0x00, 0x00
352};
353
f5762e44
MCC		 354static const unsigned char saa7113_init_auto_input[] = {
355 0x01, 0x08, /* PH7113_INCREMENT_DELAY - (1) (1) (1) (1) IDEL3 IDEL2 IDELL1 IDEL0 */
356 0x02, 0xc2, /* PH7113_ANALOG_INPUT_CONTR_1 - FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 */
357 0x03, 0x30, /* PH7113_ANALOG_INPUT_CONTR_2 - (1) HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 */
358 0x04, 0x00, /* PH7113_ANALOG_INPUT_CONTR_3 - GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 */
359 0x05, 0x00, /* PH7113_ANALOG_INPUT_CONTR_4 - GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 */
360 0x06, 0x89, /* PH7113_HORIZONTAL_SYNC_START - HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 */
361 0x07, 0x0d, /* PH7113_HORIZONTAL_SYNC_STOP - HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 */
362 0x08, 0x88, /* PH7113_SYNC_CONTROL - AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 */
363 0x09, 0x01, /* PH7113_LUMINANCE_CONTROL - BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0 */
364 0x0a, 0x80, /* PH7113_LUMINANCE_BRIGHTNESS - BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 */
365 0x0b, 0x47, /* PH7113_LUMINANCE_CONTRAST - CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 */
366 0x0c, 0x40, /* PH7113_CHROMA_SATURATION - SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 */
367 0x0d, 0x00, /* PH7113_CHROMA_HUE_CONTROL - HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 */
368 0x0e, 0x01, /* PH7113_CHROMA_CONTROL - CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0 */
369 0x0f, 0x2a, /* PH7113_CHROMA_GAIN_CONTROL - ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 */
370 0x10, 0x08, /* PH7113_FORMAT_DELAY_CONTROL - OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0 */
371 0x11, 0x0c, /* PH7113_OUTPUT_CONTROL_1 - GPSW1 CM99 GPSW0 HLSEL OEYC OERT VIPB COLO */
372 0x12, 0x07, /* PH7113_OUTPUT_CONTROL_2 - RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 */
373 0x13, 0x00, /* PH7113_OUTPUT_CONTROL_3 - ADLSB (1) (1) OLDSB FIDP (1) AOSL1 AOSL0 */
374 0x14, 0x00, /* RESERVED 14 - (1) (1) (1) (1) (1) (1) (1) (1) */
375 0x15, 0x00, /* PH7113_V_GATE1_START - VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 */
376 0x16, 0x00, /* PH7113_V_GATE1_STOP - VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 */
377 0x17, 0x00, /* PH7113_V_GATE1_MSB - (1) (1) (1) (1) (1) (1) VSTO8 VSTA8 */
378 0x00, 0x00
379};
380
e19b2fcc 381static const unsigned char saa7115_init_misc[] = {
e19b2fcc
HV		 382 0x81, 0x01, /* reg 0x15,0x16 define blanking window */
383 0x82, 0x00,
384 0x83, 0x01, /* I port settings */
385 0x84, 0x20,
386 0x85, 0x21,
387 0x86, 0xc5,
388 0x87, 0x01,
389
390 /* Task A */
391 0xa0, 0x01, /* down scale = 1 */
392 0xa1, 0x00, /* prescale accumulation length = 1 */
393 0xa2, 0x00, /* dc gain and fir prefilter control */
394 0xa4, 0x80, /* Lum Brightness, nominal value = 0x80 */
395 0xa5, 0x40, /* Lum contrast, nominal value = 0x40 */
396 0xa6, 0x40, /* Chroma satur. nominal value = 0x80 */
397 0xa8, 0x00, /* hor lum scaling 0x0200 = 2 zoom */
398 0xa9, 0x02, /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
399 0xaa, 0x00, /* H-phase offset Luma = 0 */
400 0xac, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
401 0xad, 0x01, /* H-scaling incr chroma */
402 0xae, 0x00, /* H-phase offset chroma. must be offset luma / 2 */
403
404 0xb0, 0x00, /* V-scaling incr luma low */
405 0xb1, 0x04, /* " hi */
406 0xb2, 0x00, /* V-scaling incr chroma low */
407 0xb3, 0x04, /* " hi */
408 0xb4, 0x01, /* V-scaling mode control */
409 0xb8, 0x00, /* V-phase offset chroma 00 */
410 0xb9, 0x00, /* V-phase offset chroma 01 */
411 0xba, 0x00, /* V-phase offset chroma 10 */
412 0xbb, 0x00, /* V-phase offset chroma 11 */
413 0xbc, 0x00, /* V-phase offset luma 00 */
414 0xbd, 0x00, /* V-phase offset luma 01 */
415 0xbe, 0x00, /* V-phase offset luma 10 */
416 0xbf, 0x00, /* V-phase offset luma 11 */
417
418 /* Task B */
419 0xd0, 0x01, /* down scale = 1 */
420 0xd1, 0x00, /* prescale accumulation length = 1 */
421 0xd2, 0x00, /* dc gain and fir prefilter control */
422 0xd4, 0x80, /* Lum Brightness, nominal value = 0x80 */
423 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */
424 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */
425 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */
426 0xd9, 0x04,
427 0xda, 0x00, /* H-phase offset Luma = 0 */
428 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
429 0xdd, 0x02, /* H-scaling incr chroma */
430 0xde, 0x00, /* H-phase offset chroma. must be offset luma / 2 */
431
432 0xe0, 0x00, /* V-scaling incr luma low */
433 0xe1, 0x04, /* " hi */
434 0xe2, 0x00, /* V-scaling incr chroma low */
435 0xe3, 0x04, /* " hi */
436 0xe4, 0x01, /* V-scaling mode control */
437 0xe8, 0x00, /* V-phase offset chroma 00 */
438 0xe9, 0x00, /* V-phase offset chroma 01 */
439 0xea, 0x00, /* V-phase offset chroma 10 */
440 0xeb, 0x00, /* V-phase offset chroma 11 */
441 0xec, 0x00, /* V-phase offset luma 00 */
442 0xed, 0x00, /* V-phase offset luma 01 */
443 0xee, 0x00, /* V-phase offset luma 10 */
444 0xef, 0x00, /* V-phase offset luma 11 */
445
446 0xf2, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
447 0xf3, 0x46,
448 0xf4, 0x00,
449 0xf7, 0x4b, /* not the recommended settings! */
450 0xf8, 0x00,
451 0xf9, 0x4b,
452 0xfa, 0x00,
453 0xfb, 0x4b,
454 0xff, 0x88, /* PLL2 lock detection settings: 71 lines 50% phase error */
455
456 /* Turn off VBI */
457 0x40, 0x20, /* No framing code errors allowed. */
458 0x41, 0xff,
459 0x42, 0xff,
460 0x43, 0xff,
461 0x44, 0xff,
462 0x45, 0xff,
463 0x46, 0xff,
464 0x47, 0xff,
465 0x48, 0xff,
466 0x49, 0xff,
467 0x4a, 0xff,
468 0x4b, 0xff,
469 0x4c, 0xff,
470 0x4d, 0xff,
471 0x4e, 0xff,
472 0x4f, 0xff,
473 0x50, 0xff,
474 0x51, 0xff,
475 0x52, 0xff,
476 0x53, 0xff,
477 0x54, 0xff,
478 0x55, 0xff,
479 0x56, 0xff,
480 0x57, 0xff,
481 0x58, 0x40,
482 0x59, 0x47,
483 0x5b, 0x83,
484 0x5d, 0xbd,
485 0x5e, 0x35,
486
487 0x02, 0x84, /* input tuner -> input 4, amplifier active */
488 0x09, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
489
490 0x80, 0x20, /* enable task B */
491 0x88, 0xd0,
492 0x88, 0xf0,
493 0x00, 0x00
494};
495
e19b2fcc
HV		 496static int saa7115_odd_parity(u8 c)
497{
498 c ^= (c >> 4);
499 c ^= (c >> 2);
500 c ^= (c >> 1);
501
502 return c & 1;
503}
504
505static int saa7115_decode_vps(u8 * dst, u8 * p)
506{
507 static const u8 biphase_tbl[] = {
508 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
509 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
510 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
511 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
512 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
513 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
514 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
515 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
516 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
517 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
518 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
519 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
520 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
521 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
522 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
523 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
524 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
525 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
526 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
527 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
528 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
529 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
530 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
531 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
532 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
533 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
534 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
535 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
536 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
537 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
538 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
539 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
540 };
541 int i;
542 u8 c, err = 0;
543
544 for (i = 0; i < 2 * 13; i += 2) {
545 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
546 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
547 dst[i / 2] = c;
548 }
549 return err & 0xf0;
550}
551
552static int saa7115_decode_wss(u8 * p)
553{
554 static const int wss_bits[8] = {
555 0, 0, 0, 1, 0, 1, 1, 1
556 };
557 unsigned char parity;
558 int wss = 0;
559 int i;
560
561 for (i = 0; i < 16; i++) {
562 int b1 = wss_bits[p[i] & 7];
563 int b2 = wss_bits[(p[i] >> 3) & 7];
564
565 if (b1 == b2)
566 return -1;
567 wss |= b2 << i;
568 }
569 parity = wss & 15;
570 parity ^= parity >> 2;
571 parity ^= parity >> 1;
572
573 if (!(parity & 1))
574 return -1;
575
576 return wss;
577}
578
579
3578d3dd 580static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
e19b2fcc
HV		 581{
582 struct saa7115_state *state = i2c_get_clientdata(client);
3578d3dd
HV		 583 u32 acpf;
584 u32 acni;
585 u32 hz;
586 u64 f;
b7f8292c 587 u8 acc = 0; /* reg 0x3a, audio clock control */
e19b2fcc 588
f167cb4e 589 v4l_dbg(1, debug, client, "set audio clock freq: %d\n", freq);
3578d3dd
HV		 590
591 /* sanity check */
592 if (freq < 32000 || freq > 48000)
593 return -EINVAL;
594
b7f8292c
HV		 595 /* The saa7113 has no audio clock */
596 if (state->ident == V4L2_IDENT_SAA7113)
597 return 0;
598
3578d3dd
HV		 599 /* hz is the refresh rate times 100 */
600 hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
601 /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
602 acpf = (25600 * freq) / hz;
603 /* acni = (256 * freq * 2^23) / crystal_frequency =
604 (freq * 2^(8+23)) / crystal_frequency =
b7f8292c 605 (freq << 31) / crystal_frequency */
3578d3dd
HV		 606 f = freq;
607 f = f << 31;
b7f8292c 608 do_div(f, state->crystal_freq);
3578d3dd 609 acni = f;
b7f8292c
HV		 610 if (state->ucgc) {
611 acpf = acpf * state->cgcdiv / 16;
612 acni = acni * state->cgcdiv / 16;
613 acc = 0x80;
614 if (state->cgcdiv == 3)
615 acc |= 0x40;
616 }
617 if (state->apll)
618 acc |= 0x08;
3578d3dd 619
b7f8292c
HV		 620 saa7115_write(client, 0x38, 0x03);
621 saa7115_write(client, 0x39, 0x10);
622 saa7115_write(client, 0x3a, acc);
3578d3dd
HV		 623 saa7115_write(client, 0x30, acpf & 0xff);
624 saa7115_write(client, 0x31, (acpf >> 8) & 0xff);
625 saa7115_write(client, 0x32, (acpf >> 16) & 0x03);
626 saa7115_write(client, 0x34, acni & 0xff);
627 saa7115_write(client, 0x35, (acni >> 8) & 0xff);
628 saa7115_write(client, 0x36, (acni >> 16) & 0x3f);
e19b2fcc
HV		 629 state->audclk_freq = freq;
630 return 0;
631}
632
633static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *ctrl)
634{
635 struct saa7115_state *state = i2c_get_clientdata(client);
636
637 switch (ctrl->id) {
638 case V4L2_CID_BRIGHTNESS:
639 if (ctrl->value < 0 || ctrl->value > 255) {
fac9e899 640 v4l_err(client, "invalid brightness setting %d\n", ctrl->value);
e19b2fcc
HV		 641 return -ERANGE;
642 }
643
644 state->bright = ctrl->value;
645 saa7115_write(client, 0x0a, state->bright);
646 break;
647
648 case V4L2_CID_CONTRAST:
649 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 650 v4l_err(client, "invalid contrast setting %d\n", ctrl->value);
e19b2fcc
HV		 651 return -ERANGE;
652 }
653
654 state->contrast = ctrl->value;
655 saa7115_write(client, 0x0b, state->contrast);
656 break;
657
658 case V4L2_CID_SATURATION:
659 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 660 v4l_err(client, "invalid saturation setting %d\n", ctrl->value);
e19b2fcc
HV		 661 return -ERANGE;
662 }
663
664 state->sat = ctrl->value;
665 saa7115_write(client, 0x0c, state->sat);
666 break;
667
668 case V4L2_CID_HUE:
669 if (ctrl->value < -127 || ctrl->value > 127) {
fac9e899 670 v4l_err(client, "invalid hue setting %d\n", ctrl->value);
e19b2fcc
HV		 671 return -ERANGE;
672 }
673
674 state->hue = ctrl->value;
675 saa7115_write(client, 0x0d, state->hue);
676 break;
3faeeae4
HV		 677
678 default:
679 return -EINVAL;
e19b2fcc
HV		 680 }
681
682 return 0;
683}
684
685static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *ctrl)
686{
687 struct saa7115_state *state = i2c_get_clientdata(client);
688
689 switch (ctrl->id) {
690 case V4L2_CID_BRIGHTNESS:
691 ctrl->value = state->bright;
692 break;
693 case V4L2_CID_CONTRAST:
694 ctrl->value = state->contrast;
695 break;
696 case V4L2_CID_SATURATION:
697 ctrl->value = state->sat;
698 break;
699 case V4L2_CID_HUE:
700 ctrl->value = state->hue;
701 break;
702 default:
703 return -EINVAL;
704 }
705
706 return 0;
707}
708
709static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
710{
711 struct saa7115_state *state = i2c_get_clientdata(client);
712 int taskb = saa7115_read(client, 0x80) & 0x10;
713
30b54d50
HV		 714 /* Prevent unnecessary standard changes. During a standard
715 change the I-Port is temporarily disabled. Any devices
716 reading from that port can get confused.
717 Note that VIDIOC_S_STD is also used to switch from
718 radio to TV mode, so if a VIDIOC_S_STD is broadcast to
719 all I2C devices then you do not want to have an unwanted
720 side-effect here. */
721 if (std == state->std)
722 return;
723
e19b2fcc
HV		 724 // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
725 if (std & V4L2_STD_525_60) {
f167cb4e 726 v4l_dbg(1, debug, client, "decoder set standard 60 Hz\n");
e19b2fcc
HV		 727 saa7115_writeregs(client, saa7115_cfg_60hz_video);
728 } else {
f167cb4e 729 v4l_dbg(1, debug, client, "decoder set standard 50 Hz\n");
e19b2fcc
HV		 730 saa7115_writeregs(client, saa7115_cfg_50hz_video);
731 }
732
f89982a9
MCC		 733 /* Register 0E - Bits D6-D4 on NO-AUTO mode
734 (SAA7113 doesn't have auto mode)
735 50 Hz / 625 lines 60 Hz / 525 lines
736 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz)
737 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz)
738 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
739 011 NTSC N (3.58MHz) PAL M (3.58MHz)
740 100 reserved NTSC-Japan (3.58MHz)
741 */
742 if (state->ident == V4L2_IDENT_SAA7113) {
01342358 743 u8 reg = saa7115_read(client, 0x0e) & 0x8f;
f89982a9 744
02c17224 745 if (std == V4L2_STD_PAL_M) {
01342358 746 reg |= 0x30;
02c17224 747 } else if (std == V4L2_STD_PAL_N) {
01342358 748 reg |= 0x20;
02c17224 749 } else if (std == V4L2_STD_PAL_60) {
01342358 750 reg |= 0x10;
02c17224 751 } else if (std == V4L2_STD_NTSC_M_JP) {
01342358 752 reg |= 0x40;
f89982a9
MCC		 753 }
754 saa7115_write(client, 0x0e, reg);
755 }
756
757
e19b2fcc
HV		 758 state->std = std;
759
760 /* restart task B if needed */
f5762e44 761 if (taskb && state->ident != V4L2_IDENT_SAA7115) {
e19b2fcc
HV		 762 saa7115_writeregs(client, saa7115_cfg_vbi_on);
763 }
764
765 /* switch audio mode too! */
766 saa7115_set_audio_clock_freq(client, state->audclk_freq);
767}
768
769static v4l2_std_id saa7115_get_v4lstd(struct i2c_client *client)
770{
771 struct saa7115_state *state = i2c_get_clientdata(client);
772
773 return state->std;
774}
775
776static void saa7115_log_status(struct i2c_client *client)
777{
e19b2fcc
HV		 778 struct saa7115_state *state = i2c_get_clientdata(client);
779 int reg1e, reg1f;
780 int signalOk;
781 int vcr;
782
fac9e899 783 v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq);
f5762e44 784 if (state->ident != V4L2_IDENT_SAA7115) {
e19b2fcc
HV		 785 /* status for the saa7114 */
786 reg1f = saa7115_read(client, 0x1f);
787 signalOk = (reg1f & 0xc1) == 0x81;
fac9e899
HV		 788 v4l_info(client, "Video signal: %s\n", signalOk ? "ok" : "bad");
789 v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
e19b2fcc
HV		 790 return;
791 }
792
793 /* status for the saa7115 */
794 reg1e = saa7115_read(client, 0x1e);
795 reg1f = saa7115_read(client, 0x1f);
796
797 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
798 vcr = !(reg1f & 0x10);
799
21fa715e 800 if (state->input >= 6) {
fac9e899 801 v4l_info(client, "Input: S-Video %d\n", state->input - 6);
21fa715e 802 } else {
fac9e899 803 v4l_info(client, "Input: Composite %d\n", state->input);
21fa715e 804 }
fac9e899
HV		 805 v4l_info(client, "Video signal: %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
806 v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
e19b2fcc
HV		 807
808 switch (reg1e & 0x03) {
809 case 1:
fac9e899 810 v4l_info(client, "Detected format: NTSC\n");
e19b2fcc
HV		 811 break;
812 case 2:
fac9e899 813 v4l_info(client, "Detected format: PAL\n");
e19b2fcc
HV		 814 break;
815 case 3:
fac9e899 816 v4l_info(client, "Detected format: SECAM\n");
e19b2fcc
HV		 817 break;
818 default:
fac9e899 819 v4l_info(client, "Detected format: BW/No color\n");
e19b2fcc
HV		 820 break;
821 }
822}
823
824/* setup the sliced VBI lcr registers according to the sliced VBI format */
825static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_format *fmt)
826{
827 struct saa7115_state *state = i2c_get_clientdata(client);
828 int is_50hz = (state->std & V4L2_STD_625_50);
829 u8 lcr[24];
830 int i, x;
831
01342358 832 /* saa7113/7114 doesn't yet support VBI */
f5762e44 833 if (state->ident != V4L2_IDENT_SAA7115)
e19b2fcc
HV		 834 return;
835
836 for (i = 0; i <= 23; i++)
837 lcr[i] = 0xff;
838
839 if (fmt->service_set == 0) {
840 /* raw VBI */
841 if (is_50hz)
842 for (i = 6; i <= 23; i++)
843 lcr[i] = 0xdd;
844 else
845 for (i = 10; i <= 21; i++)
846 lcr[i] = 0xdd;
847 } else {
848 /* sliced VBI */
849 /* first clear lines that cannot be captured */
850 if (is_50hz) {
851 for (i = 0; i <= 5; i++)
852 fmt->service_lines[0][i] =
853 fmt->service_lines[1][i] = 0;
854 }
855 else {
856 for (i = 0; i <= 9; i++)
857 fmt->service_lines[0][i] =
858 fmt->service_lines[1][i] = 0;
859 for (i = 22; i <= 23; i++)
860 fmt->service_lines[0][i] =
861 fmt->service_lines[1][i] = 0;
862 }
863
864 /* Now set the lcr values according to the specified service */
865 for (i = 6; i <= 23; i++) {
866 lcr[i] = 0;
867 for (x = 0; x <= 1; x++) {
868 switch (fmt->service_lines[1-x][i]) {
869 case 0:
870 lcr[i] |= 0xf << (4 * x);
871 break;
9bc7400a 872 case V4L2_SLICED_TELETEXT_B:
e19b2fcc
HV		 873 lcr[i] |= 1 << (4 * x);
874 break;
875 case V4L2_SLICED_CAPTION_525:
876 lcr[i] |= 4 << (4 * x);
877 break;
878 case V4L2_SLICED_WSS_625:
879 lcr[i] |= 5 << (4 * x);
880 break;
881 case V4L2_SLICED_VPS:
882 lcr[i] |= 7 << (4 * x);
883 break;
884 }
885 }
886 }
887 }
888
889 /* write the lcr registers */
890 for (i = 2; i <= 23; i++) {
891 saa7115_write(client, i - 2 + 0x41, lcr[i]);
892 }
893
894 /* enable/disable raw VBI capturing */
895 saa7115_writeregs(client, fmt->service_set == 0 ? saa7115_cfg_vbi_on : saa7115_cfg_vbi_off);
896}
897
898static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
899{
900 static u16 lcr2vbi[] = {
9bc7400a 901 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
e19b2fcc
HV		 902 0, V4L2_SLICED_CAPTION_525, /* 4 */
903 V4L2_SLICED_WSS_625, 0, /* 5 */
904 V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */
905 0, 0, 0, 0
906 };
907 struct v4l2_sliced_vbi_format *sliced = &fmt->fmt.sliced;
908 int i;
909
910 if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
911 return -EINVAL;
912 memset(sliced, 0, sizeof(*sliced));
913 /* done if using raw VBI */
914 if (saa7115_read(client, 0x80) & 0x10)
915 return 0;
916 for (i = 2; i <= 23; i++) {
917 u8 v = saa7115_read(client, i - 2 + 0x41);
918
919 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
920 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
921 sliced->service_set |=
922 sliced->service_lines[0][i] | sliced->service_lines[1][i];
923 }
924 return 0;
925}
926
927static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
928{
929 struct saa7115_state *state = i2c_get_clientdata(client);
930 struct v4l2_pix_format *pix;
931 int HPSC, HFSC;
932 int VSCY, Vsrc;
933 int is_50hz = state->std & V4L2_STD_625_50;
934
935 if (fmt->type == V4L2_BUF_TYPE_SLICED_VBI_CAPTURE) {
936 saa7115_set_lcr(client, &fmt->fmt.sliced);
937 return 0;
938 }
939 if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
940 return -EINVAL;
941
942 pix = &(fmt->fmt.pix);
943
f167cb4e 944 v4l_dbg(1, debug, client, "decoder set size\n");
e19b2fcc
HV		 945
946 /* FIXME need better bounds checking here */
947 if ((pix->width < 1) || (pix->width > 1440))
948 return -EINVAL;
949 if ((pix->height < 1) || (pix->height > 960))
950 return -EINVAL;
951
952 /* probably have a valid size, let's set it */
953 /* Set output width/height */
954 /* width */
955 saa7115_write(client, 0xcc, (u8) (pix->width & 0xff));
956 saa7115_write(client, 0xcd, (u8) ((pix->width >> 8) & 0xff));
957 /* height */
958 saa7115_write(client, 0xce, (u8) (pix->height & 0xff));
959 saa7115_write(client, 0xcf, (u8) ((pix->height >> 8) & 0xff));
960
961 /* Scaling settings */
962 /* Hprescaler is floor(inres/outres) */
963 /* FIXME hardcoding input res */
964 if (pix->width != 720) {
965 HPSC = (int)(720 / pix->width);
966 /* 0 is not allowed (div. by zero) */
967 HPSC = HPSC ? HPSC : 1;
968 HFSC = (int)((1024 * 720) / (HPSC * pix->width));
969
f167cb4e 970 v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
e19b2fcc
HV		 971 /* FIXME hardcodes to "Task B"
972 * write H prescaler integer */
973 saa7115_write(client, 0xd0, (u8) (HPSC & 0x3f));
974
975 /* write H fine-scaling (luminance) */
976 saa7115_write(client, 0xd8, (u8) (HFSC & 0xff));
977 saa7115_write(client, 0xd9, (u8) ((HFSC >> 8) & 0xff));
978 /* write H fine-scaling (chrominance)
979 * must be lum/2, so i'll just bitshift :) */
980 saa7115_write(client, 0xDC, (u8) ((HFSC >> 1) & 0xff));
981 saa7115_write(client, 0xDD, (u8) ((HFSC >> 9) & 0xff));
982 } else {
983 if (is_50hz) {
f167cb4e 984 v4l_dbg(1, debug, client, "Setting full 50hz width\n");
e19b2fcc
HV		 985 saa7115_writeregs(client, saa7115_cfg_50hz_fullres_x);
986 } else {
f167cb4e 987 v4l_dbg(1, debug, client, "Setting full 60hz width\n");
e19b2fcc
HV		 988 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_x);
989 }
990 }
991
992 Vsrc = is_50hz ? 576 : 480;
993
994 if (pix->height != Vsrc) {
995 VSCY = (int)((1024 * Vsrc) / pix->height);
f167cb4e 996 v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
e19b2fcc
HV		 997
998 /* Correct Contrast and Luminance */
999 saa7115_write(client, 0xd5, (u8) (64 * 1024 / VSCY));
1000 saa7115_write(client, 0xd6, (u8) (64 * 1024 / VSCY));
1001
1002 /* write V fine-scaling (luminance) */
1003 saa7115_write(client, 0xe0, (u8) (VSCY & 0xff));
1004 saa7115_write(client, 0xe1, (u8) ((VSCY >> 8) & 0xff));
1005 /* write V fine-scaling (chrominance) */
1006 saa7115_write(client, 0xe2, (u8) (VSCY & 0xff));
1007 saa7115_write(client, 0xe3, (u8) ((VSCY >> 8) & 0xff));
1008 } else {
1009 if (is_50hz) {
f167cb4e 1010 v4l_dbg(1, debug, client, "Setting full 50Hz height\n");
e19b2fcc
HV		 1011 saa7115_writeregs(client, saa7115_cfg_50hz_fullres_y);
1012 } else {
f167cb4e 1013 v4l_dbg(1, debug, client, "Setting full 60hz height\n");
e19b2fcc
HV		 1014 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_y);
1015 }
1016 }
1017
1018 saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1019 return 0;
1020}
1021
1022/* Decode the sliced VBI data stream as created by the saa7115.
1023 The format is described in the saa7115 datasheet in Tables 25 and 26
1024 and in Figure 33.
1025 The current implementation uses SAV/EAV codes and not the ancillary data
1026 headers. The vbi->p pointer points to the SDID byte right after the SAV
1027 code. */
1028static void saa7115_decode_vbi_line(struct i2c_client *client,
1029 struct v4l2_decode_vbi_line *vbi)
1030{
1031 static const char vbi_no_data_pattern[] = {
1032 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
1033 };
1034 struct saa7115_state *state = i2c_get_clientdata(client);
1035 u8 *p = vbi->p;
1036 u32 wss;
1037 int id1, id2; /* the ID1 and ID2 bytes from the internal header */
1038
1039 vbi->type = 0; /* mark result as a failure */
1040 id1 = p[2];
1041 id2 = p[3];
1042 /* Note: the field bit is inverted for 60 Hz video */
1043 if (state->std & V4L2_STD_525_60)
1044 id1 ^= 0x40;
1045
1046 /* Skip internal header, p now points to the start of the payload */
1047 p += 4;
1048 vbi->p = p;
1049
1050 /* calculate field and line number of the VBI packet (1-23) */
1051 vbi->is_second_field = ((id1 & 0x40) != 0);
1052 vbi->line = (id1 & 0x3f) << 3;
1053 vbi->line |= (id2 & 0x70) >> 4;
1054
1055 /* Obtain data type */
1056 id2 &= 0xf;
1057
1058 /* If the VBI slicer does not detect any signal it will fill up
1059 the payload buffer with 0xa0 bytes. */
1060 if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1061 return;
1062
1063 /* decode payloads */
1064 switch (id2) {
1065 case 1:
9bc7400a 1066 vbi->type = V4L2_SLICED_TELETEXT_B;
e19b2fcc
HV		 1067 break;
1068 case 4:
1069 if (!saa7115_odd_parity(p[0]) || !saa7115_odd_parity(p[1]))
1070 return;
1071 vbi->type = V4L2_SLICED_CAPTION_525;
1072 break;
1073 case 5:
1074 wss = saa7115_decode_wss(p);
1075 if (wss == -1)
1076 return;
1077 p[0] = wss & 0xff;
1078 p[1] = wss >> 8;
1079 vbi->type = V4L2_SLICED_WSS_625;
1080 break;
1081 case 7:
1082 if (saa7115_decode_vps(p, p) != 0)
1083 return;
1084 vbi->type = V4L2_SLICED_VPS;
1085 break;
1086 default:
1087 return;
1088 }
1089}
1090
1091/* ============ SAA7115 AUDIO settings (end) ============= */
1092
1093static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *arg)
1094{
1095 struct saa7115_state *state = i2c_get_clientdata(client);
1096 int *iarg = arg;
1097
1098 /* ioctls to allow direct access to the saa7115 registers for testing */
1099 switch (cmd) {
1100 case VIDIOC_S_FMT:
1101 return saa7115_set_v4lfmt(client, (struct v4l2_format *)arg);
1102
1103 case VIDIOC_G_FMT:
1104 return saa7115_get_v4lfmt(client, (struct v4l2_format *)arg);
1105
1106 case VIDIOC_INT_AUDIO_CLOCK_FREQ:
3578d3dd 1107 return saa7115_set_audio_clock_freq(client, *(u32 *)arg);
e19b2fcc
HV		 1108
1109 case VIDIOC_G_TUNER:
1110 {
1111 struct v4l2_tuner *vt = arg;
1112 int status;
1113
3faeeae4
HV		 1114 if (state->radio)
1115 break;
e19b2fcc
HV		 1116 status = saa7115_read(client, 0x1f);
1117
f167cb4e 1118 v4l_dbg(1, debug, client, "status: 0x%02x\n", status);
e19b2fcc
HV		 1119 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
1120 break;
1121 }
1122
1123 case VIDIOC_LOG_STATUS:
1124 saa7115_log_status(client);
1125 break;
1126
1127 case VIDIOC_G_CTRL:
1128 return saa7115_get_v4lctrl(client, (struct v4l2_control *)arg);
1129
1130 case VIDIOC_S_CTRL:
1131 return saa7115_set_v4lctrl(client, (struct v4l2_control *)arg);
1132
da4ae5a7
HV		 1133 case VIDIOC_QUERYCTRL:
1134 {
1135 struct v4l2_queryctrl *qc = arg;
da4ae5a7 1136
18318e00
HV		 1137 switch (qc->id) {
1138 case V4L2_CID_BRIGHTNESS:
1139 case V4L2_CID_CONTRAST:
1140 case V4L2_CID_SATURATION:
1141 case V4L2_CID_HUE:
1142 return v4l2_ctrl_query_fill_std(qc);
1143 default:
1144 return -EINVAL;
1145 }
da4ae5a7
HV		 1146 }
1147
e19b2fcc
HV		 1148 case VIDIOC_G_STD:
1149 *(v4l2_std_id *)arg = saa7115_get_v4lstd(client);
1150 break;
1151
1152 case VIDIOC_S_STD:
3faeeae4 1153 state->radio = 0;
e19b2fcc
HV		 1154 saa7115_set_v4lstd(client, *(v4l2_std_id *)arg);
1155 break;
1156
3faeeae4
HV		 1157 case AUDC_SET_RADIO:
1158 state->radio = 1;
1159 break;
1160
1f8f5fa9
HV		 1161 case VIDIOC_INT_G_VIDEO_ROUTING:
1162 {
1163 struct v4l2_routing *route = arg;
1164
1165 route->input = state->input;
1166 route->output = 0;
1167 break;
1168 }
1169
1170 case VIDIOC_INT_S_VIDEO_ROUTING:
1171 {
1172 struct v4l2_routing *route = arg;
1173
1174 v4l_dbg(1, debug, client, "decoder set input %d\n", route->input);
1175 /* saa7113 does not have these inputs */
1176 if (state->ident == V4L2_IDENT_SAA7113 &&
1177 (route->input == SAA7115_COMPOSITE4 ||
1178 route->input == SAA7115_COMPOSITE5)) {
1179 return -EINVAL;
1180 }
1181 if (route->input > SAA7115_SVIDEO3)
1182 return -EINVAL;
1183 if (state->input == route->input)
1184 break;
1185 v4l_dbg(1, debug, client, "now setting %s input\n",
1186 (route->input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite");
1187 state->input = route->input;
1188
1189 /* select mode */
1190 saa7115_write(client, 0x02,
1191 (saa7115_read(client, 0x02) & 0xf0) |
1192 state->input);
1193
1194 /* bypass chrominance trap for S-Video modes */
1195 saa7115_write(client, 0x09,
1196 (saa7115_read(client, 0x09) & 0x7f) |
1197 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1198 break;
1199 }
1200
e19b2fcc
HV		 1201 case VIDIOC_STREAMON:
1202 case VIDIOC_STREAMOFF:
f167cb4e 1203 v4l_dbg(1, debug, client, "%s output\n",
e19b2fcc
HV		 1204 (cmd == VIDIOC_STREAMON) ? "enable" : "disable");
1205
1206 if (state->enable != (cmd == VIDIOC_STREAMON)) {
1207 state->enable = (cmd == VIDIOC_STREAMON);
1208 saa7115_write(client, 0x87, state->enable);
1209 }
1210 break;
1211
b7f8292c
HV		 1212 case VIDIOC_INT_S_CRYSTAL_FREQ:
1213 {
1214 struct v4l2_crystal_freq *freq = arg;
1215
1216 if (freq->freq != SAA7115_FREQ_32_11_MHZ &&
1217 freq->freq != SAA7115_FREQ_24_576_MHZ)
1218 return -EINVAL;
1219 state->crystal_freq = freq->freq;
1220 state->cgcdiv = (freq->flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
1221 state->ucgc = (freq->flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0;
1222 state->apll = (freq->flags & SAA7115_FREQ_FL_APLL) ? 1 : 0;
1223 saa7115_set_audio_clock_freq(client, state->audclk_freq);
1224 break;
1225 }
1226
e19b2fcc
HV		 1227 case VIDIOC_INT_DECODE_VBI_LINE:
1228 saa7115_decode_vbi_line(client, arg);
1229 break;
1230
1231 case VIDIOC_INT_RESET:
f167cb4e 1232 v4l_dbg(1, debug, client, "decoder RESET\n");
e19b2fcc
HV		 1233 saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1234 break;
1235
1236 case VIDIOC_INT_G_VBI_DATA:
1237 {
1238 struct v4l2_sliced_vbi_data *data = arg;
1239
1240 switch (data->id) {
1241 case V4L2_SLICED_WSS_625:
1242 if (saa7115_read(client, 0x6b) & 0xc0)
1243 return -EIO;
1244 data->data[0] = saa7115_read(client, 0x6c);
1245 data->data[1] = saa7115_read(client, 0x6d);
1246 return 0;
1247 case V4L2_SLICED_CAPTION_525:
1248 if (data->field == 0) {
1249 /* CC */
1250 if (saa7115_read(client, 0x66) & 0xc0)
1251 return -EIO;
1252 data->data[0] = saa7115_read(client, 0x67);
1253 data->data[1] = saa7115_read(client, 0x68);
1254 return 0;
1255 }
1256 /* XDS */
1257 if (saa7115_read(client, 0x66) & 0x30)
1258 return -EIO;
1259 data->data[0] = saa7115_read(client, 0x69);
1260 data->data[1] = saa7115_read(client, 0x6a);
1261 return 0;
1262 default:
1263 return -EINVAL;
1264 }
1265 break;
1266 }
1267
1268#ifdef CONFIG_VIDEO_ADV_DEBUG
1269 case VIDIOC_INT_G_REGISTER:
1270 {
1271 struct v4l2_register *reg = arg;
1272
1273 if (reg->i2c_id != I2C_DRIVERID_SAA711X)
1274 return -EINVAL;
1275 reg->val = saa7115_read(client, reg->reg & 0xff);
1276 break;
1277 }
1278
1279 case VIDIOC_INT_S_REGISTER:
1280 {
1281 struct v4l2_register *reg = arg;
1282
1283 if (reg->i2c_id != I2C_DRIVERID_SAA711X)
1284 return -EINVAL;
1285 if (!capable(CAP_SYS_ADMIN))
1286 return -EPERM;
1287 saa7115_write(client, reg->reg & 0xff, reg->val & 0xff);
1288 break;
1289 }
1290#endif
1291
1292 case VIDIOC_INT_G_CHIP_IDENT:
1293 *iarg = state->ident;
1294 break;
1295
1296 default:
1297 return -EINVAL;
1298 }
1299
1300 return 0;
1301}
1302
1303/* ----------------------------------------------------------------------- */
1304
1305static struct i2c_driver i2c_driver_saa7115;
1306
1307static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
1308{
1309 struct i2c_client *client;
1310 struct saa7115_state *state;
236f16d2
MCC		 1311 int i;
1312 char name[17];
e19b2fcc
HV		 1313 u8 chip_id;
1314
1315 /* Check if the adapter supports the needed features */
1316 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1317 return 0;
1318
7408187d 1319 client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
e19b2fcc
HV		 1320 if (client == 0)
1321 return -ENOMEM;
e19b2fcc
HV		 1322 client->addr = address;
1323 client->adapter = adapter;
1324 client->driver = &i2c_driver_saa7115;
e19b2fcc
HV		 1325 snprintf(client->name, sizeof(client->name) - 1, "saa7115");
1326
f167cb4e 1327 v4l_dbg(1, debug, client, "detecting saa7115 client on address 0x%x\n", address << 1);
e19b2fcc 1328
236f16d2
MCC		 1329 for (i=0;i<0x0f;i++) {
1330 saa7115_write(client, 0, i);
1331 name[i] = (saa7115_read(client, 0) &0x0f) +'0';
1332 if (name[i]>'9')
1333 name[i]+='a'-'9'-1;
1334 }
1335 name[i]='\0';
1336
e19b2fcc
HV		 1337 saa7115_write(client, 0, 5);
1338 chip_id = saa7115_read(client, 0) & 0x0f;
01342358 1339 if (chip_id < 3 && chip_id > 5) {
f167cb4e 1340 v4l_dbg(1, debug, client, "saa7115 not found\n");
e19b2fcc
HV		 1341 kfree(client);
1342 return 0;
1343 }
f5762e44 1344 snprintf(client->name, sizeof(client->name) - 1, "saa711%d",chip_id);
236f16d2 1345 v4l_info(client, "saa711%d found (%s) @ 0x%x (%s)\n", chip_id, name, address << 1, adapter->name);
e19b2fcc 1346
7408187d 1347 state = kzalloc(sizeof(struct saa7115_state), GFP_KERNEL);
e19b2fcc
HV		 1348 i2c_set_clientdata(client, state);
1349 if (state == NULL) {
1350 kfree(client);
1351 return -ENOMEM;
1352 }
e19b2fcc
HV		 1353 state->std = V4L2_STD_NTSC;
1354 state->input = -1;
1355 state->enable = 1;
3faeeae4 1356 state->radio = 0;
e19b2fcc
HV		 1357 state->bright = 128;
1358 state->contrast = 64;
1359 state->hue = 0;
1360 state->sat = 64;
f5762e44
MCC		 1361 switch (chip_id) {
1362 case 3:
1363 state->ident = V4L2_IDENT_SAA7113;
1364 break;
1365 case 4:
1366 state->ident = V4L2_IDENT_SAA7114;
1367 break;
1368 default:
1369 state->ident = V4L2_IDENT_SAA7115;
1370 break;
1371 }
1372
3578d3dd 1373 state->audclk_freq = 48000;
e19b2fcc 1374
f167cb4e 1375 v4l_dbg(1, debug, client, "writing init values\n");
e19b2fcc
HV		 1376
1377 /* init to 60hz/48khz */
b7f8292c
HV		 1378 if (state->ident == V4L2_IDENT_SAA7113) {
1379 state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
f5762e44 1380 saa7115_writeregs(client, saa7113_init_auto_input);
b7f8292c
HV		 1381 } else {
1382 state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
f5762e44 1383 saa7115_writeregs(client, saa7115_init_auto_input);
b7f8292c 1384 }
e19b2fcc
HV		 1385 saa7115_writeregs(client, saa7115_init_misc);
1386 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_x);
1387 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_y);
1388 saa7115_writeregs(client, saa7115_cfg_60hz_video);
3578d3dd 1389 saa7115_set_audio_clock_freq(client, state->audclk_freq);
e19b2fcc
HV		 1390 saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1391
1392 i2c_attach_client(client);
1393
f167cb4e 1394 v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n",
e19b2fcc
HV		 1395 saa7115_read(client, 0x1e), saa7115_read(client, 0x1f));
1396
1397 return 0;
1398}
1399
1400static int saa7115_probe(struct i2c_adapter *adapter)
1401{
e19b2fcc 1402 if (adapter->class & I2C_CLASS_TV_ANALOG)
e19b2fcc
HV		 1403 return i2c_probe(adapter, &addr_data, &saa7115_attach);
1404 return 0;
1405}
1406
1407static int saa7115_detach(struct i2c_client *client)
1408{
1409 struct saa7115_state *state = i2c_get_clientdata(client);
1410 int err;
1411
1412 err = i2c_detach_client(client);
1413 if (err) {
1414 return err;
1415 }
1416
1417 kfree(state);
1418 kfree(client);
1419 return 0;
1420}
1421
1422/* ----------------------------------------------------------------------- */
1423
1424/* i2c implementation */
1425static struct i2c_driver i2c_driver_saa7115 = {
604f28e2 1426 .driver = {
604f28e2
LR		 1427 .name = "saa7115",
1428 },
e19b2fcc 1429 .id = I2C_DRIVERID_SAA711X,
e19b2fcc
HV		 1430 .attach_adapter = saa7115_probe,
1431 .detach_client = saa7115_detach,
1432 .command = saa7115_command,
e19b2fcc
HV		 1433};
1434
1435
1436static int __init saa7115_init_module(void)
1437{
1438 return i2c_add_driver(&i2c_driver_saa7115);
1439}
1440
1441static void __exit saa7115_cleanup_module(void)
1442{
1443 i2c_del_driver(&i2c_driver_saa7115);
1444}
1445
1446module_init(saa7115_init_module);
1447module_exit(saa7115_cleanup_module);
Linux 6.x block layer and io_uring tree(s)