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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
25 | #include <linux/version.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
3bc43840 GL |
28 | #include <linux/clk.h> |
29 | ||
30 | #include <media/v4l2-common.h> | |
31 | #include <media/v4l2-dev.h> | |
092d3921 | 32 | #include <media/videobuf-dma-sg.h> |
3bc43840 GL |
33 | #include <media/soc_camera.h> |
34 | ||
35 | #include <linux/videodev2.h> | |
36 | ||
cfbaf4df | 37 | #include <mach/dma.h> |
a09e64fb | 38 | #include <mach/camera.h> |
3bc43840 GL |
39 | |
40 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | |
41 | #define PXA_CAM_DRV_NAME "pxa27x-camera" | |
42 | ||
5ca11fa3 EM |
43 | /* Camera Interface */ |
44 | #define CICR0 0x0000 | |
45 | #define CICR1 0x0004 | |
46 | #define CICR2 0x0008 | |
47 | #define CICR3 0x000C | |
48 | #define CICR4 0x0010 | |
49 | #define CISR 0x0014 | |
50 | #define CIFR 0x0018 | |
51 | #define CITOR 0x001C | |
52 | #define CIBR0 0x0028 | |
53 | #define CIBR1 0x0030 | |
54 | #define CIBR2 0x0038 | |
55 | ||
56 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
57 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
58 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
59 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
60 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
61 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
62 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
63 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
64 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
65 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
66 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
67 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
68 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
69 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
70 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
71 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
72 | ||
73 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
74 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
75 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
76 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
77 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
78 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
79 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
80 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
81 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
82 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
83 | ||
84 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
85 | wait count mask */ | |
86 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
87 | wait count mask */ | |
88 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
89 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
90 | wait count mask */ | |
91 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
92 | wait count mask */ | |
93 | ||
94 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
95 | wait count mask */ | |
96 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
97 | wait count mask */ | |
98 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
99 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
100 | wait count mask */ | |
101 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
102 | ||
103 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
104 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
105 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
106 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
107 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
108 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
109 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
110 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
111 | ||
112 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
113 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
114 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
115 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
116 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
117 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
118 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
119 | #define CISR_EOL (1 << 8) /* End of line */ | |
120 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
121 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
122 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
123 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
124 | #define CISR_EOF (1 << 3) /* End of frame */ | |
125 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
126 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
127 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
128 | ||
129 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
130 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
131 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
132 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
133 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
134 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
135 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
136 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
137 | ||
7102b773 GL |
138 | #define CICR0_SIM_MP (0 << 24) |
139 | #define CICR0_SIM_SP (1 << 24) | |
140 | #define CICR0_SIM_MS (2 << 24) | |
141 | #define CICR0_SIM_EP (3 << 24) | |
142 | #define CICR0_SIM_ES (4 << 24) | |
143 | ||
144 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
145 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
146 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
147 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
148 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
149 | |
150 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
151 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
152 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
153 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
154 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
155 | ||
156 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
157 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
158 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
159 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
160 | ||
3bc43840 GL |
161 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
162 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
163 | CICR0_EOFM | CICR0_FOM) | |
164 | ||
3bc43840 GL |
165 | /* |
166 | * Structures | |
167 | */ | |
a5462e5b MR |
168 | enum pxa_camera_active_dma { |
169 | DMA_Y = 0x1, | |
170 | DMA_U = 0x2, | |
171 | DMA_V = 0x4, | |
172 | }; | |
173 | ||
174 | /* descriptor needed for the PXA DMA engine */ | |
175 | struct pxa_cam_dma { | |
176 | dma_addr_t sg_dma; | |
177 | struct pxa_dma_desc *sg_cpu; | |
178 | size_t sg_size; | |
179 | int sglen; | |
180 | }; | |
3bc43840 GL |
181 | |
182 | /* buffer for one video frame */ | |
183 | struct pxa_buffer { | |
184 | /* common v4l buffer stuff -- must be first */ | |
185 | struct videobuf_buffer vb; | |
186 | ||
187 | const struct soc_camera_data_format *fmt; | |
188 | ||
a5462e5b MR |
189 | /* our descriptor lists for Y, U and V channels */ |
190 | struct pxa_cam_dma dmas[3]; | |
191 | ||
3bc43840 | 192 | int inwork; |
a5462e5b MR |
193 | |
194 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
195 | }; |
196 | ||
3bc43840 GL |
197 | struct pxa_camera_dev { |
198 | struct device *dev; | |
199 | /* PXA27x is only supposed to handle one camera on its Quick Capture | |
200 | * interface. If anyone ever builds hardware to enable more than | |
201 | * one camera, they will have to modify this driver too */ | |
202 | struct soc_camera_device *icd; | |
203 | struct clk *clk; | |
204 | ||
205 | unsigned int irq; | |
206 | void __iomem *base; | |
a5462e5b | 207 | |
e7c50688 | 208 | int channels; |
a5462e5b | 209 | unsigned int dma_chans[3]; |
3bc43840 | 210 | |
3bc43840 GL |
211 | struct pxacamera_platform_data *pdata; |
212 | struct resource *res; | |
213 | unsigned long platform_flags; | |
cf34cba7 GL |
214 | unsigned long ciclk; |
215 | unsigned long mclk; | |
216 | u32 mclk_divisor; | |
3bc43840 GL |
217 | |
218 | struct list_head capture; | |
219 | ||
220 | spinlock_t lock; | |
221 | ||
3bc43840 | 222 | struct pxa_buffer *active; |
5aa2110f | 223 | struct pxa_dma_desc *sg_tail[3]; |
3f6ac497 RJ |
224 | |
225 | u32 save_cicr[5]; | |
3bc43840 GL |
226 | }; |
227 | ||
228 | static const char *pxa_cam_driver_description = "PXA_Camera"; | |
229 | ||
230 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
231 | ||
232 | /* | |
233 | * Videobuf operations | |
234 | */ | |
7102b773 GL |
235 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
236 | unsigned int *size) | |
3bc43840 GL |
237 | { |
238 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 239 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
5aa2110f | 240 | struct pxa_camera_dev *pcdev = ici->priv; |
3bc43840 GL |
241 | |
242 | dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); | |
243 | ||
a5462e5b | 244 | /* planar capture requires Y, U and V buffers to be page aligned */ |
5aa2110f | 245 | if (pcdev->channels == 3) { |
a5462e5b MR |
246 | *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */ |
247 | *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */ | |
248 | *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */ | |
249 | } else { | |
250 | *size = icd->width * icd->height * | |
251 | ((icd->current_fmt->depth + 7) >> 3); | |
252 | } | |
3bc43840 GL |
253 | |
254 | if (0 == *count) | |
255 | *count = 32; | |
256 | while (*size * *count > vid_limit * 1024 * 1024) | |
257 | (*count)--; | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
263 | { | |
264 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 265 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
266 | struct pxa_camera_dev *pcdev = ici->priv; |
267 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); | |
a5462e5b | 268 | int i; |
3bc43840 GL |
269 | |
270 | BUG_ON(in_interrupt()); | |
271 | ||
7e28adb2 | 272 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
273 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
274 | ||
275 | /* This waits until this buffer is out of danger, i.e., until it is no | |
276 | * longer in STATE_QUEUED or STATE_ACTIVE */ | |
277 | videobuf_waiton(&buf->vb, 0, 0); | |
278 | videobuf_dma_unmap(vq, dma); | |
279 | videobuf_dma_free(dma); | |
280 | ||
a5462e5b MR |
281 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
282 | if (buf->dmas[i].sg_cpu) | |
283 | dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size, | |
284 | buf->dmas[i].sg_cpu, | |
285 | buf->dmas[i].sg_dma); | |
286 | buf->dmas[i].sg_cpu = NULL; | |
287 | } | |
3bc43840 GL |
288 | |
289 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
290 | } | |
291 | ||
a5462e5b MR |
292 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
293 | struct pxa_buffer *buf, | |
294 | struct videobuf_dmabuf *dma, int channel, | |
295 | int sglen, int sg_start, int cibr, | |
296 | unsigned int size) | |
297 | { | |
298 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
299 | int i; | |
300 | ||
301 | if (pxa_dma->sg_cpu) | |
302 | dma_free_coherent(pcdev->dev, pxa_dma->sg_size, | |
303 | pxa_dma->sg_cpu, pxa_dma->sg_dma); | |
304 | ||
305 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); | |
306 | pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size, | |
307 | &pxa_dma->sg_dma, GFP_KERNEL); | |
308 | if (!pxa_dma->sg_cpu) | |
309 | return -ENOMEM; | |
310 | ||
311 | pxa_dma->sglen = sglen; | |
312 | ||
313 | for (i = 0; i < sglen; i++) { | |
314 | int sg_i = sg_start + i; | |
315 | struct scatterlist *sg = dma->sglist; | |
316 | unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len; | |
317 | ||
318 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
319 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]); | |
320 | ||
321 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
322 | xfer_len = (min(dma_len, size) + 7) & ~7; | |
323 | ||
324 | pxa_dma->sg_cpu[i].dcmd = | |
325 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
326 | size -= dma_len; | |
327 | pxa_dma->sg_cpu[i].ddadr = | |
328 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
329 | } | |
330 | ||
331 | pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP; | |
332 | pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN; | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
7102b773 GL |
337 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
338 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
339 | { |
340 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 341 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
342 | struct pxa_camera_dev *pcdev = ici->priv; |
343 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
a5462e5b MR |
344 | int ret; |
345 | int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0; | |
346 | int size_y, size_u = 0, size_v = 0; | |
3bc43840 | 347 | |
7e28adb2 | 348 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
349 | vb, vb->baddr, vb->bsize); |
350 | ||
351 | /* Added list head initialization on alloc */ | |
352 | WARN_ON(!list_empty(&vb->queue)); | |
353 | ||
354 | #ifdef DEBUG | |
355 | /* This can be useful if you want to see if we actually fill | |
356 | * the buffer with something */ | |
357 | memset((void *)vb->baddr, 0xaa, vb->bsize); | |
358 | #endif | |
359 | ||
360 | BUG_ON(NULL == icd->current_fmt); | |
361 | ||
362 | /* I think, in buf_prepare you only have to protect global data, | |
363 | * the actual buffer is yours */ | |
364 | buf->inwork = 1; | |
365 | ||
366 | if (buf->fmt != icd->current_fmt || | |
367 | vb->width != icd->width || | |
368 | vb->height != icd->height || | |
369 | vb->field != field) { | |
370 | buf->fmt = icd->current_fmt; | |
371 | vb->width = icd->width; | |
372 | vb->height = icd->height; | |
373 | vb->field = field; | |
374 | vb->state = VIDEOBUF_NEEDS_INIT; | |
375 | } | |
376 | ||
377 | vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3); | |
378 | if (0 != vb->baddr && vb->bsize < vb->size) { | |
379 | ret = -EINVAL; | |
380 | goto out; | |
381 | } | |
382 | ||
383 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
384 | unsigned int size = vb->size; | |
385 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); | |
386 | ||
387 | ret = videobuf_iolock(vq, vb, NULL); | |
388 | if (ret) | |
389 | goto fail; | |
390 | ||
5aa2110f | 391 | if (pcdev->channels == 3) { |
a5462e5b MR |
392 | /* FIXME the calculations should be more precise */ |
393 | sglen_y = dma->sglen / 2; | |
394 | sglen_u = sglen_v = dma->sglen / 4 + 1; | |
395 | sglen_yu = sglen_y + sglen_u; | |
396 | size_y = size / 2; | |
397 | size_u = size_v = size / 4; | |
398 | } else { | |
399 | sglen_y = dma->sglen; | |
400 | size_y = size; | |
401 | } | |
402 | ||
403 | /* init DMA for Y channel */ | |
404 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y, | |
405 | 0, 0x28, size_y); | |
3bc43840 | 406 | |
a5462e5b MR |
407 | if (ret) { |
408 | dev_err(pcdev->dev, | |
409 | "DMA initialization for Y/RGB failed\n"); | |
3bc43840 GL |
410 | goto fail; |
411 | } | |
412 | ||
5aa2110f | 413 | if (pcdev->channels == 3) { |
a5462e5b MR |
414 | /* init DMA for U channel */ |
415 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u, | |
416 | sglen_y, 0x30, size_u); | |
417 | if (ret) { | |
418 | dev_err(pcdev->dev, | |
419 | "DMA initialization for U failed\n"); | |
420 | goto fail_u; | |
421 | } | |
422 | ||
423 | /* init DMA for V channel */ | |
424 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v, | |
425 | sglen_yu, 0x38, size_v); | |
426 | if (ret) { | |
427 | dev_err(pcdev->dev, | |
428 | "DMA initialization for V failed\n"); | |
429 | goto fail_v; | |
430 | } | |
3bc43840 | 431 | } |
3bc43840 GL |
432 | |
433 | vb->state = VIDEOBUF_PREPARED; | |
434 | } | |
435 | ||
436 | buf->inwork = 0; | |
a5462e5b | 437 | buf->active_dma = DMA_Y; |
5aa2110f | 438 | if (pcdev->channels == 3) |
a5462e5b | 439 | buf->active_dma |= DMA_U | DMA_V; |
3bc43840 GL |
440 | |
441 | return 0; | |
442 | ||
a5462e5b MR |
443 | fail_v: |
444 | dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size, | |
445 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); | |
446 | fail_u: | |
447 | dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size, | |
448 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); | |
3bc43840 GL |
449 | fail: |
450 | free_buffer(vq, buf); | |
451 | out: | |
452 | buf->inwork = 0; | |
453 | return ret; | |
454 | } | |
455 | ||
7102b773 GL |
456 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
457 | struct videobuf_buffer *vb) | |
3bc43840 GL |
458 | { |
459 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 460 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
461 | struct pxa_camera_dev *pcdev = ici->priv; |
462 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
7102b773 | 463 | struct pxa_buffer *active; |
3bc43840 | 464 | unsigned long flags; |
5aa2110f | 465 | int i; |
3bc43840 | 466 | |
7e28adb2 | 467 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
468 | vb, vb->baddr, vb->bsize); |
469 | spin_lock_irqsave(&pcdev->lock, flags); | |
470 | ||
471 | list_add_tail(&vb->queue, &pcdev->capture); | |
472 | ||
473 | vb->state = VIDEOBUF_ACTIVE; | |
7102b773 | 474 | active = pcdev->active; |
3bc43840 | 475 | |
7102b773 | 476 | if (!active) { |
5ca11fa3 EM |
477 | unsigned long cifr, cicr0; |
478 | ||
479 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
480 | __raw_writel(cifr, pcdev->base + CIFR); | |
a5462e5b | 481 | |
5aa2110f GL |
482 | for (i = 0; i < pcdev->channels; i++) { |
483 | DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma; | |
484 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
485 | pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1; | |
a5462e5b MR |
486 | } |
487 | ||
3bc43840 | 488 | pcdev->active = buf; |
5ca11fa3 EM |
489 | |
490 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
491 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3bc43840 | 492 | } else { |
a5462e5b MR |
493 | struct pxa_cam_dma *buf_dma; |
494 | struct pxa_cam_dma *act_dma; | |
a5462e5b | 495 | int nents; |
a5462e5b | 496 | |
e7c50688 | 497 | for (i = 0; i < pcdev->channels; i++) { |
a5462e5b MR |
498 | buf_dma = &buf->dmas[i]; |
499 | act_dma = &active->dmas[i]; | |
500 | nents = buf_dma->sglen; | |
501 | ||
502 | /* Stop DMA engine */ | |
503 | DCSR(pcdev->dma_chans[i]) = 0; | |
504 | ||
505 | /* Add the descriptors we just initialized to | |
506 | the currently running chain */ | |
5aa2110f GL |
507 | pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma; |
508 | pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1; | |
a5462e5b MR |
509 | |
510 | /* Setup a dummy descriptor with the DMA engines current | |
511 | * state | |
3bc43840 | 512 | */ |
a5462e5b MR |
513 | buf_dma->sg_cpu[nents].dsadr = |
514 | pcdev->res->start + 0x28 + i*8; /* CIBRx */ | |
515 | buf_dma->sg_cpu[nents].dtadr = | |
516 | DTADR(pcdev->dma_chans[i]); | |
517 | buf_dma->sg_cpu[nents].dcmd = | |
518 | DCMD(pcdev->dma_chans[i]); | |
519 | ||
520 | if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) { | |
521 | /* The DMA engine is on the last | |
522 | descriptor, set the next descriptors | |
523 | address to the descriptors we just | |
524 | initialized */ | |
525 | buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma; | |
526 | } else { | |
527 | buf_dma->sg_cpu[nents].ddadr = | |
528 | DDADR(pcdev->dma_chans[i]); | |
529 | } | |
530 | ||
531 | /* The next descriptor is the dummy descriptor */ | |
532 | DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents * | |
533 | sizeof(struct pxa_dma_desc); | |
534 | ||
535 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
3bc43840 | 536 | } |
3bc43840 GL |
537 | } |
538 | ||
539 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
3bc43840 GL |
540 | } |
541 | ||
542 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
543 | struct videobuf_buffer *vb) | |
544 | { | |
545 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
546 | #ifdef DEBUG | |
547 | struct soc_camera_device *icd = vq->priv_data; | |
548 | ||
7e28adb2 | 549 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
550 | vb, vb->baddr, vb->bsize); |
551 | ||
552 | switch (vb->state) { | |
553 | case VIDEOBUF_ACTIVE: | |
7e28adb2 | 554 | dev_dbg(&icd->dev, "%s (active)\n", __func__); |
3bc43840 GL |
555 | break; |
556 | case VIDEOBUF_QUEUED: | |
7e28adb2 | 557 | dev_dbg(&icd->dev, "%s (queued)\n", __func__); |
3bc43840 GL |
558 | break; |
559 | case VIDEOBUF_PREPARED: | |
7e28adb2 | 560 | dev_dbg(&icd->dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
561 | break; |
562 | default: | |
7e28adb2 | 563 | dev_dbg(&icd->dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
564 | break; |
565 | } | |
566 | #endif | |
567 | ||
568 | free_buffer(vq, buf); | |
569 | } | |
570 | ||
a5462e5b MR |
571 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
572 | struct videobuf_buffer *vb, | |
573 | struct pxa_buffer *buf) | |
574 | { | |
5ca11fa3 EM |
575 | unsigned long cicr0; |
576 | ||
a5462e5b MR |
577 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
578 | list_del_init(&vb->queue); | |
579 | vb->state = VIDEOBUF_DONE; | |
580 | do_gettimeofday(&vb->ts); | |
581 | vb->field_count++; | |
582 | wake_up(&vb->done); | |
583 | ||
584 | if (list_empty(&pcdev->capture)) { | |
585 | pcdev->active = NULL; | |
586 | DCSR(pcdev->dma_chans[0]) = 0; | |
587 | DCSR(pcdev->dma_chans[1]) = 0; | |
588 | DCSR(pcdev->dma_chans[2]) = 0; | |
5ca11fa3 EM |
589 | |
590 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
591 | __raw_writel(cicr0, pcdev->base + CICR0); | |
a5462e5b MR |
592 | return; |
593 | } | |
594 | ||
595 | pcdev->active = list_entry(pcdev->capture.next, | |
596 | struct pxa_buffer, vb.queue); | |
597 | } | |
598 | ||
599 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, | |
600 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 601 | { |
3bc43840 GL |
602 | struct pxa_buffer *buf; |
603 | unsigned long flags; | |
e7c50688 | 604 | u32 status, camera_status, overrun; |
3bc43840 | 605 | struct videobuf_buffer *vb; |
5ca11fa3 | 606 | unsigned long cifr, cicr0; |
3bc43840 GL |
607 | |
608 | spin_lock_irqsave(&pcdev->lock, flags); | |
609 | ||
a5462e5b MR |
610 | status = DCSR(channel); |
611 | DCSR(channel) = status | DCSR_ENDINTR; | |
7102b773 | 612 | |
3bc43840 | 613 | if (status & DCSR_BUSERR) { |
7102b773 | 614 | dev_err(pcdev->dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
615 | goto out; |
616 | } | |
617 | ||
618 | if (!(status & DCSR_ENDINTR)) { | |
7102b773 GL |
619 | dev_err(pcdev->dev, "Unknown DMA IRQ source, " |
620 | "status: 0x%08x\n", status); | |
3bc43840 GL |
621 | goto out; |
622 | } | |
623 | ||
3bc43840 | 624 | if (!pcdev->active) { |
7102b773 | 625 | dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n"); |
3bc43840 GL |
626 | goto out; |
627 | } | |
628 | ||
5ca11fa3 | 629 | camera_status = __raw_readl(pcdev->base + CISR); |
e7c50688 GL |
630 | overrun = CISR_IFO_0; |
631 | if (pcdev->channels == 3) | |
632 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
633 | if (camera_status & overrun) { | |
634 | dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status); | |
635 | /* Stop the Capture Interface */ | |
5ca11fa3 EM |
636 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; |
637 | __raw_writel(cicr0, pcdev->base + CICR0); | |
638 | ||
e7c50688 GL |
639 | /* Stop DMA */ |
640 | DCSR(channel) = 0; | |
641 | /* Reset the FIFOs */ | |
5ca11fa3 EM |
642 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; |
643 | __raw_writel(cifr, pcdev->base + CIFR); | |
e7c50688 | 644 | /* Enable End-Of-Frame Interrupt */ |
5ca11fa3 EM |
645 | cicr0 &= ~CICR0_EOFM; |
646 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 | 647 | /* Restart the Capture Interface */ |
5ca11fa3 | 648 | __raw_writel(cicr0 | CICR0_ENB, pcdev->base + CICR0); |
e7c50688 GL |
649 | goto out; |
650 | } | |
651 | ||
3bc43840 GL |
652 | vb = &pcdev->active->vb; |
653 | buf = container_of(vb, struct pxa_buffer, vb); | |
654 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
7e28adb2 | 655 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
656 | vb, vb->baddr, vb->bsize); |
657 | ||
a5462e5b MR |
658 | buf->active_dma &= ~act_dma; |
659 | if (!buf->active_dma) | |
660 | pxa_camera_wakeup(pcdev, vb, buf); | |
3bc43840 GL |
661 | |
662 | out: | |
663 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
664 | } | |
665 | ||
a5462e5b MR |
666 | static void pxa_camera_dma_irq_y(int channel, void *data) |
667 | { | |
668 | struct pxa_camera_dev *pcdev = data; | |
669 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
670 | } | |
671 | ||
672 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
673 | { | |
674 | struct pxa_camera_dev *pcdev = data; | |
675 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
676 | } | |
677 | ||
678 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
679 | { | |
680 | struct pxa_camera_dev *pcdev = data; | |
681 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
682 | } | |
683 | ||
7102b773 | 684 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
685 | .buf_setup = pxa_videobuf_setup, |
686 | .buf_prepare = pxa_videobuf_prepare, | |
687 | .buf_queue = pxa_videobuf_queue, | |
688 | .buf_release = pxa_videobuf_release, | |
689 | }; | |
690 | ||
a034d1b7 | 691 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
692 | struct soc_camera_device *icd) |
693 | { | |
a034d1b7 MD |
694 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
695 | struct pxa_camera_dev *pcdev = ici->priv; | |
696 | ||
092d3921 PZ |
697 | /* We must pass NULL as dev pointer, then all pci_* dma operations |
698 | * transform to normal dma_* ones. */ | |
a034d1b7 | 699 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 PZ |
700 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
701 | sizeof(struct pxa_buffer), icd); | |
702 | } | |
703 | ||
cf34cba7 | 704 | static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev) |
3bc43840 | 705 | { |
cf34cba7 GL |
706 | unsigned long mclk = pcdev->mclk; |
707 | u32 div; | |
3bc43840 GL |
708 | unsigned long lcdclk; |
709 | ||
cf34cba7 GL |
710 | lcdclk = clk_get_rate(pcdev->clk); |
711 | pcdev->ciclk = lcdclk; | |
3bc43840 | 712 | |
cf34cba7 GL |
713 | /* mclk <= ciclk / 4 (27.4.2) */ |
714 | if (mclk > lcdclk / 4) { | |
715 | mclk = lcdclk / 4; | |
716 | dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk); | |
717 | } | |
718 | ||
719 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
720 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 721 | |
cf34cba7 GL |
722 | /* If we're not supplying MCLK, leave it at 0 */ |
723 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
724 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 725 | |
cf34cba7 GL |
726 | dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, " |
727 | "divisor %u\n", lcdclk, mclk, div); | |
3bc43840 GL |
728 | |
729 | return div; | |
730 | } | |
731 | ||
cf34cba7 GL |
732 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
733 | unsigned long pclk) | |
734 | { | |
735 | /* We want a timeout > 1 pixel time, not ">=" */ | |
736 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
737 | ||
738 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
739 | } | |
740 | ||
7102b773 | 741 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 GL |
742 | { |
743 | struct pxacamera_platform_data *pdata = pcdev->pdata; | |
744 | u32 cicr4 = 0; | |
745 | ||
746 | dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n", | |
747 | pcdev, pdata); | |
748 | ||
749 | if (pdata && pdata->init) { | |
7e28adb2 | 750 | dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__); |
3bc43840 GL |
751 | pdata->init(pcdev->dev); |
752 | } | |
753 | ||
5ca11fa3 EM |
754 | /* disable all interrupts */ |
755 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
756 | |
757 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
758 | cicr4 |= CICR4_PCLK_EN; | |
759 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
760 | cicr4 |= CICR4_MCLK_EN; | |
761 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
762 | cicr4 |= CICR4_PCP; | |
763 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
764 | cicr4 |= CICR4_HSP; | |
765 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
766 | cicr4 |= CICR4_VSP; | |
767 | ||
cf34cba7 GL |
768 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
769 | ||
770 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
771 | /* Initialise the timeout under the assumption pclk = mclk */ | |
772 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
773 | else | |
774 | /* "Safe default" - 13MHz */ | |
775 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 GL |
776 | |
777 | clk_enable(pcdev->clk); | |
778 | } | |
779 | ||
7102b773 | 780 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 781 | { |
3bc43840 | 782 | clk_disable(pcdev->clk); |
3bc43840 GL |
783 | } |
784 | ||
785 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
786 | { | |
787 | struct pxa_camera_dev *pcdev = data; | |
5ca11fa3 | 788 | unsigned long status, cicr0; |
3bc43840 | 789 | |
5ca11fa3 EM |
790 | status = __raw_readl(pcdev->base + CISR); |
791 | dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 792 | |
e7c50688 GL |
793 | if (!status) |
794 | return IRQ_NONE; | |
795 | ||
5ca11fa3 | 796 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
797 | |
798 | if (status & CISR_EOF) { | |
799 | int i; | |
800 | for (i = 0; i < pcdev->channels; i++) { | |
801 | DDADR(pcdev->dma_chans[i]) = | |
802 | pcdev->active->dmas[i].sg_dma; | |
803 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
804 | } | |
5ca11fa3 EM |
805 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
806 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 GL |
807 | } |
808 | ||
3bc43840 GL |
809 | return IRQ_HANDLED; |
810 | } | |
811 | ||
1c3bb743 GL |
812 | /* |
813 | * The following two functions absolutely depend on the fact, that | |
814 | * there can be only one camera on PXA quick capture interface | |
815 | * Called with .video_lock held | |
816 | */ | |
7102b773 | 817 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 GL |
818 | { |
819 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
820 | struct pxa_camera_dev *pcdev = ici->priv; | |
821 | int ret; | |
822 | ||
3bc43840 GL |
823 | if (pcdev->icd) { |
824 | ret = -EBUSY; | |
825 | goto ebusy; | |
826 | } | |
827 | ||
828 | dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n", | |
829 | icd->devnum); | |
830 | ||
7102b773 | 831 | pxa_camera_activate(pcdev); |
3bc43840 GL |
832 | ret = icd->ops->init(icd); |
833 | ||
834 | if (!ret) | |
835 | pcdev->icd = icd; | |
836 | ||
837 | ebusy: | |
3bc43840 GL |
838 | return ret; |
839 | } | |
840 | ||
1c3bb743 | 841 | /* Called with .video_lock held */ |
7102b773 | 842 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 GL |
843 | { |
844 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
845 | struct pxa_camera_dev *pcdev = ici->priv; | |
846 | ||
847 | BUG_ON(icd != pcdev->icd); | |
848 | ||
849 | dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n", | |
850 | icd->devnum); | |
851 | ||
852 | /* disable capture, disable interrupts */ | |
5ca11fa3 | 853 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 854 | |
3bc43840 | 855 | /* Stop DMA engine */ |
a5462e5b MR |
856 | DCSR(pcdev->dma_chans[0]) = 0; |
857 | DCSR(pcdev->dma_chans[1]) = 0; | |
858 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 GL |
859 | |
860 | icd->ops->release(icd); | |
861 | ||
7102b773 | 862 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
863 | |
864 | pcdev->icd = NULL; | |
865 | } | |
866 | ||
ad5f2e85 GL |
867 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
868 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 869 | { |
ad5f2e85 GL |
870 | /* |
871 | * Platform specified synchronization and pixel clock polarities are | |
872 | * only a recommendation and are only used during probing. The PXA270 | |
873 | * quick capture interface supports both. | |
874 | */ | |
875 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
876 | SOCAM_MASTER : SOCAM_SLAVE) | | |
877 | SOCAM_HSYNC_ACTIVE_HIGH | | |
878 | SOCAM_HSYNC_ACTIVE_LOW | | |
879 | SOCAM_VSYNC_ACTIVE_HIGH | | |
880 | SOCAM_VSYNC_ACTIVE_LOW | | |
881 | SOCAM_PCLK_SAMPLE_RISING | | |
882 | SOCAM_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
883 | |
884 | /* If requested data width is supported by the platform, use it */ | |
ad5f2e85 | 885 | switch (buswidth) { |
3bc43840 | 886 | case 10: |
ad5f2e85 GL |
887 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)) |
888 | return -EINVAL; | |
889 | *flags |= SOCAM_DATAWIDTH_10; | |
3bc43840 GL |
890 | break; |
891 | case 9: | |
ad5f2e85 GL |
892 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)) |
893 | return -EINVAL; | |
894 | *flags |= SOCAM_DATAWIDTH_9; | |
3bc43840 GL |
895 | break; |
896 | case 8: | |
ad5f2e85 GL |
897 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) |
898 | return -EINVAL; | |
899 | *flags |= SOCAM_DATAWIDTH_8; | |
2a48fc73 RJ |
900 | break; |
901 | default: | |
902 | return -EINVAL; | |
3bc43840 | 903 | } |
ad5f2e85 GL |
904 | |
905 | return 0; | |
906 | } | |
907 | ||
908 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
909 | { | |
64f5905e | 910 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
911 | struct pxa_camera_dev *pcdev = ici->priv; |
912 | unsigned long dw, bpp, bus_flags, camera_flags, common_flags; | |
5ca11fa3 | 913 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0; |
ad5f2e85 GL |
914 | int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); |
915 | ||
916 | if (ret < 0) | |
917 | return ret; | |
918 | ||
919 | camera_flags = icd->ops->query_bus_param(icd); | |
920 | ||
921 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
922 | if (!common_flags) | |
3bc43840 GL |
923 | return -EINVAL; |
924 | ||
e7c50688 GL |
925 | pcdev->channels = 1; |
926 | ||
ad5f2e85 GL |
927 | /* Make choises, based on platform preferences */ |
928 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
929 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
930 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
931 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
932 | else | |
933 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
934 | } | |
935 | ||
936 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
937 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
938 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
939 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
940 | else | |
941 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
942 | } | |
943 | ||
944 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
945 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
946 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
947 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
948 | else | |
949 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
950 | } | |
951 | ||
952 | ret = icd->ops->set_bus_param(icd, common_flags); | |
3bc43840 GL |
953 | if (ret < 0) |
954 | return ret; | |
955 | ||
956 | /* Datawidth is now guaranteed to be equal to one of the three values. | |
957 | * We fix bit-per-pixel equal to data-width... */ | |
ad5f2e85 GL |
958 | switch (common_flags & SOCAM_DATAWIDTH_MASK) { |
959 | case SOCAM_DATAWIDTH_10: | |
3bc43840 GL |
960 | dw = 4; |
961 | bpp = 0x40; | |
962 | break; | |
ad5f2e85 | 963 | case SOCAM_DATAWIDTH_9: |
3bc43840 GL |
964 | dw = 3; |
965 | bpp = 0x20; | |
966 | break; | |
967 | default: | |
968 | /* Actually it can only be 8 now, | |
969 | * default is just to silence compiler warnings */ | |
ad5f2e85 | 970 | case SOCAM_DATAWIDTH_8: |
3bc43840 GL |
971 | dw = 2; |
972 | bpp = 0; | |
973 | } | |
974 | ||
975 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
976 | cicr4 |= CICR4_PCLK_EN; | |
977 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
978 | cicr4 |= CICR4_MCLK_EN; | |
ad5f2e85 | 979 | if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) |
3bc43840 | 980 | cicr4 |= CICR4_PCP; |
ad5f2e85 | 981 | if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) |
3bc43840 | 982 | cicr4 |= CICR4_HSP; |
ad5f2e85 | 983 | if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
984 | cicr4 |= CICR4_VSP; |
985 | ||
5ca11fa3 | 986 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 987 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 988 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b MR |
989 | |
990 | cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw; | |
991 | ||
992 | switch (pixfmt) { | |
993 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 994 | pcdev->channels = 3; |
a5462e5b | 995 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
996 | /* |
997 | * Normally, pxa bus wants as input UYVY format. We allow all | |
998 | * reorderings of the YUV422 format, as no processing is done, | |
999 | * and the YUV stream is just passed through without any | |
1000 | * transformation. Note that UYVY is the only format that | |
1001 | * should be used if pxa framebuffer Overlay2 is used. | |
1002 | */ | |
1003 | case V4L2_PIX_FMT_UYVY: | |
1004 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1005 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1006 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1007 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1008 | break; | |
1009 | case V4L2_PIX_FMT_RGB555: | |
1010 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1011 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1012 | break; | |
1013 | case V4L2_PIX_FMT_RGB565: | |
1014 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1015 | break; | |
1016 | } | |
1017 | ||
5ca11fa3 EM |
1018 | cicr2 = 0; |
1019 | cicr3 = CICR3_LPF_VAL(icd->height - 1) | | |
3bc43840 | 1020 | CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top)); |
cf34cba7 | 1021 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1022 | |
1023 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1024 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1025 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1026 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1027 | |
1028 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1029 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1030 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1031 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1032 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3bc43840 GL |
1033 | |
1034 | return 0; | |
1035 | } | |
1036 | ||
2a48fc73 RJ |
1037 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1038 | unsigned char buswidth) | |
ad5f2e85 | 1039 | { |
cf34cba7 | 1040 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
1041 | struct pxa_camera_dev *pcdev = ici->priv; |
1042 | unsigned long bus_flags, camera_flags; | |
2a48fc73 | 1043 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1044 | |
1045 | if (ret < 0) | |
1046 | return ret; | |
1047 | ||
1048 | camera_flags = icd->ops->query_bus_param(icd); | |
1049 | ||
1050 | return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; | |
1051 | } | |
1052 | ||
2a48fc73 RJ |
1053 | static const struct soc_camera_data_format pxa_camera_formats[] = { |
1054 | { | |
1055 | .name = "Planar YUV422 16 bit", | |
1056 | .depth = 16, | |
1057 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
1058 | .colorspace = V4L2_COLORSPACE_JPEG, | |
1059 | }, | |
1060 | }; | |
1061 | ||
1062 | static bool buswidth_supported(struct soc_camera_device *icd, int depth) | |
ad5f2e85 | 1063 | { |
2a48fc73 RJ |
1064 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1065 | struct pxa_camera_dev *pcdev = ici->priv; | |
1066 | ||
1067 | switch (depth) { | |
1068 | case 8: | |
1069 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8); | |
1070 | case 9: | |
1071 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9); | |
1072 | case 10: | |
1073 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10); | |
1074 | } | |
1075 | return false; | |
ad5f2e85 GL |
1076 | } |
1077 | ||
2a48fc73 | 1078 | static int required_buswidth(const struct soc_camera_data_format *fmt) |
3bc43840 | 1079 | { |
2a48fc73 RJ |
1080 | switch (fmt->fourcc) { |
1081 | case V4L2_PIX_FMT_UYVY: | |
1082 | case V4L2_PIX_FMT_VYUY: | |
1083 | case V4L2_PIX_FMT_YUYV: | |
1084 | case V4L2_PIX_FMT_YVYU: | |
1085 | case V4L2_PIX_FMT_RGB565: | |
1086 | case V4L2_PIX_FMT_RGB555: | |
1087 | return 8; | |
1088 | default: | |
1089 | return fmt->depth; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, | |
1094 | struct soc_camera_format_xlate *xlate) | |
1095 | { | |
1096 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1097 | int formats = 0, buswidth, ret; | |
1098 | ||
1099 | buswidth = required_buswidth(icd->formats + idx); | |
1100 | ||
1101 | if (!buswidth_supported(icd, buswidth)) | |
1102 | return 0; | |
3bc43840 | 1103 | |
2a48fc73 RJ |
1104 | ret = pxa_camera_try_bus_param(icd, buswidth); |
1105 | if (ret < 0) | |
1106 | return 0; | |
1107 | ||
1108 | switch (icd->formats[idx].fourcc) { | |
1109 | case V4L2_PIX_FMT_UYVY: | |
1110 | formats++; | |
1111 | if (xlate) { | |
1112 | xlate->host_fmt = &pxa_camera_formats[0]; | |
1113 | xlate->cam_fmt = icd->formats + idx; | |
1114 | xlate->buswidth = buswidth; | |
1115 | xlate++; | |
1116 | dev_dbg(&ici->dev, "Providing format %s using %s\n", | |
1117 | pxa_camera_formats[0].name, | |
1118 | icd->formats[idx].name); | |
1119 | } | |
1120 | case V4L2_PIX_FMT_VYUY: | |
1121 | case V4L2_PIX_FMT_YUYV: | |
1122 | case V4L2_PIX_FMT_YVYU: | |
1123 | case V4L2_PIX_FMT_RGB565: | |
1124 | case V4L2_PIX_FMT_RGB555: | |
1125 | formats++; | |
1126 | if (xlate) { | |
1127 | xlate->host_fmt = icd->formats + idx; | |
1128 | xlate->cam_fmt = icd->formats + idx; | |
1129 | xlate->buswidth = buswidth; | |
1130 | xlate++; | |
1131 | dev_dbg(&ici->dev, "Providing format %s packed\n", | |
1132 | icd->formats[idx].name); | |
1133 | } | |
1134 | break; | |
1135 | default: | |
1136 | /* Generic pass-through */ | |
1137 | formats++; | |
1138 | if (xlate) { | |
1139 | xlate->host_fmt = icd->formats + idx; | |
1140 | xlate->cam_fmt = icd->formats + idx; | |
1141 | xlate->buswidth = icd->formats[idx].depth; | |
1142 | xlate++; | |
1143 | dev_dbg(&ici->dev, | |
1144 | "Providing format %s in pass-through mode\n", | |
1145 | icd->formats[idx].name); | |
1146 | } | |
1147 | } | |
1148 | ||
1149 | return formats; | |
1150 | } | |
1151 | ||
d8fac217 GL |
1152 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
1153 | __u32 pixfmt, struct v4l2_rect *rect) | |
ad5f2e85 | 1154 | { |
2a48fc73 | 1155 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
cf34cba7 | 1156 | struct pxa_camera_dev *pcdev = ici->priv; |
0ad675eb GL |
1157 | const struct soc_camera_data_format *cam_fmt = NULL; |
1158 | const struct soc_camera_format_xlate *xlate = NULL; | |
cf34cba7 GL |
1159 | struct soc_camera_sense sense = { |
1160 | .master_clock = pcdev->mclk, | |
1161 | .pixel_clock_max = pcdev->ciclk / 4, | |
1162 | }; | |
0ad675eb | 1163 | int ret; |
25c4d74e | 1164 | |
0ad675eb GL |
1165 | if (pixfmt) { |
1166 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | |
1167 | if (!xlate) { | |
1168 | dev_warn(&ici->dev, "Format %x not found\n", pixfmt); | |
1169 | return -EINVAL; | |
1170 | } | |
25c4d74e | 1171 | |
0ad675eb GL |
1172 | cam_fmt = xlate->cam_fmt; |
1173 | } | |
2a48fc73 | 1174 | |
cf34cba7 GL |
1175 | /* If PCLK is used to latch data from the sensor, check sense */ |
1176 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1177 | icd->sense = &sense; | |
1178 | ||
2a48fc73 RJ |
1179 | switch (pixfmt) { |
1180 | case 0: /* Only geometry change */ | |
1181 | ret = icd->ops->set_fmt(icd, pixfmt, rect); | |
1182 | break; | |
1183 | default: | |
1184 | ret = icd->ops->set_fmt(icd, cam_fmt->fourcc, rect); | |
1185 | } | |
1186 | ||
cf34cba7 GL |
1187 | icd->sense = NULL; |
1188 | ||
1189 | if (ret < 0) { | |
2a48fc73 RJ |
1190 | dev_warn(&ici->dev, "Failed to configure for format %x\n", |
1191 | pixfmt); | |
cf34cba7 GL |
1192 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1193 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
1194 | dev_err(&ici->dev, | |
1195 | "pixel clock %lu set by the camera too high!", | |
1196 | sense.pixel_clock); | |
1197 | return -EIO; | |
1198 | } | |
1199 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1200 | } | |
2a48fc73 RJ |
1201 | |
1202 | if (pixfmt && !ret) { | |
0ad675eb GL |
1203 | icd->buswidth = xlate->buswidth; |
1204 | icd->current_fmt = xlate->host_fmt; | |
2a48fc73 | 1205 | } |
25c4d74e GL |
1206 | |
1207 | return ret; | |
ad5f2e85 GL |
1208 | } |
1209 | ||
d8fac217 GL |
1210 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1211 | struct v4l2_format *f) | |
3bc43840 | 1212 | { |
2a48fc73 RJ |
1213 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1214 | const struct soc_camera_format_xlate *xlate; | |
1215 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1216 | __u32 pixfmt = pix->pixelformat; | |
06daa1af | 1217 | enum v4l2_field field; |
bf507158 | 1218 | int ret; |
a2c8c68c | 1219 | |
2a48fc73 RJ |
1220 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1221 | if (!xlate) { | |
1222 | dev_warn(&ici->dev, "Format %x not found\n", pixfmt); | |
25c4d74e | 1223 | return -EINVAL; |
2a48fc73 | 1224 | } |
25c4d74e | 1225 | |
3bc43840 | 1226 | /* limit to pxa hardware capabilities */ |
2a48fc73 RJ |
1227 | if (pix->height < 32) |
1228 | pix->height = 32; | |
1229 | if (pix->height > 2048) | |
1230 | pix->height = 2048; | |
1231 | if (pix->width < 48) | |
1232 | pix->width = 48; | |
1233 | if (pix->width > 2048) | |
1234 | pix->width = 2048; | |
1235 | pix->width &= ~0x01; | |
1236 | ||
1237 | pix->bytesperline = pix->width * | |
1238 | DIV_ROUND_UP(xlate->host_fmt->depth, 8); | |
1239 | pix->sizeimage = pix->height * pix->bytesperline; | |
25c4d74e | 1240 | |
bf507158 GL |
1241 | /* camera has to see its format, but the user the original one */ |
1242 | pix->pixelformat = xlate->cam_fmt->fourcc; | |
ad5f2e85 | 1243 | /* limit to sensor capabilities */ |
bf507158 GL |
1244 | ret = icd->ops->try_fmt(icd, f); |
1245 | pix->pixelformat = xlate->host_fmt->fourcc; | |
1246 | ||
06daa1af GL |
1247 | field = pix->field; |
1248 | ||
1249 | if (field == V4L2_FIELD_ANY) { | |
1250 | pix->field = V4L2_FIELD_NONE; | |
1251 | } else if (field != V4L2_FIELD_NONE) { | |
1252 | dev_err(&icd->dev, "Field type %d unsupported.\n", field); | |
1253 | return -EINVAL; | |
1254 | } | |
1255 | ||
bf507158 | 1256 | return ret; |
3bc43840 GL |
1257 | } |
1258 | ||
7102b773 GL |
1259 | static int pxa_camera_reqbufs(struct soc_camera_file *icf, |
1260 | struct v4l2_requestbuffers *p) | |
3bc43840 GL |
1261 | { |
1262 | int i; | |
1263 | ||
1264 | /* This is for locking debugging only. I removed spinlocks and now I | |
1265 | * check whether .prepare is ever called on a linked buffer, or whether | |
1266 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
1267 | * it hadn't triggered */ | |
1268 | for (i = 0; i < p->count; i++) { | |
1269 | struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i], | |
1270 | struct pxa_buffer, vb); | |
1271 | buf->inwork = 0; | |
1272 | INIT_LIST_HEAD(&buf->vb.queue); | |
1273 | } | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
7102b773 | 1278 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 GL |
1279 | { |
1280 | struct soc_camera_file *icf = file->private_data; | |
1281 | struct pxa_buffer *buf; | |
1282 | ||
1283 | buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer, | |
1284 | vb.stream); | |
1285 | ||
1286 | poll_wait(file, &buf->vb.done, pt); | |
1287 | ||
1288 | if (buf->vb.state == VIDEOBUF_DONE || | |
1289 | buf->vb.state == VIDEOBUF_ERROR) | |
1290 | return POLLIN|POLLRDNORM; | |
1291 | ||
1292 | return 0; | |
1293 | } | |
1294 | ||
7102b773 GL |
1295 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1296 | struct v4l2_capability *cap) | |
3bc43840 GL |
1297 | { |
1298 | /* cap->name is set by the firendly caller:-> */ | |
1299 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
1300 | cap->version = PXA_CAM_VERSION_CODE; | |
1301 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
3f6ac497 RJ |
1306 | static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) |
1307 | { | |
64f5905e | 1308 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1309 | struct pxa_camera_dev *pcdev = ici->priv; |
1310 | int i = 0, ret = 0; | |
1311 | ||
5ca11fa3 EM |
1312 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1313 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1314 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1315 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1316 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 RJ |
1317 | |
1318 | if ((pcdev->icd) && (pcdev->icd->ops->suspend)) | |
1319 | ret = pcdev->icd->ops->suspend(pcdev->icd, state); | |
1320 | ||
1321 | return ret; | |
1322 | } | |
1323 | ||
1324 | static int pxa_camera_resume(struct soc_camera_device *icd) | |
1325 | { | |
64f5905e | 1326 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1327 | struct pxa_camera_dev *pcdev = ici->priv; |
1328 | int i = 0, ret = 0; | |
1329 | ||
87f3dd77 EM |
1330 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1331 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1332 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1333 | |
5ca11fa3 EM |
1334 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1335 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1336 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1337 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1338 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 RJ |
1339 | |
1340 | if ((pcdev->icd) && (pcdev->icd->ops->resume)) | |
1341 | ret = pcdev->icd->ops->resume(pcdev->icd); | |
1342 | ||
1343 | /* Restart frame capture if active buffer exists */ | |
1344 | if (!ret && pcdev->active) { | |
5ca11fa3 EM |
1345 | unsigned long cifr, cicr0; |
1346 | ||
3f6ac497 | 1347 | /* Reset the FIFOs */ |
5ca11fa3 EM |
1348 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; |
1349 | __raw_writel(cifr, pcdev->base + CIFR); | |
1350 | ||
1351 | cicr0 = __raw_readl(pcdev->base + CICR0); | |
1352 | cicr0 &= ~CICR0_EOFM; /* Enable End-Of-Frame Interrupt */ | |
1353 | cicr0 |= CICR0_ENB; /* Restart the Capture Interface */ | |
1354 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3f6ac497 RJ |
1355 | } |
1356 | ||
1357 | return ret; | |
1358 | } | |
1359 | ||
b8d9904c GL |
1360 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1361 | .owner = THIS_MODULE, | |
1362 | .add = pxa_camera_add_device, | |
1363 | .remove = pxa_camera_remove_device, | |
3f6ac497 RJ |
1364 | .suspend = pxa_camera_suspend, |
1365 | .resume = pxa_camera_resume, | |
2a48fc73 | 1366 | .get_formats = pxa_camera_get_formats, |
d8fac217 GL |
1367 | .set_fmt = pxa_camera_set_fmt, |
1368 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1369 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1370 | .reqbufs = pxa_camera_reqbufs, |
1371 | .poll = pxa_camera_poll, | |
1372 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1373 | .set_bus_param = pxa_camera_set_bus_param, |
1374 | }; | |
1375 | ||
1376 | /* Should be allocated dynamically too, but we have only one. */ | |
3bc43840 GL |
1377 | static struct soc_camera_host pxa_soc_camera_host = { |
1378 | .drv_name = PXA_CAM_DRV_NAME, | |
b8d9904c | 1379 | .ops = &pxa_soc_camera_host_ops, |
3bc43840 GL |
1380 | }; |
1381 | ||
1382 | static int pxa_camera_probe(struct platform_device *pdev) | |
1383 | { | |
1384 | struct pxa_camera_dev *pcdev; | |
1385 | struct resource *res; | |
1386 | void __iomem *base; | |
02da4659 | 1387 | int irq; |
3bc43840 GL |
1388 | int err = 0; |
1389 | ||
1390 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1391 | irq = platform_get_irq(pdev, 0); | |
02da4659 | 1392 | if (!res || irq < 0) { |
3bc43840 GL |
1393 | err = -ENODEV; |
1394 | goto exit; | |
1395 | } | |
1396 | ||
1397 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
1398 | if (!pcdev) { | |
7102b773 | 1399 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
3bc43840 GL |
1400 | err = -ENOMEM; |
1401 | goto exit; | |
1402 | } | |
1403 | ||
e0d8b13a | 1404 | pcdev->clk = clk_get(&pdev->dev, NULL); |
3bc43840 GL |
1405 | if (IS_ERR(pcdev->clk)) { |
1406 | err = PTR_ERR(pcdev->clk); | |
1407 | goto exit_kfree; | |
1408 | } | |
1409 | ||
1410 | dev_set_drvdata(&pdev->dev, pcdev); | |
1411 | pcdev->res = res; | |
1412 | ||
1413 | pcdev->pdata = pdev->dev.platform_data; | |
1414 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
1415 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1416 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
3bc43840 GL |
1417 | /* Platform hasn't set available data widths. This is bad. |
1418 | * Warn and use a default. */ | |
1419 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " | |
1420 | "data widths, using default 10 bit\n"); | |
1421 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1422 | } | |
cf34cba7 GL |
1423 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; |
1424 | if (!pcdev->mclk) { | |
3bc43840 | 1425 | dev_warn(&pdev->dev, |
cf34cba7 | 1426 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1427 | "Using default 20MHz\n"); |
cf34cba7 | 1428 | pcdev->mclk = 20000000; |
3bc43840 GL |
1429 | } |
1430 | ||
cf34cba7 GL |
1431 | pcdev->dev = &pdev->dev; |
1432 | pcdev->mclk_divisor = mclk_get_divisor(pcdev); | |
1433 | ||
3bc43840 GL |
1434 | INIT_LIST_HEAD(&pcdev->capture); |
1435 | spin_lock_init(&pcdev->lock); | |
1436 | ||
1437 | /* | |
1438 | * Request the regions. | |
1439 | */ | |
1440 | if (!request_mem_region(res->start, res->end - res->start + 1, | |
1441 | PXA_CAM_DRV_NAME)) { | |
1442 | err = -EBUSY; | |
1443 | goto exit_clk; | |
1444 | } | |
1445 | ||
1446 | base = ioremap(res->start, res->end - res->start + 1); | |
1447 | if (!base) { | |
1448 | err = -ENOMEM; | |
1449 | goto exit_release; | |
1450 | } | |
1451 | pcdev->irq = irq; | |
1452 | pcdev->base = base; | |
3bc43840 GL |
1453 | |
1454 | /* request dma */ | |
de3e3b82 | 1455 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1456 | pxa_camera_dma_irq_y, pcdev); | |
1457 | if (err < 0) { | |
3bc43840 | 1458 | dev_err(pcdev->dev, "Can't request DMA for Y\n"); |
3bc43840 GL |
1459 | goto exit_iounmap; |
1460 | } | |
de3e3b82 | 1461 | pcdev->dma_chans[0] = err; |
a5462e5b MR |
1462 | dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
1463 | ||
de3e3b82 | 1464 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1465 | pxa_camera_dma_irq_u, pcdev); | |
1466 | if (err < 0) { | |
a5462e5b | 1467 | dev_err(pcdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1468 | goto exit_free_dma_y; |
1469 | } | |
de3e3b82 | 1470 | pcdev->dma_chans[1] = err; |
a5462e5b MR |
1471 | dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
1472 | ||
de3e3b82 | 1473 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1474 | pxa_camera_dma_irq_v, pcdev); | |
1475 | if (err < 0) { | |
a5462e5b | 1476 | dev_err(pcdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1477 | goto exit_free_dma_u; |
1478 | } | |
de3e3b82 | 1479 | pcdev->dma_chans[2] = err; |
a5462e5b | 1480 | dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1481 | |
87f3dd77 EM |
1482 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1483 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1484 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1485 | |
1486 | /* request irq */ | |
1487 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | |
1488 | pcdev); | |
1489 | if (err) { | |
1490 | dev_err(pcdev->dev, "Camera interrupt register failed \n"); | |
1491 | goto exit_free_dma; | |
1492 | } | |
1493 | ||
1494 | pxa_soc_camera_host.priv = pcdev; | |
1495 | pxa_soc_camera_host.dev.parent = &pdev->dev; | |
1496 | pxa_soc_camera_host.nr = pdev->id; | |
b8d9904c | 1497 | err = soc_camera_host_register(&pxa_soc_camera_host); |
3bc43840 GL |
1498 | if (err) |
1499 | goto exit_free_irq; | |
1500 | ||
1501 | return 0; | |
1502 | ||
1503 | exit_free_irq: | |
1504 | free_irq(pcdev->irq, pcdev); | |
1505 | exit_free_dma: | |
a5462e5b MR |
1506 | pxa_free_dma(pcdev->dma_chans[2]); |
1507 | exit_free_dma_u: | |
1508 | pxa_free_dma(pcdev->dma_chans[1]); | |
1509 | exit_free_dma_y: | |
1510 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1511 | exit_iounmap: |
1512 | iounmap(base); | |
1513 | exit_release: | |
1514 | release_mem_region(res->start, res->end - res->start + 1); | |
1515 | exit_clk: | |
1516 | clk_put(pcdev->clk); | |
1517 | exit_kfree: | |
1518 | kfree(pcdev); | |
1519 | exit: | |
1520 | return err; | |
1521 | } | |
1522 | ||
1523 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | |
1524 | { | |
1525 | struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev); | |
1526 | struct resource *res; | |
1527 | ||
1528 | clk_put(pcdev->clk); | |
1529 | ||
a5462e5b MR |
1530 | pxa_free_dma(pcdev->dma_chans[0]); |
1531 | pxa_free_dma(pcdev->dma_chans[1]); | |
1532 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 GL |
1533 | free_irq(pcdev->irq, pcdev); |
1534 | ||
1535 | soc_camera_host_unregister(&pxa_soc_camera_host); | |
1536 | ||
1537 | iounmap(pcdev->base); | |
1538 | ||
1539 | res = pcdev->res; | |
1540 | release_mem_region(res->start, res->end - res->start + 1); | |
1541 | ||
1542 | kfree(pcdev); | |
1543 | ||
7102b773 | 1544 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1545 | |
3bc43840 GL |
1546 | return 0; |
1547 | } | |
1548 | ||
3bc43840 GL |
1549 | static struct platform_driver pxa_camera_driver = { |
1550 | .driver = { | |
1551 | .name = PXA_CAM_DRV_NAME, | |
1552 | }, | |
1553 | .probe = pxa_camera_probe, | |
1554 | .remove = __exit_p(pxa_camera_remove), | |
3bc43840 GL |
1555 | }; |
1556 | ||
1557 | ||
1558 | static int __devinit pxa_camera_init(void) | |
1559 | { | |
1560 | return platform_driver_register(&pxa_camera_driver); | |
1561 | } | |
1562 | ||
1563 | static void __exit pxa_camera_exit(void) | |
1564 | { | |
01c1e4ca | 1565 | platform_driver_unregister(&pxa_camera_driver); |
3bc43840 GL |
1566 | } |
1567 | ||
1568 | module_init(pxa_camera_init); | |
1569 | module_exit(pxa_camera_exit); | |
1570 | ||
1571 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1572 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1573 | MODULE_LICENSE("GPL"); |