Commit | Line | Data |
---|---|---|
4f67130a GL |
1 | /* |
2 | * V4L2 Driver for i.MX3x camera host | |
3 | * | |
4 | * Copyright (C) 2008 | |
5 | * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
4f67130a GL |
14 | #include <linux/videodev2.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/vmalloc.h> | |
18 | #include <linux/interrupt.h> | |
f39c1ab3 | 19 | #include <linux/sched.h> |
4f67130a GL |
20 | |
21 | #include <media/v4l2-common.h> | |
22 | #include <media/v4l2-dev.h> | |
379fa5d3 | 23 | #include <media/videobuf2-dma-contig.h> |
4f67130a | 24 | #include <media/soc_camera.h> |
760697be | 25 | #include <media/soc_mediabus.h> |
4f67130a GL |
26 | |
27 | #include <mach/ipu.h> | |
28 | #include <mach/mx3_camera.h> | |
a8de6635 | 29 | #include <mach/dma.h> |
4f67130a GL |
30 | |
31 | #define MX3_CAM_DRV_NAME "mx3-camera" | |
32 | ||
33 | /* CMOS Sensor Interface Registers */ | |
34 | #define CSI_REG_START 0x60 | |
35 | ||
36 | #define CSI_SENS_CONF (0x60 - CSI_REG_START) | |
37 | #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START) | |
38 | #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START) | |
39 | #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START) | |
40 | #define CSI_TST_CTRL (0x70 - CSI_REG_START) | |
41 | #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START) | |
42 | #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START) | |
43 | #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START) | |
44 | #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START) | |
45 | #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START) | |
46 | ||
47 | #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0 | |
48 | #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1 | |
49 | #define CSI_SENS_CONF_DATA_POL_SHIFT 2 | |
50 | #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3 | |
51 | #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4 | |
52 | #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7 | |
53 | #define CSI_SENS_CONF_DATA_FMT_SHIFT 8 | |
54 | #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10 | |
55 | #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15 | |
56 | #define CSI_SENS_CONF_DIVRATIO_SHIFT 16 | |
57 | ||
58 | #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
59 | #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
60 | #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
61 | ||
62 | #define MAX_VIDEO_MEM 16 | |
63 | ||
379fa5d3 GL |
64 | enum csi_buffer_state { |
65 | CSI_BUF_NEEDS_INIT, | |
66 | CSI_BUF_PREPARED, | |
67 | }; | |
68 | ||
4f67130a GL |
69 | struct mx3_camera_buffer { |
70 | /* common v4l buffer stuff -- must be first */ | |
379fa5d3 GL |
71 | struct vb2_buffer vb; |
72 | enum csi_buffer_state state; | |
73 | struct list_head queue; | |
4f67130a GL |
74 | |
75 | /* One descriptot per scatterlist (per frame) */ | |
76 | struct dma_async_tx_descriptor *txd; | |
77 | ||
78 | /* We have to "build" a scatterlist ourselves - one element per frame */ | |
79 | struct scatterlist sg; | |
80 | }; | |
81 | ||
82 | /** | |
83 | * struct mx3_camera_dev - i.MX3x camera (CSI) object | |
84 | * @dev: camera device, to which the coherent buffer is attached | |
85 | * @icd: currently attached camera sensor | |
86 | * @clk: pointer to clock | |
87 | * @base: remapped register base address | |
88 | * @pdata: platform data | |
89 | * @platform_flags: platform flags | |
90 | * @mclk: master clock frequency in Hz | |
91 | * @capture: list of capture videobuffers | |
92 | * @lock: protects video buffer lists | |
93 | * @active: active video buffer | |
94 | * @idmac_channel: array of pointers to IPU DMAC DMA channels | |
95 | * @soc_host: embedded soc_host object | |
96 | */ | |
97 | struct mx3_camera_dev { | |
4f67130a GL |
98 | /* |
99 | * i.MX3x is only supposed to handle one camera on its Camera Sensor | |
100 | * Interface. If anyone ever builds hardware to enable more than one | |
101 | * camera _simultaneously_, they will have to modify this driver too | |
102 | */ | |
103 | struct soc_camera_device *icd; | |
104 | struct clk *clk; | |
105 | ||
106 | void __iomem *base; | |
107 | ||
108 | struct mx3_camera_pdata *pdata; | |
109 | ||
110 | unsigned long platform_flags; | |
111 | unsigned long mclk; | |
112 | ||
113 | struct list_head capture; | |
114 | spinlock_t lock; /* Protects video buffer lists */ | |
115 | struct mx3_camera_buffer *active; | |
379fa5d3 GL |
116 | struct vb2_alloc_ctx *alloc_ctx; |
117 | enum v4l2_field field; | |
118 | int sequence; | |
4f67130a GL |
119 | |
120 | /* IDMAC / dmaengine interface */ | |
121 | struct idmac_channel *idmac_channel[1]; /* We need one channel */ | |
122 | ||
123 | struct soc_camera_host soc_host; | |
124 | }; | |
125 | ||
126 | struct dma_chan_request { | |
127 | struct mx3_camera_dev *mx3_cam; | |
128 | enum ipu_channel id; | |
129 | }; | |
130 | ||
4f67130a GL |
131 | static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg) |
132 | { | |
133 | return __raw_readl(mx3->base + reg); | |
134 | } | |
135 | ||
136 | static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg) | |
137 | { | |
138 | __raw_writel(value, mx3->base + reg); | |
139 | } | |
140 | ||
379fa5d3 GL |
141 | static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb) |
142 | { | |
143 | return container_of(vb, struct mx3_camera_buffer, vb); | |
144 | } | |
145 | ||
4f67130a GL |
146 | /* Called from the IPU IDMAC ISR */ |
147 | static void mx3_cam_dma_done(void *arg) | |
148 | { | |
149 | struct idmac_tx_desc *desc = to_tx_desc(arg); | |
150 | struct dma_chan *chan = desc->txd.chan; | |
151 | struct idmac_channel *ichannel = to_idmac_chan(chan); | |
152 | struct mx3_camera_dev *mx3_cam = ichannel->client; | |
4f67130a GL |
153 | |
154 | dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n", | |
155 | desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0); | |
156 | ||
157 | spin_lock(&mx3_cam->lock); | |
158 | if (mx3_cam->active) { | |
379fa5d3 GL |
159 | struct vb2_buffer *vb = &mx3_cam->active->vb; |
160 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); | |
161 | ||
162 | list_del_init(&buf->queue); | |
163 | do_gettimeofday(&vb->v4l2_buf.timestamp); | |
164 | vb->v4l2_buf.field = mx3_cam->field; | |
165 | vb->v4l2_buf.sequence = mx3_cam->sequence++; | |
166 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
4f67130a GL |
167 | } |
168 | ||
169 | if (list_empty(&mx3_cam->capture)) { | |
170 | mx3_cam->active = NULL; | |
171 | spin_unlock(&mx3_cam->lock); | |
172 | ||
173 | /* | |
174 | * stop capture - without further buffers IPU_CHA_BUF0_RDY will | |
175 | * not get updated | |
176 | */ | |
177 | return; | |
178 | } | |
179 | ||
180 | mx3_cam->active = list_entry(mx3_cam->capture.next, | |
379fa5d3 | 181 | struct mx3_camera_buffer, queue); |
4f67130a GL |
182 | spin_unlock(&mx3_cam->lock); |
183 | } | |
184 | ||
4f67130a GL |
185 | /* |
186 | * Videobuf operations | |
187 | */ | |
188 | ||
189 | /* | |
190 | * Calculate the __buffer__ (not data) size and number of buffers. | |
4f67130a | 191 | */ |
379fa5d3 GL |
192 | static int mx3_videobuf_setup(struct vb2_queue *vq, |
193 | unsigned int *count, unsigned int *num_planes, | |
194 | unsigned long sizes[], void *alloc_ctxs[]) | |
4f67130a | 195 | { |
379fa5d3 | 196 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); |
4f67130a GL |
197 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
198 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
760697be GL |
199 | int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, |
200 | icd->current_fmt->host_fmt); | |
201 | ||
202 | if (bytes_per_line < 0) | |
203 | return bytes_per_line; | |
4f67130a GL |
204 | |
205 | if (!mx3_cam->idmac_channel[0]) | |
206 | return -EINVAL; | |
207 | ||
379fa5d3 GL |
208 | *num_planes = 1; |
209 | ||
210 | mx3_cam->sequence = 0; | |
211 | sizes[0] = bytes_per_line * icd->user_height; | |
212 | alloc_ctxs[0] = mx3_cam->alloc_ctx; | |
4f67130a GL |
213 | |
214 | if (!*count) | |
215 | *count = 32; | |
216 | ||
379fa5d3 GL |
217 | if (sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024) |
218 | *count = MAX_VIDEO_MEM * 1024 * 1024 / sizes[0]; | |
4f67130a GL |
219 | |
220 | return 0; | |
221 | } | |
222 | ||
379fa5d3 | 223 | static int mx3_videobuf_prepare(struct vb2_buffer *vb) |
4f67130a | 224 | { |
379fa5d3 | 225 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
4f67130a GL |
226 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
227 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
379fa5d3 GL |
228 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; |
229 | struct scatterlist *sg; | |
230 | struct mx3_camera_buffer *buf; | |
760697be | 231 | size_t new_size; |
760697be GL |
232 | int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, |
233 | icd->current_fmt->host_fmt); | |
234 | ||
235 | if (bytes_per_line < 0) | |
236 | return bytes_per_line; | |
237 | ||
379fa5d3 GL |
238 | buf = to_mx3_vb(vb); |
239 | sg = &buf->sg; | |
4f67130a | 240 | |
379fa5d3 | 241 | new_size = bytes_per_line * icd->user_height; |
4f67130a | 242 | |
379fa5d3 GL |
243 | if (vb2_plane_size(vb, 0) < new_size) { |
244 | dev_err(icd->dev.parent, "Buffer too small (%lu < %zu)\n", | |
245 | vb2_plane_size(vb, 0), new_size); | |
246 | return -ENOBUFS; | |
4f67130a GL |
247 | } |
248 | ||
379fa5d3 GL |
249 | if (buf->state == CSI_BUF_NEEDS_INIT) { |
250 | sg_dma_address(sg) = vb2_dma_contig_plane_paddr(vb, 0); | |
251 | sg_dma_len(sg) = new_size; | |
4f67130a GL |
252 | |
253 | buf->txd = ichan->dma_chan.device->device_prep_slave_sg( | |
254 | &ichan->dma_chan, sg, 1, DMA_FROM_DEVICE, | |
255 | DMA_PREP_INTERRUPT); | |
379fa5d3 GL |
256 | if (!buf->txd) |
257 | return -EIO; | |
4f67130a GL |
258 | |
259 | buf->txd->callback_param = buf->txd; | |
260 | buf->txd->callback = mx3_cam_dma_done; | |
261 | ||
379fa5d3 | 262 | buf->state = CSI_BUF_PREPARED; |
4f67130a GL |
263 | } |
264 | ||
379fa5d3 | 265 | vb2_set_plane_payload(vb, 0, new_size); |
4f67130a | 266 | |
379fa5d3 | 267 | return 0; |
4f67130a GL |
268 | } |
269 | ||
270 | static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc) | |
271 | { | |
272 | /* Add more formats as need arises and test possibilities appear... */ | |
273 | switch (fourcc) { | |
4f67130a GL |
274 | case V4L2_PIX_FMT_RGB24: |
275 | return IPU_PIX_FMT_RGB24; | |
a48be1d6 AP |
276 | case V4L2_PIX_FMT_UYVY: |
277 | case V4L2_PIX_FMT_RGB565: | |
4f67130a GL |
278 | default: |
279 | return IPU_PIX_FMT_GENERIC; | |
280 | } | |
281 | } | |
282 | ||
379fa5d3 | 283 | static void mx3_videobuf_queue(struct vb2_buffer *vb) |
4f67130a | 284 | { |
379fa5d3 | 285 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
4f67130a GL |
286 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
287 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
379fa5d3 | 288 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
4f67130a GL |
289 | struct dma_async_tx_descriptor *txd = buf->txd; |
290 | struct idmac_channel *ichan = to_idmac_chan(txd->chan); | |
291 | struct idmac_video_param *video = &ichan->params.video; | |
4f67130a | 292 | dma_cookie_t cookie; |
760697be | 293 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
379fa5d3 | 294 | unsigned long flags; |
4f67130a GL |
295 | |
296 | /* This is the configuration of one sg-element */ | |
760697be | 297 | video->out_pixel_fmt = fourcc_to_ipu_pix(fourcc); |
a48be1d6 AP |
298 | |
299 | if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) { | |
300 | /* | |
301 | * If the IPU DMA channel is configured to transport | |
302 | * generic 8-bit data, we have to set up correctly the | |
303 | * geometry parameters upon the current pixel format. | |
304 | * So, since the DMA horizontal parameters are expressed | |
305 | * in bytes not pixels, convert these in the right unit. | |
306 | */ | |
307 | int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, | |
308 | icd->current_fmt->host_fmt); | |
309 | BUG_ON(bytes_per_line <= 0); | |
310 | ||
311 | video->out_width = bytes_per_line; | |
312 | video->out_height = icd->user_height; | |
313 | video->out_stride = bytes_per_line; | |
314 | } else { | |
315 | /* | |
316 | * For IPU known formats the pixel unit will be managed | |
317 | * successfully by the IPU code | |
318 | */ | |
319 | video->out_width = icd->user_width; | |
320 | video->out_height = icd->user_height; | |
321 | video->out_stride = icd->user_width; | |
322 | } | |
4f67130a GL |
323 | |
324 | #ifdef DEBUG | |
325 | /* helps to see what DMA actually has written */ | |
379fa5d3 GL |
326 | if (vb2_plane_vaddr(vb, 0)) |
327 | memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0)); | |
4f67130a GL |
328 | #endif |
329 | ||
379fa5d3 GL |
330 | spin_lock_irqsave(&mx3_cam->lock, flags); |
331 | list_add_tail(&buf->queue, &mx3_cam->capture); | |
4f67130a | 332 | |
379fa5d3 | 333 | if (!mx3_cam->active) |
4f67130a | 334 | mx3_cam->active = buf; |
4f67130a | 335 | |
2dd54a54 | 336 | spin_unlock_irq(&mx3_cam->lock); |
4f67130a GL |
337 | |
338 | cookie = txd->tx_submit(txd); | |
0166b743 GL |
339 | dev_dbg(icd->dev.parent, "Submitted cookie %d DMA 0x%08x\n", |
340 | cookie, sg_dma_address(&buf->sg)); | |
2dd54a54 | 341 | |
4f67130a GL |
342 | if (cookie >= 0) |
343 | return; | |
344 | ||
379fa5d3 | 345 | spin_lock_irq(&mx3_cam->lock); |
4f67130a | 346 | |
379fa5d3 GL |
347 | /* Submit error */ |
348 | list_del_init(&buf->queue); | |
4f67130a GL |
349 | |
350 | if (mx3_cam->active == buf) | |
351 | mx3_cam->active = NULL; | |
379fa5d3 GL |
352 | |
353 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
354 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); | |
4f67130a GL |
355 | } |
356 | ||
379fa5d3 | 357 | static void mx3_videobuf_release(struct vb2_buffer *vb) |
4f67130a | 358 | { |
379fa5d3 | 359 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
4f67130a GL |
360 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
361 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
379fa5d3 GL |
362 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
363 | struct dma_async_tx_descriptor *txd = buf->txd; | |
4f67130a GL |
364 | unsigned long flags; |
365 | ||
0166b743 | 366 | dev_dbg(icd->dev.parent, |
379fa5d3 | 367 | "Release%s DMA 0x%08x, queue %sempty\n", |
4f67130a | 368 | mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg), |
379fa5d3 GL |
369 | list_empty(&buf->queue) ? "" : "not "); |
370 | ||
4f67130a | 371 | spin_lock_irqsave(&mx3_cam->lock, flags); |
4f67130a | 372 | |
379fa5d3 GL |
373 | if (mx3_cam->active == buf) |
374 | mx3_cam->active = NULL; | |
375 | ||
376 | /* Doesn't hurt also if the list is empty */ | |
377 | list_del_init(&buf->queue); | |
378 | buf->state = CSI_BUF_NEEDS_INIT; | |
379 | ||
380 | if (txd) { | |
381 | buf->txd = NULL; | |
382 | if (mx3_cam->idmac_channel[0]) | |
383 | async_tx_ack(txd); | |
4f67130a | 384 | } |
379fa5d3 | 385 | |
4f67130a | 386 | spin_unlock_irqrestore(&mx3_cam->lock, flags); |
4f67130a GL |
387 | } |
388 | ||
379fa5d3 GL |
389 | static int mx3_videobuf_init(struct vb2_buffer *vb) |
390 | { | |
391 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); | |
392 | /* This is for locking debugging only */ | |
393 | INIT_LIST_HEAD(&buf->queue); | |
394 | sg_init_table(&buf->sg, 1); | |
395 | ||
396 | buf->state = CSI_BUF_NEEDS_INIT; | |
397 | buf->txd = NULL; | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
08a31b96 GL |
402 | static int mx3_stop_streaming(struct vb2_queue *q) |
403 | { | |
404 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
405 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
406 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
407 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
408 | struct dma_chan *chan; | |
409 | struct mx3_camera_buffer *buf, *tmp; | |
410 | unsigned long flags; | |
411 | ||
412 | if (ichan) { | |
413 | chan = &ichan->dma_chan; | |
414 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); | |
415 | } | |
416 | ||
417 | spin_lock_irqsave(&mx3_cam->lock, flags); | |
418 | ||
419 | mx3_cam->active = NULL; | |
420 | ||
421 | list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) { | |
422 | buf->state = CSI_BUF_NEEDS_INIT; | |
423 | list_del_init(&buf->queue); | |
424 | } | |
425 | ||
426 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
379fa5d3 GL |
431 | static struct vb2_ops mx3_videobuf_ops = { |
432 | .queue_setup = mx3_videobuf_setup, | |
433 | .buf_prepare = mx3_videobuf_prepare, | |
434 | .buf_queue = mx3_videobuf_queue, | |
435 | .buf_cleanup = mx3_videobuf_release, | |
436 | .buf_init = mx3_videobuf_init, | |
437 | .wait_prepare = soc_camera_unlock, | |
438 | .wait_finish = soc_camera_lock, | |
08a31b96 | 439 | .stop_streaming = mx3_stop_streaming, |
4f67130a GL |
440 | }; |
441 | ||
379fa5d3 | 442 | static int mx3_camera_init_videobuf(struct vb2_queue *q, |
4f67130a GL |
443 | struct soc_camera_device *icd) |
444 | { | |
379fa5d3 GL |
445 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
446 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
447 | q->drv_priv = icd; | |
448 | q->ops = &mx3_videobuf_ops; | |
449 | q->mem_ops = &vb2_dma_contig_memops; | |
450 | q->buf_struct_size = sizeof(struct mx3_camera_buffer); | |
451 | ||
452 | return vb2_queue_init(q); | |
4f67130a GL |
453 | } |
454 | ||
455 | /* First part of ipu_csi_init_interface() */ | |
456 | static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam, | |
457 | struct soc_camera_device *icd) | |
458 | { | |
459 | u32 conf; | |
460 | long rate; | |
461 | ||
462 | /* Set default size: ipu_csi_set_window_size() */ | |
463 | csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE); | |
464 | /* ...and position to 0:0: ipu_csi_set_window_pos() */ | |
465 | conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
466 | csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL); | |
467 | ||
468 | /* We use only gated clock synchronisation mode so far */ | |
469 | conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT; | |
470 | ||
471 | /* Set generic data, platform-biggest bus-width */ | |
472 | conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
473 | ||
474 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
475 | conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
476 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
477 | conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
478 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
479 | conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
480 | else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/ | |
481 | conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
482 | ||
483 | if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC) | |
484 | conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT; | |
485 | if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC) | |
486 | conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT; | |
487 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) | |
488 | conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; | |
489 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) | |
490 | conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; | |
491 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) | |
492 | conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; | |
493 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) | |
494 | conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; | |
495 | ||
496 | /* ipu_csi_init_interface() */ | |
497 | csi_reg_write(mx3_cam, conf, CSI_SENS_CONF); | |
498 | ||
499 | clk_enable(mx3_cam->clk); | |
500 | rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk); | |
0166b743 | 501 | dev_dbg(icd->dev.parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate); |
4f67130a GL |
502 | if (rate) |
503 | clk_set_rate(mx3_cam->clk, rate); | |
504 | } | |
505 | ||
506 | /* Called with .video_lock held */ | |
507 | static int mx3_camera_add_device(struct soc_camera_device *icd) | |
508 | { | |
509 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
510 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
4f67130a | 511 | |
979ea1dd GL |
512 | if (mx3_cam->icd) |
513 | return -EBUSY; | |
4f67130a GL |
514 | |
515 | mx3_camera_activate(mx3_cam, icd); | |
4f67130a GL |
516 | |
517 | mx3_cam->icd = icd; | |
518 | ||
0166b743 | 519 | dev_info(icd->dev.parent, "MX3 Camera driver attached to camera %d\n", |
40e2e092 GL |
520 | icd->devnum); |
521 | ||
522 | return 0; | |
4f67130a GL |
523 | } |
524 | ||
525 | /* Called with .video_lock held */ | |
526 | static void mx3_camera_remove_device(struct soc_camera_device *icd) | |
527 | { | |
528 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
529 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
530 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
531 | ||
532 | BUG_ON(icd != mx3_cam->icd); | |
533 | ||
534 | if (*ichan) { | |
535 | dma_release_channel(&(*ichan)->dma_chan); | |
536 | *ichan = NULL; | |
537 | } | |
538 | ||
4f67130a GL |
539 | clk_disable(mx3_cam->clk); |
540 | ||
541 | mx3_cam->icd = NULL; | |
542 | ||
0166b743 | 543 | dev_info(icd->dev.parent, "MX3 Camera driver detached from camera %d\n", |
4f67130a GL |
544 | icd->devnum); |
545 | } | |
546 | ||
4f67130a GL |
547 | static int test_platform_param(struct mx3_camera_dev *mx3_cam, |
548 | unsigned char buswidth, unsigned long *flags) | |
549 | { | |
550 | /* | |
551 | * Platform specified synchronization and pixel clock polarities are | |
552 | * only a recommendation and are only used during probing. MX3x | |
553 | * camera interface only works in master mode, i.e., uses HSYNC and | |
554 | * VSYNC signals from the sensor | |
555 | */ | |
556 | *flags = SOCAM_MASTER | | |
557 | SOCAM_HSYNC_ACTIVE_HIGH | | |
558 | SOCAM_HSYNC_ACTIVE_LOW | | |
559 | SOCAM_VSYNC_ACTIVE_HIGH | | |
560 | SOCAM_VSYNC_ACTIVE_LOW | | |
561 | SOCAM_PCLK_SAMPLE_RISING | | |
562 | SOCAM_PCLK_SAMPLE_FALLING | | |
563 | SOCAM_DATA_ACTIVE_HIGH | | |
564 | SOCAM_DATA_ACTIVE_LOW; | |
565 | ||
5d28d525 GL |
566 | /* |
567 | * If requested data width is supported by the platform, use it or any | |
568 | * possible lower value - i.MX31 is smart enough to schift bits | |
569 | */ | |
760697be GL |
570 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) |
571 | *flags |= SOCAM_DATAWIDTH_15 | SOCAM_DATAWIDTH_10 | | |
572 | SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4; | |
573 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
574 | *flags |= SOCAM_DATAWIDTH_10 | SOCAM_DATAWIDTH_8 | | |
575 | SOCAM_DATAWIDTH_4; | |
576 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
577 | *flags |= SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4; | |
578 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4) | |
579 | *flags |= SOCAM_DATAWIDTH_4; | |
580 | ||
4f67130a GL |
581 | switch (buswidth) { |
582 | case 15: | |
760697be | 583 | if (!(*flags & SOCAM_DATAWIDTH_15)) |
4f67130a | 584 | return -EINVAL; |
4f67130a GL |
585 | break; |
586 | case 10: | |
760697be | 587 | if (!(*flags & SOCAM_DATAWIDTH_10)) |
4f67130a | 588 | return -EINVAL; |
4f67130a GL |
589 | break; |
590 | case 8: | |
760697be | 591 | if (!(*flags & SOCAM_DATAWIDTH_8)) |
4f67130a | 592 | return -EINVAL; |
4f67130a GL |
593 | break; |
594 | case 4: | |
760697be | 595 | if (!(*flags & SOCAM_DATAWIDTH_4)) |
4f67130a | 596 | return -EINVAL; |
4f67130a GL |
597 | break; |
598 | default: | |
6a6c8786 GL |
599 | dev_warn(mx3_cam->soc_host.v4l2_dev.dev, |
600 | "Unsupported bus width %d\n", buswidth); | |
4f67130a GL |
601 | return -EINVAL; |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | static int mx3_camera_try_bus_param(struct soc_camera_device *icd, | |
608 | const unsigned int depth) | |
609 | { | |
610 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
611 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
612 | unsigned long bus_flags, camera_flags; | |
613 | int ret = test_platform_param(mx3_cam, depth, &bus_flags); | |
614 | ||
6a6c8786 | 615 | dev_dbg(icd->dev.parent, "request bus width %d bit: %d\n", depth, ret); |
4f67130a GL |
616 | |
617 | if (ret < 0) | |
618 | return ret; | |
619 | ||
620 | camera_flags = icd->ops->query_bus_param(icd); | |
621 | ||
622 | ret = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
623 | if (ret < 0) | |
0166b743 GL |
624 | dev_warn(icd->dev.parent, |
625 | "Flags incompatible: camera %lx, host %lx\n", | |
4f67130a GL |
626 | camera_flags, bus_flags); |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
631 | static bool chan_filter(struct dma_chan *chan, void *arg) | |
632 | { | |
633 | struct dma_chan_request *rq = arg; | |
634 | struct mx3_camera_pdata *pdata; | |
635 | ||
a8de6635 SH |
636 | if (!imx_dma_is_ipu(chan)) |
637 | return false; | |
638 | ||
4f67130a GL |
639 | if (!rq) |
640 | return false; | |
641 | ||
979ea1dd | 642 | pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data; |
4f67130a GL |
643 | |
644 | return rq->id == chan->chan_id && | |
645 | pdata->dma_dev == chan->device->dev; | |
646 | } | |
647 | ||
760697be | 648 | static const struct soc_mbus_pixelfmt mx3_camera_formats[] = { |
4f67130a | 649 | { |
760697be GL |
650 | .fourcc = V4L2_PIX_FMT_SBGGR8, |
651 | .name = "Bayer BGGR (sRGB) 8 bit", | |
652 | .bits_per_sample = 8, | |
653 | .packing = SOC_MBUS_PACKING_NONE, | |
654 | .order = SOC_MBUS_ORDER_LE, | |
4f67130a | 655 | }, { |
760697be GL |
656 | .fourcc = V4L2_PIX_FMT_GREY, |
657 | .name = "Monochrome 8 bit", | |
658 | .bits_per_sample = 8, | |
659 | .packing = SOC_MBUS_PACKING_NONE, | |
660 | .order = SOC_MBUS_ORDER_LE, | |
4f67130a GL |
661 | }, |
662 | }; | |
663 | ||
760697be GL |
664 | /* This will be corrected as we get more formats */ |
665 | static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
4f67130a | 666 | { |
760697be GL |
667 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
668 | (fmt->bits_per_sample == 8 && | |
669 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
670 | (fmt->bits_per_sample > 8 && | |
671 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
4f67130a GL |
672 | } |
673 | ||
3805f201 | 674 | static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
4f67130a GL |
675 | struct soc_camera_format_xlate *xlate) |
676 | { | |
760697be GL |
677 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
678 | struct device *dev = icd->dev.parent; | |
679 | int formats = 0, ret; | |
680 | enum v4l2_mbus_pixelcode code; | |
681 | const struct soc_mbus_pixelfmt *fmt; | |
4f67130a | 682 | |
760697be GL |
683 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); |
684 | if (ret < 0) | |
685 | /* No more formats */ | |
686 | return 0; | |
4f67130a | 687 | |
760697be GL |
688 | fmt = soc_mbus_get_fmtdesc(code); |
689 | if (!fmt) { | |
d2dcad49 GL |
690 | dev_warn(icd->dev.parent, |
691 | "Unsupported format code #%u: %d\n", idx, code); | |
4f67130a | 692 | return 0; |
760697be | 693 | } |
4f67130a | 694 | |
760697be GL |
695 | /* This also checks support for the requested bits-per-sample */ |
696 | ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample); | |
4f67130a GL |
697 | if (ret < 0) |
698 | return 0; | |
699 | ||
760697be GL |
700 | switch (code) { |
701 | case V4L2_MBUS_FMT_SBGGR10_1X10: | |
4f67130a GL |
702 | formats++; |
703 | if (xlate) { | |
760697be GL |
704 | xlate->host_fmt = &mx3_camera_formats[0]; |
705 | xlate->code = code; | |
4f67130a | 706 | xlate++; |
760697be GL |
707 | dev_dbg(dev, "Providing format %s using code %d\n", |
708 | mx3_camera_formats[0].name, code); | |
4f67130a | 709 | } |
760697be GL |
710 | break; |
711 | case V4L2_MBUS_FMT_Y10_1X10: | |
4f67130a GL |
712 | formats++; |
713 | if (xlate) { | |
760697be GL |
714 | xlate->host_fmt = &mx3_camera_formats[1]; |
715 | xlate->code = code; | |
4f67130a | 716 | xlate++; |
760697be GL |
717 | dev_dbg(dev, "Providing format %s using code %d\n", |
718 | mx3_camera_formats[1].name, code); | |
4f67130a | 719 | } |
760697be | 720 | break; |
4f67130a | 721 | default: |
760697be GL |
722 | if (!mx3_camera_packing_supported(fmt)) |
723 | return 0; | |
724 | } | |
725 | ||
726 | /* Generic pass-through */ | |
727 | formats++; | |
728 | if (xlate) { | |
729 | xlate->host_fmt = fmt; | |
730 | xlate->code = code; | |
a48be1d6 AP |
731 | dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n", |
732 | (fmt->fourcc >> (0*8)) & 0xFF, | |
733 | (fmt->fourcc >> (1*8)) & 0xFF, | |
734 | (fmt->fourcc >> (2*8)) & 0xFF, | |
735 | (fmt->fourcc >> (3*8)) & 0xFF); | |
760697be | 736 | xlate++; |
4f67130a GL |
737 | } |
738 | ||
739 | return formats; | |
740 | } | |
741 | ||
09e231b3 | 742 | static void configure_geometry(struct mx3_camera_dev *mx3_cam, |
a48be1d6 | 743 | unsigned int width, unsigned int height, |
d2dcad49 | 744 | const struct soc_mbus_pixelfmt *fmt) |
4f67130a | 745 | { |
4f67130a | 746 | u32 ctrl, width_field, height_field; |
a48be1d6 AP |
747 | |
748 | if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) { | |
749 | /* | |
750 | * As the CSI will be configured to output BAYER, here | |
751 | * the width parameter count the number of samples to | |
752 | * capture to complete the whole image width. | |
753 | */ | |
cc552b62 GL |
754 | unsigned int num, den; |
755 | int ret = soc_mbus_samples_per_pixel(fmt, &num, &den); | |
756 | BUG_ON(ret < 0); | |
757 | width = width * num / den; | |
a48be1d6 | 758 | } |
4f67130a GL |
759 | |
760 | /* Setup frame size - this cannot be changed on-the-fly... */ | |
6a6c8786 GL |
761 | width_field = width - 1; |
762 | height_field = height - 1; | |
4f67130a GL |
763 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE); |
764 | ||
765 | csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1); | |
766 | csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2); | |
767 | ||
768 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE); | |
769 | ||
770 | /* ...and position */ | |
771 | ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
772 | /* Sensor does the cropping */ | |
773 | csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL); | |
09e231b3 GL |
774 | } |
775 | ||
776 | static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam) | |
777 | { | |
778 | dma_cap_mask_t mask; | |
779 | struct dma_chan *chan; | |
780 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
781 | /* We have to use IDMAC_IC_7 for Bayer / generic data */ | |
782 | struct dma_chan_request rq = {.mx3_cam = mx3_cam, | |
783 | .id = IDMAC_IC_7}; | |
784 | ||
09e231b3 GL |
785 | dma_cap_zero(mask); |
786 | dma_cap_set(DMA_SLAVE, mask); | |
787 | dma_cap_set(DMA_PRIVATE, mask); | |
788 | chan = dma_request_channel(mask, chan_filter, &rq); | |
789 | if (!chan) | |
790 | return -EBUSY; | |
791 | ||
792 | *ichan = to_idmac_chan(chan); | |
793 | (*ichan)->client = mx3_cam; | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
6a6c8786 GL |
798 | /* |
799 | * FIXME: learn to use stride != width, then we can keep stride properly aligned | |
800 | * and support arbitrary (even) widths. | |
801 | */ | |
e26b3144 | 802 | static inline void stride_align(__u32 *width) |
6a6c8786 | 803 | { |
d2dcad49 GL |
804 | if (ALIGN(*width, 8) < 4096) |
805 | *width = ALIGN(*width, 8); | |
6a6c8786 GL |
806 | else |
807 | *width = *width & ~7; | |
808 | } | |
809 | ||
810 | /* | |
811 | * As long as we don't implement host-side cropping and scaling, we can use | |
812 | * default g_crop and cropcap from soc_camera.c | |
813 | */ | |
09e231b3 | 814 | static int mx3_camera_set_crop(struct soc_camera_device *icd, |
08590b96 | 815 | struct v4l2_crop *a) |
09e231b3 | 816 | { |
08590b96 | 817 | struct v4l2_rect *rect = &a->c; |
09e231b3 GL |
818 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
819 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
c9c1f1c0 | 820 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
760697be | 821 | struct v4l2_mbus_framefmt mf; |
6a6c8786 | 822 | int ret; |
09e231b3 | 823 | |
6a6c8786 GL |
824 | soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); |
825 | soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); | |
826 | ||
827 | ret = v4l2_subdev_call(sd, video, s_crop, a); | |
828 | if (ret < 0) | |
829 | return ret; | |
830 | ||
d2dcad49 | 831 | /* The capture device might have changed its output sizes */ |
760697be | 832 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); |
6a6c8786 GL |
833 | if (ret < 0) |
834 | return ret; | |
835 | ||
d2dcad49 GL |
836 | if (mf.code != icd->current_fmt->code) |
837 | return -EINVAL; | |
838 | ||
760697be | 839 | if (mf.width & 7) { |
6a6c8786 | 840 | /* Ouch! We can only handle 8-byte aligned width... */ |
760697be GL |
841 | stride_align(&mf.width); |
842 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
09e231b3 GL |
843 | if (ret < 0) |
844 | return ret; | |
845 | } | |
846 | ||
379fa5d3 | 847 | if (mf.width != icd->user_width || mf.height != icd->user_height) |
d2dcad49 GL |
848 | configure_geometry(mx3_cam, mf.width, mf.height, |
849 | icd->current_fmt->host_fmt); | |
6a6c8786 GL |
850 | |
851 | dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", | |
760697be | 852 | mf.width, mf.height); |
6a6c8786 | 853 | |
760697be GL |
854 | icd->user_width = mf.width; |
855 | icd->user_height = mf.height; | |
6a6c8786 GL |
856 | |
857 | return ret; | |
09e231b3 GL |
858 | } |
859 | ||
860 | static int mx3_camera_set_fmt(struct soc_camera_device *icd, | |
861 | struct v4l2_format *f) | |
862 | { | |
863 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
864 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
c9c1f1c0 | 865 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
866 | const struct soc_camera_format_xlate *xlate; |
867 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 868 | struct v4l2_mbus_framefmt mf; |
09e231b3 GL |
869 | int ret; |
870 | ||
871 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); | |
872 | if (!xlate) { | |
0166b743 GL |
873 | dev_warn(icd->dev.parent, "Format %x not found\n", |
874 | pix->pixelformat); | |
09e231b3 GL |
875 | return -EINVAL; |
876 | } | |
877 | ||
6a6c8786 GL |
878 | stride_align(&pix->width); |
879 | dev_dbg(icd->dev.parent, "Set format %dx%d\n", pix->width, pix->height); | |
880 | ||
09e231b3 GL |
881 | /* |
882 | * Might have to perform a complete interface initialisation like in | |
883 | * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider | |
884 | * mxc_v4l2_s_fmt() | |
885 | */ | |
886 | ||
d2dcad49 | 887 | configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt); |
4f67130a | 888 | |
760697be GL |
889 | mf.width = pix->width; |
890 | mf.height = pix->height; | |
891 | mf.field = pix->field; | |
892 | mf.colorspace = pix->colorspace; | |
893 | mf.code = xlate->code; | |
894 | ||
895 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
896 | if (ret < 0) | |
897 | return ret; | |
898 | ||
899 | if (mf.code != xlate->code) | |
900 | return -EINVAL; | |
901 | ||
379fa5d3 GL |
902 | if (!mx3_cam->idmac_channel[0]) { |
903 | ret = acquire_dma_channel(mx3_cam); | |
904 | if (ret < 0) | |
905 | return ret; | |
906 | } | |
907 | ||
760697be GL |
908 | pix->width = mf.width; |
909 | pix->height = mf.height; | |
910 | pix->field = mf.field; | |
379fa5d3 | 911 | mx3_cam->field = mf.field; |
760697be GL |
912 | pix->colorspace = mf.colorspace; |
913 | icd->current_fmt = xlate; | |
4f67130a | 914 | |
6a6c8786 GL |
915 | dev_dbg(icd->dev.parent, "Sensor set %dx%d\n", pix->width, pix->height); |
916 | ||
4f67130a GL |
917 | return ret; |
918 | } | |
919 | ||
920 | static int mx3_camera_try_fmt(struct soc_camera_device *icd, | |
921 | struct v4l2_format *f) | |
922 | { | |
c9c1f1c0 | 923 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
4f67130a GL |
924 | const struct soc_camera_format_xlate *xlate; |
925 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 926 | struct v4l2_mbus_framefmt mf; |
4f67130a | 927 | __u32 pixfmt = pix->pixelformat; |
4f67130a GL |
928 | int ret; |
929 | ||
930 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | |
931 | if (pixfmt && !xlate) { | |
979ea1dd | 932 | dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); |
4f67130a GL |
933 | return -EINVAL; |
934 | } | |
935 | ||
936 | /* limit to MX3 hardware capabilities */ | |
937 | if (pix->height > 4096) | |
938 | pix->height = 4096; | |
939 | if (pix->width > 4096) | |
940 | pix->width = 4096; | |
941 | ||
4f67130a | 942 | /* limit to sensor capabilities */ |
760697be GL |
943 | mf.width = pix->width; |
944 | mf.height = pix->height; | |
945 | mf.field = pix->field; | |
946 | mf.colorspace = pix->colorspace; | |
947 | mf.code = xlate->code; | |
4f67130a | 948 | |
760697be GL |
949 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); |
950 | if (ret < 0) | |
951 | return ret; | |
4f67130a | 952 | |
760697be GL |
953 | pix->width = mf.width; |
954 | pix->height = mf.height; | |
955 | pix->colorspace = mf.colorspace; | |
956 | ||
957 | switch (mf.field) { | |
958 | case V4L2_FIELD_ANY: | |
4f67130a | 959 | pix->field = V4L2_FIELD_NONE; |
760697be GL |
960 | break; |
961 | case V4L2_FIELD_NONE: | |
962 | break; | |
963 | default: | |
964 | dev_err(icd->dev.parent, "Field type %d unsupported.\n", | |
965 | mf.field); | |
966 | ret = -EINVAL; | |
4f67130a GL |
967 | } |
968 | ||
969 | return ret; | |
970 | } | |
971 | ||
57bee29d | 972 | static int mx3_camera_reqbufs(struct soc_camera_device *icd, |
4f67130a GL |
973 | struct v4l2_requestbuffers *p) |
974 | { | |
975 | return 0; | |
976 | } | |
977 | ||
978 | static unsigned int mx3_camera_poll(struct file *file, poll_table *pt) | |
979 | { | |
57bee29d | 980 | struct soc_camera_device *icd = file->private_data; |
4f67130a | 981 | |
379fa5d3 | 982 | return vb2_poll(&icd->vb2_vidq, file, pt); |
4f67130a GL |
983 | } |
984 | ||
985 | static int mx3_camera_querycap(struct soc_camera_host *ici, | |
986 | struct v4l2_capability *cap) | |
987 | { | |
988 | /* cap->name is set by the firendly caller:-> */ | |
989 | strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card)); | |
4f67130a GL |
990 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
995 | static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
996 | { | |
997 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
998 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
999 | unsigned long bus_flags, camera_flags, common_flags; | |
1000 | u32 dw, sens_conf; | |
760697be GL |
1001 | const struct soc_mbus_pixelfmt *fmt; |
1002 | int buswidth; | |
1003 | int ret; | |
4f67130a | 1004 | const struct soc_camera_format_xlate *xlate; |
0166b743 | 1005 | struct device *dev = icd->dev.parent; |
4f67130a | 1006 | |
760697be GL |
1007 | fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code); |
1008 | if (!fmt) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | buswidth = fmt->bits_per_sample; | |
1012 | ret = test_platform_param(mx3_cam, buswidth, &bus_flags); | |
1013 | ||
4f67130a GL |
1014 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1015 | if (!xlate) { | |
0166b743 | 1016 | dev_warn(dev, "Format %x not found\n", pixfmt); |
4f67130a GL |
1017 | return -EINVAL; |
1018 | } | |
1019 | ||
760697be | 1020 | dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret); |
4f67130a GL |
1021 | |
1022 | if (ret < 0) | |
1023 | return ret; | |
1024 | ||
1025 | camera_flags = icd->ops->query_bus_param(icd); | |
1026 | ||
1027 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
0166b743 | 1028 | dev_dbg(dev, "Flags cam: 0x%lx host: 0x%lx common: 0x%lx\n", |
40e2e092 | 1029 | camera_flags, bus_flags, common_flags); |
4f67130a | 1030 | if (!common_flags) { |
0166b743 | 1031 | dev_dbg(dev, "no common flags"); |
4f67130a GL |
1032 | return -EINVAL; |
1033 | } | |
1034 | ||
1035 | /* Make choices, based on platform preferences */ | |
1036 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
1037 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
1038 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) | |
1039 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
1040 | else | |
1041 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
1042 | } | |
1043 | ||
1044 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
1045 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
1046 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) | |
1047 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
1048 | else | |
1049 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
1050 | } | |
1051 | ||
1052 | if ((common_flags & SOCAM_DATA_ACTIVE_HIGH) && | |
1053 | (common_flags & SOCAM_DATA_ACTIVE_LOW)) { | |
1054 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) | |
1055 | common_flags &= ~SOCAM_DATA_ACTIVE_HIGH; | |
1056 | else | |
1057 | common_flags &= ~SOCAM_DATA_ACTIVE_LOW; | |
1058 | } | |
1059 | ||
1060 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
1061 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
1062 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) | |
1063 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
1064 | else | |
1065 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
1066 | } | |
1067 | ||
5d28d525 GL |
1068 | /* |
1069 | * Make the camera work in widest common mode, we'll take care of | |
1070 | * the rest | |
1071 | */ | |
4f67130a GL |
1072 | if (common_flags & SOCAM_DATAWIDTH_15) |
1073 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
1074 | SOCAM_DATAWIDTH_15; | |
1075 | else if (common_flags & SOCAM_DATAWIDTH_10) | |
1076 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
1077 | SOCAM_DATAWIDTH_10; | |
1078 | else if (common_flags & SOCAM_DATAWIDTH_8) | |
1079 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
1080 | SOCAM_DATAWIDTH_8; | |
1081 | else | |
1082 | common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) | | |
1083 | SOCAM_DATAWIDTH_4; | |
1084 | ||
1085 | ret = icd->ops->set_bus_param(icd, common_flags); | |
40e2e092 | 1086 | if (ret < 0) { |
0166b743 | 1087 | dev_dbg(dev, "camera set_bus_param(%lx) returned %d\n", |
40e2e092 | 1088 | common_flags, ret); |
4f67130a | 1089 | return ret; |
40e2e092 | 1090 | } |
4f67130a GL |
1091 | |
1092 | /* | |
1093 | * So far only gated clock mode is supported. Add a line | |
1094 | * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) | | |
1095 | * below and select the required mode when supporting other | |
1096 | * synchronisation protocols. | |
1097 | */ | |
1098 | sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) & | |
1099 | ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) | | |
1100 | (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) | | |
1101 | (1 << CSI_SENS_CONF_DATA_POL_SHIFT) | | |
1102 | (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) | | |
1103 | (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) | | |
1104 | (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT)); | |
1105 | ||
1106 | /* TODO: Support RGB and YUV formats */ | |
1107 | ||
1108 | /* This has been set in mx3_camera_activate(), but we clear it above */ | |
1109 | sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
1110 | ||
1111 | if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) | |
1112 | sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; | |
1113 | if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) | |
1114 | sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; | |
1115 | if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) | |
1116 | sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; | |
1117 | if (common_flags & SOCAM_DATA_ACTIVE_LOW) | |
1118 | sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; | |
1119 | ||
1120 | /* Just do what we're asked to do */ | |
760697be | 1121 | switch (xlate->host_fmt->bits_per_sample) { |
4f67130a GL |
1122 | case 4: |
1123 | dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1124 | break; | |
1125 | case 8: | |
1126 | dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1127 | break; | |
1128 | case 10: | |
1129 | dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1130 | break; | |
1131 | default: | |
1132 | /* | |
1133 | * Actually it can only be 15 now, default is just to silence | |
1134 | * compiler warnings | |
1135 | */ | |
1136 | case 15: | |
1137 | dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1138 | } | |
1139 | ||
1140 | csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF); | |
1141 | ||
0166b743 | 1142 | dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw); |
4f67130a GL |
1143 | |
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | static struct soc_camera_host_ops mx3_soc_camera_host_ops = { | |
1148 | .owner = THIS_MODULE, | |
1149 | .add = mx3_camera_add_device, | |
1150 | .remove = mx3_camera_remove_device, | |
09e231b3 | 1151 | .set_crop = mx3_camera_set_crop, |
4f67130a GL |
1152 | .set_fmt = mx3_camera_set_fmt, |
1153 | .try_fmt = mx3_camera_try_fmt, | |
1154 | .get_formats = mx3_camera_get_formats, | |
379fa5d3 | 1155 | .init_videobuf2 = mx3_camera_init_videobuf, |
4f67130a GL |
1156 | .reqbufs = mx3_camera_reqbufs, |
1157 | .poll = mx3_camera_poll, | |
1158 | .querycap = mx3_camera_querycap, | |
1159 | .set_bus_param = mx3_camera_set_bus_param, | |
1160 | }; | |
1161 | ||
e36bc31f | 1162 | static int __devinit mx3_camera_probe(struct platform_device *pdev) |
4f67130a GL |
1163 | { |
1164 | struct mx3_camera_dev *mx3_cam; | |
1165 | struct resource *res; | |
1166 | void __iomem *base; | |
1167 | int err = 0; | |
1168 | struct soc_camera_host *soc_host; | |
1169 | ||
1170 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1171 | if (!res) { | |
1172 | err = -ENODEV; | |
1173 | goto egetres; | |
1174 | } | |
1175 | ||
101b25b5 | 1176 | mx3_cam = vzalloc(sizeof(*mx3_cam)); |
4f67130a GL |
1177 | if (!mx3_cam) { |
1178 | dev_err(&pdev->dev, "Could not allocate mx3 camera object\n"); | |
1179 | err = -ENOMEM; | |
1180 | goto ealloc; | |
1181 | } | |
4f67130a | 1182 | |
b71df97a | 1183 | mx3_cam->clk = clk_get(&pdev->dev, NULL); |
4f67130a GL |
1184 | if (IS_ERR(mx3_cam->clk)) { |
1185 | err = PTR_ERR(mx3_cam->clk); | |
1186 | goto eclkget; | |
1187 | } | |
1188 | ||
4f67130a GL |
1189 | mx3_cam->pdata = pdev->dev.platform_data; |
1190 | mx3_cam->platform_flags = mx3_cam->pdata->flags; | |
1191 | if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 | | |
1192 | MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 | | |
1193 | MX3_CAMERA_DATAWIDTH_15))) { | |
5d28d525 GL |
1194 | /* |
1195 | * Platform hasn't set available data widths. This is bad. | |
1196 | * Warn and use a default. | |
1197 | */ | |
4f67130a GL |
1198 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1199 | "data widths, using default 8 bit\n"); | |
1200 | mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8; | |
1201 | } | |
1202 | ||
1203 | mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000; | |
1204 | if (!mx3_cam->mclk) { | |
1205 | dev_warn(&pdev->dev, | |
1206 | "mclk_10khz == 0! Please, fix your platform data. " | |
1207 | "Using default 20MHz\n"); | |
1208 | mx3_cam->mclk = 20000000; | |
1209 | } | |
1210 | ||
1211 | /* list of video-buffers */ | |
1212 | INIT_LIST_HEAD(&mx3_cam->capture); | |
1213 | spin_lock_init(&mx3_cam->lock); | |
1214 | ||
40e2e092 | 1215 | base = ioremap(res->start, resource_size(res)); |
4f67130a | 1216 | if (!base) { |
40e2e092 | 1217 | pr_err("Couldn't map %x@%x\n", resource_size(res), res->start); |
4f67130a GL |
1218 | err = -ENOMEM; |
1219 | goto eioremap; | |
1220 | } | |
1221 | ||
1222 | mx3_cam->base = base; | |
4f67130a GL |
1223 | |
1224 | soc_host = &mx3_cam->soc_host; | |
1225 | soc_host->drv_name = MX3_CAM_DRV_NAME; | |
1226 | soc_host->ops = &mx3_soc_camera_host_ops; | |
1227 | soc_host->priv = mx3_cam; | |
979ea1dd | 1228 | soc_host->v4l2_dev.dev = &pdev->dev; |
4f67130a | 1229 | soc_host->nr = pdev->id; |
eff505fa | 1230 | |
379fa5d3 GL |
1231 | mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); |
1232 | if (IS_ERR(mx3_cam->alloc_ctx)) { | |
1233 | err = PTR_ERR(mx3_cam->alloc_ctx); | |
1234 | goto eallocctx; | |
1235 | } | |
1236 | ||
4f67130a GL |
1237 | err = soc_camera_host_register(soc_host); |
1238 | if (err) | |
1239 | goto ecamhostreg; | |
1240 | ||
1241 | /* IDMAC interface */ | |
1242 | dmaengine_get(); | |
1243 | ||
1244 | return 0; | |
1245 | ||
1246 | ecamhostreg: | |
379fa5d3 GL |
1247 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
1248 | eallocctx: | |
4f67130a GL |
1249 | iounmap(base); |
1250 | eioremap: | |
1251 | clk_put(mx3_cam->clk); | |
1252 | eclkget: | |
1253 | vfree(mx3_cam); | |
1254 | ealloc: | |
1255 | egetres: | |
1256 | return err; | |
1257 | } | |
1258 | ||
1259 | static int __devexit mx3_camera_remove(struct platform_device *pdev) | |
1260 | { | |
eff505fa GL |
1261 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1262 | struct mx3_camera_dev *mx3_cam = container_of(soc_host, | |
1263 | struct mx3_camera_dev, soc_host); | |
4f67130a GL |
1264 | |
1265 | clk_put(mx3_cam->clk); | |
1266 | ||
eff505fa | 1267 | soc_camera_host_unregister(soc_host); |
4f67130a GL |
1268 | |
1269 | iounmap(mx3_cam->base); | |
1270 | ||
1271 | /* | |
1272 | * The channel has either not been allocated, | |
1273 | * or should have been released | |
1274 | */ | |
1275 | if (WARN_ON(mx3_cam->idmac_channel[0])) | |
1276 | dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan); | |
1277 | ||
379fa5d3 GL |
1278 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
1279 | ||
4f67130a GL |
1280 | vfree(mx3_cam); |
1281 | ||
1282 | dmaengine_put(); | |
1283 | ||
1284 | dev_info(&pdev->dev, "i.MX3x Camera driver unloaded\n"); | |
1285 | ||
1286 | return 0; | |
1287 | } | |
1288 | ||
1289 | static struct platform_driver mx3_camera_driver = { | |
1290 | .driver = { | |
1291 | .name = MX3_CAM_DRV_NAME, | |
1292 | }, | |
1293 | .probe = mx3_camera_probe, | |
e36bc31f | 1294 | .remove = __devexit_p(mx3_camera_remove), |
4f67130a GL |
1295 | }; |
1296 | ||
1297 | ||
e36bc31f | 1298 | static int __init mx3_camera_init(void) |
4f67130a GL |
1299 | { |
1300 | return platform_driver_register(&mx3_camera_driver); | |
1301 | } | |
1302 | ||
1303 | static void __exit mx3_camera_exit(void) | |
1304 | { | |
1305 | platform_driver_unregister(&mx3_camera_driver); | |
1306 | } | |
1307 | ||
1308 | module_init(mx3_camera_init); | |
1309 | module_exit(mx3_camera_exit); | |
1310 | ||
1311 | MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver"); | |
1312 | MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>"); | |
1313 | MODULE_LICENSE("GPL v2"); | |
64dc3c1a | 1314 | MODULE_VERSION("0.2.3"); |
40e2e092 | 1315 | MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME); |