Commit | Line | Data |
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4f67130a GL |
1 | /* |
2 | * V4L2 Driver for i.MX3x camera host | |
3 | * | |
4 | * Copyright (C) 2008 | |
5 | * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
4f67130a GL |
14 | #include <linux/videodev2.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/vmalloc.h> | |
18 | #include <linux/interrupt.h> | |
f39c1ab3 | 19 | #include <linux/sched.h> |
4f67130a GL |
20 | |
21 | #include <media/v4l2-common.h> | |
22 | #include <media/v4l2-dev.h> | |
379fa5d3 | 23 | #include <media/videobuf2-dma-contig.h> |
4f67130a | 24 | #include <media/soc_camera.h> |
760697be | 25 | #include <media/soc_mediabus.h> |
4f67130a GL |
26 | |
27 | #include <mach/ipu.h> | |
28 | #include <mach/mx3_camera.h> | |
a8de6635 | 29 | #include <mach/dma.h> |
4f67130a GL |
30 | |
31 | #define MX3_CAM_DRV_NAME "mx3-camera" | |
32 | ||
33 | /* CMOS Sensor Interface Registers */ | |
34 | #define CSI_REG_START 0x60 | |
35 | ||
36 | #define CSI_SENS_CONF (0x60 - CSI_REG_START) | |
37 | #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START) | |
38 | #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START) | |
39 | #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START) | |
40 | #define CSI_TST_CTRL (0x70 - CSI_REG_START) | |
41 | #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START) | |
42 | #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START) | |
43 | #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START) | |
44 | #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START) | |
45 | #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START) | |
46 | ||
47 | #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0 | |
48 | #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1 | |
49 | #define CSI_SENS_CONF_DATA_POL_SHIFT 2 | |
50 | #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3 | |
51 | #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4 | |
52 | #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7 | |
53 | #define CSI_SENS_CONF_DATA_FMT_SHIFT 8 | |
54 | #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10 | |
55 | #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15 | |
56 | #define CSI_SENS_CONF_DIVRATIO_SHIFT 16 | |
57 | ||
58 | #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
59 | #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
60 | #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT) | |
61 | ||
62 | #define MAX_VIDEO_MEM 16 | |
63 | ||
379fa5d3 GL |
64 | enum csi_buffer_state { |
65 | CSI_BUF_NEEDS_INIT, | |
66 | CSI_BUF_PREPARED, | |
67 | }; | |
68 | ||
4f67130a GL |
69 | struct mx3_camera_buffer { |
70 | /* common v4l buffer stuff -- must be first */ | |
379fa5d3 GL |
71 | struct vb2_buffer vb; |
72 | enum csi_buffer_state state; | |
73 | struct list_head queue; | |
4f67130a GL |
74 | |
75 | /* One descriptot per scatterlist (per frame) */ | |
76 | struct dma_async_tx_descriptor *txd; | |
77 | ||
78 | /* We have to "build" a scatterlist ourselves - one element per frame */ | |
79 | struct scatterlist sg; | |
80 | }; | |
81 | ||
82 | /** | |
83 | * struct mx3_camera_dev - i.MX3x camera (CSI) object | |
84 | * @dev: camera device, to which the coherent buffer is attached | |
85 | * @icd: currently attached camera sensor | |
86 | * @clk: pointer to clock | |
87 | * @base: remapped register base address | |
88 | * @pdata: platform data | |
89 | * @platform_flags: platform flags | |
90 | * @mclk: master clock frequency in Hz | |
91 | * @capture: list of capture videobuffers | |
92 | * @lock: protects video buffer lists | |
93 | * @active: active video buffer | |
94 | * @idmac_channel: array of pointers to IPU DMAC DMA channels | |
95 | * @soc_host: embedded soc_host object | |
96 | */ | |
97 | struct mx3_camera_dev { | |
4f67130a GL |
98 | /* |
99 | * i.MX3x is only supposed to handle one camera on its Camera Sensor | |
100 | * Interface. If anyone ever builds hardware to enable more than one | |
101 | * camera _simultaneously_, they will have to modify this driver too | |
102 | */ | |
103 | struct soc_camera_device *icd; | |
104 | struct clk *clk; | |
105 | ||
106 | void __iomem *base; | |
107 | ||
108 | struct mx3_camera_pdata *pdata; | |
109 | ||
110 | unsigned long platform_flags; | |
111 | unsigned long mclk; | |
579cea03 | 112 | u16 width_flags; /* max 15 bits */ |
4f67130a GL |
113 | |
114 | struct list_head capture; | |
115 | spinlock_t lock; /* Protects video buffer lists */ | |
116 | struct mx3_camera_buffer *active; | |
07f92448 | 117 | size_t buf_total; |
379fa5d3 GL |
118 | struct vb2_alloc_ctx *alloc_ctx; |
119 | enum v4l2_field field; | |
120 | int sequence; | |
4f67130a GL |
121 | |
122 | /* IDMAC / dmaengine interface */ | |
123 | struct idmac_channel *idmac_channel[1]; /* We need one channel */ | |
124 | ||
125 | struct soc_camera_host soc_host; | |
126 | }; | |
127 | ||
128 | struct dma_chan_request { | |
129 | struct mx3_camera_dev *mx3_cam; | |
130 | enum ipu_channel id; | |
131 | }; | |
132 | ||
4f67130a GL |
133 | static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg) |
134 | { | |
135 | return __raw_readl(mx3->base + reg); | |
136 | } | |
137 | ||
138 | static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg) | |
139 | { | |
140 | __raw_writel(value, mx3->base + reg); | |
141 | } | |
142 | ||
379fa5d3 GL |
143 | static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb) |
144 | { | |
145 | return container_of(vb, struct mx3_camera_buffer, vb); | |
146 | } | |
147 | ||
4f67130a GL |
148 | /* Called from the IPU IDMAC ISR */ |
149 | static void mx3_cam_dma_done(void *arg) | |
150 | { | |
151 | struct idmac_tx_desc *desc = to_tx_desc(arg); | |
152 | struct dma_chan *chan = desc->txd.chan; | |
153 | struct idmac_channel *ichannel = to_idmac_chan(chan); | |
154 | struct mx3_camera_dev *mx3_cam = ichannel->client; | |
4f67130a GL |
155 | |
156 | dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n", | |
157 | desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0); | |
158 | ||
159 | spin_lock(&mx3_cam->lock); | |
160 | if (mx3_cam->active) { | |
379fa5d3 GL |
161 | struct vb2_buffer *vb = &mx3_cam->active->vb; |
162 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); | |
163 | ||
164 | list_del_init(&buf->queue); | |
165 | do_gettimeofday(&vb->v4l2_buf.timestamp); | |
166 | vb->v4l2_buf.field = mx3_cam->field; | |
167 | vb->v4l2_buf.sequence = mx3_cam->sequence++; | |
168 | vb2_buffer_done(vb, VB2_BUF_STATE_DONE); | |
4f67130a GL |
169 | } |
170 | ||
171 | if (list_empty(&mx3_cam->capture)) { | |
172 | mx3_cam->active = NULL; | |
173 | spin_unlock(&mx3_cam->lock); | |
174 | ||
175 | /* | |
176 | * stop capture - without further buffers IPU_CHA_BUF0_RDY will | |
177 | * not get updated | |
178 | */ | |
179 | return; | |
180 | } | |
181 | ||
182 | mx3_cam->active = list_entry(mx3_cam->capture.next, | |
379fa5d3 | 183 | struct mx3_camera_buffer, queue); |
4f67130a GL |
184 | spin_unlock(&mx3_cam->lock); |
185 | } | |
186 | ||
4f67130a GL |
187 | /* |
188 | * Videobuf operations | |
189 | */ | |
190 | ||
191 | /* | |
192 | * Calculate the __buffer__ (not data) size and number of buffers. | |
4f67130a | 193 | */ |
379fa5d3 | 194 | static int mx3_videobuf_setup(struct vb2_queue *vq, |
fc714e70 | 195 | const struct v4l2_format *fmt, |
379fa5d3 | 196 | unsigned int *count, unsigned int *num_planes, |
035aa147 | 197 | unsigned int sizes[], void *alloc_ctxs[]) |
4f67130a | 198 | { |
379fa5d3 | 199 | struct soc_camera_device *icd = soc_camera_from_vb2q(vq); |
7dfff953 | 200 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 201 | struct mx3_camera_dev *mx3_cam = ici->priv; |
4f67130a GL |
202 | |
203 | if (!mx3_cam->idmac_channel[0]) | |
204 | return -EINVAL; | |
205 | ||
07f92448 GL |
206 | if (fmt) { |
207 | const struct soc_camera_format_xlate *xlate = soc_camera_xlate_by_fourcc(icd, | |
208 | fmt->fmt.pix.pixelformat); | |
bed8d803 LP |
209 | unsigned int bytes_per_line; |
210 | int ret; | |
2b61d46e | 211 | |
07f92448 GL |
212 | if (!xlate) |
213 | return -EINVAL; | |
2b61d46e | 214 | |
bed8d803 LP |
215 | ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width, |
216 | xlate->host_fmt); | |
217 | if (ret < 0) | |
218 | return ret; | |
2b61d46e | 219 | |
bed8d803 LP |
220 | bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret); |
221 | ||
222 | ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line, | |
223 | fmt->fmt.pix.height); | |
224 | if (ret < 0) | |
225 | return ret; | |
226 | ||
227 | sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret); | |
07f92448 GL |
228 | } else { |
229 | /* Called from VIDIOC_REQBUFS or in compatibility mode */ | |
2b61d46e | 230 | sizes[0] = icd->sizeimage; |
07f92448 | 231 | } |
4f67130a | 232 | |
07f92448 | 233 | alloc_ctxs[0] = mx3_cam->alloc_ctx; |
4f67130a | 234 | |
07f92448 GL |
235 | if (!vq->num_buffers) |
236 | mx3_cam->sequence = 0; | |
4f67130a | 237 | |
07f92448 GL |
238 | if (!*count) |
239 | *count = 2; | |
4f67130a | 240 | |
07f92448 GL |
241 | /* If *num_planes != 0, we have already verified *count. */ |
242 | if (!*num_planes && | |
243 | sizes[0] * *count + mx3_cam->buf_total > MAX_VIDEO_MEM * 1024 * 1024) | |
244 | *count = (MAX_VIDEO_MEM * 1024 * 1024 - mx3_cam->buf_total) / | |
245 | sizes[0]; | |
4f67130a | 246 | |
07f92448 | 247 | *num_planes = 1; |
4f67130a | 248 | |
379fa5d3 | 249 | return 0; |
4f67130a GL |
250 | } |
251 | ||
252 | static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc) | |
253 | { | |
254 | /* Add more formats as need arises and test possibilities appear... */ | |
255 | switch (fourcc) { | |
4f67130a GL |
256 | case V4L2_PIX_FMT_RGB24: |
257 | return IPU_PIX_FMT_RGB24; | |
a48be1d6 AP |
258 | case V4L2_PIX_FMT_UYVY: |
259 | case V4L2_PIX_FMT_RGB565: | |
4f67130a GL |
260 | default: |
261 | return IPU_PIX_FMT_GENERIC; | |
262 | } | |
263 | } | |
264 | ||
379fa5d3 | 265 | static void mx3_videobuf_queue(struct vb2_buffer *vb) |
4f67130a | 266 | { |
379fa5d3 | 267 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 268 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 269 | struct mx3_camera_dev *mx3_cam = ici->priv; |
379fa5d3 | 270 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
07f92448 GL |
271 | struct scatterlist *sg = &buf->sg; |
272 | struct dma_async_tx_descriptor *txd; | |
273 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
4f67130a | 274 | struct idmac_video_param *video = &ichan->params.video; |
07f92448 | 275 | const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt; |
379fa5d3 | 276 | unsigned long flags; |
07f92448 GL |
277 | dma_cookie_t cookie; |
278 | size_t new_size; | |
279 | ||
2b61d46e | 280 | new_size = icd->sizeimage; |
07f92448 GL |
281 | |
282 | if (vb2_plane_size(vb, 0) < new_size) { | |
283 | dev_err(icd->parent, "Buffer #%d too small (%lu < %zu)\n", | |
284 | vb->v4l2_buf.index, vb2_plane_size(vb, 0), new_size); | |
285 | goto error; | |
286 | } | |
287 | ||
288 | if (buf->state == CSI_BUF_NEEDS_INIT) { | |
289 | sg_dma_address(sg) = vb2_dma_contig_plane_dma_addr(vb, 0); | |
290 | sg_dma_len(sg) = new_size; | |
291 | ||
16052827 | 292 | txd = dmaengine_prep_slave_sg( |
e0d23ef2 | 293 | &ichan->dma_chan, sg, 1, DMA_DEV_TO_MEM, |
07f92448 GL |
294 | DMA_PREP_INTERRUPT); |
295 | if (!txd) | |
296 | goto error; | |
297 | ||
298 | txd->callback_param = txd; | |
299 | txd->callback = mx3_cam_dma_done; | |
300 | ||
301 | buf->state = CSI_BUF_PREPARED; | |
302 | buf->txd = txd; | |
303 | } else { | |
304 | txd = buf->txd; | |
305 | } | |
306 | ||
307 | vb2_set_plane_payload(vb, 0, new_size); | |
4f67130a GL |
308 | |
309 | /* This is the configuration of one sg-element */ | |
07f92448 | 310 | video->out_pixel_fmt = fourcc_to_ipu_pix(host_fmt->fourcc); |
a48be1d6 AP |
311 | |
312 | if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) { | |
313 | /* | |
07f92448 GL |
314 | * If the IPU DMA channel is configured to transfer generic |
315 | * 8-bit data, we have to set up the geometry parameters | |
316 | * correctly, according to the current pixel format. The DMA | |
317 | * horizontal parameters in this case are expressed in bytes, | |
318 | * not in pixels. | |
a48be1d6 | 319 | */ |
1c0f95ee | 320 | video->out_width = icd->bytesperline; |
a48be1d6 | 321 | video->out_height = icd->user_height; |
1c0f95ee | 322 | video->out_stride = icd->bytesperline; |
a48be1d6 AP |
323 | } else { |
324 | /* | |
325 | * For IPU known formats the pixel unit will be managed | |
326 | * successfully by the IPU code | |
327 | */ | |
328 | video->out_width = icd->user_width; | |
329 | video->out_height = icd->user_height; | |
330 | video->out_stride = icd->user_width; | |
331 | } | |
4f67130a GL |
332 | |
333 | #ifdef DEBUG | |
334 | /* helps to see what DMA actually has written */ | |
379fa5d3 GL |
335 | if (vb2_plane_vaddr(vb, 0)) |
336 | memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0)); | |
4f67130a GL |
337 | #endif |
338 | ||
379fa5d3 GL |
339 | spin_lock_irqsave(&mx3_cam->lock, flags); |
340 | list_add_tail(&buf->queue, &mx3_cam->capture); | |
4f67130a | 341 | |
379fa5d3 | 342 | if (!mx3_cam->active) |
4f67130a | 343 | mx3_cam->active = buf; |
4f67130a | 344 | |
2dd54a54 | 345 | spin_unlock_irq(&mx3_cam->lock); |
4f67130a GL |
346 | |
347 | cookie = txd->tx_submit(txd); | |
7dfff953 | 348 | dev_dbg(icd->parent, "Submitted cookie %d DMA 0x%08x\n", |
0166b743 | 349 | cookie, sg_dma_address(&buf->sg)); |
2dd54a54 | 350 | |
4f67130a GL |
351 | if (cookie >= 0) |
352 | return; | |
353 | ||
379fa5d3 | 354 | spin_lock_irq(&mx3_cam->lock); |
4f67130a | 355 | |
379fa5d3 GL |
356 | /* Submit error */ |
357 | list_del_init(&buf->queue); | |
4f67130a GL |
358 | |
359 | if (mx3_cam->active == buf) | |
360 | mx3_cam->active = NULL; | |
379fa5d3 GL |
361 | |
362 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
07f92448 | 363 | error: |
379fa5d3 | 364 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); |
4f67130a GL |
365 | } |
366 | ||
379fa5d3 | 367 | static void mx3_videobuf_release(struct vb2_buffer *vb) |
4f67130a | 368 | { |
379fa5d3 | 369 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
7dfff953 | 370 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 371 | struct mx3_camera_dev *mx3_cam = ici->priv; |
379fa5d3 GL |
372 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
373 | struct dma_async_tx_descriptor *txd = buf->txd; | |
4f67130a GL |
374 | unsigned long flags; |
375 | ||
7dfff953 | 376 | dev_dbg(icd->parent, |
379fa5d3 | 377 | "Release%s DMA 0x%08x, queue %sempty\n", |
4f67130a | 378 | mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg), |
379fa5d3 GL |
379 | list_empty(&buf->queue) ? "" : "not "); |
380 | ||
4f67130a | 381 | spin_lock_irqsave(&mx3_cam->lock, flags); |
4f67130a | 382 | |
379fa5d3 GL |
383 | if (mx3_cam->active == buf) |
384 | mx3_cam->active = NULL; | |
385 | ||
386 | /* Doesn't hurt also if the list is empty */ | |
387 | list_del_init(&buf->queue); | |
388 | buf->state = CSI_BUF_NEEDS_INIT; | |
389 | ||
390 | if (txd) { | |
391 | buf->txd = NULL; | |
392 | if (mx3_cam->idmac_channel[0]) | |
393 | async_tx_ack(txd); | |
4f67130a | 394 | } |
379fa5d3 | 395 | |
4f67130a | 396 | spin_unlock_irqrestore(&mx3_cam->lock, flags); |
07f92448 GL |
397 | |
398 | mx3_cam->buf_total -= vb2_plane_size(vb, 0); | |
4f67130a GL |
399 | } |
400 | ||
379fa5d3 GL |
401 | static int mx3_videobuf_init(struct vb2_buffer *vb) |
402 | { | |
07f92448 GL |
403 | struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue); |
404 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); | |
405 | struct mx3_camera_dev *mx3_cam = ici->priv; | |
379fa5d3 | 406 | struct mx3_camera_buffer *buf = to_mx3_vb(vb); |
07f92448 | 407 | |
379fa5d3 GL |
408 | /* This is for locking debugging only */ |
409 | INIT_LIST_HEAD(&buf->queue); | |
410 | sg_init_table(&buf->sg, 1); | |
411 | ||
412 | buf->state = CSI_BUF_NEEDS_INIT; | |
07f92448 GL |
413 | |
414 | mx3_cam->buf_total += vb2_plane_size(vb, 0); | |
379fa5d3 GL |
415 | |
416 | return 0; | |
417 | } | |
418 | ||
08a31b96 GL |
419 | static int mx3_stop_streaming(struct vb2_queue *q) |
420 | { | |
421 | struct soc_camera_device *icd = soc_camera_from_vb2q(q); | |
7dfff953 | 422 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
08a31b96 GL |
423 | struct mx3_camera_dev *mx3_cam = ici->priv; |
424 | struct idmac_channel *ichan = mx3_cam->idmac_channel[0]; | |
08a31b96 GL |
425 | struct mx3_camera_buffer *buf, *tmp; |
426 | unsigned long flags; | |
427 | ||
428 | if (ichan) { | |
07f92448 GL |
429 | struct dma_chan *chan = &ichan->dma_chan; |
430 | chan->device->device_control(chan, DMA_PAUSE, 0); | |
08a31b96 GL |
431 | } |
432 | ||
433 | spin_lock_irqsave(&mx3_cam->lock, flags); | |
434 | ||
435 | mx3_cam->active = NULL; | |
436 | ||
437 | list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) { | |
08a31b96 | 438 | list_del_init(&buf->queue); |
07f92448 | 439 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); |
08a31b96 GL |
440 | } |
441 | ||
442 | spin_unlock_irqrestore(&mx3_cam->lock, flags); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
379fa5d3 GL |
447 | static struct vb2_ops mx3_videobuf_ops = { |
448 | .queue_setup = mx3_videobuf_setup, | |
379fa5d3 GL |
449 | .buf_queue = mx3_videobuf_queue, |
450 | .buf_cleanup = mx3_videobuf_release, | |
451 | .buf_init = mx3_videobuf_init, | |
452 | .wait_prepare = soc_camera_unlock, | |
453 | .wait_finish = soc_camera_lock, | |
08a31b96 | 454 | .stop_streaming = mx3_stop_streaming, |
4f67130a GL |
455 | }; |
456 | ||
379fa5d3 | 457 | static int mx3_camera_init_videobuf(struct vb2_queue *q, |
4f67130a GL |
458 | struct soc_camera_device *icd) |
459 | { | |
379fa5d3 GL |
460 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
461 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
462 | q->drv_priv = icd; | |
463 | q->ops = &mx3_videobuf_ops; | |
464 | q->mem_ops = &vb2_dma_contig_memops; | |
465 | q->buf_struct_size = sizeof(struct mx3_camera_buffer); | |
466 | ||
467 | return vb2_queue_init(q); | |
4f67130a GL |
468 | } |
469 | ||
470 | /* First part of ipu_csi_init_interface() */ | |
471 | static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam, | |
472 | struct soc_camera_device *icd) | |
473 | { | |
474 | u32 conf; | |
475 | long rate; | |
476 | ||
477 | /* Set default size: ipu_csi_set_window_size() */ | |
478 | csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE); | |
479 | /* ...and position to 0:0: ipu_csi_set_window_pos() */ | |
480 | conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
481 | csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL); | |
482 | ||
483 | /* We use only gated clock synchronisation mode so far */ | |
484 | conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT; | |
485 | ||
486 | /* Set generic data, platform-biggest bus-width */ | |
487 | conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
488 | ||
489 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
490 | conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
491 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
492 | conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
493 | else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
494 | conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
495 | else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/ | |
496 | conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
497 | ||
498 | if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC) | |
499 | conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT; | |
500 | if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC) | |
501 | conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT; | |
502 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) | |
503 | conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; | |
504 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) | |
505 | conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; | |
506 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) | |
507 | conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; | |
508 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) | |
509 | conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; | |
510 | ||
511 | /* ipu_csi_init_interface() */ | |
512 | csi_reg_write(mx3_cam, conf, CSI_SENS_CONF); | |
513 | ||
fdf7748b | 514 | clk_prepare_enable(mx3_cam->clk); |
4f67130a | 515 | rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk); |
7dfff953 | 516 | dev_dbg(icd->parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate); |
4f67130a GL |
517 | if (rate) |
518 | clk_set_rate(mx3_cam->clk, rate); | |
519 | } | |
520 | ||
521 | /* Called with .video_lock held */ | |
522 | static int mx3_camera_add_device(struct soc_camera_device *icd) | |
523 | { | |
7dfff953 | 524 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 525 | struct mx3_camera_dev *mx3_cam = ici->priv; |
4f67130a | 526 | |
979ea1dd GL |
527 | if (mx3_cam->icd) |
528 | return -EBUSY; | |
4f67130a GL |
529 | |
530 | mx3_camera_activate(mx3_cam, icd); | |
4f67130a | 531 | |
07f92448 | 532 | mx3_cam->buf_total = 0; |
4f67130a GL |
533 | mx3_cam->icd = icd; |
534 | ||
7dfff953 | 535 | dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n", |
40e2e092 GL |
536 | icd->devnum); |
537 | ||
538 | return 0; | |
4f67130a GL |
539 | } |
540 | ||
541 | /* Called with .video_lock held */ | |
542 | static void mx3_camera_remove_device(struct soc_camera_device *icd) | |
543 | { | |
7dfff953 | 544 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a GL |
545 | struct mx3_camera_dev *mx3_cam = ici->priv; |
546 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
547 | ||
548 | BUG_ON(icd != mx3_cam->icd); | |
549 | ||
550 | if (*ichan) { | |
551 | dma_release_channel(&(*ichan)->dma_chan); | |
552 | *ichan = NULL; | |
553 | } | |
554 | ||
fdf7748b | 555 | clk_disable_unprepare(mx3_cam->clk); |
4f67130a GL |
556 | |
557 | mx3_cam->icd = NULL; | |
558 | ||
7dfff953 | 559 | dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n", |
4f67130a GL |
560 | icd->devnum); |
561 | } | |
562 | ||
4f67130a GL |
563 | static int test_platform_param(struct mx3_camera_dev *mx3_cam, |
564 | unsigned char buswidth, unsigned long *flags) | |
565 | { | |
579cea03 GL |
566 | /* |
567 | * If requested data width is supported by the platform, use it or any | |
568 | * possible lower value - i.MX31 is smart enough to shift bits | |
569 | */ | |
570 | if (buswidth > fls(mx3_cam->width_flags)) | |
571 | return -EINVAL; | |
572 | ||
4f67130a GL |
573 | /* |
574 | * Platform specified synchronization and pixel clock polarities are | |
575 | * only a recommendation and are only used during probing. MX3x | |
576 | * camera interface only works in master mode, i.e., uses HSYNC and | |
577 | * VSYNC signals from the sensor | |
578 | */ | |
579cea03 GL |
579 | *flags = V4L2_MBUS_MASTER | |
580 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
581 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
582 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
583 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
584 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
585 | V4L2_MBUS_PCLK_SAMPLE_FALLING | | |
586 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
587 | V4L2_MBUS_DATA_ACTIVE_LOW; | |
4f67130a GL |
588 | |
589 | return 0; | |
590 | } | |
591 | ||
592 | static int mx3_camera_try_bus_param(struct soc_camera_device *icd, | |
593 | const unsigned int depth) | |
594 | { | |
579cea03 | 595 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 596 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 597 | struct mx3_camera_dev *mx3_cam = ici->priv; |
579cea03 GL |
598 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
599 | unsigned long bus_flags, common_flags; | |
4f67130a GL |
600 | int ret = test_platform_param(mx3_cam, depth, &bus_flags); |
601 | ||
7dfff953 | 602 | dev_dbg(icd->parent, "request bus width %d bit: %d\n", depth, ret); |
4f67130a GL |
603 | |
604 | if (ret < 0) | |
605 | return ret; | |
606 | ||
579cea03 GL |
607 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
608 | if (!ret) { | |
609 | common_flags = soc_mbus_config_compatible(&cfg, | |
610 | bus_flags); | |
611 | if (!common_flags) { | |
612 | dev_warn(icd->parent, | |
613 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
614 | cfg.flags, bus_flags); | |
615 | return -EINVAL; | |
616 | } | |
617 | } else if (ret != -ENOIOCTLCMD) { | |
618 | return ret; | |
619 | } | |
4f67130a | 620 | |
579cea03 | 621 | return 0; |
4f67130a GL |
622 | } |
623 | ||
624 | static bool chan_filter(struct dma_chan *chan, void *arg) | |
625 | { | |
626 | struct dma_chan_request *rq = arg; | |
627 | struct mx3_camera_pdata *pdata; | |
628 | ||
a8de6635 SH |
629 | if (!imx_dma_is_ipu(chan)) |
630 | return false; | |
631 | ||
4f67130a GL |
632 | if (!rq) |
633 | return false; | |
634 | ||
979ea1dd | 635 | pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data; |
4f67130a GL |
636 | |
637 | return rq->id == chan->chan_id && | |
638 | pdata->dma_dev == chan->device->dev; | |
639 | } | |
640 | ||
760697be | 641 | static const struct soc_mbus_pixelfmt mx3_camera_formats[] = { |
4f67130a | 642 | { |
760697be GL |
643 | .fourcc = V4L2_PIX_FMT_SBGGR8, |
644 | .name = "Bayer BGGR (sRGB) 8 bit", | |
645 | .bits_per_sample = 8, | |
646 | .packing = SOC_MBUS_PACKING_NONE, | |
647 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 648 | .layout = SOC_MBUS_LAYOUT_PACKED, |
4f67130a | 649 | }, { |
760697be GL |
650 | .fourcc = V4L2_PIX_FMT_GREY, |
651 | .name = "Monochrome 8 bit", | |
652 | .bits_per_sample = 8, | |
653 | .packing = SOC_MBUS_PACKING_NONE, | |
654 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 655 | .layout = SOC_MBUS_LAYOUT_PACKED, |
4f67130a GL |
656 | }, |
657 | }; | |
658 | ||
760697be GL |
659 | /* This will be corrected as we get more formats */ |
660 | static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
4f67130a | 661 | { |
760697be GL |
662 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
663 | (fmt->bits_per_sample == 8 && | |
664 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
665 | (fmt->bits_per_sample > 8 && | |
666 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
4f67130a GL |
667 | } |
668 | ||
3805f201 | 669 | static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
4f67130a GL |
670 | struct soc_camera_format_xlate *xlate) |
671 | { | |
760697be | 672 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 673 | struct device *dev = icd->parent; |
760697be GL |
674 | int formats = 0, ret; |
675 | enum v4l2_mbus_pixelcode code; | |
676 | const struct soc_mbus_pixelfmt *fmt; | |
4f67130a | 677 | |
760697be GL |
678 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); |
679 | if (ret < 0) | |
680 | /* No more formats */ | |
681 | return 0; | |
4f67130a | 682 | |
760697be GL |
683 | fmt = soc_mbus_get_fmtdesc(code); |
684 | if (!fmt) { | |
7dfff953 | 685 | dev_warn(icd->parent, |
d2dcad49 | 686 | "Unsupported format code #%u: %d\n", idx, code); |
4f67130a | 687 | return 0; |
760697be | 688 | } |
4f67130a | 689 | |
760697be GL |
690 | /* This also checks support for the requested bits-per-sample */ |
691 | ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample); | |
4f67130a GL |
692 | if (ret < 0) |
693 | return 0; | |
694 | ||
760697be GL |
695 | switch (code) { |
696 | case V4L2_MBUS_FMT_SBGGR10_1X10: | |
4f67130a GL |
697 | formats++; |
698 | if (xlate) { | |
760697be GL |
699 | xlate->host_fmt = &mx3_camera_formats[0]; |
700 | xlate->code = code; | |
4f67130a | 701 | xlate++; |
760697be GL |
702 | dev_dbg(dev, "Providing format %s using code %d\n", |
703 | mx3_camera_formats[0].name, code); | |
4f67130a | 704 | } |
760697be GL |
705 | break; |
706 | case V4L2_MBUS_FMT_Y10_1X10: | |
4f67130a GL |
707 | formats++; |
708 | if (xlate) { | |
760697be GL |
709 | xlate->host_fmt = &mx3_camera_formats[1]; |
710 | xlate->code = code; | |
4f67130a | 711 | xlate++; |
760697be GL |
712 | dev_dbg(dev, "Providing format %s using code %d\n", |
713 | mx3_camera_formats[1].name, code); | |
4f67130a | 714 | } |
760697be | 715 | break; |
4f67130a | 716 | default: |
760697be GL |
717 | if (!mx3_camera_packing_supported(fmt)) |
718 | return 0; | |
719 | } | |
720 | ||
721 | /* Generic pass-through */ | |
722 | formats++; | |
723 | if (xlate) { | |
724 | xlate->host_fmt = fmt; | |
725 | xlate->code = code; | |
a48be1d6 AP |
726 | dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n", |
727 | (fmt->fourcc >> (0*8)) & 0xFF, | |
728 | (fmt->fourcc >> (1*8)) & 0xFF, | |
729 | (fmt->fourcc >> (2*8)) & 0xFF, | |
730 | (fmt->fourcc >> (3*8)) & 0xFF); | |
760697be | 731 | xlate++; |
4f67130a GL |
732 | } |
733 | ||
734 | return formats; | |
735 | } | |
736 | ||
09e231b3 | 737 | static void configure_geometry(struct mx3_camera_dev *mx3_cam, |
a48be1d6 | 738 | unsigned int width, unsigned int height, |
d2dcad49 | 739 | const struct soc_mbus_pixelfmt *fmt) |
4f67130a | 740 | { |
4f67130a | 741 | u32 ctrl, width_field, height_field; |
a48be1d6 AP |
742 | |
743 | if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) { | |
744 | /* | |
745 | * As the CSI will be configured to output BAYER, here | |
746 | * the width parameter count the number of samples to | |
747 | * capture to complete the whole image width. | |
748 | */ | |
cc552b62 GL |
749 | unsigned int num, den; |
750 | int ret = soc_mbus_samples_per_pixel(fmt, &num, &den); | |
751 | BUG_ON(ret < 0); | |
752 | width = width * num / den; | |
a48be1d6 | 753 | } |
4f67130a GL |
754 | |
755 | /* Setup frame size - this cannot be changed on-the-fly... */ | |
6a6c8786 GL |
756 | width_field = width - 1; |
757 | height_field = height - 1; | |
4f67130a GL |
758 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE); |
759 | ||
760 | csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1); | |
761 | csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2); | |
762 | ||
763 | csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE); | |
764 | ||
765 | /* ...and position */ | |
766 | ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000; | |
767 | /* Sensor does the cropping */ | |
768 | csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL); | |
09e231b3 GL |
769 | } |
770 | ||
771 | static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam) | |
772 | { | |
773 | dma_cap_mask_t mask; | |
774 | struct dma_chan *chan; | |
775 | struct idmac_channel **ichan = &mx3_cam->idmac_channel[0]; | |
776 | /* We have to use IDMAC_IC_7 for Bayer / generic data */ | |
777 | struct dma_chan_request rq = {.mx3_cam = mx3_cam, | |
778 | .id = IDMAC_IC_7}; | |
779 | ||
09e231b3 GL |
780 | dma_cap_zero(mask); |
781 | dma_cap_set(DMA_SLAVE, mask); | |
782 | dma_cap_set(DMA_PRIVATE, mask); | |
783 | chan = dma_request_channel(mask, chan_filter, &rq); | |
784 | if (!chan) | |
785 | return -EBUSY; | |
786 | ||
787 | *ichan = to_idmac_chan(chan); | |
788 | (*ichan)->client = mx3_cam; | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
6a6c8786 GL |
793 | /* |
794 | * FIXME: learn to use stride != width, then we can keep stride properly aligned | |
795 | * and support arbitrary (even) widths. | |
796 | */ | |
e26b3144 | 797 | static inline void stride_align(__u32 *width) |
6a6c8786 | 798 | { |
d2dcad49 GL |
799 | if (ALIGN(*width, 8) < 4096) |
800 | *width = ALIGN(*width, 8); | |
6a6c8786 GL |
801 | else |
802 | *width = *width & ~7; | |
803 | } | |
804 | ||
805 | /* | |
806 | * As long as we don't implement host-side cropping and scaling, we can use | |
807 | * default g_crop and cropcap from soc_camera.c | |
808 | */ | |
09e231b3 | 809 | static int mx3_camera_set_crop(struct soc_camera_device *icd, |
08590b96 | 810 | struct v4l2_crop *a) |
09e231b3 | 811 | { |
08590b96 | 812 | struct v4l2_rect *rect = &a->c; |
7dfff953 | 813 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
09e231b3 | 814 | struct mx3_camera_dev *mx3_cam = ici->priv; |
c9c1f1c0 | 815 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
760697be | 816 | struct v4l2_mbus_framefmt mf; |
6a6c8786 | 817 | int ret; |
09e231b3 | 818 | |
6a6c8786 GL |
819 | soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); |
820 | soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); | |
821 | ||
822 | ret = v4l2_subdev_call(sd, video, s_crop, a); | |
823 | if (ret < 0) | |
824 | return ret; | |
825 | ||
d2dcad49 | 826 | /* The capture device might have changed its output sizes */ |
760697be | 827 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); |
6a6c8786 GL |
828 | if (ret < 0) |
829 | return ret; | |
830 | ||
d2dcad49 GL |
831 | if (mf.code != icd->current_fmt->code) |
832 | return -EINVAL; | |
833 | ||
760697be | 834 | if (mf.width & 7) { |
6a6c8786 | 835 | /* Ouch! We can only handle 8-byte aligned width... */ |
760697be GL |
836 | stride_align(&mf.width); |
837 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
09e231b3 GL |
838 | if (ret < 0) |
839 | return ret; | |
840 | } | |
841 | ||
379fa5d3 | 842 | if (mf.width != icd->user_width || mf.height != icd->user_height) |
d2dcad49 GL |
843 | configure_geometry(mx3_cam, mf.width, mf.height, |
844 | icd->current_fmt->host_fmt); | |
6a6c8786 | 845 | |
7dfff953 | 846 | dev_dbg(icd->parent, "Sensor cropped %dx%d\n", |
760697be | 847 | mf.width, mf.height); |
6a6c8786 | 848 | |
760697be GL |
849 | icd->user_width = mf.width; |
850 | icd->user_height = mf.height; | |
6a6c8786 GL |
851 | |
852 | return ret; | |
09e231b3 GL |
853 | } |
854 | ||
855 | static int mx3_camera_set_fmt(struct soc_camera_device *icd, | |
856 | struct v4l2_format *f) | |
857 | { | |
7dfff953 | 858 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
09e231b3 | 859 | struct mx3_camera_dev *mx3_cam = ici->priv; |
c9c1f1c0 | 860 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
861 | const struct soc_camera_format_xlate *xlate; |
862 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 863 | struct v4l2_mbus_framefmt mf; |
09e231b3 GL |
864 | int ret; |
865 | ||
866 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); | |
867 | if (!xlate) { | |
7dfff953 | 868 | dev_warn(icd->parent, "Format %x not found\n", |
0166b743 | 869 | pix->pixelformat); |
09e231b3 GL |
870 | return -EINVAL; |
871 | } | |
872 | ||
6a6c8786 | 873 | stride_align(&pix->width); |
7dfff953 | 874 | dev_dbg(icd->parent, "Set format %dx%d\n", pix->width, pix->height); |
6a6c8786 | 875 | |
09e231b3 GL |
876 | /* |
877 | * Might have to perform a complete interface initialisation like in | |
878 | * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider | |
879 | * mxc_v4l2_s_fmt() | |
880 | */ | |
881 | ||
d2dcad49 | 882 | configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt); |
4f67130a | 883 | |
760697be GL |
884 | mf.width = pix->width; |
885 | mf.height = pix->height; | |
886 | mf.field = pix->field; | |
887 | mf.colorspace = pix->colorspace; | |
888 | mf.code = xlate->code; | |
889 | ||
890 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
891 | if (ret < 0) | |
892 | return ret; | |
893 | ||
894 | if (mf.code != xlate->code) | |
895 | return -EINVAL; | |
896 | ||
379fa5d3 GL |
897 | if (!mx3_cam->idmac_channel[0]) { |
898 | ret = acquire_dma_channel(mx3_cam); | |
899 | if (ret < 0) | |
900 | return ret; | |
901 | } | |
902 | ||
760697be GL |
903 | pix->width = mf.width; |
904 | pix->height = mf.height; | |
905 | pix->field = mf.field; | |
379fa5d3 | 906 | mx3_cam->field = mf.field; |
760697be GL |
907 | pix->colorspace = mf.colorspace; |
908 | icd->current_fmt = xlate; | |
4f67130a | 909 | |
7dfff953 | 910 | dev_dbg(icd->parent, "Sensor set %dx%d\n", pix->width, pix->height); |
6a6c8786 | 911 | |
4f67130a GL |
912 | return ret; |
913 | } | |
914 | ||
915 | static int mx3_camera_try_fmt(struct soc_camera_device *icd, | |
916 | struct v4l2_format *f) | |
917 | { | |
c9c1f1c0 | 918 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
4f67130a GL |
919 | const struct soc_camera_format_xlate *xlate; |
920 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 921 | struct v4l2_mbus_framefmt mf; |
4f67130a | 922 | __u32 pixfmt = pix->pixelformat; |
4f67130a GL |
923 | int ret; |
924 | ||
925 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); | |
926 | if (pixfmt && !xlate) { | |
7dfff953 | 927 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
4f67130a GL |
928 | return -EINVAL; |
929 | } | |
930 | ||
931 | /* limit to MX3 hardware capabilities */ | |
932 | if (pix->height > 4096) | |
933 | pix->height = 4096; | |
934 | if (pix->width > 4096) | |
935 | pix->width = 4096; | |
936 | ||
4f67130a | 937 | /* limit to sensor capabilities */ |
760697be GL |
938 | mf.width = pix->width; |
939 | mf.height = pix->height; | |
940 | mf.field = pix->field; | |
941 | mf.colorspace = pix->colorspace; | |
942 | mf.code = xlate->code; | |
4f67130a | 943 | |
760697be GL |
944 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); |
945 | if (ret < 0) | |
946 | return ret; | |
4f67130a | 947 | |
760697be GL |
948 | pix->width = mf.width; |
949 | pix->height = mf.height; | |
950 | pix->colorspace = mf.colorspace; | |
951 | ||
952 | switch (mf.field) { | |
953 | case V4L2_FIELD_ANY: | |
4f67130a | 954 | pix->field = V4L2_FIELD_NONE; |
760697be GL |
955 | break; |
956 | case V4L2_FIELD_NONE: | |
957 | break; | |
958 | default: | |
7dfff953 | 959 | dev_err(icd->parent, "Field type %d unsupported.\n", |
760697be GL |
960 | mf.field); |
961 | ret = -EINVAL; | |
4f67130a GL |
962 | } |
963 | ||
964 | return ret; | |
965 | } | |
966 | ||
57bee29d | 967 | static int mx3_camera_reqbufs(struct soc_camera_device *icd, |
4f67130a GL |
968 | struct v4l2_requestbuffers *p) |
969 | { | |
970 | return 0; | |
971 | } | |
972 | ||
973 | static unsigned int mx3_camera_poll(struct file *file, poll_table *pt) | |
974 | { | |
57bee29d | 975 | struct soc_camera_device *icd = file->private_data; |
4f67130a | 976 | |
379fa5d3 | 977 | return vb2_poll(&icd->vb2_vidq, file, pt); |
4f67130a GL |
978 | } |
979 | ||
980 | static int mx3_camera_querycap(struct soc_camera_host *ici, | |
981 | struct v4l2_capability *cap) | |
982 | { | |
983 | /* cap->name is set by the firendly caller:-> */ | |
984 | strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card)); | |
4f67130a GL |
985 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
8843d119 | 990 | static int mx3_camera_set_bus_param(struct soc_camera_device *icd) |
4f67130a | 991 | { |
579cea03 | 992 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 993 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
4f67130a | 994 | struct mx3_camera_dev *mx3_cam = ici->priv; |
579cea03 | 995 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 996 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
579cea03 | 997 | unsigned long bus_flags, common_flags; |
4f67130a | 998 | u32 dw, sens_conf; |
760697be GL |
999 | const struct soc_mbus_pixelfmt *fmt; |
1000 | int buswidth; | |
1001 | int ret; | |
4f67130a | 1002 | const struct soc_camera_format_xlate *xlate; |
7dfff953 | 1003 | struct device *dev = icd->parent; |
4f67130a | 1004 | |
760697be GL |
1005 | fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code); |
1006 | if (!fmt) | |
1007 | return -EINVAL; | |
1008 | ||
4f67130a GL |
1009 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1010 | if (!xlate) { | |
0166b743 | 1011 | dev_warn(dev, "Format %x not found\n", pixfmt); |
4f67130a GL |
1012 | return -EINVAL; |
1013 | } | |
1014 | ||
579cea03 GL |
1015 | buswidth = fmt->bits_per_sample; |
1016 | ret = test_platform_param(mx3_cam, buswidth, &bus_flags); | |
1017 | ||
760697be | 1018 | dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret); |
4f67130a GL |
1019 | |
1020 | if (ret < 0) | |
1021 | return ret; | |
1022 | ||
579cea03 GL |
1023 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1024 | if (!ret) { | |
1025 | common_flags = soc_mbus_config_compatible(&cfg, | |
1026 | bus_flags); | |
1027 | if (!common_flags) { | |
1028 | dev_warn(icd->parent, | |
1029 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1030 | cfg.flags, bus_flags); | |
1031 | return -EINVAL; | |
1032 | } | |
1033 | } else if (ret != -ENOIOCTLCMD) { | |
1034 | return ret; | |
1035 | } else { | |
1036 | common_flags = bus_flags; | |
4f67130a GL |
1037 | } |
1038 | ||
579cea03 GL |
1039 | dev_dbg(dev, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n", |
1040 | cfg.flags, bus_flags, common_flags); | |
1041 | ||
4f67130a | 1042 | /* Make choices, based on platform preferences */ |
579cea03 GL |
1043 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1044 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
4f67130a | 1045 | if (mx3_cam->platform_flags & MX3_CAMERA_HSP) |
579cea03 | 1046 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
4f67130a | 1047 | else |
579cea03 | 1048 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
4f67130a GL |
1049 | } |
1050 | ||
579cea03 GL |
1051 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1052 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
4f67130a | 1053 | if (mx3_cam->platform_flags & MX3_CAMERA_VSP) |
579cea03 | 1054 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
4f67130a | 1055 | else |
579cea03 | 1056 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
4f67130a GL |
1057 | } |
1058 | ||
579cea03 GL |
1059 | if ((common_flags & V4L2_MBUS_DATA_ACTIVE_HIGH) && |
1060 | (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)) { | |
4f67130a | 1061 | if (mx3_cam->platform_flags & MX3_CAMERA_DP) |
579cea03 | 1062 | common_flags &= ~V4L2_MBUS_DATA_ACTIVE_HIGH; |
4f67130a | 1063 | else |
579cea03 | 1064 | common_flags &= ~V4L2_MBUS_DATA_ACTIVE_LOW; |
4f67130a GL |
1065 | } |
1066 | ||
579cea03 GL |
1067 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1068 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
4f67130a | 1069 | if (mx3_cam->platform_flags & MX3_CAMERA_PCP) |
579cea03 | 1070 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
4f67130a | 1071 | else |
579cea03 | 1072 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
4f67130a GL |
1073 | } |
1074 | ||
579cea03 GL |
1075 | cfg.flags = common_flags; |
1076 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1077 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1078 | dev_dbg(dev, "camera s_mbus_config(0x%lx) returned %d\n", | |
40e2e092 | 1079 | common_flags, ret); |
4f67130a | 1080 | return ret; |
40e2e092 | 1081 | } |
4f67130a GL |
1082 | |
1083 | /* | |
1084 | * So far only gated clock mode is supported. Add a line | |
1085 | * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) | | |
1086 | * below and select the required mode when supporting other | |
1087 | * synchronisation protocols. | |
1088 | */ | |
1089 | sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) & | |
1090 | ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) | | |
1091 | (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) | | |
1092 | (1 << CSI_SENS_CONF_DATA_POL_SHIFT) | | |
1093 | (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) | | |
1094 | (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) | | |
1095 | (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT)); | |
1096 | ||
1097 | /* TODO: Support RGB and YUV formats */ | |
1098 | ||
1099 | /* This has been set in mx3_camera_activate(), but we clear it above */ | |
1100 | sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER; | |
1101 | ||
579cea03 | 1102 | if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
4f67130a | 1103 | sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT; |
579cea03 | 1104 | if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
4f67130a | 1105 | sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT; |
579cea03 | 1106 | if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
4f67130a | 1107 | sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT; |
579cea03 | 1108 | if (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW) |
4f67130a GL |
1109 | sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT; |
1110 | ||
1111 | /* Just do what we're asked to do */ | |
760697be | 1112 | switch (xlate->host_fmt->bits_per_sample) { |
4f67130a GL |
1113 | case 4: |
1114 | dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1115 | break; | |
1116 | case 8: | |
1117 | dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1118 | break; | |
1119 | case 10: | |
1120 | dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1121 | break; | |
1122 | default: | |
1123 | /* | |
1124 | * Actually it can only be 15 now, default is just to silence | |
1125 | * compiler warnings | |
1126 | */ | |
1127 | case 15: | |
1128 | dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT; | |
1129 | } | |
1130 | ||
1131 | csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF); | |
1132 | ||
0166b743 | 1133 | dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw); |
4f67130a GL |
1134 | |
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static struct soc_camera_host_ops mx3_soc_camera_host_ops = { | |
1139 | .owner = THIS_MODULE, | |
1140 | .add = mx3_camera_add_device, | |
1141 | .remove = mx3_camera_remove_device, | |
09e231b3 | 1142 | .set_crop = mx3_camera_set_crop, |
4f67130a GL |
1143 | .set_fmt = mx3_camera_set_fmt, |
1144 | .try_fmt = mx3_camera_try_fmt, | |
1145 | .get_formats = mx3_camera_get_formats, | |
379fa5d3 | 1146 | .init_videobuf2 = mx3_camera_init_videobuf, |
4f67130a GL |
1147 | .reqbufs = mx3_camera_reqbufs, |
1148 | .poll = mx3_camera_poll, | |
1149 | .querycap = mx3_camera_querycap, | |
1150 | .set_bus_param = mx3_camera_set_bus_param, | |
1151 | }; | |
1152 | ||
e36bc31f | 1153 | static int __devinit mx3_camera_probe(struct platform_device *pdev) |
4f67130a GL |
1154 | { |
1155 | struct mx3_camera_dev *mx3_cam; | |
1156 | struct resource *res; | |
1157 | void __iomem *base; | |
1158 | int err = 0; | |
1159 | struct soc_camera_host *soc_host; | |
1160 | ||
1161 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1162 | if (!res) { | |
1163 | err = -ENODEV; | |
1164 | goto egetres; | |
1165 | } | |
1166 | ||
101b25b5 | 1167 | mx3_cam = vzalloc(sizeof(*mx3_cam)); |
4f67130a GL |
1168 | if (!mx3_cam) { |
1169 | dev_err(&pdev->dev, "Could not allocate mx3 camera object\n"); | |
1170 | err = -ENOMEM; | |
1171 | goto ealloc; | |
1172 | } | |
4f67130a | 1173 | |
b71df97a | 1174 | mx3_cam->clk = clk_get(&pdev->dev, NULL); |
4f67130a GL |
1175 | if (IS_ERR(mx3_cam->clk)) { |
1176 | err = PTR_ERR(mx3_cam->clk); | |
1177 | goto eclkget; | |
1178 | } | |
1179 | ||
4f67130a GL |
1180 | mx3_cam->pdata = pdev->dev.platform_data; |
1181 | mx3_cam->platform_flags = mx3_cam->pdata->flags; | |
1182 | if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 | | |
1183 | MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 | | |
1184 | MX3_CAMERA_DATAWIDTH_15))) { | |
5d28d525 GL |
1185 | /* |
1186 | * Platform hasn't set available data widths. This is bad. | |
1187 | * Warn and use a default. | |
1188 | */ | |
4f67130a GL |
1189 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1190 | "data widths, using default 8 bit\n"); | |
1191 | mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8; | |
1192 | } | |
579cea03 GL |
1193 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4) |
1194 | mx3_cam->width_flags = 1 << 3; | |
1195 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8) | |
1196 | mx3_cam->width_flags |= 1 << 7; | |
1197 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10) | |
1198 | mx3_cam->width_flags |= 1 << 9; | |
1199 | if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15) | |
1200 | mx3_cam->width_flags |= 1 << 14; | |
4f67130a GL |
1201 | |
1202 | mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000; | |
1203 | if (!mx3_cam->mclk) { | |
1204 | dev_warn(&pdev->dev, | |
1205 | "mclk_10khz == 0! Please, fix your platform data. " | |
1206 | "Using default 20MHz\n"); | |
1207 | mx3_cam->mclk = 20000000; | |
1208 | } | |
1209 | ||
1210 | /* list of video-buffers */ | |
1211 | INIT_LIST_HEAD(&mx3_cam->capture); | |
1212 | spin_lock_init(&mx3_cam->lock); | |
1213 | ||
40e2e092 | 1214 | base = ioremap(res->start, resource_size(res)); |
4f67130a | 1215 | if (!base) { |
40e2e092 | 1216 | pr_err("Couldn't map %x@%x\n", resource_size(res), res->start); |
4f67130a GL |
1217 | err = -ENOMEM; |
1218 | goto eioremap; | |
1219 | } | |
1220 | ||
1221 | mx3_cam->base = base; | |
4f67130a GL |
1222 | |
1223 | soc_host = &mx3_cam->soc_host; | |
1224 | soc_host->drv_name = MX3_CAM_DRV_NAME; | |
1225 | soc_host->ops = &mx3_soc_camera_host_ops; | |
1226 | soc_host->priv = mx3_cam; | |
979ea1dd | 1227 | soc_host->v4l2_dev.dev = &pdev->dev; |
4f67130a | 1228 | soc_host->nr = pdev->id; |
eff505fa | 1229 | |
379fa5d3 GL |
1230 | mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); |
1231 | if (IS_ERR(mx3_cam->alloc_ctx)) { | |
1232 | err = PTR_ERR(mx3_cam->alloc_ctx); | |
1233 | goto eallocctx; | |
1234 | } | |
1235 | ||
4f67130a GL |
1236 | err = soc_camera_host_register(soc_host); |
1237 | if (err) | |
1238 | goto ecamhostreg; | |
1239 | ||
1240 | /* IDMAC interface */ | |
1241 | dmaengine_get(); | |
1242 | ||
1243 | return 0; | |
1244 | ||
1245 | ecamhostreg: | |
379fa5d3 GL |
1246 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
1247 | eallocctx: | |
4f67130a GL |
1248 | iounmap(base); |
1249 | eioremap: | |
1250 | clk_put(mx3_cam->clk); | |
1251 | eclkget: | |
1252 | vfree(mx3_cam); | |
1253 | ealloc: | |
1254 | egetres: | |
1255 | return err; | |
1256 | } | |
1257 | ||
1258 | static int __devexit mx3_camera_remove(struct platform_device *pdev) | |
1259 | { | |
eff505fa GL |
1260 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1261 | struct mx3_camera_dev *mx3_cam = container_of(soc_host, | |
1262 | struct mx3_camera_dev, soc_host); | |
4f67130a GL |
1263 | |
1264 | clk_put(mx3_cam->clk); | |
1265 | ||
eff505fa | 1266 | soc_camera_host_unregister(soc_host); |
4f67130a GL |
1267 | |
1268 | iounmap(mx3_cam->base); | |
1269 | ||
1270 | /* | |
1271 | * The channel has either not been allocated, | |
1272 | * or should have been released | |
1273 | */ | |
1274 | if (WARN_ON(mx3_cam->idmac_channel[0])) | |
1275 | dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan); | |
1276 | ||
379fa5d3 GL |
1277 | vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx); |
1278 | ||
4f67130a GL |
1279 | vfree(mx3_cam); |
1280 | ||
1281 | dmaengine_put(); | |
1282 | ||
4f67130a GL |
1283 | return 0; |
1284 | } | |
1285 | ||
1286 | static struct platform_driver mx3_camera_driver = { | |
1287 | .driver = { | |
1288 | .name = MX3_CAM_DRV_NAME, | |
1289 | }, | |
1290 | .probe = mx3_camera_probe, | |
e36bc31f | 1291 | .remove = __devexit_p(mx3_camera_remove), |
4f67130a GL |
1292 | }; |
1293 | ||
1d6629b1 | 1294 | module_platform_driver(mx3_camera_driver); |
4f67130a GL |
1295 | |
1296 | MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver"); | |
1297 | MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>"); | |
1298 | MODULE_LICENSE("GPL v2"); | |
64dc3c1a | 1299 | MODULE_VERSION("0.2.3"); |
40e2e092 | 1300 | MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME); |