[media] V4L: document the new VIDIOC_CREATE_BUFS and VIDIOC_PREPARE_BUF ioctl()s
[linux-2.6-block.git] / drivers / media / video / marvell-ccic / mcam-core.c
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1/*
2 * The Marvell camera core. This device appears in a number of settings,
3 * so it needs platform-specific support outside of the core.
4 *
5 * Copyright 2011 Jonathan Corbet corbet@lwn.net
6 */
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/fs.h>
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10#include <linux/mm.h>
11#include <linux/i2c.h>
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
abfa3df3 14#include <linux/slab.h>
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15#include <linux/device.h>
16#include <linux/wait.h>
17#include <linux/list.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
abfa3df3 20#include <linux/vmalloc.h>
abfa3df3 21#include <linux/io.h>
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22#include <linux/videodev2.h>
23#include <media/v4l2-device.h>
24#include <media/v4l2-ioctl.h>
25#include <media/v4l2-chip-ident.h>
26#include <media/ov7670.h>
27#include <media/videobuf2-vmalloc.h>
a9b36e85 28#include <media/videobuf2-dma-contig.h>
cbc4f3a2 29#include <media/videobuf2-dma-sg.h>
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30
31#include "mcam-core.h"
32
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33/*
34 * Basic frame stats - to be deleted shortly
35 */
36static int frames;
37static int singles;
38static int delivered;
abfa3df3 39
7498469f 40#ifdef MCAM_MODE_VMALLOC
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41/*
42 * Internal DMA buffer management. Since the controller cannot do S/G I/O,
43 * we must have physically contiguous buffers to bring frames into.
44 * These parameters control how many buffers we use, whether we
45 * allocate them at load time (better chance of success, but nails down
46 * memory) or when somebody tries to use the camera (riskier), and,
47 * for load-time allocation, how big they should be.
48 *
49 * The controller can cycle through three buffers. We could use
50 * more by flipping pointers around, but it probably makes little
51 * sense.
52 */
53
54static int alloc_bufs_at_read;
55module_param(alloc_bufs_at_read, bool, 0444);
56MODULE_PARM_DESC(alloc_bufs_at_read,
57 "Non-zero value causes DMA buffers to be allocated when the "
58 "video capture device is read, rather than at module load "
59 "time. This saves memory, but decreases the chances of "
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60 "successfully getting those buffers. This parameter is "
61 "only used in the vmalloc buffer mode");
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62
63static int n_dma_bufs = 3;
64module_param(n_dma_bufs, uint, 0644);
65MODULE_PARM_DESC(n_dma_bufs,
66 "The number of DMA buffers to allocate. Can be either two "
67 "(saves memory, makes timing tighter) or three.");
68
69static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
70module_param(dma_buf_size, uint, 0444);
71MODULE_PARM_DESC(dma_buf_size,
72 "The size of the allocated DMA buffers. If actual operating "
73 "parameters require larger buffers, an attempt to reallocate "
74 "will be made.");
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75#else /* MCAM_MODE_VMALLOC */
76static const int alloc_bufs_at_read = 0;
77static const int n_dma_bufs = 3; /* Used by S/G_PARM */
78#endif /* MCAM_MODE_VMALLOC */
abfa3df3 79
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80static int flip;
81module_param(flip, bool, 0444);
82MODULE_PARM_DESC(flip,
83 "If set, the sensor will be instructed to flip the image "
84 "vertically.");
85
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86static int buffer_mode = -1;
87module_param(buffer_mode, int, 0444);
88MODULE_PARM_DESC(buffer_mode,
89 "Set the buffer mode to be used; default is to go with what "
90 "the platform driver asks for. Set to 0 for vmalloc, 1 for "
91 "DMA contiguous.");
92
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93/*
94 * Status flags. Always manipulated with bit operations.
95 */
96#define CF_BUF0_VALID 0 /* Buffers valid - first three */
97#define CF_BUF1_VALID 1
98#define CF_BUF2_VALID 2
99#define CF_DMA_ACTIVE 3 /* A frame is incoming */
100#define CF_CONFIG_NEEDED 4 /* Must configure hardware */
a9b36e85 101#define CF_SINGLE_BUFFER 5 /* Running with a single buffer */
cbc4f3a2 102#define CF_SG_RESTART 6 /* SG restart needed */
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103
104#define sensor_call(cam, o, f, args...) \
105 v4l2_subdev_call(cam->sensor, o, f, ##args)
106
107static struct mcam_format_struct {
108 __u8 *desc;
109 __u32 pixelformat;
110 int bpp; /* Bytes per pixel */
111 enum v4l2_mbus_pixelcode mbus_code;
112} mcam_formats[] = {
113 {
114 .desc = "YUYV 4:2:2",
115 .pixelformat = V4L2_PIX_FMT_YUYV,
116 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
117 .bpp = 2,
118 },
119 {
120 .desc = "RGB 444",
121 .pixelformat = V4L2_PIX_FMT_RGB444,
122 .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE,
123 .bpp = 2,
124 },
125 {
126 .desc = "RGB 565",
127 .pixelformat = V4L2_PIX_FMT_RGB565,
128 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE,
129 .bpp = 2,
130 },
131 {
132 .desc = "Raw RGB Bayer",
133 .pixelformat = V4L2_PIX_FMT_SBGGR8,
134 .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8,
135 .bpp = 1
136 },
137};
138#define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
139
140static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
141{
142 unsigned i;
143
144 for (i = 0; i < N_MCAM_FMTS; i++)
145 if (mcam_formats[i].pixelformat == pixelformat)
146 return mcam_formats + i;
147 /* Not found? Then return the first format. */
148 return mcam_formats;
149}
150
151/*
d43dae75 152 * The default format we use until somebody says otherwise.
abfa3df3 153 */
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154static const struct v4l2_pix_format mcam_def_pix_format = {
155 .width = VGA_WIDTH,
156 .height = VGA_HEIGHT,
157 .pixelformat = V4L2_PIX_FMT_YUYV,
158 .field = V4L2_FIELD_NONE,
159 .bytesperline = VGA_WIDTH*2,
160 .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
161};
abfa3df3 162
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163static const enum v4l2_mbus_pixelcode mcam_def_mbus_code =
164 V4L2_MBUS_FMT_YUYV8_2X8;
abfa3df3 165
abfa3df3 166
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167/*
168 * The two-word DMA descriptor format used by the Armada 610 and like. There
169 * Is a three-word format as well (set C1_DESC_3WORD) where the third
170 * word is a pointer to the next descriptor, but we don't use it. Two-word
171 * descriptors have to be contiguous in memory.
172 */
173struct mcam_dma_desc {
174 u32 dma_addr;
175 u32 segment_len;
176};
177
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178/*
179 * Our buffer type for working with videobuf2. Note that the vb2
180 * developers have decreed that struct vb2_buffer must be at the
181 * beginning of this structure.
182 */
183struct mcam_vb_buffer {
184 struct vb2_buffer vb_buf;
185 struct list_head queue;
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186 struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
187 dma_addr_t dma_desc_pa; /* Descriptor physical address */
188 int dma_desc_nent; /* Number of mapped descriptors */
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189};
190
191static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_buffer *vb)
192{
193 return container_of(vb, struct mcam_vb_buffer, vb_buf);
194}
195
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196/*
197 * Hand a completed buffer back to user space.
198 */
199static void mcam_buffer_done(struct mcam_camera *cam, int frame,
200 struct vb2_buffer *vbuf)
201{
202 vbuf->v4l2_buf.bytesused = cam->pix_format.sizeimage;
203 vbuf->v4l2_buf.sequence = cam->buf_seq[frame];
204 vb2_set_plane_payload(vbuf, 0, cam->pix_format.sizeimage);
205 vb2_buffer_done(vbuf, VB2_BUF_STATE_DONE);
206}
207
208
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209
210/*
67a8dbbc 211 * Debugging and related.
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212 */
213#define cam_err(cam, fmt, arg...) \
214 dev_err((cam)->dev, fmt, ##arg);
215#define cam_warn(cam, fmt, arg...) \
216 dev_warn((cam)->dev, fmt, ##arg);
217#define cam_dbg(cam, fmt, arg...) \
218 dev_dbg((cam)->dev, fmt, ##arg);
219
220
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221/*
222 * Flag manipulation helpers
223 */
224static void mcam_reset_buffers(struct mcam_camera *cam)
225{
226 int i;
227
228 cam->next_buf = -1;
229 for (i = 0; i < cam->nbufs; i++)
230 clear_bit(i, &cam->flags);
231}
232
233static inline int mcam_needs_config(struct mcam_camera *cam)
234{
235 return test_bit(CF_CONFIG_NEEDED, &cam->flags);
236}
237
238static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
239{
240 if (needed)
241 set_bit(CF_CONFIG_NEEDED, &cam->flags);
242 else
243 clear_bit(CF_CONFIG_NEEDED, &cam->flags);
244}
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245
246/* ------------------------------------------------------------------- */
247/*
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248 * Make the controller start grabbing images. Everything must
249 * be set up before doing this.
abfa3df3 250 */
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251static void mcam_ctlr_start(struct mcam_camera *cam)
252{
253 /* set_bit performs a read, so no other barrier should be
254 needed here */
255 mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
256}
257
258static void mcam_ctlr_stop(struct mcam_camera *cam)
259{
260 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
261}
262
263/* ------------------------------------------------------------------- */
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264
265#ifdef MCAM_MODE_VMALLOC
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266/*
267 * Code specific to the vmalloc buffer mode.
268 */
269
270/*
271 * Allocate in-kernel DMA buffers for vmalloc mode.
272 */
273static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
274{
275 int i;
276
277 mcam_set_config_needed(cam, 1);
278 if (loadtime)
279 cam->dma_buf_size = dma_buf_size;
280 else
281 cam->dma_buf_size = cam->pix_format.sizeimage;
282 if (n_dma_bufs > 3)
283 n_dma_bufs = 3;
284
285 cam->nbufs = 0;
286 for (i = 0; i < n_dma_bufs; i++) {
287 cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
288 cam->dma_buf_size, cam->dma_handles + i,
289 GFP_KERNEL);
290 if (cam->dma_bufs[i] == NULL) {
291 cam_warn(cam, "Failed to allocate DMA buffer\n");
292 break;
293 }
294 (cam->nbufs)++;
295 }
296
297 switch (cam->nbufs) {
298 case 1:
299 dma_free_coherent(cam->dev, cam->dma_buf_size,
300 cam->dma_bufs[0], cam->dma_handles[0]);
301 cam->nbufs = 0;
302 case 0:
303 cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
304 return -ENOMEM;
305
306 case 2:
307 if (n_dma_bufs > 2)
308 cam_warn(cam, "Will limp along with only 2 buffers\n");
309 break;
310 }
311 return 0;
312}
313
314static void mcam_free_dma_bufs(struct mcam_camera *cam)
315{
316 int i;
317
318 for (i = 0; i < cam->nbufs; i++) {
319 dma_free_coherent(cam->dev, cam->dma_buf_size,
320 cam->dma_bufs[i], cam->dma_handles[i]);
321 cam->dma_bufs[i] = NULL;
322 }
323 cam->nbufs = 0;
324}
325
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326
327/*
a9b36e85 328 * Set up DMA buffers when operating in vmalloc mode
abfa3df3 329 */
a9b36e85 330static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
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331{
332 /*
333 * Store the first two Y buffers (we aren't supporting
334 * planar formats for now, so no UV bufs). Then either
335 * set the third if it exists, or tell the controller
336 * to just use two.
337 */
338 mcam_reg_write(cam, REG_Y0BAR, cam->dma_handles[0]);
339 mcam_reg_write(cam, REG_Y1BAR, cam->dma_handles[1]);
340 if (cam->nbufs > 2) {
341 mcam_reg_write(cam, REG_Y2BAR, cam->dma_handles[2]);
342 mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
343 } else
344 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
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345 if (cam->chip_id == V4L2_IDENT_CAFE)
346 mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
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347}
348
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349/*
350 * Copy data out to user space in the vmalloc case
351 */
352static void mcam_frame_tasklet(unsigned long data)
353{
354 struct mcam_camera *cam = (struct mcam_camera *) data;
355 int i;
356 unsigned long flags;
357 struct mcam_vb_buffer *buf;
358
359 spin_lock_irqsave(&cam->dev_lock, flags);
360 for (i = 0; i < cam->nbufs; i++) {
361 int bufno = cam->next_buf;
362
363 if (cam->state != S_STREAMING || bufno < 0)
364 break; /* I/O got stopped */
365 if (++(cam->next_buf) >= cam->nbufs)
366 cam->next_buf = 0;
367 if (!test_bit(bufno, &cam->flags))
368 continue;
369 if (list_empty(&cam->buffers)) {
370 singles++;
371 break; /* Leave it valid, hope for better later */
372 }
373 delivered++;
374 clear_bit(bufno, &cam->flags);
375 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
376 queue);
377 list_del_init(&buf->queue);
378 /*
379 * Drop the lock during the big copy. This *should* be safe...
380 */
381 spin_unlock_irqrestore(&cam->dev_lock, flags);
382 memcpy(vb2_plane_vaddr(&buf->vb_buf, 0), cam->dma_bufs[bufno],
383 cam->pix_format.sizeimage);
384 mcam_buffer_done(cam, bufno, &buf->vb_buf);
385 spin_lock_irqsave(&cam->dev_lock, flags);
386 }
387 spin_unlock_irqrestore(&cam->dev_lock, flags);
388}
389
390
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391/*
392 * Make sure our allocated buffers are up to the task.
393 */
394static int mcam_check_dma_buffers(struct mcam_camera *cam)
395{
396 if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
397 mcam_free_dma_bufs(cam);
398 if (cam->nbufs == 0)
399 return mcam_alloc_dma_bufs(cam, 0);
400 return 0;
401}
402
403static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
404{
405 tasklet_schedule(&cam->s_tasklet);
406}
407
408#else /* MCAM_MODE_VMALLOC */
409
410static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
411{
412 return 0;
413}
414
415static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
416{
417 return;
418}
419
420static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
421{
422 return 0;
423}
424
425
426
427#endif /* MCAM_MODE_VMALLOC */
428
429
430#ifdef MCAM_MODE_DMA_CONTIG
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431/* ---------------------------------------------------------------------- */
432/*
433 * DMA-contiguous code.
434 */
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435/*
436 * Set up a contiguous buffer for the given frame. Here also is where
437 * the underrun strategy is set: if there is no buffer available, reuse
438 * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to
439 * keep the interrupt handler from giving that buffer back to user
440 * space. In this way, we always have a buffer to DMA to and don't
441 * have to try to play games stopping and restarting the controller.
442 */
443static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
444{
445 struct mcam_vb_buffer *buf;
446 /*
447 * If there are no available buffers, go into single mode
448 */
449 if (list_empty(&cam->buffers)) {
450 buf = cam->vb_bufs[frame ^ 0x1];
451 cam->vb_bufs[frame] = buf;
452 mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR,
ba7fcb0c 453 vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0));
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454 set_bit(CF_SINGLE_BUFFER, &cam->flags);
455 singles++;
456 return;
457 }
458 /*
459 * OK, we have a buffer we can use.
460 */
461 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
462 list_del_init(&buf->queue);
463 mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR,
ba7fcb0c 464 vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0));
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465 cam->vb_bufs[frame] = buf;
466 clear_bit(CF_SINGLE_BUFFER, &cam->flags);
467}
468
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469/*
470 * Initial B_DMA_contig setup.
471 */
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472static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
473{
474 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
475 cam->nbufs = 2;
476 mcam_set_contig_buffer(cam, 0);
477 mcam_set_contig_buffer(cam, 1);
478}
479
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480/*
481 * Frame completion handling.
482 */
483static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
484{
485 struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
486
487 if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
488 delivered++;
489 mcam_buffer_done(cam, frame, &buf->vb_buf);
490 }
491 mcam_set_contig_buffer(cam, frame);
492}
493
7498469f 494#endif /* MCAM_MODE_DMA_CONTIG */
d43dae75 495
7498469f 496#ifdef MCAM_MODE_DMA_SG
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497/* ---------------------------------------------------------------------- */
498/*
499 * Scatter/gather-specific code.
500 */
a9b36e85 501
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502/*
503 * Set up the next buffer for S/G I/O; caller should be sure that
504 * the controller is stopped and a buffer is available.
505 */
506static void mcam_sg_next_buffer(struct mcam_camera *cam)
a9b36e85 507{
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508 struct mcam_vb_buffer *buf;
509
510 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
511 list_del_init(&buf->queue);
512 mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
513 mcam_reg_write(cam, REG_DESC_LEN_Y,
514 buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
515 mcam_reg_write(cam, REG_DESC_LEN_U, 0);
516 mcam_reg_write(cam, REG_DESC_LEN_V, 0);
517 cam->vb_bufs[0] = buf;
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518}
519
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520/*
521 * Initial B_DMA_sg setup
522 */
523static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
524{
525 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
526 mcam_sg_next_buffer(cam);
527 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
528 cam->nbufs = 3;
529}
530
d43dae75 531
cbc4f3a2 532/*
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533 * Frame completion with S/G is trickier. We can't muck with
534 * a descriptor chain on the fly, since the controller buffers it
535 * internally. So we have to actually stop and restart; Marvell
536 * says this is the way to do it.
537 *
538 * Of course, stopping is easier said than done; experience shows
539 * that the controller can start a frame *after* C0_ENABLE has been
540 * cleared. So when running in S/G mode, the controller is "stopped"
541 * on receipt of the start-of-frame interrupt. That means we can
542 * safely change the DMA descriptor array here and restart things
543 * (assuming there's another buffer waiting to go).
544 */
545static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
546{
547 struct mcam_vb_buffer *buf = cam->vb_bufs[0];
548
549 /*
550 * Very Bad Not Good Things happen if you don't clear
551 * C1_DESC_ENA before making any descriptor changes.
552 */
553 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
554 /*
555 * If we have another buffer available, put it in and
556 * restart the engine.
557 */
558 if (!list_empty(&cam->buffers)) {
559 mcam_sg_next_buffer(cam);
560 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
561 mcam_ctlr_start(cam);
562 /*
563 * Otherwise set CF_SG_RESTART and the controller will
564 * be restarted once another buffer shows up.
565 */
566 } else {
567 set_bit(CF_SG_RESTART, &cam->flags);
568 singles++;
569 }
570 /*
571 * Now we can give the completed frame back to user space.
572 */
573 delivered++;
574 mcam_buffer_done(cam, frame, &buf->vb_buf);
575}
576
577
578/*
579 * Scatter/gather mode requires stopping the controller between
580 * frames so we can put in a new DMA descriptor array. If no new
581 * buffer exists at frame completion, the controller is left stopped;
582 * this function is charged with gettig things going again.
583 */
584static void mcam_sg_restart(struct mcam_camera *cam)
585{
586 mcam_ctlr_dma_sg(cam);
587 mcam_ctlr_start(cam);
588 clear_bit(CF_SG_RESTART, &cam->flags);
589}
590
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591#else /* MCAM_MODE_DMA_SG */
592
593static inline void mcam_sg_restart(struct mcam_camera *cam)
594{
595 return;
596}
597
598#endif /* MCAM_MODE_DMA_SG */
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599
600/* ---------------------------------------------------------------------- */
601/*
602 * Buffer-mode-independent controller code.
603 */
604
605/*
606 * Image format setup
cbc4f3a2 607 */
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608static void mcam_ctlr_image(struct mcam_camera *cam)
609{
610 int imgsz;
611 struct v4l2_pix_format *fmt = &cam->pix_format;
612
613 imgsz = ((fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK) |
614 (fmt->bytesperline & IMGSZ_H_MASK);
615 mcam_reg_write(cam, REG_IMGSIZE, imgsz);
616 mcam_reg_write(cam, REG_IMGOFFSET, 0);
617 /* YPITCH just drops the last two bits */
618 mcam_reg_write_mask(cam, REG_IMGPITCH, fmt->bytesperline,
619 IMGP_YP_MASK);
620 /*
621 * Tell the controller about the image format we are using.
622 */
623 switch (cam->pix_format.pixelformat) {
624 case V4L2_PIX_FMT_YUYV:
625 mcam_reg_write_mask(cam, REG_CTRL0,
626 C0_DF_YUV|C0_YUV_PACKED|C0_YUVE_YUYV,
627 C0_DF_MASK);
628 break;
629
630 case V4L2_PIX_FMT_RGB444:
631 mcam_reg_write_mask(cam, REG_CTRL0,
632 C0_DF_RGB|C0_RGBF_444|C0_RGB4_XRGB,
633 C0_DF_MASK);
634 /* Alpha value? */
635 break;
636
637 case V4L2_PIX_FMT_RGB565:
638 mcam_reg_write_mask(cam, REG_CTRL0,
639 C0_DF_RGB|C0_RGBF_565|C0_RGB5_BGGR,
640 C0_DF_MASK);
641 break;
642
643 default:
644 cam_err(cam, "Unknown format %x\n", cam->pix_format.pixelformat);
645 break;
646 }
647 /*
648 * Make sure it knows we want to use hsync/vsync.
649 */
650 mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC,
651 C0_SIFM_MASK);
652}
653
654
655/*
656 * Configure the controller for operation; caller holds the
657 * device mutex.
658 */
659static int mcam_ctlr_configure(struct mcam_camera *cam)
660{
661 unsigned long flags;
662
663 spin_lock_irqsave(&cam->dev_lock, flags);
7498469f 664 cam->dma_setup(cam);
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665 mcam_ctlr_image(cam);
666 mcam_set_config_needed(cam, 0);
cbc4f3a2 667 clear_bit(CF_SG_RESTART, &cam->flags);
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668 spin_unlock_irqrestore(&cam->dev_lock, flags);
669 return 0;
670}
671
672static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
673{
674 /*
675 * Clear any pending interrupts, since we do not
676 * expect to have I/O active prior to enabling.
677 */
678 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
679 mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
680}
681
682static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
683{
684 mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
685}
686
abfa3df3 687
cbc4f3a2 688
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689static void mcam_ctlr_init(struct mcam_camera *cam)
690{
691 unsigned long flags;
692
693 spin_lock_irqsave(&cam->dev_lock, flags);
694 /*
695 * Make sure it's not powered down.
696 */
697 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
698 /*
699 * Turn off the enable bit. It sure should be off anyway,
700 * but it's good to be sure.
701 */
702 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
703 /*
704 * Clock the sensor appropriately. Controller clock should
705 * be 48MHz, sensor "typical" value is half that.
706 */
707 mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
708 spin_unlock_irqrestore(&cam->dev_lock, flags);
709}
710
711
712/*
713 * Stop the controller, and don't return until we're really sure that no
714 * further DMA is going on.
715 */
716static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
717{
718 unsigned long flags;
719
720 /*
721 * Theory: stop the camera controller (whether it is operating
722 * or not). Delay briefly just in case we race with the SOF
723 * interrupt, then wait until no DMA is active.
724 */
725 spin_lock_irqsave(&cam->dev_lock, flags);
cbc4f3a2 726 clear_bit(CF_SG_RESTART, &cam->flags);
abfa3df3 727 mcam_ctlr_stop(cam);
cbc4f3a2 728 cam->state = S_IDLE;
abfa3df3 729 spin_unlock_irqrestore(&cam->dev_lock, flags);
cbc4f3a2 730 msleep(40);
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731 if (test_bit(CF_DMA_ACTIVE, &cam->flags))
732 cam_err(cam, "Timeout waiting for DMA to end\n");
733 /* This would be bad news - what now? */
734 spin_lock_irqsave(&cam->dev_lock, flags);
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735 mcam_ctlr_irq_disable(cam);
736 spin_unlock_irqrestore(&cam->dev_lock, flags);
737}
738
739/*
740 * Power up and down.
741 */
742static void mcam_ctlr_power_up(struct mcam_camera *cam)
743{
744 unsigned long flags;
745
746 spin_lock_irqsave(&cam->dev_lock, flags);
abfa3df3 747 cam->plat_power_up(cam);
67a8dbbc 748 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
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749 spin_unlock_irqrestore(&cam->dev_lock, flags);
750 msleep(5); /* Just to be sure */
751}
752
753static void mcam_ctlr_power_down(struct mcam_camera *cam)
754{
755 unsigned long flags;
756
757 spin_lock_irqsave(&cam->dev_lock, flags);
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758 /*
759 * School of hard knocks department: be sure we do any register
760 * twiddling on the controller *before* calling the platform
761 * power down routine.
762 */
abfa3df3 763 mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
67a8dbbc 764 cam->plat_power_down(cam);
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765 spin_unlock_irqrestore(&cam->dev_lock, flags);
766}
767
768/* -------------------------------------------------------------------- */
769/*
770 * Communications with the sensor.
771 */
772
773static int __mcam_cam_reset(struct mcam_camera *cam)
774{
775 return sensor_call(cam, core, reset, 0);
776}
777
778/*
779 * We have found the sensor on the i2c. Let's try to have a
780 * conversation.
781 */
782static int mcam_cam_init(struct mcam_camera *cam)
783{
784 struct v4l2_dbg_chip_ident chip;
785 int ret;
786
787 mutex_lock(&cam->s_mutex);
788 if (cam->state != S_NOTREADY)
789 cam_warn(cam, "Cam init with device in funky state %d",
790 cam->state);
791 ret = __mcam_cam_reset(cam);
792 if (ret)
793 goto out;
794 chip.ident = V4L2_IDENT_NONE;
795 chip.match.type = V4L2_CHIP_MATCH_I2C_ADDR;
796 chip.match.addr = cam->sensor_addr;
797 ret = sensor_call(cam, core, g_chip_ident, &chip);
798 if (ret)
799 goto out;
800 cam->sensor_type = chip.ident;
801 if (cam->sensor_type != V4L2_IDENT_OV7670) {
802 cam_err(cam, "Unsupported sensor type 0x%x", cam->sensor_type);
803 ret = -EINVAL;
804 goto out;
805 }
806/* Get/set parameters? */
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807 ret = 0;
808 cam->state = S_IDLE;
809out:
810 mcam_ctlr_power_down(cam);
811 mutex_unlock(&cam->s_mutex);
812 return ret;
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813}
814
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815/*
816 * Configure the sensor to match the parameters we have. Caller should
817 * hold s_mutex
818 */
819static int mcam_cam_set_flip(struct mcam_camera *cam)
abfa3df3 820{
d43dae75 821 struct v4l2_control ctrl;
abfa3df3 822
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823 memset(&ctrl, 0, sizeof(ctrl));
824 ctrl.id = V4L2_CID_VFLIP;
825 ctrl.value = flip;
826 return sensor_call(cam, core, s_ctrl, &ctrl);
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827}
828
829
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830static int mcam_cam_configure(struct mcam_camera *cam)
831{
832 struct v4l2_mbus_framefmt mbus_fmt;
833 int ret;
abfa3df3 834
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835 v4l2_fill_mbus_format(&mbus_fmt, &cam->pix_format, cam->mbus_code);
836 ret = sensor_call(cam, core, init, 0);
837 if (ret == 0)
838 ret = sensor_call(cam, video, s_mbus_fmt, &mbus_fmt);
839 /*
840 * OV7670 does weird things if flip is set *before* format...
841 */
842 ret += mcam_cam_set_flip(cam);
843 return ret;
844}
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845
846/*
847 * Get everything ready, and start grabbing frames.
848 */
a9b36e85 849static int mcam_read_setup(struct mcam_camera *cam)
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850{
851 int ret;
852 unsigned long flags;
853
854 /*
855 * Configuration. If we still don't have DMA buffers,
856 * make one last, desperate attempt.
857 */
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858 if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
859 mcam_alloc_dma_bufs(cam, 0))
860 return -ENOMEM;
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861
862 if (mcam_needs_config(cam)) {
863 mcam_cam_configure(cam);
864 ret = mcam_ctlr_configure(cam);
865 if (ret)
866 return ret;
867 }
868
869 /*
870 * Turn it loose.
871 */
872 spin_lock_irqsave(&cam->dev_lock, flags);
873 mcam_reset_buffers(cam);
874 mcam_ctlr_irq_enable(cam);
a9b36e85 875 cam->state = S_STREAMING;
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876 mcam_ctlr_start(cam);
877 spin_unlock_irqrestore(&cam->dev_lock, flags);
878 return 0;
879}
880
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881/* ----------------------------------------------------------------------- */
882/*
883 * Videobuf2 interface code.
884 */
abfa3df3 885
b5210fd2 886static int mcam_vb_queue_setup(struct vb2_queue *vq, unsigned int *nbufs,
035aa147 887 unsigned int *num_planes, unsigned int sizes[],
b5210fd2 888 void *alloc_ctxs[])
abfa3df3 889{
b5210fd2 890 struct mcam_camera *cam = vb2_get_drv_priv(vq);
cbc4f3a2 891 int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
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892
893 sizes[0] = cam->pix_format.sizeimage;
894 *num_planes = 1; /* Someday we have to support planar formats... */
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895 if (*nbufs < minbufs)
896 *nbufs = minbufs;
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897 if (cam->buffer_mode == B_DMA_contig)
898 alloc_ctxs[0] = cam->vb_alloc_ctx;
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899 return 0;
900}
901
cbc4f3a2 902
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903static void mcam_vb_buf_queue(struct vb2_buffer *vb)
904{
905 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
906 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
907 unsigned long flags;
a9b36e85 908 int start;
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909
910 spin_lock_irqsave(&cam->dev_lock, flags);
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911 start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
912 list_add(&mvb->queue, &cam->buffers);
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913 if (test_bit(CF_SG_RESTART, &cam->flags))
914 mcam_sg_restart(cam);
b5210fd2 915 spin_unlock_irqrestore(&cam->dev_lock, flags);
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916 if (start)
917 mcam_read_setup(cam);
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918}
919
cbc4f3a2 920
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921/*
922 * vb2 uses these to release the mutex when waiting in dqbuf. I'm
923 * not actually sure we need to do this (I'm not sure that vb2_dqbuf() needs
924 * to be called with the mutex held), but better safe than sorry.
925 */
926static void mcam_vb_wait_prepare(struct vb2_queue *vq)
927{
928 struct mcam_camera *cam = vb2_get_drv_priv(vq);
929
930 mutex_unlock(&cam->s_mutex);
931}
932
933static void mcam_vb_wait_finish(struct vb2_queue *vq)
934{
935 struct mcam_camera *cam = vb2_get_drv_priv(vq);
abfa3df3 936
abfa3df3 937 mutex_lock(&cam->s_mutex);
b5210fd2 938}
abfa3df3 939
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940/*
941 * These need to be called with the mutex held from vb2
942 */
bd323e28 943static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
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944{
945 struct mcam_camera *cam = vb2_get_drv_priv(vq);
abfa3df3 946
bd323e28
MS
947 if (cam->state != S_IDLE) {
948 INIT_LIST_HEAD(&cam->buffers);
a9b36e85 949 return -EINVAL;
bd323e28 950 }
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951 cam->sequence = 0;
952 /*
953 * Videobuf2 sneakily hoards all the buffers and won't
954 * give them to us until *after* streaming starts. But
955 * we can't actually start streaming until we have a
956 * destination. So go into a wait state and hope they
957 * give us buffers soon.
958 */
959 if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
960 cam->state = S_BUFWAIT;
961 return 0;
abfa3df3 962 }
a9b36e85 963 return mcam_read_setup(cam);
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964}
965
966static int mcam_vb_stop_streaming(struct vb2_queue *vq)
967{
968 struct mcam_camera *cam = vb2_get_drv_priv(vq);
969 unsigned long flags;
970
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971 if (cam->state == S_BUFWAIT) {
972 /* They never gave us buffers */
973 cam->state = S_IDLE;
974 return 0;
975 }
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976 if (cam->state != S_STREAMING)
977 return -EINVAL;
978 mcam_ctlr_stop_dma(cam);
abfa3df3 979 /*
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980 * VB2 reclaims the buffers, so we need to forget
981 * about them.
abfa3df3 982 */
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983 spin_lock_irqsave(&cam->dev_lock, flags);
984 INIT_LIST_HEAD(&cam->buffers);
985 spin_unlock_irqrestore(&cam->dev_lock, flags);
986 return 0;
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987}
988
989
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990static const struct vb2_ops mcam_vb2_ops = {
991 .queue_setup = mcam_vb_queue_setup,
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992 .buf_queue = mcam_vb_buf_queue,
993 .start_streaming = mcam_vb_start_streaming,
994 .stop_streaming = mcam_vb_stop_streaming,
995 .wait_prepare = mcam_vb_wait_prepare,
996 .wait_finish = mcam_vb_wait_finish,
997};
abfa3df3 998
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999
1000#ifdef MCAM_MODE_DMA_SG
cbc4f3a2 1001/*
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1002 * Scatter/gather mode uses all of the above functions plus a
1003 * few extras to deal with DMA mapping.
cbc4f3a2 1004 */
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1005static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1006{
1007 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1008 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1009 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1010
1011 mvb->dma_desc = dma_alloc_coherent(cam->dev,
1012 ndesc * sizeof(struct mcam_dma_desc),
1013 &mvb->dma_desc_pa, GFP_KERNEL);
1014 if (mvb->dma_desc == NULL) {
1015 cam_err(cam, "Unable to get DMA descriptor array\n");
1016 return -ENOMEM;
1017 }
1018 return 0;
1019}
1020
1021static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1022{
1023 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1024 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1025 struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
1026 struct mcam_dma_desc *desc = mvb->dma_desc;
1027 struct scatterlist *sg;
1028 int i;
1029
1030 mvb->dma_desc_nent = dma_map_sg(cam->dev, sgd->sglist, sgd->num_pages,
1031 DMA_FROM_DEVICE);
1032 if (mvb->dma_desc_nent <= 0)
1033 return -EIO; /* Not sure what's right here */
1034 for_each_sg(sgd->sglist, sg, mvb->dma_desc_nent, i) {
1035 desc->dma_addr = sg_dma_address(sg);
1036 desc->segment_len = sg_dma_len(sg);
1037 desc++;
1038 }
1039 return 0;
1040}
1041
1042static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb)
1043{
1044 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1045 struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
1046
1047 dma_unmap_sg(cam->dev, sgd->sglist, sgd->num_pages, DMA_FROM_DEVICE);
1048 return 0;
1049}
1050
1051static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1052{
1053 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1054 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1055 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1056
1057 dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1058 mvb->dma_desc, mvb->dma_desc_pa);
1059}
1060
1061
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1062static const struct vb2_ops mcam_vb2_sg_ops = {
1063 .queue_setup = mcam_vb_queue_setup,
1064 .buf_init = mcam_vb_sg_buf_init,
1065 .buf_prepare = mcam_vb_sg_buf_prepare,
1066 .buf_queue = mcam_vb_buf_queue,
1067 .buf_finish = mcam_vb_sg_buf_finish,
1068 .buf_cleanup = mcam_vb_sg_buf_cleanup,
1069 .start_streaming = mcam_vb_start_streaming,
1070 .stop_streaming = mcam_vb_stop_streaming,
1071 .wait_prepare = mcam_vb_wait_prepare,
1072 .wait_finish = mcam_vb_wait_finish,
1073};
1074
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1075#endif /* MCAM_MODE_DMA_SG */
1076
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1077static int mcam_setup_vb2(struct mcam_camera *cam)
1078{
1079 struct vb2_queue *vq = &cam->vb_queue;
abfa3df3 1080
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1081 memset(vq, 0, sizeof(*vq));
1082 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
b5210fd2 1083 vq->drv_priv = cam;
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1084 INIT_LIST_HEAD(&cam->buffers);
1085 switch (cam->buffer_mode) {
1086 case B_DMA_contig:
7498469f 1087#ifdef MCAM_MODE_DMA_CONTIG
cbc4f3a2 1088 vq->ops = &mcam_vb2_ops;
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1089 vq->mem_ops = &vb2_dma_contig_memops;
1090 cam->vb_alloc_ctx = vb2_dma_contig_init_ctx(cam->dev);
cbc4f3a2 1091 vq->io_modes = VB2_MMAP | VB2_USERPTR;
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1092 cam->dma_setup = mcam_ctlr_dma_contig;
1093 cam->frame_complete = mcam_dma_contig_done;
1094#endif
cbc4f3a2
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1095 break;
1096 case B_DMA_sg:
7498469f 1097#ifdef MCAM_MODE_DMA_SG
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1098 vq->ops = &mcam_vb2_sg_ops;
1099 vq->mem_ops = &vb2_dma_sg_memops;
1100 vq->io_modes = VB2_MMAP | VB2_USERPTR;
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1101 cam->dma_setup = mcam_ctlr_dma_sg;
1102 cam->frame_complete = mcam_dma_sg_done;
1103#endif
cbc4f3a2
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1104 break;
1105 case B_vmalloc:
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1106#ifdef MCAM_MODE_VMALLOC
1107 tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1108 (unsigned long) cam);
cbc4f3a2 1109 vq->ops = &mcam_vb2_ops;
a9b36e85 1110 vq->mem_ops = &vb2_vmalloc_memops;
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1111 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1112 vq->io_modes = VB2_MMAP;
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1113 cam->dma_setup = mcam_ctlr_dma_vmalloc;
1114 cam->frame_complete = mcam_vmalloc_done;
1115#endif
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1116 break;
1117 }
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1118 return vb2_queue_init(vq);
1119}
1120
1121static void mcam_cleanup_vb2(struct mcam_camera *cam)
1122{
1123 vb2_queue_release(&cam->vb_queue);
7498469f 1124#ifdef MCAM_MODE_DMA_CONTIG
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1125 if (cam->buffer_mode == B_DMA_contig)
1126 vb2_dma_contig_cleanup_ctx(cam->vb_alloc_ctx);
7498469f 1127#endif
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1128}
1129
abfa3df3 1130
d43dae75 1131/* ---------------------------------------------------------------------- */
abfa3df3 1132/*
d43dae75 1133 * The long list of V4L2 ioctl() operations.
abfa3df3
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1134 */
1135
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1136static int mcam_vidioc_streamon(struct file *filp, void *priv,
1137 enum v4l2_buf_type type)
1138{
1139 struct mcam_camera *cam = filp->private_data;
b5210fd2 1140 int ret;
abfa3df3 1141
abfa3df3 1142 mutex_lock(&cam->s_mutex);
b5210fd2 1143 ret = vb2_streamon(&cam->vb_queue, type);
abfa3df3 1144 mutex_unlock(&cam->s_mutex);
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1145 return ret;
1146}
1147
1148
1149static int mcam_vidioc_streamoff(struct file *filp, void *priv,
1150 enum v4l2_buf_type type)
1151{
1152 struct mcam_camera *cam = filp->private_data;
b5210fd2 1153 int ret;
abfa3df3 1154
abfa3df3 1155 mutex_lock(&cam->s_mutex);
b5210fd2 1156 ret = vb2_streamoff(&cam->vb_queue, type);
abfa3df3 1157 mutex_unlock(&cam->s_mutex);
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1158 return ret;
1159}
1160
1161
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1162static int mcam_vidioc_reqbufs(struct file *filp, void *priv,
1163 struct v4l2_requestbuffers *req)
1164{
1165 struct mcam_camera *cam = filp->private_data;
b5210fd2 1166 int ret;
abfa3df3 1167
abfa3df3 1168 mutex_lock(&cam->s_mutex);
b5210fd2 1169 ret = vb2_reqbufs(&cam->vb_queue, req);
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1170 mutex_unlock(&cam->s_mutex);
1171 return ret;
1172}
1173
1174
1175static int mcam_vidioc_querybuf(struct file *filp, void *priv,
1176 struct v4l2_buffer *buf)
1177{
1178 struct mcam_camera *cam = filp->private_data;
b5210fd2 1179 int ret;
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1180
1181 mutex_lock(&cam->s_mutex);
d43dae75 1182 ret = vb2_querybuf(&cam->vb_queue, buf);
abfa3df3 1183 mutex_unlock(&cam->s_mutex);
d43dae75 1184 return ret;
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1185}
1186
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1187static int mcam_vidioc_qbuf(struct file *filp, void *priv,
1188 struct v4l2_buffer *buf)
1189{
1190 struct mcam_camera *cam = filp->private_data;
1191 int ret;
abfa3df3 1192
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1193 mutex_lock(&cam->s_mutex);
1194 ret = vb2_qbuf(&cam->vb_queue, buf);
1195 mutex_unlock(&cam->s_mutex);
1196 return ret;
1197}
abfa3df3 1198
d43dae75
JC
1199static int mcam_vidioc_dqbuf(struct file *filp, void *priv,
1200 struct v4l2_buffer *buf)
abfa3df3
JC
1201{
1202 struct mcam_camera *cam = filp->private_data;
b5210fd2 1203 int ret;
abfa3df3 1204
b5210fd2 1205 mutex_lock(&cam->s_mutex);
d43dae75 1206 ret = vb2_dqbuf(&cam->vb_queue, buf, filp->f_flags & O_NONBLOCK);
b5210fd2
JC
1207 mutex_unlock(&cam->s_mutex);
1208 return ret;
abfa3df3
JC
1209}
1210
1211
1212
1213static int mcam_vidioc_queryctrl(struct file *filp, void *priv,
1214 struct v4l2_queryctrl *qc)
1215{
1216 struct mcam_camera *cam = priv;
1217 int ret;
1218
1219 mutex_lock(&cam->s_mutex);
1220 ret = sensor_call(cam, core, queryctrl, qc);
1221 mutex_unlock(&cam->s_mutex);
1222 return ret;
1223}
1224
1225
1226static int mcam_vidioc_g_ctrl(struct file *filp, void *priv,
1227 struct v4l2_control *ctrl)
1228{
1229 struct mcam_camera *cam = priv;
1230 int ret;
1231
1232 mutex_lock(&cam->s_mutex);
1233 ret = sensor_call(cam, core, g_ctrl, ctrl);
1234 mutex_unlock(&cam->s_mutex);
1235 return ret;
1236}
1237
1238
1239static int mcam_vidioc_s_ctrl(struct file *filp, void *priv,
1240 struct v4l2_control *ctrl)
1241{
1242 struct mcam_camera *cam = priv;
1243 int ret;
1244
1245 mutex_lock(&cam->s_mutex);
1246 ret = sensor_call(cam, core, s_ctrl, ctrl);
1247 mutex_unlock(&cam->s_mutex);
1248 return ret;
1249}
1250
1251
abfa3df3
JC
1252static int mcam_vidioc_querycap(struct file *file, void *priv,
1253 struct v4l2_capability *cap)
1254{
1255 strcpy(cap->driver, "marvell_ccic");
1256 strcpy(cap->card, "marvell_ccic");
1257 cap->version = 1;
1258 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
1259 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1260 return 0;
1261}
1262
1263
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JC
1264static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1265 void *priv, struct v4l2_fmtdesc *fmt)
1266{
1267 if (fmt->index >= N_MCAM_FMTS)
1268 return -EINVAL;
1269 strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1270 sizeof(fmt->description));
1271 fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1272 return 0;
1273}
1274
1275static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1276 struct v4l2_format *fmt)
1277{
1278 struct mcam_camera *cam = priv;
1279 struct mcam_format_struct *f;
1280 struct v4l2_pix_format *pix = &fmt->fmt.pix;
1281 struct v4l2_mbus_framefmt mbus_fmt;
1282 int ret;
1283
1284 f = mcam_find_format(pix->pixelformat);
1285 pix->pixelformat = f->pixelformat;
1286 v4l2_fill_mbus_format(&mbus_fmt, pix, f->mbus_code);
1287 mutex_lock(&cam->s_mutex);
1288 ret = sensor_call(cam, video, try_mbus_fmt, &mbus_fmt);
1289 mutex_unlock(&cam->s_mutex);
1290 v4l2_fill_pix_format(pix, &mbus_fmt);
1291 pix->bytesperline = pix->width * f->bpp;
1292 pix->sizeimage = pix->height * pix->bytesperline;
1293 return ret;
1294}
1295
1296static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1297 struct v4l2_format *fmt)
1298{
1299 struct mcam_camera *cam = priv;
1300 struct mcam_format_struct *f;
1301 int ret;
1302
1303 /*
1304 * Can't do anything if the device is not idle
1305 * Also can't if there are streaming buffers in place.
1306 */
b5210fd2 1307 if (cam->state != S_IDLE || cam->vb_queue.num_buffers > 0)
abfa3df3
JC
1308 return -EBUSY;
1309
1310 f = mcam_find_format(fmt->fmt.pix.pixelformat);
1311
1312 /*
1313 * See if the formatting works in principle.
1314 */
1315 ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1316 if (ret)
1317 return ret;
1318 /*
1319 * Now we start to change things for real, so let's do it
1320 * under lock.
1321 */
1322 mutex_lock(&cam->s_mutex);
1323 cam->pix_format = fmt->fmt.pix;
1324 cam->mbus_code = f->mbus_code;
1325
1326 /*
1327 * Make sure we have appropriate DMA buffers.
1328 */
a9b36e85 1329 if (cam->buffer_mode == B_vmalloc) {
7498469f
JC
1330 ret = mcam_check_dma_buffers(cam);
1331 if (ret)
1332 goto out;
abfa3df3 1333 }
a9b36e85
JC
1334 mcam_set_config_needed(cam, 1);
1335 ret = 0;
abfa3df3
JC
1336out:
1337 mutex_unlock(&cam->s_mutex);
1338 return ret;
1339}
1340
1341/*
1342 * Return our stored notion of how the camera is/should be configured.
1343 * The V4l2 spec wants us to be smarter, and actually get this from
1344 * the camera (and not mess with it at open time). Someday.
1345 */
1346static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1347 struct v4l2_format *f)
1348{
1349 struct mcam_camera *cam = priv;
1350
1351 f->fmt.pix = cam->pix_format;
1352 return 0;
1353}
1354
1355/*
1356 * We only have one input - the sensor - so minimize the nonsense here.
1357 */
1358static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1359 struct v4l2_input *input)
1360{
1361 if (input->index != 0)
1362 return -EINVAL;
1363
1364 input->type = V4L2_INPUT_TYPE_CAMERA;
1365 input->std = V4L2_STD_ALL; /* Not sure what should go here */
1366 strcpy(input->name, "Camera");
1367 return 0;
1368}
1369
1370static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1371{
1372 *i = 0;
1373 return 0;
1374}
1375
1376static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1377{
1378 if (i != 0)
1379 return -EINVAL;
1380 return 0;
1381}
1382
1383/* from vivi.c */
1384static int mcam_vidioc_s_std(struct file *filp, void *priv, v4l2_std_id *a)
1385{
1386 return 0;
1387}
1388
1389/*
1390 * G/S_PARM. Most of this is done by the sensor, but we are
1391 * the level which controls the number of read buffers.
1392 */
1393static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1394 struct v4l2_streamparm *parms)
1395{
1396 struct mcam_camera *cam = priv;
1397 int ret;
1398
1399 mutex_lock(&cam->s_mutex);
1400 ret = sensor_call(cam, video, g_parm, parms);
1401 mutex_unlock(&cam->s_mutex);
1402 parms->parm.capture.readbuffers = n_dma_bufs;
1403 return ret;
1404}
1405
1406static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1407 struct v4l2_streamparm *parms)
1408{
1409 struct mcam_camera *cam = priv;
1410 int ret;
1411
1412 mutex_lock(&cam->s_mutex);
1413 ret = sensor_call(cam, video, s_parm, parms);
1414 mutex_unlock(&cam->s_mutex);
1415 parms->parm.capture.readbuffers = n_dma_bufs;
1416 return ret;
1417}
1418
1419static int mcam_vidioc_g_chip_ident(struct file *file, void *priv,
1420 struct v4l2_dbg_chip_ident *chip)
1421{
1422 struct mcam_camera *cam = priv;
1423
1424 chip->ident = V4L2_IDENT_NONE;
1425 chip->revision = 0;
1426 if (v4l2_chip_match_host(&chip->match)) {
1427 chip->ident = cam->chip_id;
1428 return 0;
1429 }
1430 return sensor_call(cam, core, g_chip_ident, chip);
1431}
1432
1433static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1434 struct v4l2_frmsizeenum *sizes)
1435{
1436 struct mcam_camera *cam = priv;
1437 int ret;
1438
1439 mutex_lock(&cam->s_mutex);
1440 ret = sensor_call(cam, video, enum_framesizes, sizes);
1441 mutex_unlock(&cam->s_mutex);
1442 return ret;
1443}
1444
1445static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1446 struct v4l2_frmivalenum *interval)
1447{
1448 struct mcam_camera *cam = priv;
1449 int ret;
1450
1451 mutex_lock(&cam->s_mutex);
1452 ret = sensor_call(cam, video, enum_frameintervals, interval);
1453 mutex_unlock(&cam->s_mutex);
1454 return ret;
1455}
1456
1457#ifdef CONFIG_VIDEO_ADV_DEBUG
1458static int mcam_vidioc_g_register(struct file *file, void *priv,
1459 struct v4l2_dbg_register *reg)
1460{
1461 struct mcam_camera *cam = priv;
1462
1463 if (v4l2_chip_match_host(&reg->match)) {
1464 reg->val = mcam_reg_read(cam, reg->reg);
1465 reg->size = 4;
1466 return 0;
1467 }
1468 return sensor_call(cam, core, g_register, reg);
1469}
1470
1471static int mcam_vidioc_s_register(struct file *file, void *priv,
1472 struct v4l2_dbg_register *reg)
1473{
1474 struct mcam_camera *cam = priv;
1475
1476 if (v4l2_chip_match_host(&reg->match)) {
1477 mcam_reg_write(cam, reg->reg, reg->val);
1478 return 0;
1479 }
1480 return sensor_call(cam, core, s_register, reg);
1481}
1482#endif
1483
abfa3df3
JC
1484static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1485 .vidioc_querycap = mcam_vidioc_querycap,
1486 .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1487 .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1488 .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap,
1489 .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap,
1490 .vidioc_enum_input = mcam_vidioc_enum_input,
1491 .vidioc_g_input = mcam_vidioc_g_input,
1492 .vidioc_s_input = mcam_vidioc_s_input,
1493 .vidioc_s_std = mcam_vidioc_s_std,
1494 .vidioc_reqbufs = mcam_vidioc_reqbufs,
1495 .vidioc_querybuf = mcam_vidioc_querybuf,
1496 .vidioc_qbuf = mcam_vidioc_qbuf,
1497 .vidioc_dqbuf = mcam_vidioc_dqbuf,
1498 .vidioc_streamon = mcam_vidioc_streamon,
1499 .vidioc_streamoff = mcam_vidioc_streamoff,
1500 .vidioc_queryctrl = mcam_vidioc_queryctrl,
1501 .vidioc_g_ctrl = mcam_vidioc_g_ctrl,
1502 .vidioc_s_ctrl = mcam_vidioc_s_ctrl,
1503 .vidioc_g_parm = mcam_vidioc_g_parm,
1504 .vidioc_s_parm = mcam_vidioc_s_parm,
1505 .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1506 .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
1507 .vidioc_g_chip_ident = mcam_vidioc_g_chip_ident,
1508#ifdef CONFIG_VIDEO_ADV_DEBUG
1509 .vidioc_g_register = mcam_vidioc_g_register,
1510 .vidioc_s_register = mcam_vidioc_s_register,
1511#endif
1512};
1513
abfa3df3
JC
1514/* ---------------------------------------------------------------------- */
1515/*
d43dae75 1516 * Our various file operations.
abfa3df3 1517 */
d43dae75
JC
1518static int mcam_v4l_open(struct file *filp)
1519{
1520 struct mcam_camera *cam = video_drvdata(filp);
1521 int ret = 0;
abfa3df3 1522
d43dae75 1523 filp->private_data = cam;
abfa3df3 1524
d43dae75
JC
1525 frames = singles = delivered = 0;
1526 mutex_lock(&cam->s_mutex);
1527 if (cam->users == 0) {
1528 ret = mcam_setup_vb2(cam);
1529 if (ret)
1530 goto out;
1531 mcam_ctlr_power_up(cam);
1532 __mcam_cam_reset(cam);
1533 mcam_set_config_needed(cam, 1);
1534 }
1535 (cam->users)++;
1536out:
1537 mutex_unlock(&cam->s_mutex);
1538 return ret;
a9b36e85 1539}
abfa3df3 1540
abfa3df3 1541
d43dae75
JC
1542static int mcam_v4l_release(struct file *filp)
1543{
1544 struct mcam_camera *cam = filp->private_data;
b5210fd2 1545
d43dae75
JC
1546 cam_err(cam, "Release, %d frames, %d singles, %d delivered\n", frames,
1547 singles, delivered);
1548 mutex_lock(&cam->s_mutex);
1549 (cam->users)--;
1550 if (filp == cam->owner) {
1551 mcam_ctlr_stop_dma(cam);
1552 cam->owner = NULL;
abfa3df3 1553 }
d43dae75
JC
1554 if (cam->users == 0) {
1555 mcam_cleanup_vb2(cam);
1556 mcam_ctlr_power_down(cam);
1557 if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1558 mcam_free_dma_bufs(cam);
1559 }
1560 mutex_unlock(&cam->s_mutex);
1561 return 0;
abfa3df3
JC
1562}
1563
d43dae75
JC
1564static ssize_t mcam_v4l_read(struct file *filp,
1565 char __user *buffer, size_t len, loff_t *pos)
a9b36e85 1566{
d43dae75
JC
1567 struct mcam_camera *cam = filp->private_data;
1568 int ret;
a9b36e85 1569
d43dae75
JC
1570 mutex_lock(&cam->s_mutex);
1571 ret = vb2_read(&cam->vb_queue, buffer, len, pos,
1572 filp->f_flags & O_NONBLOCK);
1573 mutex_unlock(&cam->s_mutex);
1574 return ret;
a9b36e85 1575}
abfa3df3 1576
d43dae75
JC
1577
1578
1579static unsigned int mcam_v4l_poll(struct file *filp,
1580 struct poll_table_struct *pt)
cbc4f3a2 1581{
d43dae75
JC
1582 struct mcam_camera *cam = filp->private_data;
1583 int ret;
cbc4f3a2 1584
d43dae75
JC
1585 mutex_lock(&cam->s_mutex);
1586 ret = vb2_poll(&cam->vb_queue, filp, pt);
1587 mutex_unlock(&cam->s_mutex);
1588 return ret;
1589}
1590
1591
1592static int mcam_v4l_mmap(struct file *filp, struct vm_area_struct *vma)
1593{
1594 struct mcam_camera *cam = filp->private_data;
1595 int ret;
1596
1597 mutex_lock(&cam->s_mutex);
1598 ret = vb2_mmap(&cam->vb_queue, vma);
1599 mutex_unlock(&cam->s_mutex);
1600 return ret;
cbc4f3a2
JC
1601}
1602
1603
abfa3df3 1604
d43dae75
JC
1605static const struct v4l2_file_operations mcam_v4l_fops = {
1606 .owner = THIS_MODULE,
1607 .open = mcam_v4l_open,
1608 .release = mcam_v4l_release,
1609 .read = mcam_v4l_read,
1610 .poll = mcam_v4l_poll,
1611 .mmap = mcam_v4l_mmap,
1612 .unlocked_ioctl = video_ioctl2,
1613};
1614
1615
1616/*
1617 * This template device holds all of those v4l2 methods; we
1618 * clone it for specific real devices.
1619 */
1620static struct video_device mcam_v4l_template = {
1621 .name = "mcam",
1622 .tvnorms = V4L2_STD_NTSC_M,
1623 .current_norm = V4L2_STD_NTSC_M, /* make mplayer happy */
1624
1625 .fops = &mcam_v4l_fops,
1626 .ioctl_ops = &mcam_v4l_ioctl_ops,
1627 .release = video_device_release_empty,
1628};
1629
1630/* ---------------------------------------------------------------------- */
1631/*
1632 * Interrupt handler stuff
1633 */
abfa3df3
JC
1634static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1635{
1636 /*
1637 * Basic frame housekeeping.
1638 */
abfa3df3
JC
1639 set_bit(frame, &cam->flags);
1640 clear_bit(CF_DMA_ACTIVE, &cam->flags);
a9b36e85 1641 cam->next_buf = frame;
abfa3df3 1642 cam->buf_seq[frame] = ++(cam->sequence);
a9b36e85 1643 frames++;
abfa3df3 1644 /*
cbc4f3a2 1645 * "This should never happen"
abfa3df3 1646 */
cbc4f3a2
JC
1647 if (cam->state != S_STREAMING)
1648 return;
1649 /*
1650 * Process the frame and set up the next one.
1651 */
7498469f 1652 cam->frame_complete(cam, frame);
abfa3df3
JC
1653}
1654
1655
d43dae75
JC
1656/*
1657 * The interrupt handler; this needs to be called from the
1658 * platform irq handler with the lock held.
1659 */
abfa3df3
JC
1660int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1661{
1662 unsigned int frame, handled = 0;
1663
1664 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
1665 /*
1666 * Handle any frame completions. There really should
1667 * not be more than one of these, or we have fallen
1668 * far behind.
cbc4f3a2
JC
1669 *
1670 * When running in S/G mode, the frame number lacks any
1671 * real meaning - there's only one descriptor array - but
1672 * the controller still picks a different one to signal
1673 * each time.
abfa3df3
JC
1674 */
1675 for (frame = 0; frame < cam->nbufs; frame++)
1676 if (irqs & (IRQ_EOF0 << frame)) {
1677 mcam_frame_complete(cam, frame);
1678 handled = 1;
1679 }
1680 /*
1681 * If a frame starts, note that we have DMA active. This
1682 * code assumes that we won't get multiple frame interrupts
1683 * at once; may want to rethink that.
1684 */
1685 if (irqs & (IRQ_SOF0 | IRQ_SOF1 | IRQ_SOF2)) {
1686 set_bit(CF_DMA_ACTIVE, &cam->flags);
1687 handled = 1;
cbc4f3a2
JC
1688 if (cam->buffer_mode == B_DMA_sg)
1689 mcam_ctlr_stop(cam);
abfa3df3
JC
1690 }
1691 return handled;
1692}
1693
d43dae75 1694/* ---------------------------------------------------------------------- */
abfa3df3
JC
1695/*
1696 * Registration and such.
1697 */
abfa3df3 1698static struct ov7670_config sensor_cfg = {
abfa3df3
JC
1699 /*
1700 * Exclude QCIF mode, because it only captures a tiny portion
1701 * of the sensor FOV
1702 */
1703 .min_width = 320,
1704 .min_height = 240,
1705};
1706
1707
1708int mccic_register(struct mcam_camera *cam)
1709{
1710 struct i2c_board_info ov7670_info = {
1711 .type = "ov7670",
1c68f889 1712 .addr = 0x42 >> 1,
abfa3df3
JC
1713 .platform_data = &sensor_cfg,
1714 };
1715 int ret;
1716
7498469f
JC
1717 /*
1718 * Validate the requested buffer mode.
1719 */
1720 if (buffer_mode >= 0)
1721 cam->buffer_mode = buffer_mode;
1722 if (cam->buffer_mode == B_DMA_sg &&
1723 cam->chip_id == V4L2_IDENT_CAFE) {
1724 printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, "
1725 "attempting vmalloc mode instead\n");
1726 cam->buffer_mode = B_vmalloc;
1727 }
1728 if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1729 printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1730 cam->buffer_mode);
1731 return -EINVAL;
1732 }
abfa3df3
JC
1733 /*
1734 * Register with V4L
1735 */
1736 ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1737 if (ret)
1738 return ret;
1739
1740 mutex_init(&cam->s_mutex);
1741 cam->state = S_NOTREADY;
1742 mcam_set_config_needed(cam, 1);
abfa3df3
JC
1743 cam->pix_format = mcam_def_pix_format;
1744 cam->mbus_code = mcam_def_mbus_code;
b5210fd2 1745 INIT_LIST_HEAD(&cam->buffers);
abfa3df3
JC
1746 mcam_ctlr_init(cam);
1747
abfa3df3
JC
1748 /*
1749 * Try to find the sensor.
1750 */
2164b5af
JC
1751 sensor_cfg.clock_speed = cam->clock_speed;
1752 sensor_cfg.use_smbus = cam->use_smbus;
abfa3df3
JC
1753 cam->sensor_addr = ov7670_info.addr;
1754 cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
595a93a4 1755 cam->i2c_adapter, &ov7670_info, NULL);
abfa3df3
JC
1756 if (cam->sensor == NULL) {
1757 ret = -ENODEV;
1758 goto out_unregister;
1759 }
1760
1761 ret = mcam_cam_init(cam);
1762 if (ret)
1763 goto out_unregister;
1764 /*
1765 * Get the v4l2 setup done.
1766 */
1767 mutex_lock(&cam->s_mutex);
1768 cam->vdev = mcam_v4l_template;
1769 cam->vdev.debug = 0;
1770 cam->vdev.v4l2_dev = &cam->v4l2_dev;
1771 ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1772 if (ret)
1773 goto out;
1774 video_set_drvdata(&cam->vdev, cam);
1775
1776 /*
1777 * If so requested, try to get our DMA buffers now.
1778 */
a9b36e85 1779 if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
abfa3df3
JC
1780 if (mcam_alloc_dma_bufs(cam, 1))
1781 cam_warn(cam, "Unable to alloc DMA buffers at load"
1782 " will try again later.");
1783 }
1784
1785out:
1786 mutex_unlock(&cam->s_mutex);
1787 return ret;
1788out_unregister:
1789 v4l2_device_unregister(&cam->v4l2_dev);
1790 return ret;
1791}
1792
1793
1794void mccic_shutdown(struct mcam_camera *cam)
1795{
67a8dbbc
JC
1796 /*
1797 * If we have no users (and we really, really should have no
1798 * users) the device will already be powered down. Trying to
1799 * take it down again will wedge the machine, which is frowned
1800 * upon.
1801 */
1802 if (cam->users > 0) {
abfa3df3 1803 cam_warn(cam, "Removing a device with users!\n");
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1804 mcam_ctlr_power_down(cam);
1805 }
b5210fd2 1806 vb2_queue_release(&cam->vb_queue);
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1807 if (cam->buffer_mode == B_vmalloc)
1808 mcam_free_dma_bufs(cam);
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1809 video_unregister_device(&cam->vdev);
1810 v4l2_device_unregister(&cam->v4l2_dev);
1811}
1812
1813/*
1814 * Power management
1815 */
1816#ifdef CONFIG_PM
1817
1818void mccic_suspend(struct mcam_camera *cam)
1819{
1820 enum mcam_state cstate = cam->state;
1821
1822 mcam_ctlr_stop_dma(cam);
1823 mcam_ctlr_power_down(cam);
1824 cam->state = cstate;
1825}
1826
1827int mccic_resume(struct mcam_camera *cam)
1828{
1829 int ret = 0;
1830
1831 mutex_lock(&cam->s_mutex);
1832 if (cam->users > 0) {
1833 mcam_ctlr_power_up(cam);
1834 __mcam_cam_reset(cam);
1835 } else {
1836 mcam_ctlr_power_down(cam);
1837 }
1838 mutex_unlock(&cam->s_mutex);
1839
1840 set_bit(CF_CONFIG_NEEDED, &cam->flags);
b5210fd2 1841 if (cam->state == S_STREAMING)
a9b36e85 1842 ret = mcam_read_setup(cam);
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1843 return ret;
1844}
1845#endif /* CONFIG_PM */