[media] common: move media/common/tuners to media/tuners
[linux-2.6-block.git] / drivers / media / video / marvell-ccic / mcam-core.c
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1/*
2 * The Marvell camera core. This device appears in a number of settings,
3 * so it needs platform-specific support outside of the core.
4 *
5 * Copyright 2011 Jonathan Corbet corbet@lwn.net
6 */
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/fs.h>
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10#include <linux/mm.h>
11#include <linux/i2c.h>
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
abfa3df3 14#include <linux/slab.h>
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15#include <linux/device.h>
16#include <linux/wait.h>
17#include <linux/list.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
abfa3df3 20#include <linux/vmalloc.h>
abfa3df3 21#include <linux/io.h>
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22#include <linux/videodev2.h>
23#include <media/v4l2-device.h>
24#include <media/v4l2-ioctl.h>
25#include <media/v4l2-chip-ident.h>
26#include <media/ov7670.h>
27#include <media/videobuf2-vmalloc.h>
a9b36e85 28#include <media/videobuf2-dma-contig.h>
cbc4f3a2 29#include <media/videobuf2-dma-sg.h>
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30
31#include "mcam-core.h"
32
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33/*
34 * Basic frame stats - to be deleted shortly
35 */
36static int frames;
37static int singles;
38static int delivered;
abfa3df3 39
7498469f 40#ifdef MCAM_MODE_VMALLOC
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41/*
42 * Internal DMA buffer management. Since the controller cannot do S/G I/O,
43 * we must have physically contiguous buffers to bring frames into.
44 * These parameters control how many buffers we use, whether we
45 * allocate them at load time (better chance of success, but nails down
46 * memory) or when somebody tries to use the camera (riskier), and,
47 * for load-time allocation, how big they should be.
48 *
49 * The controller can cycle through three buffers. We could use
50 * more by flipping pointers around, but it probably makes little
51 * sense.
52 */
53
90ab5ee9 54static bool alloc_bufs_at_read;
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55module_param(alloc_bufs_at_read, bool, 0444);
56MODULE_PARM_DESC(alloc_bufs_at_read,
57 "Non-zero value causes DMA buffers to be allocated when the "
58 "video capture device is read, rather than at module load "
59 "time. This saves memory, but decreases the chances of "
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60 "successfully getting those buffers. This parameter is "
61 "only used in the vmalloc buffer mode");
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62
63static int n_dma_bufs = 3;
64module_param(n_dma_bufs, uint, 0644);
65MODULE_PARM_DESC(n_dma_bufs,
66 "The number of DMA buffers to allocate. Can be either two "
67 "(saves memory, makes timing tighter) or three.");
68
69static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
70module_param(dma_buf_size, uint, 0444);
71MODULE_PARM_DESC(dma_buf_size,
72 "The size of the allocated DMA buffers. If actual operating "
73 "parameters require larger buffers, an attempt to reallocate "
74 "will be made.");
7498469f 75#else /* MCAM_MODE_VMALLOC */
90ab5ee9 76static const bool alloc_bufs_at_read = 0;
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77static const int n_dma_bufs = 3; /* Used by S/G_PARM */
78#endif /* MCAM_MODE_VMALLOC */
abfa3df3 79
90ab5ee9 80static bool flip;
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81module_param(flip, bool, 0444);
82MODULE_PARM_DESC(flip,
83 "If set, the sensor will be instructed to flip the image "
84 "vertically.");
85
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86static int buffer_mode = -1;
87module_param(buffer_mode, int, 0444);
88MODULE_PARM_DESC(buffer_mode,
89 "Set the buffer mode to be used; default is to go with what "
90 "the platform driver asks for. Set to 0 for vmalloc, 1 for "
91 "DMA contiguous.");
92
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93/*
94 * Status flags. Always manipulated with bit operations.
95 */
96#define CF_BUF0_VALID 0 /* Buffers valid - first three */
97#define CF_BUF1_VALID 1
98#define CF_BUF2_VALID 2
99#define CF_DMA_ACTIVE 3 /* A frame is incoming */
100#define CF_CONFIG_NEEDED 4 /* Must configure hardware */
a9b36e85 101#define CF_SINGLE_BUFFER 5 /* Running with a single buffer */
cbc4f3a2 102#define CF_SG_RESTART 6 /* SG restart needed */
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103
104#define sensor_call(cam, o, f, args...) \
105 v4l2_subdev_call(cam->sensor, o, f, ##args)
106
107static struct mcam_format_struct {
108 __u8 *desc;
109 __u32 pixelformat;
110 int bpp; /* Bytes per pixel */
111 enum v4l2_mbus_pixelcode mbus_code;
112} mcam_formats[] = {
113 {
114 .desc = "YUYV 4:2:2",
115 .pixelformat = V4L2_PIX_FMT_YUYV,
116 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
117 .bpp = 2,
118 },
119 {
120 .desc = "RGB 444",
121 .pixelformat = V4L2_PIX_FMT_RGB444,
122 .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE,
123 .bpp = 2,
124 },
125 {
126 .desc = "RGB 565",
127 .pixelformat = V4L2_PIX_FMT_RGB565,
128 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE,
129 .bpp = 2,
130 },
131 {
132 .desc = "Raw RGB Bayer",
133 .pixelformat = V4L2_PIX_FMT_SBGGR8,
134 .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8,
135 .bpp = 1
136 },
137};
138#define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
139
140static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
141{
142 unsigned i;
143
144 for (i = 0; i < N_MCAM_FMTS; i++)
145 if (mcam_formats[i].pixelformat == pixelformat)
146 return mcam_formats + i;
147 /* Not found? Then return the first format. */
148 return mcam_formats;
149}
150
151/*
d43dae75 152 * The default format we use until somebody says otherwise.
abfa3df3 153 */
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154static const struct v4l2_pix_format mcam_def_pix_format = {
155 .width = VGA_WIDTH,
156 .height = VGA_HEIGHT,
157 .pixelformat = V4L2_PIX_FMT_YUYV,
158 .field = V4L2_FIELD_NONE,
159 .bytesperline = VGA_WIDTH*2,
160 .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
161};
abfa3df3 162
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163static const enum v4l2_mbus_pixelcode mcam_def_mbus_code =
164 V4L2_MBUS_FMT_YUYV8_2X8;
abfa3df3 165
abfa3df3 166
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167/*
168 * The two-word DMA descriptor format used by the Armada 610 and like. There
169 * Is a three-word format as well (set C1_DESC_3WORD) where the third
170 * word is a pointer to the next descriptor, but we don't use it. Two-word
171 * descriptors have to be contiguous in memory.
172 */
173struct mcam_dma_desc {
174 u32 dma_addr;
175 u32 segment_len;
176};
177
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178/*
179 * Our buffer type for working with videobuf2. Note that the vb2
180 * developers have decreed that struct vb2_buffer must be at the
181 * beginning of this structure.
182 */
183struct mcam_vb_buffer {
184 struct vb2_buffer vb_buf;
185 struct list_head queue;
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186 struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
187 dma_addr_t dma_desc_pa; /* Descriptor physical address */
188 int dma_desc_nent; /* Number of mapped descriptors */
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189};
190
191static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_buffer *vb)
192{
193 return container_of(vb, struct mcam_vb_buffer, vb_buf);
194}
195
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196/*
197 * Hand a completed buffer back to user space.
198 */
199static void mcam_buffer_done(struct mcam_camera *cam, int frame,
200 struct vb2_buffer *vbuf)
201{
202 vbuf->v4l2_buf.bytesused = cam->pix_format.sizeimage;
203 vbuf->v4l2_buf.sequence = cam->buf_seq[frame];
204 vb2_set_plane_payload(vbuf, 0, cam->pix_format.sizeimage);
205 vb2_buffer_done(vbuf, VB2_BUF_STATE_DONE);
206}
207
208
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209
210/*
67a8dbbc 211 * Debugging and related.
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212 */
213#define cam_err(cam, fmt, arg...) \
214 dev_err((cam)->dev, fmt, ##arg);
215#define cam_warn(cam, fmt, arg...) \
216 dev_warn((cam)->dev, fmt, ##arg);
217#define cam_dbg(cam, fmt, arg...) \
218 dev_dbg((cam)->dev, fmt, ##arg);
219
220
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221/*
222 * Flag manipulation helpers
223 */
224static void mcam_reset_buffers(struct mcam_camera *cam)
225{
226 int i;
227
228 cam->next_buf = -1;
229 for (i = 0; i < cam->nbufs; i++)
230 clear_bit(i, &cam->flags);
231}
232
233static inline int mcam_needs_config(struct mcam_camera *cam)
234{
235 return test_bit(CF_CONFIG_NEEDED, &cam->flags);
236}
237
238static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
239{
240 if (needed)
241 set_bit(CF_CONFIG_NEEDED, &cam->flags);
242 else
243 clear_bit(CF_CONFIG_NEEDED, &cam->flags);
244}
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245
246/* ------------------------------------------------------------------- */
247/*
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248 * Make the controller start grabbing images. Everything must
249 * be set up before doing this.
abfa3df3 250 */
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251static void mcam_ctlr_start(struct mcam_camera *cam)
252{
253 /* set_bit performs a read, so no other barrier should be
254 needed here */
255 mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
256}
257
258static void mcam_ctlr_stop(struct mcam_camera *cam)
259{
260 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
261}
262
263/* ------------------------------------------------------------------- */
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264
265#ifdef MCAM_MODE_VMALLOC
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266/*
267 * Code specific to the vmalloc buffer mode.
268 */
269
270/*
271 * Allocate in-kernel DMA buffers for vmalloc mode.
272 */
273static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
274{
275 int i;
276
277 mcam_set_config_needed(cam, 1);
278 if (loadtime)
279 cam->dma_buf_size = dma_buf_size;
280 else
281 cam->dma_buf_size = cam->pix_format.sizeimage;
282 if (n_dma_bufs > 3)
283 n_dma_bufs = 3;
284
285 cam->nbufs = 0;
286 for (i = 0; i < n_dma_bufs; i++) {
287 cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
288 cam->dma_buf_size, cam->dma_handles + i,
289 GFP_KERNEL);
290 if (cam->dma_bufs[i] == NULL) {
291 cam_warn(cam, "Failed to allocate DMA buffer\n");
292 break;
293 }
294 (cam->nbufs)++;
295 }
296
297 switch (cam->nbufs) {
298 case 1:
299 dma_free_coherent(cam->dev, cam->dma_buf_size,
300 cam->dma_bufs[0], cam->dma_handles[0]);
301 cam->nbufs = 0;
302 case 0:
303 cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
304 return -ENOMEM;
305
306 case 2:
307 if (n_dma_bufs > 2)
308 cam_warn(cam, "Will limp along with only 2 buffers\n");
309 break;
310 }
311 return 0;
312}
313
314static void mcam_free_dma_bufs(struct mcam_camera *cam)
315{
316 int i;
317
318 for (i = 0; i < cam->nbufs; i++) {
319 dma_free_coherent(cam->dev, cam->dma_buf_size,
320 cam->dma_bufs[i], cam->dma_handles[i]);
321 cam->dma_bufs[i] = NULL;
322 }
323 cam->nbufs = 0;
324}
325
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326
327/*
a9b36e85 328 * Set up DMA buffers when operating in vmalloc mode
abfa3df3 329 */
a9b36e85 330static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
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331{
332 /*
333 * Store the first two Y buffers (we aren't supporting
334 * planar formats for now, so no UV bufs). Then either
335 * set the third if it exists, or tell the controller
336 * to just use two.
337 */
338 mcam_reg_write(cam, REG_Y0BAR, cam->dma_handles[0]);
339 mcam_reg_write(cam, REG_Y1BAR, cam->dma_handles[1]);
340 if (cam->nbufs > 2) {
341 mcam_reg_write(cam, REG_Y2BAR, cam->dma_handles[2]);
342 mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
343 } else
344 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
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345 if (cam->chip_id == V4L2_IDENT_CAFE)
346 mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
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347}
348
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349/*
350 * Copy data out to user space in the vmalloc case
351 */
352static void mcam_frame_tasklet(unsigned long data)
353{
354 struct mcam_camera *cam = (struct mcam_camera *) data;
355 int i;
356 unsigned long flags;
357 struct mcam_vb_buffer *buf;
358
359 spin_lock_irqsave(&cam->dev_lock, flags);
360 for (i = 0; i < cam->nbufs; i++) {
361 int bufno = cam->next_buf;
362
363 if (cam->state != S_STREAMING || bufno < 0)
364 break; /* I/O got stopped */
365 if (++(cam->next_buf) >= cam->nbufs)
366 cam->next_buf = 0;
367 if (!test_bit(bufno, &cam->flags))
368 continue;
369 if (list_empty(&cam->buffers)) {
370 singles++;
371 break; /* Leave it valid, hope for better later */
372 }
373 delivered++;
374 clear_bit(bufno, &cam->flags);
375 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
376 queue);
377 list_del_init(&buf->queue);
378 /*
379 * Drop the lock during the big copy. This *should* be safe...
380 */
381 spin_unlock_irqrestore(&cam->dev_lock, flags);
382 memcpy(vb2_plane_vaddr(&buf->vb_buf, 0), cam->dma_bufs[bufno],
383 cam->pix_format.sizeimage);
384 mcam_buffer_done(cam, bufno, &buf->vb_buf);
385 spin_lock_irqsave(&cam->dev_lock, flags);
386 }
387 spin_unlock_irqrestore(&cam->dev_lock, flags);
388}
389
390
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391/*
392 * Make sure our allocated buffers are up to the task.
393 */
394static int mcam_check_dma_buffers(struct mcam_camera *cam)
395{
396 if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
397 mcam_free_dma_bufs(cam);
398 if (cam->nbufs == 0)
399 return mcam_alloc_dma_bufs(cam, 0);
400 return 0;
401}
402
403static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
404{
405 tasklet_schedule(&cam->s_tasklet);
406}
407
408#else /* MCAM_MODE_VMALLOC */
409
410static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
411{
412 return 0;
413}
414
415static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
416{
417 return;
418}
419
420static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
421{
422 return 0;
423}
424
425
426
427#endif /* MCAM_MODE_VMALLOC */
428
429
430#ifdef MCAM_MODE_DMA_CONTIG
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431/* ---------------------------------------------------------------------- */
432/*
433 * DMA-contiguous code.
434 */
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435/*
436 * Set up a contiguous buffer for the given frame. Here also is where
437 * the underrun strategy is set: if there is no buffer available, reuse
438 * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to
439 * keep the interrupt handler from giving that buffer back to user
440 * space. In this way, we always have a buffer to DMA to and don't
441 * have to try to play games stopping and restarting the controller.
442 */
443static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
444{
445 struct mcam_vb_buffer *buf;
446 /*
447 * If there are no available buffers, go into single mode
448 */
449 if (list_empty(&cam->buffers)) {
450 buf = cam->vb_bufs[frame ^ 0x1];
451 cam->vb_bufs[frame] = buf;
452 mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR,
ba7fcb0c 453 vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0));
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454 set_bit(CF_SINGLE_BUFFER, &cam->flags);
455 singles++;
456 return;
457 }
458 /*
459 * OK, we have a buffer we can use.
460 */
461 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
462 list_del_init(&buf->queue);
463 mcam_reg_write(cam, frame == 0 ? REG_Y0BAR : REG_Y1BAR,
ba7fcb0c 464 vb2_dma_contig_plane_dma_addr(&buf->vb_buf, 0));
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465 cam->vb_bufs[frame] = buf;
466 clear_bit(CF_SINGLE_BUFFER, &cam->flags);
467}
468
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469/*
470 * Initial B_DMA_contig setup.
471 */
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472static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
473{
474 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
475 cam->nbufs = 2;
476 mcam_set_contig_buffer(cam, 0);
477 mcam_set_contig_buffer(cam, 1);
478}
479
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480/*
481 * Frame completion handling.
482 */
483static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
484{
485 struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
486
487 if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
488 delivered++;
489 mcam_buffer_done(cam, frame, &buf->vb_buf);
490 }
491 mcam_set_contig_buffer(cam, frame);
492}
493
7498469f 494#endif /* MCAM_MODE_DMA_CONTIG */
d43dae75 495
7498469f 496#ifdef MCAM_MODE_DMA_SG
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497/* ---------------------------------------------------------------------- */
498/*
499 * Scatter/gather-specific code.
500 */
a9b36e85 501
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502/*
503 * Set up the next buffer for S/G I/O; caller should be sure that
504 * the controller is stopped and a buffer is available.
505 */
506static void mcam_sg_next_buffer(struct mcam_camera *cam)
a9b36e85 507{
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508 struct mcam_vb_buffer *buf;
509
510 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
511 list_del_init(&buf->queue);
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512 /*
513 * Very Bad Not Good Things happen if you don't clear
514 * C1_DESC_ENA before making any descriptor changes.
515 */
516 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
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517 mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
518 mcam_reg_write(cam, REG_DESC_LEN_Y,
519 buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
520 mcam_reg_write(cam, REG_DESC_LEN_U, 0);
521 mcam_reg_write(cam, REG_DESC_LEN_V, 0);
121bbe25 522 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
cbc4f3a2 523 cam->vb_bufs[0] = buf;
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524}
525
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526/*
527 * Initial B_DMA_sg setup
528 */
529static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
530{
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531 /*
532 * The list-empty condition can hit us at resume time
533 * if the buffer list was empty when the system was suspended.
534 */
535 if (list_empty(&cam->buffers)) {
536 set_bit(CF_SG_RESTART, &cam->flags);
537 return;
538 }
539
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540 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
541 mcam_sg_next_buffer(cam);
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542 cam->nbufs = 3;
543}
544
d43dae75 545
cbc4f3a2 546/*
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547 * Frame completion with S/G is trickier. We can't muck with
548 * a descriptor chain on the fly, since the controller buffers it
549 * internally. So we have to actually stop and restart; Marvell
550 * says this is the way to do it.
551 *
552 * Of course, stopping is easier said than done; experience shows
553 * that the controller can start a frame *after* C0_ENABLE has been
554 * cleared. So when running in S/G mode, the controller is "stopped"
555 * on receipt of the start-of-frame interrupt. That means we can
556 * safely change the DMA descriptor array here and restart things
557 * (assuming there's another buffer waiting to go).
558 */
559static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
560{
561 struct mcam_vb_buffer *buf = cam->vb_bufs[0];
562
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563 /*
564 * If we're no longer supposed to be streaming, don't do anything.
565 */
566 if (cam->state != S_STREAMING)
567 return;
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568 /*
569 * If we have another buffer available, put it in and
570 * restart the engine.
571 */
572 if (!list_empty(&cam->buffers)) {
573 mcam_sg_next_buffer(cam);
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574 mcam_ctlr_start(cam);
575 /*
576 * Otherwise set CF_SG_RESTART and the controller will
577 * be restarted once another buffer shows up.
578 */
579 } else {
580 set_bit(CF_SG_RESTART, &cam->flags);
581 singles++;
bb0a896e 582 cam->vb_bufs[0] = NULL;
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583 }
584 /*
585 * Now we can give the completed frame back to user space.
586 */
587 delivered++;
588 mcam_buffer_done(cam, frame, &buf->vb_buf);
589}
590
591
592/*
593 * Scatter/gather mode requires stopping the controller between
594 * frames so we can put in a new DMA descriptor array. If no new
595 * buffer exists at frame completion, the controller is left stopped;
596 * this function is charged with gettig things going again.
597 */
598static void mcam_sg_restart(struct mcam_camera *cam)
599{
600 mcam_ctlr_dma_sg(cam);
601 mcam_ctlr_start(cam);
602 clear_bit(CF_SG_RESTART, &cam->flags);
603}
604
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605#else /* MCAM_MODE_DMA_SG */
606
607static inline void mcam_sg_restart(struct mcam_camera *cam)
608{
609 return;
610}
611
612#endif /* MCAM_MODE_DMA_SG */
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613
614/* ---------------------------------------------------------------------- */
615/*
616 * Buffer-mode-independent controller code.
617 */
618
619/*
620 * Image format setup
cbc4f3a2 621 */
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622static void mcam_ctlr_image(struct mcam_camera *cam)
623{
624 int imgsz;
625 struct v4l2_pix_format *fmt = &cam->pix_format;
626
627 imgsz = ((fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK) |
628 (fmt->bytesperline & IMGSZ_H_MASK);
629 mcam_reg_write(cam, REG_IMGSIZE, imgsz);
630 mcam_reg_write(cam, REG_IMGOFFSET, 0);
631 /* YPITCH just drops the last two bits */
632 mcam_reg_write_mask(cam, REG_IMGPITCH, fmt->bytesperline,
633 IMGP_YP_MASK);
634 /*
635 * Tell the controller about the image format we are using.
636 */
637 switch (cam->pix_format.pixelformat) {
638 case V4L2_PIX_FMT_YUYV:
639 mcam_reg_write_mask(cam, REG_CTRL0,
640 C0_DF_YUV|C0_YUV_PACKED|C0_YUVE_YUYV,
641 C0_DF_MASK);
642 break;
643
644 case V4L2_PIX_FMT_RGB444:
645 mcam_reg_write_mask(cam, REG_CTRL0,
646 C0_DF_RGB|C0_RGBF_444|C0_RGB4_XRGB,
647 C0_DF_MASK);
648 /* Alpha value? */
649 break;
650
651 case V4L2_PIX_FMT_RGB565:
652 mcam_reg_write_mask(cam, REG_CTRL0,
653 C0_DF_RGB|C0_RGBF_565|C0_RGB5_BGGR,
654 C0_DF_MASK);
655 break;
656
657 default:
658 cam_err(cam, "Unknown format %x\n", cam->pix_format.pixelformat);
659 break;
660 }
661 /*
662 * Make sure it knows we want to use hsync/vsync.
663 */
664 mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC,
665 C0_SIFM_MASK);
666}
667
668
669/*
670 * Configure the controller for operation; caller holds the
671 * device mutex.
672 */
673static int mcam_ctlr_configure(struct mcam_camera *cam)
674{
675 unsigned long flags;
676
677 spin_lock_irqsave(&cam->dev_lock, flags);
bb0a896e 678 clear_bit(CF_SG_RESTART, &cam->flags);
7498469f 679 cam->dma_setup(cam);
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680 mcam_ctlr_image(cam);
681 mcam_set_config_needed(cam, 0);
682 spin_unlock_irqrestore(&cam->dev_lock, flags);
683 return 0;
684}
685
686static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
687{
688 /*
689 * Clear any pending interrupts, since we do not
690 * expect to have I/O active prior to enabling.
691 */
692 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
693 mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
694}
695
696static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
697{
698 mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
699}
700
abfa3df3 701
cbc4f3a2 702
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703static void mcam_ctlr_init(struct mcam_camera *cam)
704{
705 unsigned long flags;
706
707 spin_lock_irqsave(&cam->dev_lock, flags);
708 /*
709 * Make sure it's not powered down.
710 */
711 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
712 /*
713 * Turn off the enable bit. It sure should be off anyway,
714 * but it's good to be sure.
715 */
716 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
717 /*
718 * Clock the sensor appropriately. Controller clock should
719 * be 48MHz, sensor "typical" value is half that.
720 */
721 mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
722 spin_unlock_irqrestore(&cam->dev_lock, flags);
723}
724
725
726/*
727 * Stop the controller, and don't return until we're really sure that no
728 * further DMA is going on.
729 */
730static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
731{
732 unsigned long flags;
733
734 /*
735 * Theory: stop the camera controller (whether it is operating
736 * or not). Delay briefly just in case we race with the SOF
737 * interrupt, then wait until no DMA is active.
738 */
739 spin_lock_irqsave(&cam->dev_lock, flags);
cbc4f3a2 740 clear_bit(CF_SG_RESTART, &cam->flags);
abfa3df3 741 mcam_ctlr_stop(cam);
cbc4f3a2 742 cam->state = S_IDLE;
abfa3df3 743 spin_unlock_irqrestore(&cam->dev_lock, flags);
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744 /*
745 * This is a brutally long sleep, but experience shows that
746 * it can take the controller a while to get the message that
747 * it needs to stop grabbing frames. In particular, we can
748 * sometimes (on mmp) get a frame at the end WITHOUT the
749 * start-of-frame indication.
750 */
751 msleep(150);
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752 if (test_bit(CF_DMA_ACTIVE, &cam->flags))
753 cam_err(cam, "Timeout waiting for DMA to end\n");
754 /* This would be bad news - what now? */
755 spin_lock_irqsave(&cam->dev_lock, flags);
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756 mcam_ctlr_irq_disable(cam);
757 spin_unlock_irqrestore(&cam->dev_lock, flags);
758}
759
760/*
761 * Power up and down.
762 */
763static void mcam_ctlr_power_up(struct mcam_camera *cam)
764{
765 unsigned long flags;
766
767 spin_lock_irqsave(&cam->dev_lock, flags);
abfa3df3 768 cam->plat_power_up(cam);
67a8dbbc 769 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
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770 spin_unlock_irqrestore(&cam->dev_lock, flags);
771 msleep(5); /* Just to be sure */
772}
773
774static void mcam_ctlr_power_down(struct mcam_camera *cam)
775{
776 unsigned long flags;
777
778 spin_lock_irqsave(&cam->dev_lock, flags);
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779 /*
780 * School of hard knocks department: be sure we do any register
781 * twiddling on the controller *before* calling the platform
782 * power down routine.
783 */
abfa3df3 784 mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
67a8dbbc 785 cam->plat_power_down(cam);
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786 spin_unlock_irqrestore(&cam->dev_lock, flags);
787}
788
789/* -------------------------------------------------------------------- */
790/*
791 * Communications with the sensor.
792 */
793
794static int __mcam_cam_reset(struct mcam_camera *cam)
795{
796 return sensor_call(cam, core, reset, 0);
797}
798
799/*
800 * We have found the sensor on the i2c. Let's try to have a
801 * conversation.
802 */
803static int mcam_cam_init(struct mcam_camera *cam)
804{
805 struct v4l2_dbg_chip_ident chip;
806 int ret;
807
808 mutex_lock(&cam->s_mutex);
809 if (cam->state != S_NOTREADY)
810 cam_warn(cam, "Cam init with device in funky state %d",
811 cam->state);
812 ret = __mcam_cam_reset(cam);
813 if (ret)
814 goto out;
815 chip.ident = V4L2_IDENT_NONE;
816 chip.match.type = V4L2_CHIP_MATCH_I2C_ADDR;
817 chip.match.addr = cam->sensor_addr;
818 ret = sensor_call(cam, core, g_chip_ident, &chip);
819 if (ret)
820 goto out;
821 cam->sensor_type = chip.ident;
822 if (cam->sensor_type != V4L2_IDENT_OV7670) {
823 cam_err(cam, "Unsupported sensor type 0x%x", cam->sensor_type);
824 ret = -EINVAL;
825 goto out;
826 }
827/* Get/set parameters? */
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828 ret = 0;
829 cam->state = S_IDLE;
830out:
831 mcam_ctlr_power_down(cam);
832 mutex_unlock(&cam->s_mutex);
833 return ret;
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834}
835
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836/*
837 * Configure the sensor to match the parameters we have. Caller should
838 * hold s_mutex
839 */
840static int mcam_cam_set_flip(struct mcam_camera *cam)
abfa3df3 841{
d43dae75 842 struct v4l2_control ctrl;
abfa3df3 843
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JC
844 memset(&ctrl, 0, sizeof(ctrl));
845 ctrl.id = V4L2_CID_VFLIP;
846 ctrl.value = flip;
847 return sensor_call(cam, core, s_ctrl, &ctrl);
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848}
849
850
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851static int mcam_cam_configure(struct mcam_camera *cam)
852{
853 struct v4l2_mbus_framefmt mbus_fmt;
854 int ret;
abfa3df3 855
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856 v4l2_fill_mbus_format(&mbus_fmt, &cam->pix_format, cam->mbus_code);
857 ret = sensor_call(cam, core, init, 0);
858 if (ret == 0)
859 ret = sensor_call(cam, video, s_mbus_fmt, &mbus_fmt);
860 /*
861 * OV7670 does weird things if flip is set *before* format...
862 */
863 ret += mcam_cam_set_flip(cam);
864 return ret;
865}
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866
867/*
868 * Get everything ready, and start grabbing frames.
869 */
a9b36e85 870static int mcam_read_setup(struct mcam_camera *cam)
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871{
872 int ret;
873 unsigned long flags;
874
875 /*
876 * Configuration. If we still don't have DMA buffers,
877 * make one last, desperate attempt.
878 */
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879 if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
880 mcam_alloc_dma_bufs(cam, 0))
881 return -ENOMEM;
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882
883 if (mcam_needs_config(cam)) {
884 mcam_cam_configure(cam);
885 ret = mcam_ctlr_configure(cam);
886 if (ret)
887 return ret;
888 }
889
890 /*
891 * Turn it loose.
892 */
893 spin_lock_irqsave(&cam->dev_lock, flags);
482d35c4 894 clear_bit(CF_DMA_ACTIVE, &cam->flags);
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895 mcam_reset_buffers(cam);
896 mcam_ctlr_irq_enable(cam);
a9b36e85 897 cam->state = S_STREAMING;
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898 if (!test_bit(CF_SG_RESTART, &cam->flags))
899 mcam_ctlr_start(cam);
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900 spin_unlock_irqrestore(&cam->dev_lock, flags);
901 return 0;
902}
903
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904/* ----------------------------------------------------------------------- */
905/*
906 * Videobuf2 interface code.
907 */
abfa3df3 908
fc714e70
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909static int mcam_vb_queue_setup(struct vb2_queue *vq,
910 const struct v4l2_format *fmt, unsigned int *nbufs,
035aa147 911 unsigned int *num_planes, unsigned int sizes[],
b5210fd2 912 void *alloc_ctxs[])
abfa3df3 913{
b5210fd2 914 struct mcam_camera *cam = vb2_get_drv_priv(vq);
cbc4f3a2 915 int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
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916
917 sizes[0] = cam->pix_format.sizeimage;
918 *num_planes = 1; /* Someday we have to support planar formats... */
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919 if (*nbufs < minbufs)
920 *nbufs = minbufs;
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921 if (cam->buffer_mode == B_DMA_contig)
922 alloc_ctxs[0] = cam->vb_alloc_ctx;
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923 return 0;
924}
925
cbc4f3a2 926
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927static void mcam_vb_buf_queue(struct vb2_buffer *vb)
928{
929 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
930 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
931 unsigned long flags;
a9b36e85 932 int start;
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933
934 spin_lock_irqsave(&cam->dev_lock, flags);
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935 start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
936 list_add(&mvb->queue, &cam->buffers);
49df19eb 937 if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags))
cbc4f3a2 938 mcam_sg_restart(cam);
b5210fd2 939 spin_unlock_irqrestore(&cam->dev_lock, flags);
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940 if (start)
941 mcam_read_setup(cam);
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942}
943
cbc4f3a2 944
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945/*
946 * vb2 uses these to release the mutex when waiting in dqbuf. I'm
947 * not actually sure we need to do this (I'm not sure that vb2_dqbuf() needs
948 * to be called with the mutex held), but better safe than sorry.
949 */
950static void mcam_vb_wait_prepare(struct vb2_queue *vq)
951{
952 struct mcam_camera *cam = vb2_get_drv_priv(vq);
953
954 mutex_unlock(&cam->s_mutex);
955}
956
957static void mcam_vb_wait_finish(struct vb2_queue *vq)
958{
959 struct mcam_camera *cam = vb2_get_drv_priv(vq);
abfa3df3 960
abfa3df3 961 mutex_lock(&cam->s_mutex);
b5210fd2 962}
abfa3df3 963
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964/*
965 * These need to be called with the mutex held from vb2
966 */
bd323e28 967static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
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968{
969 struct mcam_camera *cam = vb2_get_drv_priv(vq);
abfa3df3 970
bd323e28
MS
971 if (cam->state != S_IDLE) {
972 INIT_LIST_HEAD(&cam->buffers);
a9b36e85 973 return -EINVAL;
bd323e28 974 }
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975 cam->sequence = 0;
976 /*
977 * Videobuf2 sneakily hoards all the buffers and won't
978 * give them to us until *after* streaming starts. But
979 * we can't actually start streaming until we have a
980 * destination. So go into a wait state and hope they
981 * give us buffers soon.
982 */
983 if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
984 cam->state = S_BUFWAIT;
985 return 0;
abfa3df3 986 }
a9b36e85 987 return mcam_read_setup(cam);
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988}
989
990static int mcam_vb_stop_streaming(struct vb2_queue *vq)
991{
992 struct mcam_camera *cam = vb2_get_drv_priv(vq);
993 unsigned long flags;
994
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995 if (cam->state == S_BUFWAIT) {
996 /* They never gave us buffers */
997 cam->state = S_IDLE;
998 return 0;
999 }
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1000 if (cam->state != S_STREAMING)
1001 return -EINVAL;
1002 mcam_ctlr_stop_dma(cam);
abfa3df3 1003 /*
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1004 * VB2 reclaims the buffers, so we need to forget
1005 * about them.
abfa3df3 1006 */
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1007 spin_lock_irqsave(&cam->dev_lock, flags);
1008 INIT_LIST_HEAD(&cam->buffers);
1009 spin_unlock_irqrestore(&cam->dev_lock, flags);
1010 return 0;
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JC
1011}
1012
1013
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1014static const struct vb2_ops mcam_vb2_ops = {
1015 .queue_setup = mcam_vb_queue_setup,
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1016 .buf_queue = mcam_vb_buf_queue,
1017 .start_streaming = mcam_vb_start_streaming,
1018 .stop_streaming = mcam_vb_stop_streaming,
1019 .wait_prepare = mcam_vb_wait_prepare,
1020 .wait_finish = mcam_vb_wait_finish,
1021};
abfa3df3 1022
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1023
1024#ifdef MCAM_MODE_DMA_SG
cbc4f3a2 1025/*
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1026 * Scatter/gather mode uses all of the above functions plus a
1027 * few extras to deal with DMA mapping.
cbc4f3a2 1028 */
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1029static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1030{
1031 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1032 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1033 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1034
1035 mvb->dma_desc = dma_alloc_coherent(cam->dev,
1036 ndesc * sizeof(struct mcam_dma_desc),
1037 &mvb->dma_desc_pa, GFP_KERNEL);
1038 if (mvb->dma_desc == NULL) {
1039 cam_err(cam, "Unable to get DMA descriptor array\n");
1040 return -ENOMEM;
1041 }
1042 return 0;
1043}
1044
1045static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1046{
1047 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1048 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1049 struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
1050 struct mcam_dma_desc *desc = mvb->dma_desc;
1051 struct scatterlist *sg;
1052 int i;
1053
1054 mvb->dma_desc_nent = dma_map_sg(cam->dev, sgd->sglist, sgd->num_pages,
1055 DMA_FROM_DEVICE);
1056 if (mvb->dma_desc_nent <= 0)
1057 return -EIO; /* Not sure what's right here */
1058 for_each_sg(sgd->sglist, sg, mvb->dma_desc_nent, i) {
1059 desc->dma_addr = sg_dma_address(sg);
1060 desc->segment_len = sg_dma_len(sg);
1061 desc++;
1062 }
1063 return 0;
1064}
1065
1066static int mcam_vb_sg_buf_finish(struct vb2_buffer *vb)
1067{
1068 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1069 struct vb2_dma_sg_desc *sgd = vb2_dma_sg_plane_desc(vb, 0);
1070
1071 dma_unmap_sg(cam->dev, sgd->sglist, sgd->num_pages, DMA_FROM_DEVICE);
1072 return 0;
1073}
1074
1075static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1076{
1077 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1078 struct mcam_vb_buffer *mvb = vb_to_mvb(vb);
1079 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1080
1081 dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1082 mvb->dma_desc, mvb->dma_desc_pa);
1083}
1084
1085
cbc4f3a2
JC
1086static const struct vb2_ops mcam_vb2_sg_ops = {
1087 .queue_setup = mcam_vb_queue_setup,
1088 .buf_init = mcam_vb_sg_buf_init,
1089 .buf_prepare = mcam_vb_sg_buf_prepare,
1090 .buf_queue = mcam_vb_buf_queue,
1091 .buf_finish = mcam_vb_sg_buf_finish,
1092 .buf_cleanup = mcam_vb_sg_buf_cleanup,
1093 .start_streaming = mcam_vb_start_streaming,
1094 .stop_streaming = mcam_vb_stop_streaming,
1095 .wait_prepare = mcam_vb_wait_prepare,
1096 .wait_finish = mcam_vb_wait_finish,
1097};
1098
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1099#endif /* MCAM_MODE_DMA_SG */
1100
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1101static int mcam_setup_vb2(struct mcam_camera *cam)
1102{
1103 struct vb2_queue *vq = &cam->vb_queue;
abfa3df3 1104
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JC
1105 memset(vq, 0, sizeof(*vq));
1106 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
b5210fd2 1107 vq->drv_priv = cam;
cbc4f3a2
JC
1108 INIT_LIST_HEAD(&cam->buffers);
1109 switch (cam->buffer_mode) {
1110 case B_DMA_contig:
7498469f 1111#ifdef MCAM_MODE_DMA_CONTIG
cbc4f3a2 1112 vq->ops = &mcam_vb2_ops;
a9b36e85
JC
1113 vq->mem_ops = &vb2_dma_contig_memops;
1114 cam->vb_alloc_ctx = vb2_dma_contig_init_ctx(cam->dev);
cbc4f3a2 1115 vq->io_modes = VB2_MMAP | VB2_USERPTR;
7498469f
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1116 cam->dma_setup = mcam_ctlr_dma_contig;
1117 cam->frame_complete = mcam_dma_contig_done;
1118#endif
cbc4f3a2
JC
1119 break;
1120 case B_DMA_sg:
7498469f 1121#ifdef MCAM_MODE_DMA_SG
cbc4f3a2
JC
1122 vq->ops = &mcam_vb2_sg_ops;
1123 vq->mem_ops = &vb2_dma_sg_memops;
1124 vq->io_modes = VB2_MMAP | VB2_USERPTR;
7498469f
JC
1125 cam->dma_setup = mcam_ctlr_dma_sg;
1126 cam->frame_complete = mcam_dma_sg_done;
1127#endif
cbc4f3a2
JC
1128 break;
1129 case B_vmalloc:
7498469f
JC
1130#ifdef MCAM_MODE_VMALLOC
1131 tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1132 (unsigned long) cam);
cbc4f3a2 1133 vq->ops = &mcam_vb2_ops;
a9b36e85 1134 vq->mem_ops = &vb2_vmalloc_memops;
cbc4f3a2
JC
1135 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1136 vq->io_modes = VB2_MMAP;
7498469f
JC
1137 cam->dma_setup = mcam_ctlr_dma_vmalloc;
1138 cam->frame_complete = mcam_vmalloc_done;
1139#endif
cbc4f3a2
JC
1140 break;
1141 }
b5210fd2
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1142 return vb2_queue_init(vq);
1143}
1144
1145static void mcam_cleanup_vb2(struct mcam_camera *cam)
1146{
1147 vb2_queue_release(&cam->vb_queue);
7498469f 1148#ifdef MCAM_MODE_DMA_CONTIG
a9b36e85
JC
1149 if (cam->buffer_mode == B_DMA_contig)
1150 vb2_dma_contig_cleanup_ctx(cam->vb_alloc_ctx);
7498469f 1151#endif
b5210fd2
JC
1152}
1153
abfa3df3 1154
d43dae75 1155/* ---------------------------------------------------------------------- */
abfa3df3 1156/*
d43dae75 1157 * The long list of V4L2 ioctl() operations.
abfa3df3
JC
1158 */
1159
abfa3df3
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1160static int mcam_vidioc_streamon(struct file *filp, void *priv,
1161 enum v4l2_buf_type type)
1162{
1163 struct mcam_camera *cam = filp->private_data;
b5210fd2 1164 int ret;
abfa3df3 1165
abfa3df3 1166 mutex_lock(&cam->s_mutex);
b5210fd2 1167 ret = vb2_streamon(&cam->vb_queue, type);
abfa3df3 1168 mutex_unlock(&cam->s_mutex);
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JC
1169 return ret;
1170}
1171
1172
1173static int mcam_vidioc_streamoff(struct file *filp, void *priv,
1174 enum v4l2_buf_type type)
1175{
1176 struct mcam_camera *cam = filp->private_data;
b5210fd2 1177 int ret;
abfa3df3 1178
abfa3df3 1179 mutex_lock(&cam->s_mutex);
b5210fd2 1180 ret = vb2_streamoff(&cam->vb_queue, type);
abfa3df3 1181 mutex_unlock(&cam->s_mutex);
abfa3df3
JC
1182 return ret;
1183}
1184
1185
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1186static int mcam_vidioc_reqbufs(struct file *filp, void *priv,
1187 struct v4l2_requestbuffers *req)
1188{
1189 struct mcam_camera *cam = filp->private_data;
b5210fd2 1190 int ret;
abfa3df3 1191
abfa3df3 1192 mutex_lock(&cam->s_mutex);
b5210fd2 1193 ret = vb2_reqbufs(&cam->vb_queue, req);
abfa3df3
JC
1194 mutex_unlock(&cam->s_mutex);
1195 return ret;
1196}
1197
1198
1199static int mcam_vidioc_querybuf(struct file *filp, void *priv,
1200 struct v4l2_buffer *buf)
1201{
1202 struct mcam_camera *cam = filp->private_data;
b5210fd2 1203 int ret;
abfa3df3
JC
1204
1205 mutex_lock(&cam->s_mutex);
d43dae75 1206 ret = vb2_querybuf(&cam->vb_queue, buf);
abfa3df3 1207 mutex_unlock(&cam->s_mutex);
d43dae75 1208 return ret;
abfa3df3
JC
1209}
1210
d43dae75
JC
1211static int mcam_vidioc_qbuf(struct file *filp, void *priv,
1212 struct v4l2_buffer *buf)
1213{
1214 struct mcam_camera *cam = filp->private_data;
1215 int ret;
abfa3df3 1216
d43dae75
JC
1217 mutex_lock(&cam->s_mutex);
1218 ret = vb2_qbuf(&cam->vb_queue, buf);
1219 mutex_unlock(&cam->s_mutex);
1220 return ret;
1221}
abfa3df3 1222
d43dae75
JC
1223static int mcam_vidioc_dqbuf(struct file *filp, void *priv,
1224 struct v4l2_buffer *buf)
abfa3df3
JC
1225{
1226 struct mcam_camera *cam = filp->private_data;
b5210fd2 1227 int ret;
abfa3df3 1228
b5210fd2 1229 mutex_lock(&cam->s_mutex);
d43dae75 1230 ret = vb2_dqbuf(&cam->vb_queue, buf, filp->f_flags & O_NONBLOCK);
b5210fd2
JC
1231 mutex_unlock(&cam->s_mutex);
1232 return ret;
abfa3df3
JC
1233}
1234
1235
1236
1237static int mcam_vidioc_queryctrl(struct file *filp, void *priv,
1238 struct v4l2_queryctrl *qc)
1239{
1240 struct mcam_camera *cam = priv;
1241 int ret;
1242
1243 mutex_lock(&cam->s_mutex);
1244 ret = sensor_call(cam, core, queryctrl, qc);
1245 mutex_unlock(&cam->s_mutex);
1246 return ret;
1247}
1248
1249
1250static int mcam_vidioc_g_ctrl(struct file *filp, void *priv,
1251 struct v4l2_control *ctrl)
1252{
1253 struct mcam_camera *cam = priv;
1254 int ret;
1255
1256 mutex_lock(&cam->s_mutex);
1257 ret = sensor_call(cam, core, g_ctrl, ctrl);
1258 mutex_unlock(&cam->s_mutex);
1259 return ret;
1260}
1261
1262
1263static int mcam_vidioc_s_ctrl(struct file *filp, void *priv,
1264 struct v4l2_control *ctrl)
1265{
1266 struct mcam_camera *cam = priv;
1267 int ret;
1268
1269 mutex_lock(&cam->s_mutex);
1270 ret = sensor_call(cam, core, s_ctrl, ctrl);
1271 mutex_unlock(&cam->s_mutex);
1272 return ret;
1273}
1274
1275
abfa3df3
JC
1276static int mcam_vidioc_querycap(struct file *file, void *priv,
1277 struct v4l2_capability *cap)
1278{
1279 strcpy(cap->driver, "marvell_ccic");
1280 strcpy(cap->card, "marvell_ccic");
1281 cap->version = 1;
1282 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
1283 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1284 return 0;
1285}
1286
1287
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JC
1288static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1289 void *priv, struct v4l2_fmtdesc *fmt)
1290{
1291 if (fmt->index >= N_MCAM_FMTS)
1292 return -EINVAL;
1293 strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1294 sizeof(fmt->description));
1295 fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1296 return 0;
1297}
1298
1299static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1300 struct v4l2_format *fmt)
1301{
1302 struct mcam_camera *cam = priv;
1303 struct mcam_format_struct *f;
1304 struct v4l2_pix_format *pix = &fmt->fmt.pix;
1305 struct v4l2_mbus_framefmt mbus_fmt;
1306 int ret;
1307
1308 f = mcam_find_format(pix->pixelformat);
1309 pix->pixelformat = f->pixelformat;
1310 v4l2_fill_mbus_format(&mbus_fmt, pix, f->mbus_code);
1311 mutex_lock(&cam->s_mutex);
1312 ret = sensor_call(cam, video, try_mbus_fmt, &mbus_fmt);
1313 mutex_unlock(&cam->s_mutex);
1314 v4l2_fill_pix_format(pix, &mbus_fmt);
1315 pix->bytesperline = pix->width * f->bpp;
1316 pix->sizeimage = pix->height * pix->bytesperline;
1317 return ret;
1318}
1319
1320static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1321 struct v4l2_format *fmt)
1322{
1323 struct mcam_camera *cam = priv;
1324 struct mcam_format_struct *f;
1325 int ret;
1326
1327 /*
1328 * Can't do anything if the device is not idle
1329 * Also can't if there are streaming buffers in place.
1330 */
b5210fd2 1331 if (cam->state != S_IDLE || cam->vb_queue.num_buffers > 0)
abfa3df3
JC
1332 return -EBUSY;
1333
1334 f = mcam_find_format(fmt->fmt.pix.pixelformat);
1335
1336 /*
1337 * See if the formatting works in principle.
1338 */
1339 ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1340 if (ret)
1341 return ret;
1342 /*
1343 * Now we start to change things for real, so let's do it
1344 * under lock.
1345 */
1346 mutex_lock(&cam->s_mutex);
1347 cam->pix_format = fmt->fmt.pix;
1348 cam->mbus_code = f->mbus_code;
1349
1350 /*
1351 * Make sure we have appropriate DMA buffers.
1352 */
a9b36e85 1353 if (cam->buffer_mode == B_vmalloc) {
7498469f
JC
1354 ret = mcam_check_dma_buffers(cam);
1355 if (ret)
1356 goto out;
abfa3df3 1357 }
a9b36e85 1358 mcam_set_config_needed(cam, 1);
abfa3df3
JC
1359out:
1360 mutex_unlock(&cam->s_mutex);
1361 return ret;
1362}
1363
1364/*
1365 * Return our stored notion of how the camera is/should be configured.
1366 * The V4l2 spec wants us to be smarter, and actually get this from
1367 * the camera (and not mess with it at open time). Someday.
1368 */
1369static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1370 struct v4l2_format *f)
1371{
1372 struct mcam_camera *cam = priv;
1373
1374 f->fmt.pix = cam->pix_format;
1375 return 0;
1376}
1377
1378/*
1379 * We only have one input - the sensor - so minimize the nonsense here.
1380 */
1381static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1382 struct v4l2_input *input)
1383{
1384 if (input->index != 0)
1385 return -EINVAL;
1386
1387 input->type = V4L2_INPUT_TYPE_CAMERA;
1388 input->std = V4L2_STD_ALL; /* Not sure what should go here */
1389 strcpy(input->name, "Camera");
1390 return 0;
1391}
1392
1393static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1394{
1395 *i = 0;
1396 return 0;
1397}
1398
1399static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1400{
1401 if (i != 0)
1402 return -EINVAL;
1403 return 0;
1404}
1405
1406/* from vivi.c */
1407static int mcam_vidioc_s_std(struct file *filp, void *priv, v4l2_std_id *a)
1408{
1409 return 0;
1410}
1411
1412/*
1413 * G/S_PARM. Most of this is done by the sensor, but we are
1414 * the level which controls the number of read buffers.
1415 */
1416static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1417 struct v4l2_streamparm *parms)
1418{
1419 struct mcam_camera *cam = priv;
1420 int ret;
1421
1422 mutex_lock(&cam->s_mutex);
1423 ret = sensor_call(cam, video, g_parm, parms);
1424 mutex_unlock(&cam->s_mutex);
1425 parms->parm.capture.readbuffers = n_dma_bufs;
1426 return ret;
1427}
1428
1429static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1430 struct v4l2_streamparm *parms)
1431{
1432 struct mcam_camera *cam = priv;
1433 int ret;
1434
1435 mutex_lock(&cam->s_mutex);
1436 ret = sensor_call(cam, video, s_parm, parms);
1437 mutex_unlock(&cam->s_mutex);
1438 parms->parm.capture.readbuffers = n_dma_bufs;
1439 return ret;
1440}
1441
1442static int mcam_vidioc_g_chip_ident(struct file *file, void *priv,
1443 struct v4l2_dbg_chip_ident *chip)
1444{
1445 struct mcam_camera *cam = priv;
1446
1447 chip->ident = V4L2_IDENT_NONE;
1448 chip->revision = 0;
1449 if (v4l2_chip_match_host(&chip->match)) {
1450 chip->ident = cam->chip_id;
1451 return 0;
1452 }
1453 return sensor_call(cam, core, g_chip_ident, chip);
1454}
1455
1456static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1457 struct v4l2_frmsizeenum *sizes)
1458{
1459 struct mcam_camera *cam = priv;
1460 int ret;
1461
1462 mutex_lock(&cam->s_mutex);
1463 ret = sensor_call(cam, video, enum_framesizes, sizes);
1464 mutex_unlock(&cam->s_mutex);
1465 return ret;
1466}
1467
1468static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1469 struct v4l2_frmivalenum *interval)
1470{
1471 struct mcam_camera *cam = priv;
1472 int ret;
1473
1474 mutex_lock(&cam->s_mutex);
1475 ret = sensor_call(cam, video, enum_frameintervals, interval);
1476 mutex_unlock(&cam->s_mutex);
1477 return ret;
1478}
1479
1480#ifdef CONFIG_VIDEO_ADV_DEBUG
1481static int mcam_vidioc_g_register(struct file *file, void *priv,
1482 struct v4l2_dbg_register *reg)
1483{
1484 struct mcam_camera *cam = priv;
1485
1486 if (v4l2_chip_match_host(&reg->match)) {
1487 reg->val = mcam_reg_read(cam, reg->reg);
1488 reg->size = 4;
1489 return 0;
1490 }
1491 return sensor_call(cam, core, g_register, reg);
1492}
1493
1494static int mcam_vidioc_s_register(struct file *file, void *priv,
1495 struct v4l2_dbg_register *reg)
1496{
1497 struct mcam_camera *cam = priv;
1498
1499 if (v4l2_chip_match_host(&reg->match)) {
1500 mcam_reg_write(cam, reg->reg, reg->val);
1501 return 0;
1502 }
1503 return sensor_call(cam, core, s_register, reg);
1504}
1505#endif
1506
abfa3df3
JC
1507static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1508 .vidioc_querycap = mcam_vidioc_querycap,
1509 .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1510 .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1511 .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap,
1512 .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap,
1513 .vidioc_enum_input = mcam_vidioc_enum_input,
1514 .vidioc_g_input = mcam_vidioc_g_input,
1515 .vidioc_s_input = mcam_vidioc_s_input,
1516 .vidioc_s_std = mcam_vidioc_s_std,
1517 .vidioc_reqbufs = mcam_vidioc_reqbufs,
1518 .vidioc_querybuf = mcam_vidioc_querybuf,
1519 .vidioc_qbuf = mcam_vidioc_qbuf,
1520 .vidioc_dqbuf = mcam_vidioc_dqbuf,
1521 .vidioc_streamon = mcam_vidioc_streamon,
1522 .vidioc_streamoff = mcam_vidioc_streamoff,
1523 .vidioc_queryctrl = mcam_vidioc_queryctrl,
1524 .vidioc_g_ctrl = mcam_vidioc_g_ctrl,
1525 .vidioc_s_ctrl = mcam_vidioc_s_ctrl,
1526 .vidioc_g_parm = mcam_vidioc_g_parm,
1527 .vidioc_s_parm = mcam_vidioc_s_parm,
1528 .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1529 .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
1530 .vidioc_g_chip_ident = mcam_vidioc_g_chip_ident,
1531#ifdef CONFIG_VIDEO_ADV_DEBUG
1532 .vidioc_g_register = mcam_vidioc_g_register,
1533 .vidioc_s_register = mcam_vidioc_s_register,
1534#endif
1535};
1536
abfa3df3
JC
1537/* ---------------------------------------------------------------------- */
1538/*
d43dae75 1539 * Our various file operations.
abfa3df3 1540 */
d43dae75
JC
1541static int mcam_v4l_open(struct file *filp)
1542{
1543 struct mcam_camera *cam = video_drvdata(filp);
1544 int ret = 0;
abfa3df3 1545
d43dae75 1546 filp->private_data = cam;
abfa3df3 1547
d43dae75
JC
1548 frames = singles = delivered = 0;
1549 mutex_lock(&cam->s_mutex);
1550 if (cam->users == 0) {
1551 ret = mcam_setup_vb2(cam);
1552 if (ret)
1553 goto out;
1554 mcam_ctlr_power_up(cam);
1555 __mcam_cam_reset(cam);
1556 mcam_set_config_needed(cam, 1);
1557 }
1558 (cam->users)++;
1559out:
1560 mutex_unlock(&cam->s_mutex);
1561 return ret;
a9b36e85 1562}
abfa3df3 1563
abfa3df3 1564
d43dae75
JC
1565static int mcam_v4l_release(struct file *filp)
1566{
1567 struct mcam_camera *cam = filp->private_data;
b5210fd2 1568
67de3311 1569 cam_dbg(cam, "Release, %d frames, %d singles, %d delivered\n", frames,
d43dae75
JC
1570 singles, delivered);
1571 mutex_lock(&cam->s_mutex);
1572 (cam->users)--;
d43dae75 1573 if (cam->users == 0) {
0770d07f 1574 mcam_ctlr_stop_dma(cam);
d43dae75
JC
1575 mcam_cleanup_vb2(cam);
1576 mcam_ctlr_power_down(cam);
1577 if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1578 mcam_free_dma_bufs(cam);
1579 }
1580 mutex_unlock(&cam->s_mutex);
1581 return 0;
abfa3df3
JC
1582}
1583
d43dae75
JC
1584static ssize_t mcam_v4l_read(struct file *filp,
1585 char __user *buffer, size_t len, loff_t *pos)
a9b36e85 1586{
d43dae75
JC
1587 struct mcam_camera *cam = filp->private_data;
1588 int ret;
a9b36e85 1589
d43dae75
JC
1590 mutex_lock(&cam->s_mutex);
1591 ret = vb2_read(&cam->vb_queue, buffer, len, pos,
1592 filp->f_flags & O_NONBLOCK);
1593 mutex_unlock(&cam->s_mutex);
1594 return ret;
a9b36e85 1595}
abfa3df3 1596
d43dae75
JC
1597
1598
1599static unsigned int mcam_v4l_poll(struct file *filp,
1600 struct poll_table_struct *pt)
cbc4f3a2 1601{
d43dae75
JC
1602 struct mcam_camera *cam = filp->private_data;
1603 int ret;
cbc4f3a2 1604
d43dae75
JC
1605 mutex_lock(&cam->s_mutex);
1606 ret = vb2_poll(&cam->vb_queue, filp, pt);
1607 mutex_unlock(&cam->s_mutex);
1608 return ret;
1609}
1610
1611
1612static int mcam_v4l_mmap(struct file *filp, struct vm_area_struct *vma)
1613{
1614 struct mcam_camera *cam = filp->private_data;
1615 int ret;
1616
1617 mutex_lock(&cam->s_mutex);
1618 ret = vb2_mmap(&cam->vb_queue, vma);
1619 mutex_unlock(&cam->s_mutex);
1620 return ret;
cbc4f3a2
JC
1621}
1622
1623
abfa3df3 1624
d43dae75
JC
1625static const struct v4l2_file_operations mcam_v4l_fops = {
1626 .owner = THIS_MODULE,
1627 .open = mcam_v4l_open,
1628 .release = mcam_v4l_release,
1629 .read = mcam_v4l_read,
1630 .poll = mcam_v4l_poll,
1631 .mmap = mcam_v4l_mmap,
1632 .unlocked_ioctl = video_ioctl2,
1633};
1634
1635
1636/*
1637 * This template device holds all of those v4l2 methods; we
1638 * clone it for specific real devices.
1639 */
1640static struct video_device mcam_v4l_template = {
1641 .name = "mcam",
1642 .tvnorms = V4L2_STD_NTSC_M,
1643 .current_norm = V4L2_STD_NTSC_M, /* make mplayer happy */
1644
1645 .fops = &mcam_v4l_fops,
1646 .ioctl_ops = &mcam_v4l_ioctl_ops,
1647 .release = video_device_release_empty,
1648};
1649
1650/* ---------------------------------------------------------------------- */
1651/*
1652 * Interrupt handler stuff
1653 */
abfa3df3
JC
1654static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1655{
1656 /*
1657 * Basic frame housekeeping.
1658 */
abfa3df3
JC
1659 set_bit(frame, &cam->flags);
1660 clear_bit(CF_DMA_ACTIVE, &cam->flags);
a9b36e85 1661 cam->next_buf = frame;
abfa3df3 1662 cam->buf_seq[frame] = ++(cam->sequence);
a9b36e85 1663 frames++;
abfa3df3 1664 /*
cbc4f3a2 1665 * "This should never happen"
abfa3df3 1666 */
cbc4f3a2
JC
1667 if (cam->state != S_STREAMING)
1668 return;
1669 /*
1670 * Process the frame and set up the next one.
1671 */
7498469f 1672 cam->frame_complete(cam, frame);
abfa3df3
JC
1673}
1674
1675
d43dae75
JC
1676/*
1677 * The interrupt handler; this needs to be called from the
1678 * platform irq handler with the lock held.
1679 */
abfa3df3
JC
1680int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1681{
1682 unsigned int frame, handled = 0;
1683
1684 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
1685 /*
1686 * Handle any frame completions. There really should
1687 * not be more than one of these, or we have fallen
1688 * far behind.
cbc4f3a2
JC
1689 *
1690 * When running in S/G mode, the frame number lacks any
1691 * real meaning - there's only one descriptor array - but
1692 * the controller still picks a different one to signal
1693 * each time.
abfa3df3
JC
1694 */
1695 for (frame = 0; frame < cam->nbufs; frame++)
1696 if (irqs & (IRQ_EOF0 << frame)) {
1697 mcam_frame_complete(cam, frame);
1698 handled = 1;
f2354dd1
JC
1699 if (cam->buffer_mode == B_DMA_sg)
1700 break;
abfa3df3
JC
1701 }
1702 /*
1703 * If a frame starts, note that we have DMA active. This
1704 * code assumes that we won't get multiple frame interrupts
1705 * at once; may want to rethink that.
1706 */
1707 if (irqs & (IRQ_SOF0 | IRQ_SOF1 | IRQ_SOF2)) {
1708 set_bit(CF_DMA_ACTIVE, &cam->flags);
1709 handled = 1;
cbc4f3a2
JC
1710 if (cam->buffer_mode == B_DMA_sg)
1711 mcam_ctlr_stop(cam);
abfa3df3
JC
1712 }
1713 return handled;
1714}
1715
d43dae75 1716/* ---------------------------------------------------------------------- */
abfa3df3
JC
1717/*
1718 * Registration and such.
1719 */
abfa3df3 1720static struct ov7670_config sensor_cfg = {
abfa3df3
JC
1721 /*
1722 * Exclude QCIF mode, because it only captures a tiny portion
1723 * of the sensor FOV
1724 */
1725 .min_width = 320,
1726 .min_height = 240,
1727};
1728
1729
1730int mccic_register(struct mcam_camera *cam)
1731{
1732 struct i2c_board_info ov7670_info = {
1733 .type = "ov7670",
1c68f889 1734 .addr = 0x42 >> 1,
abfa3df3
JC
1735 .platform_data = &sensor_cfg,
1736 };
1737 int ret;
1738
7498469f
JC
1739 /*
1740 * Validate the requested buffer mode.
1741 */
1742 if (buffer_mode >= 0)
1743 cam->buffer_mode = buffer_mode;
1744 if (cam->buffer_mode == B_DMA_sg &&
1745 cam->chip_id == V4L2_IDENT_CAFE) {
1746 printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, "
1747 "attempting vmalloc mode instead\n");
1748 cam->buffer_mode = B_vmalloc;
1749 }
1750 if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1751 printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1752 cam->buffer_mode);
1753 return -EINVAL;
1754 }
abfa3df3
JC
1755 /*
1756 * Register with V4L
1757 */
1758 ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1759 if (ret)
1760 return ret;
1761
1762 mutex_init(&cam->s_mutex);
1763 cam->state = S_NOTREADY;
1764 mcam_set_config_needed(cam, 1);
abfa3df3
JC
1765 cam->pix_format = mcam_def_pix_format;
1766 cam->mbus_code = mcam_def_mbus_code;
b5210fd2 1767 INIT_LIST_HEAD(&cam->buffers);
abfa3df3
JC
1768 mcam_ctlr_init(cam);
1769
abfa3df3
JC
1770 /*
1771 * Try to find the sensor.
1772 */
2164b5af
JC
1773 sensor_cfg.clock_speed = cam->clock_speed;
1774 sensor_cfg.use_smbus = cam->use_smbus;
abfa3df3
JC
1775 cam->sensor_addr = ov7670_info.addr;
1776 cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
595a93a4 1777 cam->i2c_adapter, &ov7670_info, NULL);
abfa3df3
JC
1778 if (cam->sensor == NULL) {
1779 ret = -ENODEV;
1780 goto out_unregister;
1781 }
1782
1783 ret = mcam_cam_init(cam);
1784 if (ret)
1785 goto out_unregister;
1786 /*
1787 * Get the v4l2 setup done.
1788 */
1789 mutex_lock(&cam->s_mutex);
1790 cam->vdev = mcam_v4l_template;
1791 cam->vdev.debug = 0;
1792 cam->vdev.v4l2_dev = &cam->v4l2_dev;
1793 ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1794 if (ret)
1795 goto out;
1796 video_set_drvdata(&cam->vdev, cam);
1797
1798 /*
1799 * If so requested, try to get our DMA buffers now.
1800 */
a9b36e85 1801 if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
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1802 if (mcam_alloc_dma_bufs(cam, 1))
1803 cam_warn(cam, "Unable to alloc DMA buffers at load"
1804 " will try again later.");
1805 }
1806
1807out:
1808 mutex_unlock(&cam->s_mutex);
1809 return ret;
1810out_unregister:
1811 v4l2_device_unregister(&cam->v4l2_dev);
1812 return ret;
1813}
1814
1815
1816void mccic_shutdown(struct mcam_camera *cam)
1817{
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1818 /*
1819 * If we have no users (and we really, really should have no
1820 * users) the device will already be powered down. Trying to
1821 * take it down again will wedge the machine, which is frowned
1822 * upon.
1823 */
1824 if (cam->users > 0) {
abfa3df3 1825 cam_warn(cam, "Removing a device with users!\n");
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1826 mcam_ctlr_power_down(cam);
1827 }
b5210fd2 1828 vb2_queue_release(&cam->vb_queue);
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1829 if (cam->buffer_mode == B_vmalloc)
1830 mcam_free_dma_bufs(cam);
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1831 video_unregister_device(&cam->vdev);
1832 v4l2_device_unregister(&cam->v4l2_dev);
1833}
1834
1835/*
1836 * Power management
1837 */
1838#ifdef CONFIG_PM
1839
1840void mccic_suspend(struct mcam_camera *cam)
1841{
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1842 mutex_lock(&cam->s_mutex);
1843 if (cam->users > 0) {
1844 enum mcam_state cstate = cam->state;
abfa3df3 1845
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1846 mcam_ctlr_stop_dma(cam);
1847 mcam_ctlr_power_down(cam);
1848 cam->state = cstate;
1849 }
1850 mutex_unlock(&cam->s_mutex);
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1851}
1852
1853int mccic_resume(struct mcam_camera *cam)
1854{
1855 int ret = 0;
1856
1857 mutex_lock(&cam->s_mutex);
1858 if (cam->users > 0) {
1859 mcam_ctlr_power_up(cam);
1860 __mcam_cam_reset(cam);
1861 } else {
1862 mcam_ctlr_power_down(cam);
1863 }
1864 mutex_unlock(&cam->s_mutex);
1865
1866 set_bit(CF_CONFIG_NEEDED, &cam->flags);
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1867 if (cam->state == S_STREAMING) {
1868 /*
1869 * If there was a buffer in the DMA engine at suspend
1870 * time, put it back on the queue or we'll forget about it.
1871 */
1872 if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0])
1873 list_add(&cam->vb_bufs[0]->queue, &cam->buffers);
a9b36e85 1874 ret = mcam_read_setup(cam);
bb0a896e 1875 }
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1876 return ret;
1877}
1878#endif /* CONFIG_PM */