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Merge branch 'timers-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / media / video / gspca / ov519.c
CommitLineData
6a7eba24
JFM		 1/**
2 * OV519 driver
3 *
4 * Copyright (C) 2008 Jean-Francois Moine (http://moinejf.free.fr)
b46aaa02 5 * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
6a7eba24 6 *
2961e875
RB		 7 * This module is adapted from the ov51x-jpeg package, which itself
8 * was adapted from the ov511 driver.
9 *
10 * Original copyright for the ov511 driver is:
11 *
b46aaa02 12 * Copyright (c) 1999-2006 Mark W. McClelland
2961e875 13 * Support for OV519, OV8610 Copyright (c) 2003 Joerg Heckenbach
b46aaa02
HG		 14 * Many improvements by Bret Wallach <bwallac1@san.rr.com>
15 * Color fixes by by Orion Sky Lawlor <olawlor@acm.org> (2/26/2000)
16 * OV7620 fixes by Charl P. Botha <cpbotha@ieee.org>
17 * Changes by Claudio Matsuoka <claudio@conectiva.com>
2961e875
RB		 18 *
19 * ov51x-jpeg original copyright is:
20 *
21 * Copyright (c) 2004-2007 Romain Beauxis <toots@rastageeks.org>
22 * Support for OV7670 sensors was contributed by Sam Skipsey <aoanla@yahoo.com>
6a7eba24
JFM		 23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37 *
38 */
39#define MODULE_NAME "ov519"
40
417a4d26 41#include <linux/input.h>
6a7eba24
JFM		 42#include "gspca.h"
43
9a731a32
JFM		 44/* The jpeg_hdr is used by w996Xcf only */
45/* The CONEX_CAM define for jpeg.h needs renaming, now its used here too */
46#define CONEX_CAM
47#include "jpeg.h"
48
6a7eba24
JFM		 49MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
50MODULE_DESCRIPTION("OV519 USB Camera Driver");
51MODULE_LICENSE("GPL");
52
53/* global parameters */
54static int frame_rate;
55
56/* Number of times to retry a failed I2C transaction. Increase this if you
57 * are getting "Failed to read sensor ID..." */
58static int i2c_detect_tries = 10;
59
62833acd
JFM		 60/* controls */
61enum e_ctrl {
62 BRIGHTNESS,
63 CONTRAST,
64 COLORS,
65 HFLIP,
66 VFLIP,
67 AUTOBRIGHT,
68 FREQ,
69 NCTRL /* number of controls */
70};
71
6a7eba24
JFM		 72/* ov519 device descriptor */
73struct sd {
74 struct gspca_dev gspca_dev; /* !! must be the first item */
75
62833acd
JFM		 76 struct gspca_ctrl ctrls[NCTRL];
77
9d1593a8 78 u8 packet_nr;
92918a53 79
49809d6a
HG		 80 char bridge;
81#define BRIDGE_OV511 0
82#define BRIDGE_OV511PLUS 1
83#define BRIDGE_OV518 2
84#define BRIDGE_OV518PLUS 3
42e142f6 85#define BRIDGE_OV519 4 /* = ov530 */
635118d5 86#define BRIDGE_OVFX2 5
a511ba94 87#define BRIDGE_W9968CF 6
9e4d8258
HG		 88#define BRIDGE_MASK 7
89
90 char invert_led;
91#define BRIDGE_INVERT_LED 8
49809d6a 92
417a4d26
HG		 93 char snapshot_pressed;
94 char snapshot_needs_reset;
95
6a7eba24 96 /* Determined by sensor type */
9d1593a8 97 u8 sif;
6a7eba24 98
9d1593a8 99 u8 quality;
79b35902
HG		 100#define QUALITY_MIN 50
101#define QUALITY_MAX 70
102#define QUALITY_DEF 50
6a7eba24 103
9d1593a8
JFM		 104 u8 stopped; /* Streaming is temporarily paused */
105 u8 first_frame;
6a7eba24 106
9d1593a8
JFM		 107 u8 frame_rate; /* current Framerate */
108 u8 clockdiv; /* clockdiv override */
6a7eba24 109
7bbe6b8d 110 s8 sensor; /* Type of image sensor chip (SEN_*) */
a511ba94
HG		 111
112 u8 sensor_addr;
d6fa6638
JFM		 113 u16 sensor_width;
114 u16 sensor_height;
115 s16 sensor_reg_cache[256];
79b35902 116
9a731a32 117 u8 jpeg_hdr[JPEG_HDR_SZ];
6a7eba24 118};
7bbe6b8d
JFM		 119enum sensors {
120 SEN_OV2610,
121 SEN_OV3610,
122 SEN_OV6620,
123 SEN_OV6630,
124 SEN_OV66308AF,
125 SEN_OV7610,
126 SEN_OV7620,
127 SEN_OV7620AE,
128 SEN_OV7640,
129 SEN_OV7648,
42e142f6 130 SEN_OV7660,
7bbe6b8d
JFM		 131 SEN_OV7670,
132 SEN_OV76BE,
133 SEN_OV8610,
134};
6a7eba24 135
a511ba94
HG		 136/* Note this is a bit of a hack, but the w9968cf driver needs the code for all
137 the ov sensors which is already present here. When we have the time we
138 really should move the sensor drivers to v4l2 sub drivers. */
139#include "w996Xcf.c"
140
6a7eba24 141/* V4L2 controls supported by the driver */
49809d6a
HG		 142static void setbrightness(struct gspca_dev *gspca_dev);
143static void setcontrast(struct gspca_dev *gspca_dev);
144static void setcolors(struct gspca_dev *gspca_dev);
62833acd
JFM		 145static void sethvflip(struct gspca_dev *gspca_dev);
146static void setautobright(struct gspca_dev *gspca_dev);
147static void setfreq(struct gspca_dev *gspca_dev);
148static void setfreq_i(struct sd *sd);
6a7eba24 149
02ab18b0 150static const struct ctrl sd_ctrls[] = {
62833acd 151[BRIGHTNESS] = {
6a7eba24
JFM		 152 {
153 .id = V4L2_CID_BRIGHTNESS,
154 .type = V4L2_CTRL_TYPE_INTEGER,
155 .name = "Brightness",
156 .minimum = 0,
157 .maximum = 255,
158 .step = 1,
62833acd 159 .default_value = 127,
6a7eba24 160 },
62833acd 161 .set_control = setbrightness,
6a7eba24 162 },
62833acd 163[CONTRAST] = {
6a7eba24
JFM		 164 {
165 .id = V4L2_CID_CONTRAST,
166 .type = V4L2_CTRL_TYPE_INTEGER,
167 .name = "Contrast",
168 .minimum = 0,
169 .maximum = 255,
170 .step = 1,
62833acd 171 .default_value = 127,
6a7eba24 172 },
62833acd 173 .set_control = setcontrast,
6a7eba24 174 },
62833acd 175[COLORS] = {
6a7eba24
JFM		 176 {
177 .id = V4L2_CID_SATURATION,
178 .type = V4L2_CTRL_TYPE_INTEGER,
594f5b8b 179 .name = "Color",
6a7eba24
JFM		 180 .minimum = 0,
181 .maximum = 255,
182 .step = 1,
62833acd 183 .default_value = 127,
6a7eba24 184 },
62833acd 185 .set_control = setcolors,
6a7eba24 186 },
42e142f6 187/* The flip controls work for sensors ov7660 and ov7670 only */
62833acd 188[HFLIP] = {
0cd6759d
JFM		 189 {
190 .id = V4L2_CID_HFLIP,
191 .type = V4L2_CTRL_TYPE_BOOLEAN,
192 .name = "Mirror",
193 .minimum = 0,
194 .maximum = 1,
195 .step = 1,
62833acd 196 .default_value = 0,
0cd6759d 197 },
62833acd 198 .set_control = sethvflip,
0cd6759d 199 },
62833acd 200[VFLIP] = {
0cd6759d
JFM		 201 {
202 .id = V4L2_CID_VFLIP,
203 .type = V4L2_CTRL_TYPE_BOOLEAN,
204 .name = "Vflip",
205 .minimum = 0,
206 .maximum = 1,
207 .step = 1,
62833acd 208 .default_value = 0,
0cd6759d 209 },
62833acd 210 .set_control = sethvflip,
0cd6759d 211 },
62833acd 212[AUTOBRIGHT] = {
02ab18b0
HG		 213 {
214 .id = V4L2_CID_AUTOBRIGHTNESS,
215 .type = V4L2_CTRL_TYPE_BOOLEAN,
216 .name = "Auto Brightness",
217 .minimum = 0,
218 .maximum = 1,
219 .step = 1,
62833acd 220 .default_value = 1,
02ab18b0 221 },
62833acd 222 .set_control = setautobright,
02ab18b0 223 },
62833acd 224[FREQ] = {
02ab18b0
HG		 225 {
226 .id = V4L2_CID_POWER_LINE_FREQUENCY,
227 .type = V4L2_CTRL_TYPE_MENU,
228 .name = "Light frequency filter",
229 .minimum = 0,
87bae740 230 .maximum = 2, /* 0: no flicker, 1: 50Hz, 2:60Hz, 3: auto */
02ab18b0 231 .step = 1,
62833acd 232 .default_value = 0,
02ab18b0 233 },
62833acd 234 .set_control = setfreq,
02ab18b0 235 },
6a7eba24
JFM		 236};
237
83db7688
JFM		 238/* table of the disabled controls */
239static const unsigned ctrl_dis[] = {
240[SEN_OV2610] = (1 << NCTRL) - 1, /* no control */
241
242[SEN_OV3610] = (1 << NCTRL) - 1, /* no control */
243
244[SEN_OV6620] = (1 << HFLIP) |
245 (1 << VFLIP),
246
247[SEN_OV6630] = (1 << HFLIP) |
248 (1 << VFLIP),
249
250[SEN_OV66308AF] = (1 << HFLIP) |
251 (1 << VFLIP),
252
253[SEN_OV7610] = (1 << HFLIP) |
254 (1 << VFLIP),
255
256[SEN_OV7620] = (1 << HFLIP) |
257 (1 << VFLIP),
258
259[SEN_OV7620AE] = (1 << HFLIP) |
260 (1 << VFLIP),
261
262[SEN_OV7640] = (1 << HFLIP) |
263 (1 << VFLIP) |
264 (1 << AUTOBRIGHT) |
265 (1 << CONTRAST),
266
267[SEN_OV7648] = (1 << HFLIP) |
268 (1 << VFLIP) |
269 (1 << AUTOBRIGHT) |
270 (1 << CONTRAST),
271
42e142f6
JFM		 272[SEN_OV7660] = (1 << AUTOBRIGHT),
273
83db7688
JFM		 274[SEN_OV7670] = (1 << COLORS) |
275 (1 << AUTOBRIGHT),
276
277[SEN_OV76BE] = (1 << HFLIP) |
278 (1 << VFLIP),
279
280[SEN_OV8610] = (1 << HFLIP) |
281 (1 << VFLIP) |
282 (1 << FREQ),
283};
284
49809d6a 285static const struct v4l2_pix_format ov519_vga_mode[] = {
c2446b3e
JFM		 286 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
287 .bytesperline = 320,
594f5b8b 288 .sizeimage = 320 * 240 * 3 / 8 + 590,
c2446b3e
JFM		 289 .colorspace = V4L2_COLORSPACE_JPEG,
290 .priv = 1},
291 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
292 .bytesperline = 640,
293 .sizeimage = 640 * 480 * 3 / 8 + 590,
294 .colorspace = V4L2_COLORSPACE_JPEG,
295 .priv = 0},
6a7eba24 296};
49809d6a 297static const struct v4l2_pix_format ov519_sif_mode[] = {
124cc9c0
HG		 298 {160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
299 .bytesperline = 160,
300 .sizeimage = 160 * 120 * 3 / 8 + 590,
301 .colorspace = V4L2_COLORSPACE_JPEG,
302 .priv = 3},
c2446b3e
JFM		 303 {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
304 .bytesperline = 176,
594f5b8b 305 .sizeimage = 176 * 144 * 3 / 8 + 590,
c2446b3e
JFM		 306 .colorspace = V4L2_COLORSPACE_JPEG,
307 .priv = 1},
124cc9c0
HG		 308 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
309 .bytesperline = 320,
310 .sizeimage = 320 * 240 * 3 / 8 + 590,
311 .colorspace = V4L2_COLORSPACE_JPEG,
312 .priv = 2},
c2446b3e
JFM		 313 {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
314 .bytesperline = 352,
594f5b8b 315 .sizeimage = 352 * 288 * 3 / 8 + 590,
c2446b3e
JFM		 316 .colorspace = V4L2_COLORSPACE_JPEG,
317 .priv = 0},
6a7eba24
JFM		 318};
319
b282d873
HG		 320/* Note some of the sizeimage values for the ov511 / ov518 may seem
321 larger then necessary, however they need to be this big as the ov511 /
322 ov518 always fills the entire isoc frame, using 0 padding bytes when
323 it doesn't have any data. So with low framerates the amount of data
324 transfered can become quite large (libv4l will remove all the 0 padding
325 in userspace). */
49809d6a
HG		 326static const struct v4l2_pix_format ov518_vga_mode[] = {
327 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
328 .bytesperline = 320,
b282d873 329 .sizeimage = 320 * 240 * 3,
49809d6a
HG		 330 .colorspace = V4L2_COLORSPACE_JPEG,
331 .priv = 1},
332 {640, 480, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
333 .bytesperline = 640,
b282d873 334 .sizeimage = 640 * 480 * 2,
49809d6a
HG		 335 .colorspace = V4L2_COLORSPACE_JPEG,
336 .priv = 0},
337};
338static const struct v4l2_pix_format ov518_sif_mode[] = {
124cc9c0
HG		 339 {160, 120, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
340 .bytesperline = 160,
b282d873 341 .sizeimage = 70000,
124cc9c0
HG		 342 .colorspace = V4L2_COLORSPACE_JPEG,
343 .priv = 3},
49809d6a
HG		 344 {176, 144, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
345 .bytesperline = 176,
b282d873 346 .sizeimage = 70000,
49809d6a
HG		 347 .colorspace = V4L2_COLORSPACE_JPEG,
348 .priv = 1},
124cc9c0
HG		 349 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
350 .bytesperline = 320,
b282d873 351 .sizeimage = 320 * 240 * 3,
124cc9c0
HG		 352 .colorspace = V4L2_COLORSPACE_JPEG,
353 .priv = 2},
49809d6a
HG		 354 {352, 288, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
355 .bytesperline = 352,
b282d873 356 .sizeimage = 352 * 288 * 3,
49809d6a
HG		 357 .colorspace = V4L2_COLORSPACE_JPEG,
358 .priv = 0},
359};
360
1876bb92
HG		 361static const struct v4l2_pix_format ov511_vga_mode[] = {
362 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
363 .bytesperline = 320,
364 .sizeimage = 320 * 240 * 3,
365 .colorspace = V4L2_COLORSPACE_JPEG,
366 .priv = 1},
367 {640, 480, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
368 .bytesperline = 640,
369 .sizeimage = 640 * 480 * 2,
370 .colorspace = V4L2_COLORSPACE_JPEG,
371 .priv = 0},
372};
373static const struct v4l2_pix_format ov511_sif_mode[] = {
374 {160, 120, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
375 .bytesperline = 160,
b282d873 376 .sizeimage = 70000,
1876bb92
HG		 377 .colorspace = V4L2_COLORSPACE_JPEG,
378 .priv = 3},
379 {176, 144, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
380 .bytesperline = 176,
b282d873 381 .sizeimage = 70000,
1876bb92
HG		 382 .colorspace = V4L2_COLORSPACE_JPEG,
383 .priv = 1},
384 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
385 .bytesperline = 320,
386 .sizeimage = 320 * 240 * 3,
387 .colorspace = V4L2_COLORSPACE_JPEG,
388 .priv = 2},
389 {352, 288, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
390 .bytesperline = 352,
391 .sizeimage = 352 * 288 * 3,
392 .colorspace = V4L2_COLORSPACE_JPEG,
393 .priv = 0},
394};
49809d6a 395
635118d5
HG		 396static const struct v4l2_pix_format ovfx2_vga_mode[] = {
397 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
398 .bytesperline = 320,
399 .sizeimage = 320 * 240,
400 .colorspace = V4L2_COLORSPACE_SRGB,
401 .priv = 1},
402 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
403 .bytesperline = 640,
404 .sizeimage = 640 * 480,
405 .colorspace = V4L2_COLORSPACE_SRGB,
406 .priv = 0},
407};
408static const struct v4l2_pix_format ovfx2_cif_mode[] = {
409 {160, 120, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
410 .bytesperline = 160,
411 .sizeimage = 160 * 120,
412 .colorspace = V4L2_COLORSPACE_SRGB,
413 .priv = 3},
414 {176, 144, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
415 .bytesperline = 176,
416 .sizeimage = 176 * 144,
417 .colorspace = V4L2_COLORSPACE_SRGB,
418 .priv = 1},
419 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
420 .bytesperline = 320,
421 .sizeimage = 320 * 240,
422 .colorspace = V4L2_COLORSPACE_SRGB,
423 .priv = 2},
424 {352, 288, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
425 .bytesperline = 352,
426 .sizeimage = 352 * 288,
427 .colorspace = V4L2_COLORSPACE_SRGB,
428 .priv = 0},
429};
430static const struct v4l2_pix_format ovfx2_ov2610_mode[] = {
431 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
432 .bytesperline = 1600,
433 .sizeimage = 1600 * 1200,
434 .colorspace = V4L2_COLORSPACE_SRGB},
435};
436static const struct v4l2_pix_format ovfx2_ov3610_mode[] = {
635118d5
HG		 437 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
438 .bytesperline = 640,
439 .sizeimage = 640 * 480,
b46aaa02
HG		 440 .colorspace = V4L2_COLORSPACE_SRGB,
441 .priv = 1},
442 {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
443 .bytesperline = 800,
444 .sizeimage = 800 * 600,
445 .colorspace = V4L2_COLORSPACE_SRGB,
446 .priv = 1},
447 {1024, 768, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
448 .bytesperline = 1024,
449 .sizeimage = 1024 * 768,
450 .colorspace = V4L2_COLORSPACE_SRGB,
451 .priv = 1},
452 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
453 .bytesperline = 1600,
454 .sizeimage = 1600 * 1200,
455 .colorspace = V4L2_COLORSPACE_SRGB,
456 .priv = 0},
457 {2048, 1536, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
458 .bytesperline = 2048,
459 .sizeimage = 2048 * 1536,
460 .colorspace = V4L2_COLORSPACE_SRGB,
461 .priv = 0},
635118d5
HG		 462};
463
49809d6a 464/* Registers common to OV511 / OV518 */
1876bb92 465#define R51x_FIFO_PSIZE 0x30 /* 2 bytes wide w/ OV518(+) */
780e3121 466#define R51x_SYS_RESET 0x50
1876bb92
HG		 467 /* Reset type flags */
468 #define OV511_RESET_OMNICE 0x08
780e3121 469#define R51x_SYS_INIT 0x53
49809d6a 470#define R51x_SYS_SNAP 0x52
87bae740 471#define R51x_SYS_CUST_ID 0x5f
49809d6a
HG		 472#define R51x_COMP_LUT_BEGIN 0x80
473
474/* OV511 Camera interface register numbers */
1876bb92
HG		 475#define R511_CAM_DELAY 0x10
476#define R511_CAM_EDGE 0x11
477#define R511_CAM_PXCNT 0x12
478#define R511_CAM_LNCNT 0x13
479#define R511_CAM_PXDIV 0x14
480#define R511_CAM_LNDIV 0x15
481#define R511_CAM_UV_EN 0x16
482#define R511_CAM_LINE_MODE 0x17
483#define R511_CAM_OPTS 0x18
484
485#define R511_SNAP_FRAME 0x19
87bae740
JFM		 486#define R511_SNAP_PXCNT 0x1a
487#define R511_SNAP_LNCNT 0x1b
488#define R511_SNAP_PXDIV 0x1c
489#define R511_SNAP_LNDIV 0x1d
490#define R511_SNAP_UV_EN 0x1e
87bae740 491#define R511_SNAP_OPTS 0x1f
1876bb92
HG		 492
493#define R511_DRAM_FLOW_CTL 0x20
494#define R511_FIFO_OPTS 0x31
495#define R511_I2C_CTL 0x40
49809d6a 496#define R511_SYS_LED_CTL 0x55 /* OV511+ only */
1876bb92
HG		 497#define R511_COMP_EN 0x78
498#define R511_COMP_LUT_EN 0x79
49809d6a
HG		 499
500/* OV518 Camera interface register numbers */
501#define R518_GPIO_OUT 0x56 /* OV518(+) only */
502#define R518_GPIO_CTL 0x57 /* OV518(+) only */
503
6a7eba24 504/* OV519 Camera interface register numbers */
ac40b1fa
JFM		 505#define OV519_R10_H_SIZE 0x10
506#define OV519_R11_V_SIZE 0x11
507#define OV519_R12_X_OFFSETL 0x12
508#define OV519_R13_X_OFFSETH 0x13
509#define OV519_R14_Y_OFFSETL 0x14
510#define OV519_R15_Y_OFFSETH 0x15
511#define OV519_R16_DIVIDER 0x16
512#define OV519_R20_DFR 0x20
513#define OV519_R25_FORMAT 0x25
6a7eba24
JFM		 514
515/* OV519 System Controller register numbers */
21867803
JFM		 516#define OV519_R51_RESET1 0x51
517#define OV519_R54_EN_CLK1 0x54
b4e96ea3 518#define OV519_R57_SNAPSHOT 0x57
6a7eba24
JFM		 519
520#define OV519_GPIO_DATA_OUT0 0x71
521#define OV519_GPIO_IO_CTRL0 0x72
522
87bae740 523/*#define OV511_ENDPOINT_ADDRESS 1 * Isoc endpoint number */
6a7eba24 524
b46aaa02
HG		 525/*
526 * The FX2 chip does not give us a zero length read at end of frame.
527 * It does, however, give a short read at the end of a frame, if
3ad2f3fb 528 * necessary, rather than run two frames together.
b46aaa02
HG		 529 *
530 * By choosing the right bulk transfer size, we are guaranteed to always
531 * get a short read for the last read of each frame. Frame sizes are
532 * always a composite number (width * height, or a multiple) so if we
533 * choose a prime number, we are guaranteed that the last read of a
534 * frame will be short.
535 *
536 * But it isn't that easy: the 2.6 kernel requires a multiple of 4KB,
537 * otherwise EOVERFLOW "babbling" errors occur. I have not been able
538 * to figure out why. [PMiller]
539 *
540 * The constant (13 * 4096) is the largest "prime enough" number less than 64KB.
541 *
542 * It isn't enough to know the number of bytes per frame, in case we
543 * have data dropouts or buffer overruns (even though the FX2 double
544 * buffers, there are some pretty strict real time constraints for
545 * isochronous transfer for larger frame sizes).
546 */
547#define OVFX2_BULK_SIZE (13 * 4096)
548
6a7eba24
JFM		 549/* I2C registers */
550#define R51x_I2C_W_SID 0x41
551#define R51x_I2C_SADDR_3 0x42
552#define R51x_I2C_SADDR_2 0x43
553#define R51x_I2C_R_SID 0x44
554#define R51x_I2C_DATA 0x45
555#define R518_I2C_CTL 0x47 /* OV518(+) only */
b46aaa02 556#define OVFX2_I2C_ADDR 0x00
6a7eba24
JFM		 557
558/* I2C ADDRESSES */
559#define OV7xx0_SID 0x42
229bb7dc 560#define OV_HIRES_SID 0x60 /* OV9xxx / OV2xxx / OV3xxx */
6a7eba24
JFM		 561#define OV8xx0_SID 0xa0
562#define OV6xx0_SID 0xc0
563
564/* OV7610 registers */
565#define OV7610_REG_GAIN 0x00 /* gain setting (5:0) */
49809d6a
HG		 566#define OV7610_REG_BLUE 0x01 /* blue channel balance */
567#define OV7610_REG_RED 0x02 /* red channel balance */
6a7eba24
JFM		 568#define OV7610_REG_SAT 0x03 /* saturation */
569#define OV8610_REG_HUE 0x04 /* 04 reserved */
570#define OV7610_REG_CNT 0x05 /* Y contrast */
571#define OV7610_REG_BRT 0x06 /* Y brightness */
572#define OV7610_REG_COM_C 0x14 /* misc common regs */
573#define OV7610_REG_ID_HIGH 0x1c /* manufacturer ID MSB */
574#define OV7610_REG_ID_LOW 0x1d /* manufacturer ID LSB */
575#define OV7610_REG_COM_I 0x29 /* misc settings */
576
42e142f6 577/* OV7660 and OV7670 registers */
21867803
JFM		 578#define OV7670_R00_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
579#define OV7670_R01_BLUE 0x01 /* blue gain */
580#define OV7670_R02_RED 0x02 /* red gain */
581#define OV7670_R03_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
582#define OV7670_R04_COM1 0x04 /* Control 1 */
583/*#define OV7670_R07_AECHH 0x07 * AEC MS 5 bits */
584#define OV7670_R0C_COM3 0x0c /* Control 3 */
585#define OV7670_R0D_COM4 0x0d /* Control 4 */
586#define OV7670_R0E_COM5 0x0e /* All "reserved" */
587#define OV7670_R0F_COM6 0x0f /* Control 6 */
588#define OV7670_R10_AECH 0x10 /* More bits of AEC value */
589#define OV7670_R11_CLKRC 0x11 /* Clock control */
590#define OV7670_R12_COM7 0x12 /* Control 7 */
87bae740
JFM		 591#define OV7670_COM7_FMT_VGA 0x00
592/*#define OV7670_COM7_YUV 0x00 * YUV */
593#define OV7670_COM7_FMT_QVGA 0x10 /* QVGA format */
594#define OV7670_COM7_FMT_MASK 0x38
595#define OV7670_COM7_RESET 0x80 /* Register reset */
21867803 596#define OV7670_R13_COM8 0x13 /* Control 8 */
87bae740
JFM		 597#define OV7670_COM8_AEC 0x01 /* Auto exposure enable */
598#define OV7670_COM8_AWB 0x02 /* White balance enable */
599#define OV7670_COM8_AGC 0x04 /* Auto gain enable */
600#define OV7670_COM8_BFILT 0x20 /* Band filter enable */
601#define OV7670_COM8_AECSTEP 0x40 /* Unlimited AEC step size */
602#define OV7670_COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
21867803
JFM		 603#define OV7670_R14_COM9 0x14 /* Control 9 - gain ceiling */
604#define OV7670_R15_COM10 0x15 /* Control 10 */
605#define OV7670_R17_HSTART 0x17 /* Horiz start high bits */
606#define OV7670_R18_HSTOP 0x18 /* Horiz stop high bits */
607#define OV7670_R19_VSTART 0x19 /* Vert start high bits */
608#define OV7670_R1A_VSTOP 0x1a /* Vert stop high bits */
609#define OV7670_R1E_MVFP 0x1e /* Mirror / vflip */
87bae740
JFM		 610#define OV7670_MVFP_VFLIP 0x10 /* vertical flip */
611#define OV7670_MVFP_MIRROR 0x20 /* Mirror image */
21867803
JFM		 612#define OV7670_R24_AEW 0x24 /* AGC upper limit */
613#define OV7670_R25_AEB 0x25 /* AGC lower limit */
614#define OV7670_R26_VPT 0x26 /* AGC/AEC fast mode op region */
615#define OV7670_R32_HREF 0x32 /* HREF pieces */
616#define OV7670_R3A_TSLB 0x3a /* lots of stuff */
617#define OV7670_R3B_COM11 0x3b /* Control 11 */
87bae740
JFM		 618#define OV7670_COM11_EXP 0x02
619#define OV7670_COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
21867803
JFM		 620#define OV7670_R3C_COM12 0x3c /* Control 12 */
621#define OV7670_R3D_COM13 0x3d /* Control 13 */
87bae740
JFM		 622#define OV7670_COM13_GAMMA 0x80 /* Gamma enable */
623#define OV7670_COM13_UVSAT 0x40 /* UV saturation auto adjustment */
21867803
JFM		 624#define OV7670_R3E_COM14 0x3e /* Control 14 */
625#define OV7670_R3F_EDGE 0x3f /* Edge enhancement factor */
626#define OV7670_R40_COM15 0x40 /* Control 15 */
87bae740 627/*#define OV7670_COM15_R00FF 0xc0 * 00 to FF */
21867803 628#define OV7670_R41_COM16 0x41 /* Control 16 */
87bae740 629#define OV7670_COM16_AWBGAIN 0x08 /* AWB gain enable */
42e142f6 630/* end of ov7660 common registers */
21867803
JFM		 631#define OV7670_R55_BRIGHT 0x55 /* Brightness */
632#define OV7670_R56_CONTRAS 0x56 /* Contrast control */
633#define OV7670_R69_GFIX 0x69 /* Fix gain control */
634/*#define OV7670_R8C_RGB444 0x8c * RGB 444 control */
635#define OV7670_R9F_HAECC1 0x9f /* Hist AEC/AGC control 1 */
636#define OV7670_RA0_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
637#define OV7670_RA5_BD50MAX 0xa5 /* 50hz banding step limit */
638#define OV7670_RA6_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
639#define OV7670_RA7_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
640#define OV7670_RA8_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
641#define OV7670_RA9_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
642#define OV7670_RAA_HAECC7 0xaa /* Hist AEC/AGC control 7 */
643#define OV7670_RAB_BD60MAX 0xab /* 60hz banding step limit */
6a7eba24 644
4202f71c 645struct ov_regvals {
9d1593a8
JFM		 646 u8 reg;
647 u8 val;
4202f71c
JFM		 648};
649struct ov_i2c_regvals {
9d1593a8
JFM		 650 u8 reg;
651 u8 val;
4202f71c
JFM		 652};
653
635118d5 654/* Settings for OV2610 camera chip */
780e3121 655static const struct ov_i2c_regvals norm_2610[] = {
b46aaa02 656 { 0x12, 0x80 }, /* reset */
635118d5
HG		 657};
658
780e3121 659static const struct ov_i2c_regvals norm_3620b[] = {
635118d5
HG		 660 /*
661 * From the datasheet: "Note that after writing to register COMH
662 * (0x12) to change the sensor mode, registers related to the
663 * sensor’s cropping window will be reset back to their default
664 * values."
665 *
666 * "wait 4096 external clock ... to make sure the sensor is
667 * stable and ready to access registers" i.e. 160us at 24MHz
668 */
635118d5
HG		 669 { 0x12, 0x80 }, /* COMH reset */
670 { 0x12, 0x00 }, /* QXGA, master */
671
672 /*
673 * 11 CLKRC "Clock Rate Control"
674 * [7] internal frequency doublers: on
675 * [6] video port mode: master
676 * [5:0] clock divider: 1
677 */
678 { 0x11, 0x80 },
679
680 /*
681 * 13 COMI "Common Control I"
682 * = 192 (0xC0) 11000000
683 * COMI[7] "AEC speed selection"
684 * = 1 (0x01) 1....... "Faster AEC correction"
685 * COMI[6] "AEC speed step selection"
686 * = 1 (0x01) .1...... "Big steps, fast"
687 * COMI[5] "Banding filter on off"
688 * = 0 (0x00) ..0..... "Off"
689 * COMI[4] "Banding filter option"
690 * = 0 (0x00) ...0.... "Main clock is 48 MHz and
691 * the PLL is ON"
692 * COMI[3] "Reserved"
693 * = 0 (0x00) ....0...
694 * COMI[2] "AGC auto manual control selection"
695 * = 0 (0x00) .....0.. "Manual"
696 * COMI[1] "AWB auto manual control selection"
697 * = 0 (0x00) ......0. "Manual"
698 * COMI[0] "Exposure control"
699 * = 0 (0x00) .......0 "Manual"
700 */
87bae740 701 { 0x13, 0xc0 },
635118d5
HG		 702
703 /*
704 * 09 COMC "Common Control C"
705 * = 8 (0x08) 00001000
706 * COMC[7:5] "Reserved"
707 * = 0 (0x00) 000.....
708 * COMC[4] "Sleep Mode Enable"
709 * = 0 (0x00) ...0.... "Normal mode"
710 * COMC[3:2] "Sensor sampling reset timing selection"
711 * = 2 (0x02) ....10.. "Longer reset time"
712 * COMC[1:0] "Output drive current select"
713 * = 0 (0x00) ......00 "Weakest"
714 */
715 { 0x09, 0x08 },
716
717 /*
718 * 0C COMD "Common Control D"
719 * = 8 (0x08) 00001000
720 * COMD[7] "Reserved"
721 * = 0 (0x00) 0.......
722 * COMD[6] "Swap MSB and LSB at the output port"
723 * = 0 (0x00) .0...... "False"
724 * COMD[5:3] "Reserved"
725 * = 1 (0x01) ..001...
726 * COMD[2] "Output Average On Off"
727 * = 0 (0x00) .....0.. "Output Normal"
728 * COMD[1] "Sensor precharge voltage selection"
729 * = 0 (0x00) ......0. "Selects internal
730 * reference precharge
731 * voltage"
732 * COMD[0] "Snapshot option"
733 * = 0 (0x00) .......0 "Enable live video output
734 * after snapshot sequence"
735 */
736 { 0x0c, 0x08 },
737
738 /*
739 * 0D COME "Common Control E"
740 * = 161 (0xA1) 10100001
741 * COME[7] "Output average option"
742 * = 1 (0x01) 1....... "Output average of 4 pixels"
743 * COME[6] "Anti-blooming control"
744 * = 0 (0x00) .0...... "Off"
745 * COME[5:3] "Reserved"
746 * = 4 (0x04) ..100...
747 * COME[2] "Clock output power down pin status"
748 * = 0 (0x00) .....0.. "Tri-state data output pin
749 * on power down"
750 * COME[1] "Data output pin status selection at power down"
751 * = 0 (0x00) ......0. "Tri-state VSYNC, PCLK,
752 * HREF, and CHSYNC pins on
753 * power down"
754 * COME[0] "Auto zero circuit select"
755 * = 1 (0x01) .......1 "On"
756 */
87bae740 757 { 0x0d, 0xa1 },
635118d5
HG		 758
759 /*
760 * 0E COMF "Common Control F"
761 * = 112 (0x70) 01110000
762 * COMF[7] "System clock selection"
763 * = 0 (0x00) 0....... "Use 24 MHz system clock"
764 * COMF[6:4] "Reserved"
765 * = 7 (0x07) .111....
766 * COMF[3] "Manual auto negative offset canceling selection"
767 * = 0 (0x00) ....0... "Auto detect negative
768 * offset and cancel it"
769 * COMF[2:0] "Reserved"
770 * = 0 (0x00) .....000
771 */
772 { 0x0e, 0x70 },
773
774 /*
775 * 0F COMG "Common Control G"
776 * = 66 (0x42) 01000010
777 * COMG[7] "Optical black output selection"
778 * = 0 (0x00) 0....... "Disable"
779 * COMG[6] "Black level calibrate selection"
780 * = 1 (0x01) .1...... "Use optical black pixels
781 * to calibrate"
782 * COMG[5:4] "Reserved"
783 * = 0 (0x00) ..00....
784 * COMG[3] "Channel offset adjustment"
785 * = 0 (0x00) ....0... "Disable offset adjustment"
786 * COMG[2] "ADC black level calibration option"
787 * = 0 (0x00) .....0.. "Use B/G line and G/R
788 * line to calibrate each
789 * channel's black level"
790 * COMG[1] "Reserved"
791 * = 1 (0x01) ......1.
792 * COMG[0] "ADC black level calibration enable"
793 * = 0 (0x00) .......0 "Disable"
794 */
795 { 0x0f, 0x42 },
796
797 /*
798 * 14 COMJ "Common Control J"
799 * = 198 (0xC6) 11000110
800 * COMJ[7:6] "AGC gain ceiling"
801 * = 3 (0x03) 11...... "8x"
802 * COMJ[5:4] "Reserved"
803 * = 0 (0x00) ..00....
804 * COMJ[3] "Auto banding filter"
805 * = 0 (0x00) ....0... "Banding filter is always
806 * on off depending on
807 * COMI[5] setting"
808 * COMJ[2] "VSYNC drop option"
809 * = 1 (0x01) .....1.. "SYNC is dropped if frame
810 * data is dropped"
811 * COMJ[1] "Frame data drop"
812 * = 1 (0x01) ......1. "Drop frame data if
813 * exposure is not within
814 * tolerance. In AEC mode,
815 * data is normally dropped
816 * when data is out of
817 * range."
818 * COMJ[0] "Reserved"
819 * = 0 (0x00) .......0
820 */
87bae740 821 { 0x14, 0xc6 },
635118d5
HG		 822
823 /*
824 * 15 COMK "Common Control K"
825 * = 2 (0x02) 00000010
826 * COMK[7] "CHSYNC pin output swap"
827 * = 0 (0x00) 0....... "CHSYNC"
828 * COMK[6] "HREF pin output swap"
829 * = 0 (0x00) .0...... "HREF"
830 * COMK[5] "PCLK output selection"
831 * = 0 (0x00) ..0..... "PCLK always output"
832 * COMK[4] "PCLK edge selection"
833 * = 0 (0x00) ...0.... "Data valid on falling edge"
834 * COMK[3] "HREF output polarity"
835 * = 0 (0x00) ....0... "positive"
836 * COMK[2] "Reserved"
837 * = 0 (0x00) .....0..
838 * COMK[1] "VSYNC polarity"
839 * = 1 (0x01) ......1. "negative"
840 * COMK[0] "HSYNC polarity"
841 * = 0 (0x00) .......0 "positive"
842 */
843 { 0x15, 0x02 },
844
845 /*
846 * 33 CHLF "Current Control"
847 * = 9 (0x09) 00001001
848 * CHLF[7:6] "Sensor current control"
849 * = 0 (0x00) 00......
850 * CHLF[5] "Sensor current range control"
851 * = 0 (0x00) ..0..... "normal range"
852 * CHLF[4] "Sensor current"
853 * = 0 (0x00) ...0.... "normal current"
854 * CHLF[3] "Sensor buffer current control"
855 * = 1 (0x01) ....1... "half current"
856 * CHLF[2] "Column buffer current control"
857 * = 0 (0x00) .....0.. "normal current"
858 * CHLF[1] "Analog DSP current control"
859 * = 0 (0x00) ......0. "normal current"
860 * CHLF[1] "ADC current control"
861 * = 0 (0x00) ......0. "normal current"
862 */
863 { 0x33, 0x09 },
864
865 /*
866 * 34 VBLM "Blooming Control"
867 * = 80 (0x50) 01010000
868 * VBLM[7] "Hard soft reset switch"
869 * = 0 (0x00) 0....... "Hard reset"
870 * VBLM[6:4] "Blooming voltage selection"
871 * = 5 (0x05) .101....
872 * VBLM[3:0] "Sensor current control"
873 * = 0 (0x00) ....0000
874 */
875 { 0x34, 0x50 },
876
877 /*
878 * 36 VCHG "Sensor Precharge Voltage Control"
879 * = 0 (0x00) 00000000
880 * VCHG[7] "Reserved"
881 * = 0 (0x00) 0.......
882 * VCHG[6:4] "Sensor precharge voltage control"
883 * = 0 (0x00) .000....
884 * VCHG[3:0] "Sensor array common reference"
885 * = 0 (0x00) ....0000
886 */
887 { 0x36, 0x00 },
888
889 /*
890 * 37 ADC "ADC Reference Control"
891 * = 4 (0x04) 00000100
892 * ADC[7:4] "Reserved"
893 * = 0 (0x00) 0000....
894 * ADC[3] "ADC input signal range"
895 * = 0 (0x00) ....0... "Input signal 1.0x"
896 * ADC[2:0] "ADC range control"
897 * = 4 (0x04) .....100
898 */
899 { 0x37, 0x04 },
900
901 /*
902 * 38 ACOM "Analog Common Ground"
903 * = 82 (0x52) 01010010
904 * ACOM[7] "Analog gain control"
905 * = 0 (0x00) 0....... "Gain 1x"
906 * ACOM[6] "Analog black level calibration"
907 * = 1 (0x01) .1...... "On"
908 * ACOM[5:0] "Reserved"
909 * = 18 (0x12) ..010010
910 */
911 { 0x38, 0x52 },
912
913 /*
914 * 3A FREFA "Internal Reference Adjustment"
915 * = 0 (0x00) 00000000
916 * FREFA[7:0] "Range"
917 * = 0 (0x00) 00000000
918 */
919 { 0x3a, 0x00 },
920
921 /*
922 * 3C FVOPT "Internal Reference Adjustment"
923 * = 31 (0x1F) 00011111
924 * FVOPT[7:0] "Range"
925 * = 31 (0x1F) 00011111
926 */
87bae740 927 { 0x3c, 0x1f },
635118d5
HG		 928
929 /*
930 * 44 Undocumented = 0 (0x00) 00000000
931 * 44[7:0] "It's a secret"
932 * = 0 (0x00) 00000000
933 */
934 { 0x44, 0x00 },
935
936 /*
937 * 40 Undocumented = 0 (0x00) 00000000
938 * 40[7:0] "It's a secret"
939 * = 0 (0x00) 00000000
940 */
941 { 0x40, 0x00 },
942
943 /*
944 * 41 Undocumented = 0 (0x00) 00000000
945 * 41[7:0] "It's a secret"
946 * = 0 (0x00) 00000000
947 */
948 { 0x41, 0x00 },
949
950 /*
951 * 42 Undocumented = 0 (0x00) 00000000
952 * 42[7:0] "It's a secret"
953 * = 0 (0x00) 00000000
954 */
955 { 0x42, 0x00 },
956
957 /*
958 * 43 Undocumented = 0 (0x00) 00000000
959 * 43[7:0] "It's a secret"
960 * = 0 (0x00) 00000000
961 */
962 { 0x43, 0x00 },
963
964 /*
965 * 45 Undocumented = 128 (0x80) 10000000
966 * 45[7:0] "It's a secret"
967 * = 128 (0x80) 10000000
968 */
969 { 0x45, 0x80 },
970
971 /*
972 * 48 Undocumented = 192 (0xC0) 11000000
973 * 48[7:0] "It's a secret"
974 * = 192 (0xC0) 11000000
975 */
87bae740 976 { 0x48, 0xc0 },
635118d5
HG		 977
978 /*
979 * 49 Undocumented = 25 (0x19) 00011001
980 * 49[7:0] "It's a secret"
981 * = 25 (0x19) 00011001
982 */
983 { 0x49, 0x19 },
984
985 /*
986 * 4B Undocumented = 128 (0x80) 10000000
987 * 4B[7:0] "It's a secret"
988 * = 128 (0x80) 10000000
989 */
87bae740 990 { 0x4b, 0x80 },
635118d5
HG		 991
992 /*
993 * 4D Undocumented = 196 (0xC4) 11000100
994 * 4D[7:0] "It's a secret"
995 * = 196 (0xC4) 11000100
996 */
87bae740 997 { 0x4d, 0xc4 },
635118d5
HG		 998
999 /*
1000 * 35 VREF "Reference Voltage Control"
87bae740 1001 * = 76 (0x4c) 01001100
635118d5
HG		 1002 * VREF[7:5] "Column high reference control"
1003 * = 2 (0x02) 010..... "higher voltage"
1004 * VREF[4:2] "Column low reference control"
1005 * = 3 (0x03) ...011.. "Highest voltage"
1006 * VREF[1:0] "Reserved"
1007 * = 0 (0x00) ......00
1008 */
87bae740 1009 { 0x35, 0x4c },
635118d5
HG		 1010
1011 /*
1012 * 3D Undocumented = 0 (0x00) 00000000
1013 * 3D[7:0] "It's a secret"
1014 * = 0 (0x00) 00000000
1015 */
87bae740 1016 { 0x3d, 0x00 },
635118d5
HG		 1017
1018 /*
1019 * 3E Undocumented = 0 (0x00) 00000000
1020 * 3E[7:0] "It's a secret"
1021 * = 0 (0x00) 00000000
1022 */
87bae740 1023 { 0x3e, 0x00 },
635118d5
HG		 1024
1025 /*
1026 * 3B FREFB "Internal Reference Adjustment"
1027 * = 24 (0x18) 00011000
1028 * FREFB[7:0] "Range"
1029 * = 24 (0x18) 00011000
1030 */
1031 { 0x3b, 0x18 },
1032
1033 /*
1034 * 33 CHLF "Current Control"
1035 * = 25 (0x19) 00011001
1036 * CHLF[7:6] "Sensor current control"
1037 * = 0 (0x00) 00......
1038 * CHLF[5] "Sensor current range control"
1039 * = 0 (0x00) ..0..... "normal range"
1040 * CHLF[4] "Sensor current"
1041 * = 1 (0x01) ...1.... "double current"
1042 * CHLF[3] "Sensor buffer current control"
1043 * = 1 (0x01) ....1... "half current"
1044 * CHLF[2] "Column buffer current control"
1045 * = 0 (0x00) .....0.. "normal current"
1046 * CHLF[1] "Analog DSP current control"
1047 * = 0 (0x00) ......0. "normal current"
1048 * CHLF[1] "ADC current control"
1049 * = 0 (0x00) ......0. "normal current"
1050 */
1051 { 0x33, 0x19 },
1052
1053 /*
1054 * 34 VBLM "Blooming Control"
1055 * = 90 (0x5A) 01011010
1056 * VBLM[7] "Hard soft reset switch"
1057 * = 0 (0x00) 0....... "Hard reset"
1058 * VBLM[6:4] "Blooming voltage selection"
1059 * = 5 (0x05) .101....
1060 * VBLM[3:0] "Sensor current control"
1061 * = 10 (0x0A) ....1010
1062 */
87bae740 1063 { 0x34, 0x5a },
635118d5
HG		 1064
1065 /*
1066 * 3B FREFB "Internal Reference Adjustment"
1067 * = 0 (0x00) 00000000
1068 * FREFB[7:0] "Range"
1069 * = 0 (0x00) 00000000
1070 */
1071 { 0x3b, 0x00 },
1072
1073 /*
1074 * 33 CHLF "Current Control"
1075 * = 9 (0x09) 00001001
1076 * CHLF[7:6] "Sensor current control"
1077 * = 0 (0x00) 00......
1078 * CHLF[5] "Sensor current range control"
1079 * = 0 (0x00) ..0..... "normal range"
1080 * CHLF[4] "Sensor current"
1081 * = 0 (0x00) ...0.... "normal current"
1082 * CHLF[3] "Sensor buffer current control"
1083 * = 1 (0x01) ....1... "half current"
1084 * CHLF[2] "Column buffer current control"
1085 * = 0 (0x00) .....0.. "normal current"
1086 * CHLF[1] "Analog DSP current control"
1087 * = 0 (0x00) ......0. "normal current"
1088 * CHLF[1] "ADC current control"
1089 * = 0 (0x00) ......0. "normal current"
1090 */
1091 { 0x33, 0x09 },
1092
1093 /*
1094 * 34 VBLM "Blooming Control"
1095 * = 80 (0x50) 01010000
1096 * VBLM[7] "Hard soft reset switch"
1097 * = 0 (0x00) 0....... "Hard reset"
1098 * VBLM[6:4] "Blooming voltage selection"
1099 * = 5 (0x05) .101....
1100 * VBLM[3:0] "Sensor current control"
1101 * = 0 (0x00) ....0000
1102 */
1103 { 0x34, 0x50 },
1104
1105 /*
1106 * 12 COMH "Common Control H"
1107 * = 64 (0x40) 01000000
1108 * COMH[7] "SRST"
1109 * = 0 (0x00) 0....... "No-op"
1110 * COMH[6:4] "Resolution selection"
1111 * = 4 (0x04) .100.... "XGA"
1112 * COMH[3] "Master slave selection"
1113 * = 0 (0x00) ....0... "Master mode"
1114 * COMH[2] "Internal B/R channel option"
1115 * = 0 (0x00) .....0.. "B/R use same channel"
1116 * COMH[1] "Color bar test pattern"
1117 * = 0 (0x00) ......0. "Off"
1118 * COMH[0] "Reserved"
1119 * = 0 (0x00) .......0
1120 */
1121 { 0x12, 0x40 },
1122
1123 /*
1124 * 17 HREFST "Horizontal window start"
1125 * = 31 (0x1F) 00011111
1126 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1127 * = 31 (0x1F) 00011111
1128 */
87bae740 1129 { 0x17, 0x1f },
635118d5
HG		 1130
1131 /*
1132 * 18 HREFEND "Horizontal window end"
1133 * = 95 (0x5F) 01011111
1134 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1135 * = 95 (0x5F) 01011111
1136 */
87bae740 1137 { 0x18, 0x5f },
635118d5
HG		 1138
1139 /*
1140 * 19 VSTRT "Vertical window start"
1141 * = 0 (0x00) 00000000
1142 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1143 * = 0 (0x00) 00000000
1144 */
1145 { 0x19, 0x00 },
1146
1147 /*
1148 * 1A VEND "Vertical window end"
1149 * = 96 (0x60) 01100000
1150 * VEND[7:0] "Vertical Window End, 8 MSBs"
1151 * = 96 (0x60) 01100000
1152 */
1153 { 0x1a, 0x60 },
1154
1155 /*
1156 * 32 COMM "Common Control M"
1157 * = 18 (0x12) 00010010
1158 * COMM[7:6] "Pixel clock divide option"
1159 * = 0 (0x00) 00...... "/1"
1160 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1161 * = 2 (0x02) ..010...
1162 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1163 * = 2 (0x02) .....010
1164 */
1165 { 0x32, 0x12 },
1166
1167 /*
1168 * 03 COMA "Common Control A"
1169 * = 74 (0x4A) 01001010
1170 * COMA[7:4] "AWB Update Threshold"
1171 * = 4 (0x04) 0100....
1172 * COMA[3:2] "Vertical window end line control 2 LSBs"
1173 * = 2 (0x02) ....10..
1174 * COMA[1:0] "Vertical window start line control 2 LSBs"
1175 * = 2 (0x02) ......10
1176 */
87bae740 1177 { 0x03, 0x4a },
635118d5
HG		 1178
1179 /*
1180 * 11 CLKRC "Clock Rate Control"
1181 * = 128 (0x80) 10000000
1182 * CLKRC[7] "Internal frequency doublers on off seclection"
1183 * = 1 (0x01) 1....... "On"
1184 * CLKRC[6] "Digital video master slave selection"
1185 * = 0 (0x00) .0...... "Master mode, sensor
1186 * provides PCLK"
1187 * CLKRC[5:0] "Clock divider { CLK = PCLK/(1+CLKRC[5:0]) }"
1188 * = 0 (0x00) ..000000
1189 */
1190 { 0x11, 0x80 },
1191
1192 /*
1193 * 12 COMH "Common Control H"
1194 * = 0 (0x00) 00000000
1195 * COMH[7] "SRST"
1196 * = 0 (0x00) 0....... "No-op"
1197 * COMH[6:4] "Resolution selection"
1198 * = 0 (0x00) .000.... "QXGA"
1199 * COMH[3] "Master slave selection"
1200 * = 0 (0x00) ....0... "Master mode"
1201 * COMH[2] "Internal B/R channel option"
1202 * = 0 (0x00) .....0.. "B/R use same channel"
1203 * COMH[1] "Color bar test pattern"
1204 * = 0 (0x00) ......0. "Off"
1205 * COMH[0] "Reserved"
1206 * = 0 (0x00) .......0
1207 */
1208 { 0x12, 0x00 },
1209
1210 /*
1211 * 12 COMH "Common Control H"
1212 * = 64 (0x40) 01000000
1213 * COMH[7] "SRST"
1214 * = 0 (0x00) 0....... "No-op"
1215 * COMH[6:4] "Resolution selection"
1216 * = 4 (0x04) .100.... "XGA"
1217 * COMH[3] "Master slave selection"
1218 * = 0 (0x00) ....0... "Master mode"
1219 * COMH[2] "Internal B/R channel option"
1220 * = 0 (0x00) .....0.. "B/R use same channel"
1221 * COMH[1] "Color bar test pattern"
1222 * = 0 (0x00) ......0. "Off"
1223 * COMH[0] "Reserved"
1224 * = 0 (0x00) .......0
1225 */
1226 { 0x12, 0x40 },
1227
1228 /*
1229 * 17 HREFST "Horizontal window start"
1230 * = 31 (0x1F) 00011111
1231 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1232 * = 31 (0x1F) 00011111
1233 */
87bae740 1234 { 0x17, 0x1f },
635118d5
HG		 1235
1236 /*
1237 * 18 HREFEND "Horizontal window end"
1238 * = 95 (0x5F) 01011111
1239 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1240 * = 95 (0x5F) 01011111
1241 */
87bae740 1242 { 0x18, 0x5f },
635118d5
HG		 1243
1244 /*
1245 * 19 VSTRT "Vertical window start"
1246 * = 0 (0x00) 00000000
1247 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1248 * = 0 (0x00) 00000000
1249 */
1250 { 0x19, 0x00 },
1251
1252 /*
1253 * 1A VEND "Vertical window end"
1254 * = 96 (0x60) 01100000
1255 * VEND[7:0] "Vertical Window End, 8 MSBs"
1256 * = 96 (0x60) 01100000
1257 */
1258 { 0x1a, 0x60 },
1259
1260 /*
1261 * 32 COMM "Common Control M"
1262 * = 18 (0x12) 00010010
1263 * COMM[7:6] "Pixel clock divide option"
1264 * = 0 (0x00) 00...... "/1"
1265 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1266 * = 2 (0x02) ..010...
1267 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1268 * = 2 (0x02) .....010
1269 */
1270 { 0x32, 0x12 },
1271
1272 /*
1273 * 03 COMA "Common Control A"
1274 * = 74 (0x4A) 01001010
1275 * COMA[7:4] "AWB Update Threshold"
1276 * = 4 (0x04) 0100....
1277 * COMA[3:2] "Vertical window end line control 2 LSBs"
1278 * = 2 (0x02) ....10..
1279 * COMA[1:0] "Vertical window start line control 2 LSBs"
1280 * = 2 (0x02) ......10
1281 */
87bae740 1282 { 0x03, 0x4a },
635118d5
HG		 1283
1284 /*
1285 * 02 RED "Red Gain Control"
1286 * = 175 (0xAF) 10101111
1287 * RED[7] "Action"
1288 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1289 * RED[6:0] "Value"
1290 * = 47 (0x2F) .0101111
1291 */
87bae740 1292 { 0x02, 0xaf },
635118d5
HG		 1293
1294 /*
1295 * 2D ADDVSL "VSYNC Pulse Width"
1296 * = 210 (0xD2) 11010010
1297 * ADDVSL[7:0] "VSYNC pulse width, LSB"
1298 * = 210 (0xD2) 11010010
1299 */
87bae740 1300 { 0x2d, 0xd2 },
635118d5
HG		 1301
1302 /*
1303 * 00 GAIN = 24 (0x18) 00011000
1304 * GAIN[7:6] "Reserved"
1305 * = 0 (0x00) 00......
1306 * GAIN[5] "Double"
1307 * = 0 (0x00) ..0..... "False"
1308 * GAIN[4] "Double"
1309 * = 1 (0x01) ...1.... "True"
1310 * GAIN[3:0] "Range"
1311 * = 8 (0x08) ....1000
1312 */
1313 { 0x00, 0x18 },
1314
1315 /*
1316 * 01 BLUE "Blue Gain Control"
1317 * = 240 (0xF0) 11110000
1318 * BLUE[7] "Action"
1319 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1320 * BLUE[6:0] "Value"
1321 * = 112 (0x70) .1110000
1322 */
87bae740 1323 { 0x01, 0xf0 },
635118d5
HG		 1324
1325 /*
1326 * 10 AEC "Automatic Exposure Control"
1327 * = 10 (0x0A) 00001010
1328 * AEC[7:0] "Automatic Exposure Control, 8 MSBs"
1329 * = 10 (0x0A) 00001010
1330 */
87bae740
JFM		 1331 { 0x10, 0x0a },
1332
1333 { 0xe1, 0x67 },
1334 { 0xe3, 0x03 },
1335 { 0xe4, 0x26 },
1336 { 0xe5, 0x3e },
1337 { 0xf8, 0x01 },
1338 { 0xff, 0x01 },
635118d5
HG		 1339};
1340
4202f71c
JFM		 1341static const struct ov_i2c_regvals norm_6x20[] = {
1342 { 0x12, 0x80 }, /* reset */
1343 { 0x11, 0x01 },
1344 { 0x03, 0x60 },
1345 { 0x05, 0x7f }, /* For when autoadjust is off */
1346 { 0x07, 0xa8 },
87bae740 1347 /* The ratio of 0x0c and 0x0d controls the white point */
4202f71c
JFM		 1348 { 0x0c, 0x24 },
1349 { 0x0d, 0x24 },
1350 { 0x0f, 0x15 }, /* COMS */
1351 { 0x10, 0x75 }, /* AEC Exposure time */
1352 { 0x12, 0x24 }, /* Enable AGC */
1353 { 0x14, 0x04 },
1354 /* 0x16: 0x06 helps frame stability with moving objects */
1355 { 0x16, 0x06 },
1356/* { 0x20, 0x30 }, * Aperture correction enable */
1357 { 0x26, 0xb2 }, /* BLC enable */
1358 /* 0x28: 0x05 Selects RGB format if RGB on */
1359 { 0x28, 0x05 },
1360 { 0x2a, 0x04 }, /* Disable framerate adjust */
1361/* { 0x2b, 0xac }, * Framerate; Set 2a[7] first */
ae49c404 1362 { 0x2d, 0x85 },
4202f71c
JFM		 1363 { 0x33, 0xa0 }, /* Color Processing Parameter */
1364 { 0x34, 0xd2 }, /* Max A/D range */
1365 { 0x38, 0x8b },
1366 { 0x39, 0x40 },
1367
1368 { 0x3c, 0x39 }, /* Enable AEC mode changing */
1369 { 0x3c, 0x3c }, /* Change AEC mode */
1370 { 0x3c, 0x24 }, /* Disable AEC mode changing */
1371
1372 { 0x3d, 0x80 },
1373 /* These next two registers (0x4a, 0x4b) are undocumented.
1374 * They control the color balance */
1375 { 0x4a, 0x80 },
1376 { 0x4b, 0x80 },
1377 { 0x4d, 0xd2 }, /* This reduces noise a bit */
1378 { 0x4e, 0xc1 },
1379 { 0x4f, 0x04 },
1380/* Do 50-53 have any effect? */
1381/* Toggle 0x12[2] off and on here? */
1382};
1383
1384static const struct ov_i2c_regvals norm_6x30[] = {
1385 { 0x12, 0x80 }, /* Reset */
1386 { 0x00, 0x1f }, /* Gain */
1387 { 0x01, 0x99 }, /* Blue gain */
1388 { 0x02, 0x7c }, /* Red gain */
1389 { 0x03, 0xc0 }, /* Saturation */
1390 { 0x05, 0x0a }, /* Contrast */
1391 { 0x06, 0x95 }, /* Brightness */
1392 { 0x07, 0x2d }, /* Sharpness */
1393 { 0x0c, 0x20 },
1394 { 0x0d, 0x20 },
02ab18b0 1395 { 0x0e, 0xa0 }, /* Was 0x20, bit7 enables a 2x gain which we need */
4202f71c
JFM		 1396 { 0x0f, 0x05 },
1397 { 0x10, 0x9a },
1398 { 0x11, 0x00 }, /* Pixel clock = fastest */
1399 { 0x12, 0x24 }, /* Enable AGC and AWB */
1400 { 0x13, 0x21 },
1401 { 0x14, 0x80 },
1402 { 0x15, 0x01 },
1403 { 0x16, 0x03 },
1404 { 0x17, 0x38 },
1405 { 0x18, 0xea },
1406 { 0x19, 0x04 },
1407 { 0x1a, 0x93 },
1408 { 0x1b, 0x00 },
1409 { 0x1e, 0xc4 },
1410 { 0x1f, 0x04 },
1411 { 0x20, 0x20 },
1412 { 0x21, 0x10 },
1413 { 0x22, 0x88 },
1414 { 0x23, 0xc0 }, /* Crystal circuit power level */
1415 { 0x25, 0x9a }, /* Increase AEC black ratio */
1416 { 0x26, 0xb2 }, /* BLC enable */
1417 { 0x27, 0xa2 },
1418 { 0x28, 0x00 },
1419 { 0x29, 0x00 },
1420 { 0x2a, 0x84 }, /* 60 Hz power */
1421 { 0x2b, 0xa8 }, /* 60 Hz power */
1422 { 0x2c, 0xa0 },
1423 { 0x2d, 0x95 }, /* Enable auto-brightness */
1424 { 0x2e, 0x88 },
1425 { 0x33, 0x26 },
1426 { 0x34, 0x03 },
1427 { 0x36, 0x8f },
1428 { 0x37, 0x80 },
1429 { 0x38, 0x83 },
1430 { 0x39, 0x80 },
1431 { 0x3a, 0x0f },
1432 { 0x3b, 0x3c },
1433 { 0x3c, 0x1a },
1434 { 0x3d, 0x80 },
1435 { 0x3e, 0x80 },
1436 { 0x3f, 0x0e },
1437 { 0x40, 0x00 }, /* White bal */
1438 { 0x41, 0x00 }, /* White bal */
1439 { 0x42, 0x80 },
1440 { 0x43, 0x3f }, /* White bal */
1441 { 0x44, 0x80 },
1442 { 0x45, 0x20 },
1443 { 0x46, 0x20 },
1444 { 0x47, 0x80 },
1445 { 0x48, 0x7f },
1446 { 0x49, 0x00 },
1447 { 0x4a, 0x00 },
1448 { 0x4b, 0x80 },
1449 { 0x4c, 0xd0 },
1450 { 0x4d, 0x10 }, /* U = 0.563u, V = 0.714v */
1451 { 0x4e, 0x40 },
1452 { 0x4f, 0x07 }, /* UV avg., col. killer: max */
1453 { 0x50, 0xff },
1454 { 0x54, 0x23 }, /* Max AGC gain: 18dB */
1455 { 0x55, 0xff },
1456 { 0x56, 0x12 },
1457 { 0x57, 0x81 },
1458 { 0x58, 0x75 },
1459 { 0x59, 0x01 }, /* AGC dark current comp.: +1 */
1460 { 0x5a, 0x2c },
1461 { 0x5b, 0x0f }, /* AWB chrominance levels */
1462 { 0x5c, 0x10 },
1463 { 0x3d, 0x80 },
1464 { 0x27, 0xa6 },
1465 { 0x12, 0x20 }, /* Toggle AWB */
1466 { 0x12, 0x24 },
1467};
1468
1469/* Lawrence Glaister <lg@jfm.bc.ca> reports:
1470 *
1471 * Register 0x0f in the 7610 has the following effects:
1472 *
1473 * 0x85 (AEC method 1): Best overall, good contrast range
1474 * 0x45 (AEC method 2): Very overexposed
1475 * 0xa5 (spec sheet default): Ok, but the black level is
1476 * shifted resulting in loss of contrast
1477 * 0x05 (old driver setting): very overexposed, too much
1478 * contrast
1479 */
1480static const struct ov_i2c_regvals norm_7610[] = {
1481 { 0x10, 0xff },
1482 { 0x16, 0x06 },
1483 { 0x28, 0x24 },
1484 { 0x2b, 0xac },
1485 { 0x12, 0x00 },
1486 { 0x38, 0x81 },
1487 { 0x28, 0x24 }, /* 0c */
1488 { 0x0f, 0x85 }, /* lg's setting */
1489 { 0x15, 0x01 },
1490 { 0x20, 0x1c },
1491 { 0x23, 0x2a },
1492 { 0x24, 0x10 },
1493 { 0x25, 0x8a },
1494 { 0x26, 0xa2 },
1495 { 0x27, 0xc2 },
1496 { 0x2a, 0x04 },
1497 { 0x2c, 0xfe },
1498 { 0x2d, 0x93 },
1499 { 0x30, 0x71 },
1500 { 0x31, 0x60 },
1501 { 0x32, 0x26 },
1502 { 0x33, 0x20 },
1503 { 0x34, 0x48 },
1504 { 0x12, 0x24 },
1505 { 0x11, 0x01 },
1506 { 0x0c, 0x24 },
1507 { 0x0d, 0x24 },
1508};
1509
1510static const struct ov_i2c_regvals norm_7620[] = {
a511ba94 1511 { 0x12, 0x80 }, /* reset */
4202f71c
JFM		 1512 { 0x00, 0x00 }, /* gain */
1513 { 0x01, 0x80 }, /* blue gain */
1514 { 0x02, 0x80 }, /* red gain */
21867803 1515 { 0x03, 0xc0 }, /* OV7670_R03_VREF */
4202f71c
JFM		 1516 { 0x06, 0x60 },
1517 { 0x07, 0x00 },
1518 { 0x0c, 0x24 },
1519 { 0x0c, 0x24 },
1520 { 0x0d, 0x24 },
1521 { 0x11, 0x01 },
1522 { 0x12, 0x24 },
1523 { 0x13, 0x01 },
1524 { 0x14, 0x84 },
1525 { 0x15, 0x01 },
1526 { 0x16, 0x03 },
1527 { 0x17, 0x2f },
1528 { 0x18, 0xcf },
1529 { 0x19, 0x06 },
1530 { 0x1a, 0xf5 },
1531 { 0x1b, 0x00 },
1532 { 0x20, 0x18 },
1533 { 0x21, 0x80 },
1534 { 0x22, 0x80 },
1535 { 0x23, 0x00 },
1536 { 0x26, 0xa2 },
1537 { 0x27, 0xea },
b282d873 1538 { 0x28, 0x22 }, /* Was 0x20, bit1 enables a 2x gain which we need */
4202f71c
JFM		 1539 { 0x29, 0x00 },
1540 { 0x2a, 0x10 },
1541 { 0x2b, 0x00 },
1542 { 0x2c, 0x88 },
1543 { 0x2d, 0x91 },
1544 { 0x2e, 0x80 },
1545 { 0x2f, 0x44 },
1546 { 0x60, 0x27 },
1547 { 0x61, 0x02 },
1548 { 0x62, 0x5f },
1549 { 0x63, 0xd5 },
1550 { 0x64, 0x57 },
1551 { 0x65, 0x83 },
1552 { 0x66, 0x55 },
1553 { 0x67, 0x92 },
1554 { 0x68, 0xcf },
1555 { 0x69, 0x76 },
1556 { 0x6a, 0x22 },
1557 { 0x6b, 0x00 },
1558 { 0x6c, 0x02 },
1559 { 0x6d, 0x44 },
1560 { 0x6e, 0x80 },
1561 { 0x6f, 0x1d },
1562 { 0x70, 0x8b },
1563 { 0x71, 0x00 },
1564 { 0x72, 0x14 },
1565 { 0x73, 0x54 },
1566 { 0x74, 0x00 },
1567 { 0x75, 0x8e },
1568 { 0x76, 0x00 },
1569 { 0x77, 0xff },
1570 { 0x78, 0x80 },
1571 { 0x79, 0x80 },
1572 { 0x7a, 0x80 },
1573 { 0x7b, 0xe2 },
1574 { 0x7c, 0x00 },
1575};
1576
1577/* 7640 and 7648. The defaults should be OK for most registers. */
1578static const struct ov_i2c_regvals norm_7640[] = {
1579 { 0x12, 0x80 },
1580 { 0x12, 0x14 },
1581};
1582
42e142f6
JFM		 1583static const struct ov_regvals init_519_ov7660[] = {
1584 { 0x5d, 0x03 }, /* Turn off suspend mode */
1585 { 0x53, 0x9b }, /* 0x9f enables the (unused) microcontroller */
1586 { 0x54, 0x0f }, /* bit2 (jpeg enable) */
1587 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
1588 { 0xa3, 0x18 },
1589 { 0xa4, 0x04 },
1590 { 0xa5, 0x28 },
1591 { 0x37, 0x00 }, /* SetUsbInit */
1592 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
1593 /* Enable both fields, YUV Input, disable defect comp (why?) */
1594 { 0x20, 0x0c }, /* 0x0d does U <-> V swap */
1595 { 0x21, 0x38 },
1596 { 0x22, 0x1d },
1597 { 0x17, 0x50 }, /* undocumented */
1598 { 0x37, 0x00 }, /* undocumented */
1599 { 0x40, 0xff }, /* I2C timeout counter */
1600 { 0x46, 0x00 }, /* I2C clock prescaler */
1601};
1602static const struct ov_i2c_regvals norm_7660[] = {
1603 {OV7670_R12_COM7, OV7670_COM7_RESET},
1604 {OV7670_R11_CLKRC, 0x81},
1605 {0x92, 0x00}, /* DM_LNL */
1606 {0x93, 0x00}, /* DM_LNH */
1607 {0x9d, 0x4c}, /* BD50ST */
1608 {0x9e, 0x3f}, /* BD60ST */
1609 {OV7670_R3B_COM11, 0x02},
1610 {OV7670_R13_COM8, 0xf5},
1611 {OV7670_R10_AECH, 0x00},
1612 {OV7670_R00_GAIN, 0x00},
1613 {OV7670_R01_BLUE, 0x7c},
1614 {OV7670_R02_RED, 0x9d},
1615 {OV7670_R12_COM7, 0x00},
1616 {OV7670_R04_COM1, 00},
1617 {OV7670_R18_HSTOP, 0x01},
1618 {OV7670_R17_HSTART, 0x13},
1619 {OV7670_R32_HREF, 0x92},
1620 {OV7670_R19_VSTART, 0x02},
1621 {OV7670_R1A_VSTOP, 0x7a},
1622 {OV7670_R03_VREF, 0x00},
1623 {OV7670_R0E_COM5, 0x04},
1624 {OV7670_R0F_COM6, 0x62},
1625 {OV7670_R15_COM10, 0x00},
1626 {0x16, 0x02}, /* RSVD */
1627 {0x1b, 0x00}, /* PSHFT */
1628 {OV7670_R1E_MVFP, 0x01},
1629 {0x29, 0x3c}, /* RSVD */
1630 {0x33, 0x00}, /* CHLF */
1631 {0x34, 0x07}, /* ARBLM */
1632 {0x35, 0x84}, /* RSVD */
1633 {0x36, 0x00}, /* RSVD */
1634 {0x37, 0x04}, /* ADC */
1635 {0x39, 0x43}, /* OFON */
1636 {OV7670_R3A_TSLB, 0x00},
1637 {OV7670_R3C_COM12, 0x6c},
1638 {OV7670_R3D_COM13, 0x98},
1639 {OV7670_R3F_EDGE, 0x23},
1640 {OV7670_R40_COM15, 0xc1},
1641 {OV7670_R41_COM16, 0x22},
1642 {0x6b, 0x0a}, /* DBLV */
1643 {0xa1, 0x08}, /* RSVD */
1644 {0x69, 0x80}, /* HV */
1645 {0x43, 0xf0}, /* RSVD.. */
1646 {0x44, 0x10},
1647 {0x45, 0x78},
1648 {0x46, 0xa8},
1649 {0x47, 0x60},
1650 {0x48, 0x80},
1651 {0x59, 0xba},
1652 {0x5a, 0x9a},
1653 {0x5b, 0x22},
1654 {0x5c, 0xb9},
1655 {0x5d, 0x9b},
1656 {0x5e, 0x10},
1657 {0x5f, 0xe0},
1658 {0x60, 0x85},
1659 {0x61, 0x60},
1660 {0x9f, 0x9d}, /* RSVD */
1661 {0xa0, 0xa0}, /* DSPC2 */
1662 {0x4f, 0x60}, /* matrix */
1663 {0x50, 0x64},
1664 {0x51, 0x04},
1665 {0x52, 0x18},
1666 {0x53, 0x3c},
1667 {0x54, 0x54},
1668 {0x55, 0x40},
1669 {0x56, 0x40},
1670 {0x57, 0x40},
1671 {0x58, 0x0d}, /* matrix sign */
1672 {0x8b, 0xcc}, /* RSVD */
1673 {0x8c, 0xcc},
1674 {0x8d, 0xcf},
1675 {0x6c, 0x40}, /* gamma curve */
1676 {0x6d, 0xe0},
1677 {0x6e, 0xa0},
1678 {0x6f, 0x80},
1679 {0x70, 0x70},
1680 {0x71, 0x80},
1681 {0x72, 0x60},
1682 {0x73, 0x60},
1683 {0x74, 0x50},
1684 {0x75, 0x40},
1685 {0x76, 0x38},
1686 {0x77, 0x3c},
1687 {0x78, 0x32},
1688 {0x79, 0x1a},
1689 {0x7a, 0x28},
1690 {0x7b, 0x24},
1691 {0x7c, 0x04}, /* gamma curve */
1692 {0x7d, 0x12},
1693 {0x7e, 0x26},
1694 {0x7f, 0x46},
1695 {0x80, 0x54},
1696 {0x81, 0x64},
1697 {0x82, 0x70},
1698 {0x83, 0x7c},
1699 {0x84, 0x86},
1700 {0x85, 0x8e},
1701 {0x86, 0x9c},
1702 {0x87, 0xab},
1703 {0x88, 0xc4},
1704 {0x89, 0xd1},
1705 {0x8a, 0xe5},
1706 {OV7670_R14_COM9, 0x1e},
1707 {OV7670_R24_AEW, 0x80},
1708 {OV7670_R25_AEB, 0x72},
1709 {OV7670_R26_VPT, 0xb3},
1710 {0x62, 0x80}, /* LCC1 */
1711 {0x63, 0x80}, /* LCC2 */
1712 {0x64, 0x06}, /* LCC3 */
1713 {0x65, 0x00}, /* LCC4 */
1714 {0x66, 0x01}, /* LCC5 */
1715 {0x94, 0x0e}, /* RSVD.. */
1716 {0x95, 0x14},
1717 {OV7670_R13_COM8, OV7670_COM8_FASTAEC
1718 | OV7670_COM8_AECSTEP
1719 | OV7670_COM8_BFILT
1720 | 0x10
1721 | OV7670_COM8_AGC
1722 | OV7670_COM8_AWB
1723 | OV7670_COM8_AEC},
1724 {0xa1, 0xc8}
1725};
1726
4202f71c
JFM		 1727/* 7670. Defaults taken from OmniVision provided data,
1728* as provided by Jonathan Corbet of OLPC */
1729static const struct ov_i2c_regvals norm_7670[] = {
21867803
JFM		 1730 { OV7670_R12_COM7, OV7670_COM7_RESET },
1731 { OV7670_R3A_TSLB, 0x04 }, /* OV */
1732 { OV7670_R12_COM7, OV7670_COM7_FMT_VGA }, /* VGA */
1733 { OV7670_R11_CLKRC, 0x01 },
4202f71c
JFM		 1734/*
1735 * Set the hardware window. These values from OV don't entirely
1736 * make sense - hstop is less than hstart. But they work...
1737 */
21867803
JFM		 1738 { OV7670_R17_HSTART, 0x13 },
1739 { OV7670_R18_HSTOP, 0x01 },
1740 { OV7670_R32_HREF, 0xb6 },
1741 { OV7670_R19_VSTART, 0x02 },
1742 { OV7670_R1A_VSTOP, 0x7a },
1743 { OV7670_R03_VREF, 0x0a },
1744
1745 { OV7670_R0C_COM3, 0x00 },
1746 { OV7670_R3E_COM14, 0x00 },
4202f71c
JFM		 1747/* Mystery scaling numbers */
1748 { 0x70, 0x3a },
1749 { 0x71, 0x35 },
1750 { 0x72, 0x11 },
1751 { 0x73, 0xf0 },
1752 { 0xa2, 0x02 },
21867803 1753/* { OV7670_R15_COM10, 0x0 }, */
4202f71c
JFM		 1754
1755/* Gamma curve values */
1756 { 0x7a, 0x20 },
1757 { 0x7b, 0x10 },
1758 { 0x7c, 0x1e },
1759 { 0x7d, 0x35 },
1760 { 0x7e, 0x5a },
1761 { 0x7f, 0x69 },
1762 { 0x80, 0x76 },
1763 { 0x81, 0x80 },
1764 { 0x82, 0x88 },
1765 { 0x83, 0x8f },
1766 { 0x84, 0x96 },
1767 { 0x85, 0xa3 },
1768 { 0x86, 0xaf },
1769 { 0x87, 0xc4 },
1770 { 0x88, 0xd7 },
1771 { 0x89, 0xe8 },
1772
1773/* AGC and AEC parameters. Note we start by disabling those features,
1774 then turn them only after tweaking the values. */
21867803 1775 { OV7670_R13_COM8, OV7670_COM8_FASTAEC
4202f71c
JFM		 1776 | OV7670_COM8_AECSTEP
1777 | OV7670_COM8_BFILT },
21867803
JFM		 1778 { OV7670_R00_GAIN, 0x00 },
1779 { OV7670_R10_AECH, 0x00 },
1780 { OV7670_R0D_COM4, 0x40 }, /* magic reserved bit */
1781 { OV7670_R14_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
1782 { OV7670_RA5_BD50MAX, 0x05 },
1783 { OV7670_RAB_BD60MAX, 0x07 },
1784 { OV7670_R24_AEW, 0x95 },
1785 { OV7670_R25_AEB, 0x33 },
1786 { OV7670_R26_VPT, 0xe3 },
1787 { OV7670_R9F_HAECC1, 0x78 },
1788 { OV7670_RA0_HAECC2, 0x68 },
4202f71c 1789 { 0xa1, 0x03 }, /* magic */
21867803
JFM		 1790 { OV7670_RA6_HAECC3, 0xd8 },
1791 { OV7670_RA7_HAECC4, 0xd8 },
1792 { OV7670_RA8_HAECC5, 0xf0 },
1793 { OV7670_RA9_HAECC6, 0x90 },
1794 { OV7670_RAA_HAECC7, 0x94 },
1795 { OV7670_R13_COM8, OV7670_COM8_FASTAEC
4202f71c
JFM		 1796 | OV7670_COM8_AECSTEP
1797 | OV7670_COM8_BFILT
1798 | OV7670_COM8_AGC
1799 | OV7670_COM8_AEC },
1800
1801/* Almost all of these are magic "reserved" values. */
21867803
JFM		 1802 { OV7670_R0E_COM5, 0x61 },
1803 { OV7670_R0F_COM6, 0x4b },
4202f71c 1804 { 0x16, 0x02 },
21867803 1805 { OV7670_R1E_MVFP, 0x07 },
4202f71c
JFM		 1806 { 0x21, 0x02 },
1807 { 0x22, 0x91 },
1808 { 0x29, 0x07 },
1809 { 0x33, 0x0b },
1810 { 0x35, 0x0b },
1811 { 0x37, 0x1d },
1812 { 0x38, 0x71 },
1813 { 0x39, 0x2a },
21867803 1814 { OV7670_R3C_COM12, 0x78 },
4202f71c
JFM		 1815 { 0x4d, 0x40 },
1816 { 0x4e, 0x20 },
21867803 1817 { OV7670_R69_GFIX, 0x00 },
4202f71c
JFM		 1818 { 0x6b, 0x4a },
1819 { 0x74, 0x10 },
1820 { 0x8d, 0x4f },
ac40b1fa
JFM		 1821 { 0x8e, 0x00 },
1822 { 0x8f, 0x00 },
1823 { 0x90, 0x00 },
1824 { 0x91, 0x00 },
1825 { 0x96, 0x00 },
1826 { 0x9a, 0x00 },
4202f71c
JFM		 1827 { 0xb0, 0x84 },
1828 { 0xb1, 0x0c },
1829 { 0xb2, 0x0e },
1830 { 0xb3, 0x82 },
1831 { 0xb8, 0x0a },
1832
1833/* More reserved magic, some of which tweaks white balance */
1834 { 0x43, 0x0a },
1835 { 0x44, 0xf0 },
1836 { 0x45, 0x34 },
1837 { 0x46, 0x58 },
1838 { 0x47, 0x28 },
1839 { 0x48, 0x3a },
1840 { 0x59, 0x88 },
1841 { 0x5a, 0x88 },
1842 { 0x5b, 0x44 },
1843 { 0x5c, 0x67 },
1844 { 0x5d, 0x49 },
1845 { 0x5e, 0x0e },
1846 { 0x6c, 0x0a },
1847 { 0x6d, 0x55 },
1848 { 0x6e, 0x11 },
fc63de88 1849 { 0x6f, 0x9f }, /* "9e for advance AWB" */
4202f71c 1850 { 0x6a, 0x40 },
21867803
JFM		 1851 { OV7670_R01_BLUE, 0x40 },
1852 { OV7670_R02_RED, 0x60 },
1853 { OV7670_R13_COM8, OV7670_COM8_FASTAEC
4202f71c
JFM		 1854 | OV7670_COM8_AECSTEP
1855 | OV7670_COM8_BFILT
1856 | OV7670_COM8_AGC
1857 | OV7670_COM8_AEC
1858 | OV7670_COM8_AWB },
1859
1860/* Matrix coefficients */
1861 { 0x4f, 0x80 },
1862 { 0x50, 0x80 },
ac40b1fa 1863 { 0x51, 0x00 },
4202f71c
JFM		 1864 { 0x52, 0x22 },
1865 { 0x53, 0x5e },
1866 { 0x54, 0x80 },
1867 { 0x58, 0x9e },
1868
21867803
JFM		 1869 { OV7670_R41_COM16, OV7670_COM16_AWBGAIN },
1870 { OV7670_R3F_EDGE, 0x00 },
4202f71c
JFM		 1871 { 0x75, 0x05 },
1872 { 0x76, 0xe1 },
ac40b1fa 1873 { 0x4c, 0x00 },
4202f71c 1874 { 0x77, 0x01 },
21867803 1875 { OV7670_R3D_COM13, OV7670_COM13_GAMMA
4202f71c
JFM		 1876 | OV7670_COM13_UVSAT
1877 | 2}, /* was 3 */
1878 { 0x4b, 0x09 },
1879 { 0xc9, 0x60 },
21867803 1880 { OV7670_R41_COM16, 0x38 },
4202f71c
JFM		 1881 { 0x56, 0x40 },
1882
1883 { 0x34, 0x11 },
21867803 1884 { OV7670_R3B_COM11, OV7670_COM11_EXP|OV7670_COM11_HZAUTO },
4202f71c 1885 { 0xa4, 0x88 },
ac40b1fa 1886 { 0x96, 0x00 },
4202f71c
JFM		 1887 { 0x97, 0x30 },
1888 { 0x98, 0x20 },
1889 { 0x99, 0x30 },
1890 { 0x9a, 0x84 },
1891 { 0x9b, 0x29 },
1892 { 0x9c, 0x03 },
1893 { 0x9d, 0x4c },
1894 { 0x9e, 0x3f },
1895 { 0x78, 0x04 },
1896
1897/* Extra-weird stuff. Some sort of multiplexor register */
1898 { 0x79, 0x01 },
1899 { 0xc8, 0xf0 },
1900 { 0x79, 0x0f },
1901 { 0xc8, 0x00 },
1902 { 0x79, 0x10 },
1903 { 0xc8, 0x7e },
1904 { 0x79, 0x0a },
1905 { 0xc8, 0x80 },
1906 { 0x79, 0x0b },
1907 { 0xc8, 0x01 },
1908 { 0x79, 0x0c },
1909 { 0xc8, 0x0f },
1910 { 0x79, 0x0d },
1911 { 0xc8, 0x20 },
1912 { 0x79, 0x09 },
1913 { 0xc8, 0x80 },
1914 { 0x79, 0x02 },
1915 { 0xc8, 0xc0 },
1916 { 0x79, 0x03 },
1917 { 0xc8, 0x40 },
1918 { 0x79, 0x05 },
1919 { 0xc8, 0x30 },
1920 { 0x79, 0x26 },
1921};
1922
1923static const struct ov_i2c_regvals norm_8610[] = {
1924 { 0x12, 0x80 },
1925 { 0x00, 0x00 },
1926 { 0x01, 0x80 },
1927 { 0x02, 0x80 },
1928 { 0x03, 0xc0 },
1929 { 0x04, 0x30 },
1930 { 0x05, 0x30 }, /* was 0x10, new from windrv 090403 */
1931 { 0x06, 0x70 }, /* was 0x80, new from windrv 090403 */
1932 { 0x0a, 0x86 },
1933 { 0x0b, 0xb0 },
1934 { 0x0c, 0x20 },
1935 { 0x0d, 0x20 },
1936 { 0x11, 0x01 },
1937 { 0x12, 0x25 },
1938 { 0x13, 0x01 },
1939 { 0x14, 0x04 },
1940 { 0x15, 0x01 }, /* Lin and Win think different about UV order */
1941 { 0x16, 0x03 },
1942 { 0x17, 0x38 }, /* was 0x2f, new from windrv 090403 */
1943 { 0x18, 0xea }, /* was 0xcf, new from windrv 090403 */
1944 { 0x19, 0x02 }, /* was 0x06, new from windrv 090403 */
1945 { 0x1a, 0xf5 },
1946 { 0x1b, 0x00 },
1947 { 0x20, 0xd0 }, /* was 0x90, new from windrv 090403 */
1948 { 0x23, 0xc0 }, /* was 0x00, new from windrv 090403 */
1949 { 0x24, 0x30 }, /* was 0x1d, new from windrv 090403 */
1950 { 0x25, 0x50 }, /* was 0x57, new from windrv 090403 */
1951 { 0x26, 0xa2 },
1952 { 0x27, 0xea },
1953 { 0x28, 0x00 },
1954 { 0x29, 0x00 },
1955 { 0x2a, 0x80 },
1956 { 0x2b, 0xc8 }, /* was 0xcc, new from windrv 090403 */
1957 { 0x2c, 0xac },
1958 { 0x2d, 0x45 }, /* was 0xd5, new from windrv 090403 */
1959 { 0x2e, 0x80 },
1960 { 0x2f, 0x14 }, /* was 0x01, new from windrv 090403 */
1961 { 0x4c, 0x00 },
1962 { 0x4d, 0x30 }, /* was 0x10, new from windrv 090403 */
1963 { 0x60, 0x02 }, /* was 0x01, new from windrv 090403 */
1964 { 0x61, 0x00 }, /* was 0x09, new from windrv 090403 */
1965 { 0x62, 0x5f }, /* was 0xd7, new from windrv 090403 */
1966 { 0x63, 0xff },
1967 { 0x64, 0x53 }, /* new windrv 090403 says 0x57,
1968 * maybe thats wrong */
1969 { 0x65, 0x00 },
1970 { 0x66, 0x55 },
1971 { 0x67, 0xb0 },
1972 { 0x68, 0xc0 }, /* was 0xaf, new from windrv 090403 */
1973 { 0x69, 0x02 },
1974 { 0x6a, 0x22 },
1975 { 0x6b, 0x00 },
1976 { 0x6c, 0x99 }, /* was 0x80, old windrv says 0x00, but
1977 * deleting bit7 colors the first images red */
1978 { 0x6d, 0x11 }, /* was 0x00, new from windrv 090403 */
1979 { 0x6e, 0x11 }, /* was 0x00, new from windrv 090403 */
1980 { 0x6f, 0x01 },
1981 { 0x70, 0x8b },
1982 { 0x71, 0x00 },
1983 { 0x72, 0x14 },
1984 { 0x73, 0x54 },
1985 { 0x74, 0x00 },/* 0x60? - was 0x00, new from windrv 090403 */
1986 { 0x75, 0x0e },
1987 { 0x76, 0x02 }, /* was 0x02, new from windrv 090403 */
1988 { 0x77, 0xff },
1989 { 0x78, 0x80 },
1990 { 0x79, 0x80 },
1991 { 0x7a, 0x80 },
1992 { 0x7b, 0x10 }, /* was 0x13, new from windrv 090403 */
1993 { 0x7c, 0x00 },
1994 { 0x7d, 0x08 }, /* was 0x09, new from windrv 090403 */
1995 { 0x7e, 0x08 }, /* was 0xc0, new from windrv 090403 */
1996 { 0x7f, 0xfb },
1997 { 0x80, 0x28 },
1998 { 0x81, 0x00 },
1999 { 0x82, 0x23 },
2000 { 0x83, 0x0b },
2001 { 0x84, 0x00 },
2002 { 0x85, 0x62 }, /* was 0x61, new from windrv 090403 */
2003 { 0x86, 0xc9 },
2004 { 0x87, 0x00 },
2005 { 0x88, 0x00 },
2006 { 0x89, 0x01 },
2007 { 0x12, 0x20 },
2008 { 0x12, 0x25 }, /* was 0x24, new from windrv 090403 */
2009};
2010
6a7eba24
JFM		 2011static unsigned char ov7670_abs_to_sm(unsigned char v)
2012{
2013 if (v > 127)
2014 return v & 0x7f;
2015 return (128 - v) | 0x80;
2016}
2017
2018/* Write a OV519 register */
f8f20188 2019static void reg_w(struct sd *sd, u16 index, u16 value)
6a7eba24 2020{
a511ba94 2021 int ret, req = 0;
b46aaa02 2022
f8f20188
JFM		 2023 if (sd->gspca_dev.usb_err < 0)
2024 return;
2025
b46aaa02
HG		 2026 switch (sd->bridge) {
2027 case BRIDGE_OV511:
2028 case BRIDGE_OV511PLUS:
2029 req = 2;
2030 break;
2031 case BRIDGE_OVFX2:
a511ba94
HG		 2032 req = 0x0a;
2033 /* fall through */
2034 case BRIDGE_W9968CF:
858ea5e9
JFM		 2035 PDEBUG(D_USBO, "SET %02x %04x %04x",
2036 req, value, index);
b46aaa02
HG		 2037 ret = usb_control_msg(sd->gspca_dev.dev,
2038 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
a511ba94 2039 req,
b46aaa02 2040 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
a511ba94 2041 value, index, NULL, 0, 500);
b46aaa02
HG		 2042 goto leave;
2043 default:
2044 req = 1;
2045 }
6a7eba24 2046
858ea5e9
JFM		 2047 PDEBUG(D_USBO, "SET %02x 0000 %04x %02x",
2048 req, index, value);
739570bb 2049 sd->gspca_dev.usb_buf[0] = value;
6a7eba24
JFM		 2050 ret = usb_control_msg(sd->gspca_dev.dev,
2051 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 2052 req,
6a7eba24
JFM		 2053 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2054 0, index,
739570bb 2055 sd->gspca_dev.usb_buf, 1, 500);
b46aaa02 2056leave:
a511ba94 2057 if (ret < 0) {
858ea5e9 2058 err("reg_w %02x failed %d", index, ret);
f8f20188
JFM		 2059 sd->gspca_dev.usb_err = ret;
2060 return;
a511ba94 2061 }
6a7eba24
JFM		 2062}
2063
a511ba94 2064/* Read from a OV519 register, note not valid for the w9968cf!! */
6a7eba24 2065/* returns: negative is error, pos or zero is data */
9d1593a8 2066static int reg_r(struct sd *sd, u16 index)
6a7eba24
JFM		 2067{
2068 int ret;
b46aaa02
HG		 2069 int req;
2070
f8f20188
JFM		 2071 if (sd->gspca_dev.usb_err < 0)
2072 return -1;
2073
b46aaa02
HG		 2074 switch (sd->bridge) {
2075 case BRIDGE_OV511:
2076 case BRIDGE_OV511PLUS:
2077 req = 3;
2078 break;
2079 case BRIDGE_OVFX2:
2080 req = 0x0b;
2081 break;
2082 default:
2083 req = 1;
2084 }
6a7eba24
JFM		 2085
2086 ret = usb_control_msg(sd->gspca_dev.dev,
2087 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 2088 req,
6a7eba24 2089 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 2090 0, index, sd->gspca_dev.usb_buf, 1, 500);
6a7eba24 2091
a511ba94 2092 if (ret >= 0) {
739570bb 2093 ret = sd->gspca_dev.usb_buf[0];
858ea5e9
JFM		 2094 PDEBUG(D_USBI, "GET %02x 0000 %04x %02x",
2095 req, index, ret);
f8f20188 2096 } else {
858ea5e9 2097 err("reg_r %02x failed %d", index, ret);
f8f20188
JFM		 2098 sd->gspca_dev.usb_err = ret;
2099 }
a511ba94 2100
6a7eba24
JFM		 2101 return ret;
2102}
2103
2104/* Read 8 values from a OV519 register */
2105static int reg_r8(struct sd *sd,
9d1593a8 2106 u16 index)
6a7eba24
JFM		 2107{
2108 int ret;
6a7eba24 2109
f8f20188
JFM		 2110 if (sd->gspca_dev.usb_err < 0)
2111 return -1;
2112
6a7eba24
JFM		 2113 ret = usb_control_msg(sd->gspca_dev.dev,
2114 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2115 1, /* REQ_IO */
2116 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 2117 0, index, sd->gspca_dev.usb_buf, 8, 500);
6a7eba24 2118
f8f20188 2119 if (ret >= 0) {
739570bb 2120 ret = sd->gspca_dev.usb_buf[0];
f8f20188 2121 } else {
858ea5e9 2122 err("reg_r8 %02x failed %d", index, ret);
f8f20188
JFM		 2123 sd->gspca_dev.usb_err = ret;
2124 }
a511ba94 2125
6a7eba24
JFM		 2126 return ret;
2127}
2128
2129/*
2130 * Writes bits at positions specified by mask to an OV51x reg. Bits that are in
2131 * the same position as 1's in "mask" are cleared and set to "value". Bits
2132 * that are in the same position as 0's in "mask" are preserved, regardless
2133 * of their respective state in "value".
2134 */
f8f20188 2135static void reg_w_mask(struct sd *sd,
9d1593a8
JFM		 2136 u16 index,
2137 u8 value,
2138 u8 mask)
6a7eba24
JFM		 2139{
2140 int ret;
9d1593a8 2141 u8 oldval;
6a7eba24
JFM		 2142
2143 if (mask != 0xff) {
2144 value &= mask; /* Enforce mask on value */
2145 ret = reg_r(sd, index);
2146 if (ret < 0)
f8f20188 2147 return;
6a7eba24
JFM		 2148
2149 oldval = ret & ~mask; /* Clear the masked bits */
2150 value |= oldval; /* Set the desired bits */
2151 }
f8f20188 2152 reg_w(sd, index, value);
6a7eba24
JFM		 2153}
2154
49809d6a
HG		 2155/*
2156 * Writes multiple (n) byte value to a single register. Only valid with certain
2157 * registers (0x30 and 0xc4 - 0xce).
2158 */
f8f20188 2159static void ov518_reg_w32(struct sd *sd, u16 index, u32 value, int n)
49809d6a
HG		 2160{
2161 int ret;
2162
f8f20188
JFM		 2163 if (sd->gspca_dev.usb_err < 0)
2164 return;
2165
83955556 2166 *((__le32 *) sd->gspca_dev.usb_buf) = __cpu_to_le32(value);
49809d6a
HG		 2167
2168 ret = usb_control_msg(sd->gspca_dev.dev,
2169 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2170 1 /* REG_IO */,
2171 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2172 0, index,
2173 sd->gspca_dev.usb_buf, n, 500);
a511ba94 2174 if (ret < 0) {
858ea5e9 2175 err("reg_w32 %02x failed %d", index, ret);
f8f20188 2176 sd->gspca_dev.usb_err = ret;
a511ba94 2177 }
49809d6a
HG		 2178}
2179
f8f20188 2180static void ov511_i2c_w(struct sd *sd, u8 reg, u8 value)
1876bb92
HG		 2181{
2182 int rc, retries;
2183
858ea5e9 2184 PDEBUG(D_USBO, "ov511_i2c_w %02x %02x", reg, value);
1876bb92
HG		 2185
2186 /* Three byte write cycle */
2187 for (retries = 6; ; ) {
2188 /* Select camera register */
f8f20188 2189 reg_w(sd, R51x_I2C_SADDR_3, reg);
1876bb92
HG		 2190
2191 /* Write "value" to I2C data port of OV511 */
f8f20188 2192 reg_w(sd, R51x_I2C_DATA, value);
1876bb92
HG		 2193
2194 /* Initiate 3-byte write cycle */
f8f20188 2195 reg_w(sd, R511_I2C_CTL, 0x01);
1876bb92 2196
83955556 2197 do {
1876bb92 2198 rc = reg_r(sd, R511_I2C_CTL);
83955556 2199 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2200
2201 if (rc < 0)
f8f20188 2202 return;
1876bb92
HG		 2203
2204 if ((rc & 2) == 0) /* Ack? */
2205 break;
2206 if (--retries < 0) {
2207 PDEBUG(D_USBO, "i2c write retries exhausted");
f8f20188 2208 return;
1876bb92
HG		 2209 }
2210 }
1876bb92
HG		 2211}
2212
9d1593a8 2213static int ov511_i2c_r(struct sd *sd, u8 reg)
1876bb92
HG		 2214{
2215 int rc, value, retries;
2216
2217 /* Two byte write cycle */
2218 for (retries = 6; ; ) {
2219 /* Select camera register */
f8f20188 2220 reg_w(sd, R51x_I2C_SADDR_2, reg);
1876bb92
HG		 2221
2222 /* Initiate 2-byte write cycle */
f8f20188 2223 reg_w(sd, R511_I2C_CTL, 0x03);
1876bb92 2224
83955556 2225 do {
1876bb92 2226 rc = reg_r(sd, R511_I2C_CTL);
83955556 2227 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2228
2229 if (rc < 0)
2230 return rc;
2231
2232 if ((rc & 2) == 0) /* Ack? */
2233 break;
2234
2235 /* I2C abort */
2236 reg_w(sd, R511_I2C_CTL, 0x10);
2237
2238 if (--retries < 0) {
2239 PDEBUG(D_USBI, "i2c write retries exhausted");
2240 return -1;
2241 }
2242 }
2243
2244 /* Two byte read cycle */
2245 for (retries = 6; ; ) {
2246 /* Initiate 2-byte read cycle */
f8f20188 2247 reg_w(sd, R511_I2C_CTL, 0x05);
1876bb92 2248
83955556 2249 do {
1876bb92 2250 rc = reg_r(sd, R511_I2C_CTL);
83955556 2251 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2252
2253 if (rc < 0)
2254 return rc;
2255
2256 if ((rc & 2) == 0) /* Ack? */
2257 break;
2258
2259 /* I2C abort */
f8f20188 2260 reg_w(sd, R511_I2C_CTL, 0x10);
1876bb92
HG		 2261
2262 if (--retries < 0) {
2263 PDEBUG(D_USBI, "i2c read retries exhausted");
2264 return -1;
2265 }
2266 }
2267
2268 value = reg_r(sd, R51x_I2C_DATA);
2269
858ea5e9 2270 PDEBUG(D_USBI, "ov511_i2c_r %02x %02x", reg, value);
1876bb92
HG		 2271
2272 /* This is needed to make i2c_w() work */
f8f20188 2273 reg_w(sd, R511_I2C_CTL, 0x05);
1876bb92
HG		 2274
2275 return value;
2276}
49809d6a 2277
6a7eba24
JFM		 2278/*
2279 * The OV518 I2C I/O procedure is different, hence, this function.
2280 * This is normally only called from i2c_w(). Note that this function
2281 * always succeeds regardless of whether the sensor is present and working.
2282 */
f8f20188 2283static void ov518_i2c_w(struct sd *sd,
9d1593a8
JFM		 2284 u8 reg,
2285 u8 value)
6a7eba24 2286{
858ea5e9 2287 PDEBUG(D_USBO, "ov518_i2c_w %02x %02x", reg, value);
6a7eba24
JFM		 2288
2289 /* Select camera register */
f8f20188 2290 reg_w(sd, R51x_I2C_SADDR_3, reg);
6a7eba24
JFM		 2291
2292 /* Write "value" to I2C data port of OV511 */
f8f20188 2293 reg_w(sd, R51x_I2C_DATA, value);
6a7eba24
JFM		 2294
2295 /* Initiate 3-byte write cycle */
f8f20188 2296 reg_w(sd, R518_I2C_CTL, 0x01);
6a7eba24
JFM		 2297
2298 /* wait for write complete */
2299 msleep(4);
f8f20188 2300 reg_r8(sd, R518_I2C_CTL);
6a7eba24
JFM		 2301}
2302
2303/*
2304 * returns: negative is error, pos or zero is data
2305 *
2306 * The OV518 I2C I/O procedure is different, hence, this function.
2307 * This is normally only called from i2c_r(). Note that this function
2308 * always succeeds regardless of whether the sensor is present and working.
2309 */
9d1593a8 2310static int ov518_i2c_r(struct sd *sd, u8 reg)
6a7eba24 2311{
f8f20188 2312 int value;
6a7eba24
JFM		 2313
2314 /* Select camera register */
f8f20188 2315 reg_w(sd, R51x_I2C_SADDR_2, reg);
6a7eba24
JFM		 2316
2317 /* Initiate 2-byte write cycle */
f8f20188 2318 reg_w(sd, R518_I2C_CTL, 0x03);
6a7eba24
JFM		 2319
2320 /* Initiate 2-byte read cycle */
f8f20188 2321 reg_w(sd, R518_I2C_CTL, 0x05);
6a7eba24 2322 value = reg_r(sd, R51x_I2C_DATA);
858ea5e9 2323 PDEBUG(D_USBI, "ov518_i2c_r %02x %02x", reg, value);
6a7eba24
JFM		 2324 return value;
2325}
2326
f8f20188 2327static void ovfx2_i2c_w(struct sd *sd, u8 reg, u8 value)
b46aaa02
HG		 2328{
2329 int ret;
2330
f8f20188
JFM		 2331 if (sd->gspca_dev.usb_err < 0)
2332 return;
2333
b46aaa02
HG		 2334 ret = usb_control_msg(sd->gspca_dev.dev,
2335 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2336 0x02,
2337 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
9d1593a8 2338 (u16) value, (u16) reg, NULL, 0, 500);
b46aaa02 2339
a511ba94 2340 if (ret < 0) {
858ea5e9 2341 err("ovfx2_i2c_w %02x failed %d", reg, ret);
f8f20188 2342 sd->gspca_dev.usb_err = ret;
a511ba94 2343 }
b46aaa02 2344
858ea5e9 2345 PDEBUG(D_USBO, "ovfx2_i2c_w %02x %02x", reg, value);
b46aaa02
HG		 2346}
2347
9d1593a8 2348static int ovfx2_i2c_r(struct sd *sd, u8 reg)
b46aaa02
HG		 2349{
2350 int ret;
2351
f8f20188
JFM		 2352 if (sd->gspca_dev.usb_err < 0)
2353 return -1;
2354
b46aaa02
HG		 2355 ret = usb_control_msg(sd->gspca_dev.dev,
2356 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2357 0x03,
2358 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
9d1593a8 2359 0, (u16) reg, sd->gspca_dev.usb_buf, 1, 500);
b46aaa02
HG		 2360
2361 if (ret >= 0) {
2362 ret = sd->gspca_dev.usb_buf[0];
858ea5e9 2363 PDEBUG(D_USBI, "ovfx2_i2c_r %02x %02x", reg, ret);
f8f20188 2364 } else {
858ea5e9 2365 err("ovfx2_i2c_r %02x failed %d", reg, ret);
f8f20188
JFM		 2366 sd->gspca_dev.usb_err = ret;
2367 }
b46aaa02
HG		 2368
2369 return ret;
2370}
2371
f8f20188 2372static void i2c_w(struct sd *sd, u8 reg, u8 value)
1876bb92 2373{
fb1f9020 2374 if (sd->sensor_reg_cache[reg] == value)
f8f20188 2375 return;
fb1f9020 2376
1876bb92
HG		 2377 switch (sd->bridge) {
2378 case BRIDGE_OV511:
2379 case BRIDGE_OV511PLUS:
f8f20188 2380 ov511_i2c_w(sd, reg, value);
fb1f9020 2381 break;
1876bb92
HG		 2382 case BRIDGE_OV518:
2383 case BRIDGE_OV518PLUS:
2384 case BRIDGE_OV519:
f8f20188 2385 ov518_i2c_w(sd, reg, value);
fb1f9020 2386 break;
b46aaa02 2387 case BRIDGE_OVFX2:
f8f20188 2388 ovfx2_i2c_w(sd, reg, value);
fb1f9020 2389 break;
a511ba94 2390 case BRIDGE_W9968CF:
f8f20188 2391 w9968cf_i2c_w(sd, reg, value);
fb1f9020 2392 break;
1876bb92 2393 }
fb1f9020 2394
f8f20188 2395 if (sd->gspca_dev.usb_err >= 0) {
fb1f9020
HG		 2396 /* Up on sensor reset empty the register cache */
2397 if (reg == 0x12 && (value & 0x80))
2398 memset(sd->sensor_reg_cache, -1,
87bae740 2399 sizeof(sd->sensor_reg_cache));
fb1f9020
HG		 2400 else
2401 sd->sensor_reg_cache[reg] = value;
2402 }
1876bb92
HG		 2403}
2404
9d1593a8 2405static int i2c_r(struct sd *sd, u8 reg)
1876bb92 2406{
8394bcf3 2407 int ret = -1;
fb1f9020
HG		 2408
2409 if (sd->sensor_reg_cache[reg] != -1)
2410 return sd->sensor_reg_cache[reg];
2411
1876bb92
HG		 2412 switch (sd->bridge) {
2413 case BRIDGE_OV511:
2414 case BRIDGE_OV511PLUS:
fb1f9020
HG		 2415 ret = ov511_i2c_r(sd, reg);
2416 break;
1876bb92
HG		 2417 case BRIDGE_OV518:
2418 case BRIDGE_OV518PLUS:
2419 case BRIDGE_OV519:
fb1f9020
HG		 2420 ret = ov518_i2c_r(sd, reg);
2421 break;
b46aaa02 2422 case BRIDGE_OVFX2:
fb1f9020
HG		 2423 ret = ovfx2_i2c_r(sd, reg);
2424 break;
a511ba94 2425 case BRIDGE_W9968CF:
fb1f9020
HG		 2426 ret = w9968cf_i2c_r(sd, reg);
2427 break;
1876bb92 2428 }
fb1f9020
HG		 2429
2430 if (ret >= 0)
2431 sd->sensor_reg_cache[reg] = ret;
2432
2433 return ret;
1876bb92
HG		 2434}
2435
6a7eba24
JFM		 2436/* Writes bits at positions specified by mask to an I2C reg. Bits that are in
2437 * the same position as 1's in "mask" are cleared and set to "value". Bits
2438 * that are in the same position as 0's in "mask" are preserved, regardless
2439 * of their respective state in "value".
2440 */
f8f20188 2441static void i2c_w_mask(struct sd *sd,
9d1593a8
JFM		 2442 u8 reg,
2443 u8 value,
2444 u8 mask)
6a7eba24
JFM		 2445{
2446 int rc;
9d1593a8 2447 u8 oldval;
6a7eba24
JFM		 2448
2449 value &= mask; /* Enforce mask on value */
2450 rc = i2c_r(sd, reg);
2451 if (rc < 0)
f8f20188 2452 return;
6a7eba24
JFM		 2453 oldval = rc & ~mask; /* Clear the masked bits */
2454 value |= oldval; /* Set the desired bits */
f8f20188 2455 i2c_w(sd, reg, value);
6a7eba24
JFM		 2456}
2457
2458/* Temporarily stops OV511 from functioning. Must do this before changing
2459 * registers while the camera is streaming */
f8f20188 2460static inline void ov51x_stop(struct sd *sd)
6a7eba24
JFM		 2461{
2462 PDEBUG(D_STREAM, "stopping");
2463 sd->stopped = 1;
49809d6a
HG		 2464 switch (sd->bridge) {
2465 case BRIDGE_OV511:
2466 case BRIDGE_OV511PLUS:
f8f20188
JFM		 2467 reg_w(sd, R51x_SYS_RESET, 0x3d);
2468 break;
49809d6a
HG		 2469 case BRIDGE_OV518:
2470 case BRIDGE_OV518PLUS:
f8f20188
JFM		 2471 reg_w_mask(sd, R51x_SYS_RESET, 0x3a, 0x3a);
2472 break;
49809d6a 2473 case BRIDGE_OV519:
f8f20188 2474 reg_w(sd, OV519_R51_RESET1, 0x0f);
5927abcb
JFM		 2475 reg_w(sd, OV519_R51_RESET1, 0x00);
2476 reg_w(sd, 0x22, 0x00); /* FRAR */
f8f20188 2477 break;
b46aaa02 2478 case BRIDGE_OVFX2:
f8f20188
JFM		 2479 reg_w_mask(sd, 0x0f, 0x00, 0x02);
2480 break;
a511ba94 2481 case BRIDGE_W9968CF:
f8f20188
JFM		 2482 reg_w(sd, 0x3c, 0x0a05); /* stop USB transfer */
2483 break;
49809d6a 2484 }
6a7eba24
JFM		 2485}
2486
2487/* Restarts OV511 after ov511_stop() is called. Has no effect if it is not
2488 * actually stopped (for performance). */
f8f20188 2489static inline void ov51x_restart(struct sd *sd)
6a7eba24
JFM		 2490{
2491 PDEBUG(D_STREAM, "restarting");
2492 if (!sd->stopped)
f8f20188 2493 return;
6a7eba24
JFM		 2494 sd->stopped = 0;
2495
2496 /* Reinitialize the stream */
49809d6a
HG		 2497 switch (sd->bridge) {
2498 case BRIDGE_OV511:
2499 case BRIDGE_OV511PLUS:
f8f20188
JFM		 2500 reg_w(sd, R51x_SYS_RESET, 0x00);
2501 break;
49809d6a
HG		 2502 case BRIDGE_OV518:
2503 case BRIDGE_OV518PLUS:
f8f20188
JFM		 2504 reg_w(sd, 0x2f, 0x80);
2505 reg_w(sd, R51x_SYS_RESET, 0x00);
2506 break;
49809d6a 2507 case BRIDGE_OV519:
5927abcb 2508 reg_w(sd, OV519_R51_RESET1, 0x0f);
f8f20188 2509 reg_w(sd, OV519_R51_RESET1, 0x00);
5927abcb 2510 reg_w(sd, 0x22, 0x1d); /* FRAR */
f8f20188 2511 break;
b46aaa02 2512 case BRIDGE_OVFX2:
f8f20188
JFM		 2513 reg_w_mask(sd, 0x0f, 0x02, 0x02);
2514 break;
a511ba94 2515 case BRIDGE_W9968CF:
f8f20188
JFM		 2516 reg_w(sd, 0x3c, 0x8a05); /* USB FIFO enable */
2517 break;
49809d6a 2518 }
6a7eba24
JFM		 2519}
2520
f8f20188 2521static void ov51x_set_slave_ids(struct sd *sd, u8 slave);
229bb7dc 2522
6a7eba24
JFM		 2523/* This does an initial reset of an OmniVision sensor and ensures that I2C
2524 * is synchronized. Returns <0 on failure.
2525 */
9d1593a8 2526static int init_ov_sensor(struct sd *sd, u8 slave)
6a7eba24 2527{
ac40b1fa 2528 int i;
6a7eba24 2529
f8f20188 2530 ov51x_set_slave_ids(sd, slave);
229bb7dc 2531
6a7eba24 2532 /* Reset the sensor */
f8f20188 2533 i2c_w(sd, 0x12, 0x80);
6a7eba24
JFM		 2534
2535 /* Wait for it to initialize */
2536 msleep(150);
2537
ac40b1fa 2538 for (i = 0; i < i2c_detect_tries; i++) {
6a7eba24
JFM		 2539 if (i2c_r(sd, OV7610_REG_ID_HIGH) == 0x7f &&
2540 i2c_r(sd, OV7610_REG_ID_LOW) == 0xa2) {
ac40b1fa
JFM		 2541 PDEBUG(D_PROBE, "I2C synced in %d attempt(s)", i);
2542 return 0;
6a7eba24
JFM		 2543 }
2544
2545 /* Reset the sensor */
f8f20188
JFM		 2546 i2c_w(sd, 0x12, 0x80);
2547
6a7eba24
JFM		 2548 /* Wait for it to initialize */
2549 msleep(150);
87bae740 2550
6a7eba24
JFM		 2551 /* Dummy read to sync I2C */
2552 if (i2c_r(sd, 0x00) < 0)
f8f20188 2553 return -1;
6a7eba24 2554 }
f8f20188 2555 return -1;
6a7eba24
JFM		 2556}
2557
6a7eba24
JFM		 2558/* Set the read and write slave IDs. The "slave" argument is the write slave,
2559 * and the read slave will be set to (slave + 1).
2560 * This should not be called from outside the i2c I/O functions.
2561 * Sets I2C read and write slave IDs. Returns <0 for error
2562 */
f8f20188 2563static void ov51x_set_slave_ids(struct sd *sd,
9d1593a8 2564 u8 slave)
6a7eba24 2565{
a511ba94
HG		 2566 switch (sd->bridge) {
2567 case BRIDGE_OVFX2:
f8f20188
JFM		 2568 reg_w(sd, OVFX2_I2C_ADDR, slave);
2569 return;
a511ba94
HG		 2570 case BRIDGE_W9968CF:
2571 sd->sensor_addr = slave;
f8f20188 2572 return;
a511ba94 2573 }
b46aaa02 2574
f8f20188
JFM		 2575 reg_w(sd, R51x_I2C_W_SID, slave);
2576 reg_w(sd, R51x_I2C_R_SID, slave + 1);
6a7eba24
JFM		 2577}
2578
f8f20188 2579static void write_regvals(struct sd *sd,
a5ae2062 2580 const struct ov_regvals *regvals,
6a7eba24
JFM		 2581 int n)
2582{
6a7eba24 2583 while (--n >= 0) {
f8f20188 2584 reg_w(sd, regvals->reg, regvals->val);
6a7eba24
JFM		 2585 regvals++;
2586 }
6a7eba24
JFM		 2587}
2588
f8f20188
JFM		 2589static void write_i2c_regvals(struct sd *sd,
2590 const struct ov_i2c_regvals *regvals,
2591 int n)
6a7eba24 2592{
6a7eba24 2593 while (--n >= 0) {
f8f20188 2594 i2c_w(sd, regvals->reg, regvals->val);
6a7eba24
JFM		 2595 regvals++;
2596 }
6a7eba24
JFM		 2597}
2598
2599/****************************************************************************
2600 *
2601 * OV511 and sensor configuration
2602 *
2603 ***************************************************************************/
2604
635118d5 2605/* This initializes the OV2x10 / OV3610 / OV3620 */
f8f20188 2606static void ov_hires_configure(struct sd *sd)
635118d5
HG		 2607{
2608 int high, low;
2609
2610 if (sd->bridge != BRIDGE_OVFX2) {
0b656321 2611 err("error hires sensors only supported with ovfx2");
f8f20188 2612 return;
635118d5
HG		 2613 }
2614
2615 PDEBUG(D_PROBE, "starting ov hires configuration");
2616
2617 /* Detect sensor (sub)type */
2618 high = i2c_r(sd, 0x0a);
2619 low = i2c_r(sd, 0x0b);
2620 /* info("%x, %x", high, low); */
2621 if (high == 0x96 && low == 0x40) {
2622 PDEBUG(D_PROBE, "Sensor is an OV2610");
2623 sd->sensor = SEN_OV2610;
2624 } else if (high == 0x36 && (low & 0x0f) == 0x00) {
2625 PDEBUG(D_PROBE, "Sensor is an OV3610");
2626 sd->sensor = SEN_OV3610;
2627 } else {
858ea5e9 2628 err("Error unknown sensor type: %02x%02x",
87bae740 2629 high, low);
635118d5 2630 }
635118d5
HG		 2631}
2632
6a7eba24
JFM		 2633/* This initializes the OV8110, OV8610 sensor. The OV8110 uses
2634 * the same register settings as the OV8610, since they are very similar.
2635 */
f8f20188 2636static void ov8xx0_configure(struct sd *sd)
6a7eba24
JFM		 2637{
2638 int rc;
6a7eba24
JFM		 2639
2640 PDEBUG(D_PROBE, "starting ov8xx0 configuration");
2641
6a7eba24
JFM		 2642 /* Detect sensor (sub)type */
2643 rc = i2c_r(sd, OV7610_REG_COM_I);
2644 if (rc < 0) {
2645 PDEBUG(D_ERR, "Error detecting sensor type");
f8f20188 2646 return;
6a7eba24 2647 }
f8f20188 2648 if ((rc & 3) == 1)
6a7eba24 2649 sd->sensor = SEN_OV8610;
f8f20188 2650 else
0b656321 2651 err("Unknown image sensor version: %d", rc & 3);
6a7eba24
JFM		 2652}
2653
2654/* This initializes the OV7610, OV7620, or OV76BE sensor. The OV76BE uses
2655 * the same register settings as the OV7610, since they are very similar.
2656 */
f8f20188 2657static void ov7xx0_configure(struct sd *sd)
6a7eba24
JFM		 2658{
2659 int rc, high, low;
2660
6a7eba24
JFM		 2661 PDEBUG(D_PROBE, "starting OV7xx0 configuration");
2662
6a7eba24
JFM		 2663 /* Detect sensor (sub)type */
2664 rc = i2c_r(sd, OV7610_REG_COM_I);
2665
2666 /* add OV7670 here
2667 * it appears to be wrongly detected as a 7610 by default */
2668 if (rc < 0) {
2669 PDEBUG(D_ERR, "Error detecting sensor type");
f8f20188 2670 return;
6a7eba24
JFM		 2671 }
2672 if ((rc & 3) == 3) {
2673 /* quick hack to make OV7670s work */
2674 high = i2c_r(sd, 0x0a);
2675 low = i2c_r(sd, 0x0b);
2676 /* info("%x, %x", high, low); */
7a5a414c
JFM		 2677 if (high == 0x76 && (low & 0xf0) == 0x70) {
2678 PDEBUG(D_PROBE, "Sensor is an OV76%02x", low);
6a7eba24
JFM		 2679 sd->sensor = SEN_OV7670;
2680 } else {
2681 PDEBUG(D_PROBE, "Sensor is an OV7610");
2682 sd->sensor = SEN_OV7610;
2683 }
2684 } else if ((rc & 3) == 1) {
2685 /* I don't know what's different about the 76BE yet. */
b282d873 2686 if (i2c_r(sd, 0x15) & 1) {
6a7eba24 2687 PDEBUG(D_PROBE, "Sensor is an OV7620AE");
859cc470 2688 sd->sensor = SEN_OV7620AE;
b282d873 2689 } else {
6a7eba24 2690 PDEBUG(D_PROBE, "Sensor is an OV76BE");
b282d873
HG		 2691 sd->sensor = SEN_OV76BE;
2692 }
6a7eba24
JFM		 2693 } else if ((rc & 3) == 0) {
2694 /* try to read product id registers */
2695 high = i2c_r(sd, 0x0a);
2696 if (high < 0) {
2697 PDEBUG(D_ERR, "Error detecting camera chip PID");
f8f20188 2698 return;
6a7eba24
JFM		 2699 }
2700 low = i2c_r(sd, 0x0b);
2701 if (low < 0) {
2702 PDEBUG(D_ERR, "Error detecting camera chip VER");
f8f20188 2703 return;
6a7eba24
JFM		 2704 }
2705 if (high == 0x76) {
594f5b8b
JFM		 2706 switch (low) {
2707 case 0x30:
0b656321
JFM		 2708 err("Sensor is an OV7630/OV7635");
2709 err("7630 is not supported by this driver");
f8f20188 2710 return;
594f5b8b 2711 case 0x40:
6a7eba24
JFM		 2712 PDEBUG(D_PROBE, "Sensor is an OV7645");
2713 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2714 break;
2715 case 0x45:
6a7eba24
JFM		 2716 PDEBUG(D_PROBE, "Sensor is an OV7645B");
2717 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2718 break;
2719 case 0x48:
6a7eba24 2720 PDEBUG(D_PROBE, "Sensor is an OV7648");
035d3a3d 2721 sd->sensor = SEN_OV7648;
594f5b8b 2722 break;
42e142f6
JFM		 2723 case 0x60:
2724 PDEBUG(D_PROBE, "Sensor is a OV7660");
2725 sd->sensor = SEN_OV7660;
2726 sd->invert_led = 0;
2727 break;
594f5b8b
JFM		 2728 default:
2729 PDEBUG(D_PROBE, "Unknown sensor: 0x76%x", low);
f8f20188 2730 return;
6a7eba24
JFM		 2731 }
2732 } else {
2733 PDEBUG(D_PROBE, "Sensor is an OV7620");
2734 sd->sensor = SEN_OV7620;
2735 }
2736 } else {
0b656321 2737 err("Unknown image sensor version: %d", rc & 3);
6a7eba24 2738 }
6a7eba24
JFM		 2739}
2740
2741/* This initializes the OV6620, OV6630, OV6630AE, or OV6630AF sensor. */
f8f20188 2742static void ov6xx0_configure(struct sd *sd)
6a7eba24
JFM		 2743{
2744 int rc;
4202f71c 2745 PDEBUG(D_PROBE, "starting OV6xx0 configuration");
6a7eba24
JFM		 2746
2747 /* Detect sensor (sub)type */
2748 rc = i2c_r(sd, OV7610_REG_COM_I);
2749 if (rc < 0) {
2750 PDEBUG(D_ERR, "Error detecting sensor type");
f8f20188 2751 return;
6a7eba24
JFM		 2752 }
2753
2754 /* Ugh. The first two bits are the version bits, but
2755 * the entire register value must be used. I guess OVT
2756 * underestimated how many variants they would make. */
594f5b8b
JFM		 2757 switch (rc) {
2758 case 0x00:
6a7eba24 2759 sd->sensor = SEN_OV6630;
0b656321
JFM		 2760 warn("WARNING: Sensor is an OV66308. Your camera may have");
2761 warn("been misdetected in previous driver versions.");
594f5b8b
JFM		 2762 break;
2763 case 0x01:
6a7eba24 2764 sd->sensor = SEN_OV6620;
7d971373 2765 PDEBUG(D_PROBE, "Sensor is an OV6620");
594f5b8b
JFM		 2766 break;
2767 case 0x02:
6a7eba24
JFM		 2768 sd->sensor = SEN_OV6630;
2769 PDEBUG(D_PROBE, "Sensor is an OV66308AE");
594f5b8b
JFM		 2770 break;
2771 case 0x03:
7d971373 2772 sd->sensor = SEN_OV66308AF;
6a7eba24 2773 PDEBUG(D_PROBE, "Sensor is an OV66308AF");
594f5b8b
JFM		 2774 break;
2775 case 0x90:
6a7eba24 2776 sd->sensor = SEN_OV6630;
0b656321
JFM		 2777 warn("WARNING: Sensor is an OV66307. Your camera may have");
2778 warn("been misdetected in previous driver versions.");
594f5b8b
JFM		 2779 break;
2780 default:
0b656321 2781 err("FATAL: Unknown sensor version: 0x%02x", rc);
f8f20188 2782 return;
6a7eba24
JFM		 2783 }
2784
2785 /* Set sensor-specific vars */
594f5b8b 2786 sd->sif = 1;
6a7eba24
JFM		 2787}
2788
2789/* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */
2790static void ov51x_led_control(struct sd *sd, int on)
2791{
9e4d8258
HG		 2792 if (sd->invert_led)
2793 on = !on;
2794
49809d6a
HG		 2795 switch (sd->bridge) {
2796 /* OV511 has no LED control */
2797 case BRIDGE_OV511PLUS:
a23acec4 2798 reg_w(sd, R511_SYS_LED_CTL, on);
49809d6a
HG		 2799 break;
2800 case BRIDGE_OV518:
2801 case BRIDGE_OV518PLUS:
a23acec4 2802 reg_w_mask(sd, R518_GPIO_OUT, 0x02 * on, 0x02);
49809d6a
HG		 2803 break;
2804 case BRIDGE_OV519:
a23acec4 2805 reg_w_mask(sd, OV519_GPIO_DATA_OUT0, on, 1);
49809d6a
HG		 2806 break;
2807 }
6a7eba24
JFM		 2808}
2809
417a4d26
HG		 2810static void sd_reset_snapshot(struct gspca_dev *gspca_dev)
2811{
2812 struct sd *sd = (struct sd *) gspca_dev;
2813
2814 if (!sd->snapshot_needs_reset)
2815 return;
2816
2817 /* Note it is important that we clear sd->snapshot_needs_reset,
2818 before actually clearing the snapshot state in the bridge
2819 otherwise we might race with the pkt_scan interrupt handler */
2820 sd->snapshot_needs_reset = 0;
2821
2822 switch (sd->bridge) {
88e8d20a
HG		 2823 case BRIDGE_OV511:
2824 case BRIDGE_OV511PLUS:
2825 reg_w(sd, R51x_SYS_SNAP, 0x02);
2826 reg_w(sd, R51x_SYS_SNAP, 0x00);
2827 break;
92e232ac
HG		 2828 case BRIDGE_OV518:
2829 case BRIDGE_OV518PLUS:
2830 reg_w(sd, R51x_SYS_SNAP, 0x02); /* Reset */
2831 reg_w(sd, R51x_SYS_SNAP, 0x01); /* Enable */
2832 break;
417a4d26
HG		 2833 case BRIDGE_OV519:
2834 reg_w(sd, R51x_SYS_RESET, 0x40);
2835 reg_w(sd, R51x_SYS_RESET, 0x00);
2836 break;
2837 }
2838}
2839
f8f20188 2840static void ov51x_upload_quan_tables(struct sd *sd)
49809d6a 2841{
1876bb92
HG		 2842 const unsigned char yQuanTable511[] = {
2843 0, 1, 1, 2, 2, 3, 3, 4,
2844 1, 1, 1, 2, 2, 3, 4, 4,
2845 1, 1, 2, 2, 3, 4, 4, 4,
2846 2, 2, 2, 3, 4, 4, 4, 4,
2847 2, 2, 3, 4, 4, 5, 5, 5,
2848 3, 3, 4, 4, 5, 5, 5, 5,
2849 3, 4, 4, 4, 5, 5, 5, 5,
2850 4, 4, 4, 4, 5, 5, 5, 5
2851 };
2852
2853 const unsigned char uvQuanTable511[] = {
2854 0, 2, 2, 3, 4, 4, 4, 4,
2855 2, 2, 2, 4, 4, 4, 4, 4,
2856 2, 2, 3, 4, 4, 4, 4, 4,
2857 3, 4, 4, 4, 4, 4, 4, 4,
2858 4, 4, 4, 4, 4, 4, 4, 4,
2859 4, 4, 4, 4, 4, 4, 4, 4,
2860 4, 4, 4, 4, 4, 4, 4, 4,
2861 4, 4, 4, 4, 4, 4, 4, 4
2862 };
2863
2864 /* OV518 quantization tables are 8x4 (instead of 8x8) */
49809d6a
HG		 2865 const unsigned char yQuanTable518[] = {
2866 5, 4, 5, 6, 6, 7, 7, 7,
2867 5, 5, 5, 5, 6, 7, 7, 7,
2868 6, 6, 6, 6, 7, 7, 7, 8,
2869 7, 7, 6, 7, 7, 7, 8, 8
2870 };
49809d6a
HG		 2871 const unsigned char uvQuanTable518[] = {
2872 6, 6, 6, 7, 7, 7, 7, 7,
2873 6, 6, 6, 7, 7, 7, 7, 7,
2874 6, 6, 6, 7, 7, 7, 7, 8,
2875 7, 7, 7, 7, 7, 7, 8, 8
2876 };
2877
1876bb92 2878 const unsigned char *pYTable, *pUVTable;
49809d6a 2879 unsigned char val0, val1;
f8f20188 2880 int i, size, reg = R51x_COMP_LUT_BEGIN;
49809d6a
HG		 2881
2882 PDEBUG(D_PROBE, "Uploading quantization tables");
2883
1876bb92
HG		 2884 if (sd->bridge == BRIDGE_OV511 || sd->bridge == BRIDGE_OV511PLUS) {
2885 pYTable = yQuanTable511;
2886 pUVTable = uvQuanTable511;
87bae740 2887 size = 32;
1876bb92
HG		 2888 } else {
2889 pYTable = yQuanTable518;
2890 pUVTable = uvQuanTable518;
87bae740 2891 size = 16;
1876bb92
HG		 2892 }
2893
2894 for (i = 0; i < size; i++) {
49809d6a
HG		 2895 val0 = *pYTable++;
2896 val1 = *pYTable++;
2897 val0 &= 0x0f;
2898 val1 &= 0x0f;
2899 val0 |= val1 << 4;
f8f20188 2900 reg_w(sd, reg, val0);
49809d6a
HG		 2901
2902 val0 = *pUVTable++;
2903 val1 = *pUVTable++;
2904 val0 &= 0x0f;
2905 val1 &= 0x0f;
2906 val0 |= val1 << 4;
f8f20188 2907 reg_w(sd, reg + size, val0);
49809d6a
HG		 2908
2909 reg++;
2910 }
49809d6a
HG		 2911}
2912
1876bb92 2913/* This initializes the OV511/OV511+ and the sensor */
f8f20188 2914static void ov511_configure(struct gspca_dev *gspca_dev)
1876bb92
HG		 2915{
2916 struct sd *sd = (struct sd *) gspca_dev;
1876bb92
HG		 2917
2918 /* For 511 and 511+ */
2919 const struct ov_regvals init_511[] = {
2920 { R51x_SYS_RESET, 0x7f },
2921 { R51x_SYS_INIT, 0x01 },
2922 { R51x_SYS_RESET, 0x7f },
2923 { R51x_SYS_INIT, 0x01 },
2924 { R51x_SYS_RESET, 0x3f },
2925 { R51x_SYS_INIT, 0x01 },
2926 { R51x_SYS_RESET, 0x3d },
2927 };
2928
2929 const struct ov_regvals norm_511[] = {
780e3121 2930 { R511_DRAM_FLOW_CTL, 0x01 },
1876bb92
HG		 2931 { R51x_SYS_SNAP, 0x00 },
2932 { R51x_SYS_SNAP, 0x02 },
2933 { R51x_SYS_SNAP, 0x00 },
2934 { R511_FIFO_OPTS, 0x1f },
2935 { R511_COMP_EN, 0x00 },
2936 { R511_COMP_LUT_EN, 0x03 },
2937 };
2938
2939 const struct ov_regvals norm_511_p[] = {
2940 { R511_DRAM_FLOW_CTL, 0xff },
2941 { R51x_SYS_SNAP, 0x00 },
2942 { R51x_SYS_SNAP, 0x02 },
2943 { R51x_SYS_SNAP, 0x00 },
2944 { R511_FIFO_OPTS, 0xff },
2945 { R511_COMP_EN, 0x00 },
2946 { R511_COMP_LUT_EN, 0x03 },
2947 };
2948
2949 const struct ov_regvals compress_511[] = {
2950 { 0x70, 0x1f },
2951 { 0x71, 0x05 },
2952 { 0x72, 0x06 },
2953 { 0x73, 0x06 },
2954 { 0x74, 0x14 },
2955 { 0x75, 0x03 },
2956 { 0x76, 0x04 },
2957 { 0x77, 0x04 },
2958 };
2959
2960 PDEBUG(D_PROBE, "Device custom id %x", reg_r(sd, R51x_SYS_CUST_ID));
2961
f8f20188 2962 write_regvals(sd, init_511, ARRAY_SIZE(init_511));
1876bb92
HG		 2963
2964 switch (sd->bridge) {
2965 case BRIDGE_OV511:
f8f20188 2966 write_regvals(sd, norm_511, ARRAY_SIZE(norm_511));
1876bb92
HG		 2967 break;
2968 case BRIDGE_OV511PLUS:
f8f20188 2969 write_regvals(sd, norm_511_p, ARRAY_SIZE(norm_511_p));
1876bb92
HG		 2970 break;
2971 }
2972
2973 /* Init compression */
f8f20188 2974 write_regvals(sd, compress_511, ARRAY_SIZE(compress_511));
1876bb92 2975
f8f20188 2976 ov51x_upload_quan_tables(sd);
1876bb92
HG		 2977}
2978
49809d6a 2979/* This initializes the OV518/OV518+ and the sensor */
f8f20188 2980static void ov518_configure(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 2981{
2982 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 2983
2984 /* For 518 and 518+ */
e080fcd9 2985 const struct ov_regvals init_518[] = {
49809d6a
HG		 2986 { R51x_SYS_RESET, 0x40 },
2987 { R51x_SYS_INIT, 0xe1 },
2988 { R51x_SYS_RESET, 0x3e },
2989 { R51x_SYS_INIT, 0xe1 },
2990 { R51x_SYS_RESET, 0x00 },
2991 { R51x_SYS_INIT, 0xe1 },
2992 { 0x46, 0x00 },
2993 { 0x5d, 0x03 },
2994 };
2995
e080fcd9 2996 const struct ov_regvals norm_518[] = {
49809d6a
HG		 2997 { R51x_SYS_SNAP, 0x02 }, /* Reset */
2998 { R51x_SYS_SNAP, 0x01 }, /* Enable */
780e3121 2999 { 0x31, 0x0f },
49809d6a
HG		 3000 { 0x5d, 0x03 },
3001 { 0x24, 0x9f },
3002 { 0x25, 0x90 },
3003 { 0x20, 0x00 },
3004 { 0x51, 0x04 },
3005 { 0x71, 0x19 },
3006 { 0x2f, 0x80 },
3007 };
3008
e080fcd9 3009 const struct ov_regvals norm_518_p[] = {
49809d6a
HG		 3010 { R51x_SYS_SNAP, 0x02 }, /* Reset */
3011 { R51x_SYS_SNAP, 0x01 }, /* Enable */
780e3121 3012 { 0x31, 0x0f },
49809d6a
HG		 3013 { 0x5d, 0x03 },
3014 { 0x24, 0x9f },
3015 { 0x25, 0x90 },
3016 { 0x20, 0x60 },
3017 { 0x51, 0x02 },
3018 { 0x71, 0x19 },
3019 { 0x40, 0xff },
3020 { 0x41, 0x42 },
3021 { 0x46, 0x00 },
3022 { 0x33, 0x04 },
3023 { 0x21, 0x19 },
3024 { 0x3f, 0x10 },
3025 { 0x2f, 0x80 },
3026 };
3027
3028 /* First 5 bits of custom ID reg are a revision ID on OV518 */
3029 PDEBUG(D_PROBE, "Device revision %d",
87bae740 3030 0x1f & reg_r(sd, R51x_SYS_CUST_ID));
49809d6a 3031
f8f20188 3032 write_regvals(sd, init_518, ARRAY_SIZE(init_518));
49809d6a
HG		 3033
3034 /* Set LED GPIO pin to output mode */
f8f20188 3035 reg_w_mask(sd, R518_GPIO_CTL, 0x00, 0x02);
6a7eba24 3036
49809d6a
HG		 3037 switch (sd->bridge) {
3038 case BRIDGE_OV518:
f8f20188 3039 write_regvals(sd, norm_518, ARRAY_SIZE(norm_518));
49809d6a
HG		 3040 break;
3041 case BRIDGE_OV518PLUS:
f8f20188 3042 write_regvals(sd, norm_518_p, ARRAY_SIZE(norm_518_p));
49809d6a
HG		 3043 break;
3044 }
3045
f8f20188 3046 ov51x_upload_quan_tables(sd);
49809d6a 3047
f8f20188 3048 reg_w(sd, 0x2f, 0x80);
49809d6a
HG		 3049}
3050
f8f20188 3051static void ov519_configure(struct sd *sd)
49809d6a 3052{
a5ae2062 3053 static const struct ov_regvals init_519[] = {
87bae740 3054 { 0x5a, 0x6d }, /* EnableSystem */
fc63de88 3055 { 0x53, 0x9b }, /* don't enable the microcontroller */
21867803 3056 { OV519_R54_EN_CLK1, 0xff }, /* set bit2 to enable jpeg */
87bae740
JFM		 3057 { 0x5d, 0x03 },
3058 { 0x49, 0x01 },
3059 { 0x48, 0x00 },
6a7eba24
JFM		 3060 /* Set LED pin to output mode. Bit 4 must be cleared or sensor
3061 * detection will fail. This deserves further investigation. */
3062 { OV519_GPIO_IO_CTRL0, 0xee },
21867803
JFM		 3063 { OV519_R51_RESET1, 0x0f },
3064 { OV519_R51_RESET1, 0x00 },
87bae740 3065 { 0x22, 0x00 },
6a7eba24
JFM		 3066 /* windows reads 0x55 at this point*/
3067 };
3068
f8f20188 3069 write_regvals(sd, init_519, ARRAY_SIZE(init_519));
49809d6a
HG		 3070}
3071
f8f20188 3072static void ovfx2_configure(struct sd *sd)
b46aaa02
HG		 3073{
3074 static const struct ov_regvals init_fx2[] = {
3075 { 0x00, 0x60 },
3076 { 0x02, 0x01 },
3077 { 0x0f, 0x1d },
3078 { 0xe9, 0x82 },
3079 { 0xea, 0xc7 },
3080 { 0xeb, 0x10 },
3081 { 0xec, 0xf6 },
3082 };
3083
3084 sd->stopped = 1;
3085
f8f20188 3086 write_regvals(sd, init_fx2, ARRAY_SIZE(init_fx2));
b46aaa02
HG		 3087}
3088
42e142f6
JFM		 3089/* set the mode */
3090/* This function works for ov7660 only */
3091static void ov519_set_mode(struct sd *sd)
3092{
3093 static const struct ov_regvals bridge_ov7660[2][10] = {
3094 {{0x10, 0x14}, {0x11, 0x1e}, {0x12, 0x00}, {0x13, 0x00},
3095 {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
3096 {0x25, 0x01}, {0x26, 0x00}},
3097 {{0x10, 0x28}, {0x11, 0x3c}, {0x12, 0x00}, {0x13, 0x00},
3098 {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
3099 {0x25, 0x03}, {0x26, 0x00}}
3100 };
3101 static const struct ov_i2c_regvals sensor_ov7660[2][3] = {
3102 {{0x12, 0x00}, {0x24, 0x00}, {0x0c, 0x0c}},
3103 {{0x12, 0x00}, {0x04, 0x00}, {0x0c, 0x00}}
3104 };
3105 static const struct ov_i2c_regvals sensor_ov7660_2[] = {
3106 {OV7670_R17_HSTART, 0x13},
3107 {OV7670_R18_HSTOP, 0x01},
3108 {OV7670_R32_HREF, 0x92},
3109 {OV7670_R19_VSTART, 0x02},
3110 {OV7670_R1A_VSTOP, 0x7a},
3111 {OV7670_R03_VREF, 0x00},
3112/* {0x33, 0x00}, */
3113/* {0x34, 0x07}, */
3114/* {0x36, 0x00}, */
3115/* {0x6b, 0x0a}, */
3116 };
3117
3118 write_regvals(sd, bridge_ov7660[sd->gspca_dev.curr_mode],
3119 ARRAY_SIZE(bridge_ov7660[0]));
3120 write_i2c_regvals(sd, sensor_ov7660[sd->gspca_dev.curr_mode],
3121 ARRAY_SIZE(sensor_ov7660[0]));
3122 write_i2c_regvals(sd, sensor_ov7660_2,
3123 ARRAY_SIZE(sensor_ov7660_2));
3124}
3125
3126/* set the frame rate */
3127/* This function works for sensors ov7640, ov7648 ov7660 and ov7670 only */
3128static void ov519_set_fr(struct sd *sd)
3129{
3130 int fr;
3131 u8 clock;
3132 /* frame rate table with indices:
3133 * - mode = 0: 320x240, 1: 640x480
3134 * - fr rate = 0: 30, 1: 25, 2: 20, 3: 15, 4: 10, 5: 5
3135 * - reg = 0: bridge a4, 1: bridge 23, 2: sensor 11 (clock)
3136 */
3137 static const u8 fr_tb[2][6][3] = {
3138 {{0x04, 0xff, 0x00},
3139 {0x04, 0x1f, 0x00},
3140 {0x04, 0x1b, 0x00},
3141 {0x04, 0x15, 0x00},
3142 {0x04, 0x09, 0x00},
3143 {0x04, 0x01, 0x00}},
3144 {{0x0c, 0xff, 0x00},
3145 {0x0c, 0x1f, 0x00},
3146 {0x0c, 0x1b, 0x00},
3147 {0x04, 0xff, 0x01},
3148 {0x04, 0x1f, 0x01},
3149 {0x04, 0x1b, 0x01}},
3150 };
3151
3152 if (frame_rate > 0)
3153 sd->frame_rate = frame_rate;
3154 if (sd->frame_rate >= 30)
3155 fr = 0;
3156 else if (sd->frame_rate >= 25)
3157 fr = 1;
3158 else if (sd->frame_rate >= 20)
3159 fr = 2;
3160 else if (sd->frame_rate >= 15)
3161 fr = 3;
3162 else if (sd->frame_rate >= 10)
3163 fr = 4;
3164 else
3165 fr = 5;
3166 reg_w(sd, 0xa4, fr_tb[sd->gspca_dev.curr_mode][fr][0]);
3167 reg_w(sd, 0x23, fr_tb[sd->gspca_dev.curr_mode][fr][1]);
3168 clock = fr_tb[sd->gspca_dev.curr_mode][fr][2];
3169 if (sd->sensor == SEN_OV7660)
3170 clock |= 0x80; /* enable double clock */
3171 ov518_i2c_w(sd, OV7670_R11_CLKRC, clock);
3172}
3173
49809d6a
HG		 3174/* this function is called at probe time */
3175static int sd_config(struct gspca_dev *gspca_dev,
3176 const struct usb_device_id *id)
3177{
3178 struct sd *sd = (struct sd *) gspca_dev;
b46aaa02 3179 struct cam *cam = &gspca_dev->cam;
49809d6a 3180
9e4d8258 3181 sd->bridge = id->driver_info & BRIDGE_MASK;
a23acec4 3182 sd->invert_led = (id->driver_info & BRIDGE_INVERT_LED) != 0;
49809d6a
HG		 3183
3184 switch (sd->bridge) {
1876bb92
HG		 3185 case BRIDGE_OV511:
3186 case BRIDGE_OV511PLUS:
7491f785
JFM		 3187 cam->cam_mode = ov511_vga_mode;
3188 cam->nmodes = ARRAY_SIZE(ov511_vga_mode);
1876bb92 3189 break;
49809d6a
HG		 3190 case BRIDGE_OV518:
3191 case BRIDGE_OV518PLUS:
7491f785
JFM		 3192 cam->cam_mode = ov518_vga_mode;
3193 cam->nmodes = ARRAY_SIZE(ov518_vga_mode);
49809d6a
HG		 3194 break;
3195 case BRIDGE_OV519:
7491f785
JFM		 3196 cam->cam_mode = ov519_vga_mode;
3197 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3198 sd->invert_led = !sd->invert_led;
49809d6a 3199 break;
b46aaa02 3200 case BRIDGE_OVFX2:
7491f785
JFM		 3201 cam->cam_mode = ov519_vga_mode;
3202 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
b46aaa02
HG		 3203 cam->bulk_size = OVFX2_BULK_SIZE;
3204 cam->bulk_nurbs = MAX_NURBS;
3205 cam->bulk = 1;
3206 break;
a511ba94 3207 case BRIDGE_W9968CF:
7491f785
JFM		 3208 cam->cam_mode = w9968cf_vga_mode;
3209 cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode);
a511ba94
HG		 3210 cam->reverse_alts = 1;
3211 break;
49809d6a
HG		 3212 }
3213
7491f785
JFM		 3214 gspca_dev->cam.ctrls = sd->ctrls;
3215 sd->quality = QUALITY_DEF;
3216
3217 return 0;
3218}
3219
3220/* this function is called at probe and resume time */
3221static int sd_init(struct gspca_dev *gspca_dev)
3222{
3223 struct sd *sd = (struct sd *) gspca_dev;
3224 struct cam *cam = &gspca_dev->cam;
3225
3226 switch (sd->bridge) {
3227 case BRIDGE_OV511:
3228 case BRIDGE_OV511PLUS:
3229 ov511_configure(gspca_dev);
3230 break;
3231 case BRIDGE_OV518:
3232 case BRIDGE_OV518PLUS:
3233 ov518_configure(gspca_dev);
3234 break;
3235 case BRIDGE_OV519:
3236 ov519_configure(sd);
3237 break;
3238 case BRIDGE_OVFX2:
3239 ovfx2_configure(sd);
3240 break;
3241 case BRIDGE_W9968CF:
3242 w9968cf_configure(sd);
3243 break;
3244 }
6a7eba24 3245
6a7eba24
JFM		 3246 /* The OV519 must be more aggressive about sensor detection since
3247 * I2C write will never fail if the sensor is not present. We have
3248 * to try to initialize the sensor to detect its presence */
7bbe6b8d 3249 sd->sensor = -1;
229bb7dc
HG		 3250
3251 /* Test for 76xx */
3252 if (init_ov_sensor(sd, OV7xx0_SID) >= 0) {
f8f20188
JFM		 3253 ov7xx0_configure(sd);
3254
229bb7dc
HG		 3255 /* Test for 6xx0 */
3256 } else if (init_ov_sensor(sd, OV6xx0_SID) >= 0) {
f8f20188
JFM		 3257 ov6xx0_configure(sd);
3258
229bb7dc
HG		 3259 /* Test for 8xx0 */
3260 } else if (init_ov_sensor(sd, OV8xx0_SID) >= 0) {
f8f20188
JFM		 3261 ov8xx0_configure(sd);
3262
635118d5
HG		 3263 /* Test for 3xxx / 2xxx */
3264 } else if (init_ov_sensor(sd, OV_HIRES_SID) >= 0) {
f8f20188 3265 ov_hires_configure(sd);
229bb7dc 3266 } else {
0b656321 3267 err("Can't determine sensor slave IDs");
229bb7dc 3268 goto error;
6a7eba24
JFM		 3269 }
3270
7bbe6b8d
JFM		 3271 if (sd->sensor < 0)
3272 goto error;
3273
7491f785
JFM		 3274 ov51x_led_control(sd, 0); /* turn LED off */
3275
49809d6a 3276 switch (sd->bridge) {
1876bb92
HG		 3277 case BRIDGE_OV511:
3278 case BRIDGE_OV511PLUS:
7491f785 3279 if (sd->sif) {
1876bb92
HG		 3280 cam->cam_mode = ov511_sif_mode;
3281 cam->nmodes = ARRAY_SIZE(ov511_sif_mode);
3282 }
3283 break;
49809d6a
HG		 3284 case BRIDGE_OV518:
3285 case BRIDGE_OV518PLUS:
7491f785 3286 if (sd->sif) {
49809d6a
HG		 3287 cam->cam_mode = ov518_sif_mode;
3288 cam->nmodes = ARRAY_SIZE(ov518_sif_mode);
3289 }
3290 break;
3291 case BRIDGE_OV519:
7491f785 3292 if (sd->sif) {
49809d6a
HG		 3293 cam->cam_mode = ov519_sif_mode;
3294 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3295 }
3296 break;
635118d5
HG		 3297 case BRIDGE_OVFX2:
3298 if (sd->sensor == SEN_OV2610) {
3299 cam->cam_mode = ovfx2_ov2610_mode;
3300 cam->nmodes = ARRAY_SIZE(ovfx2_ov2610_mode);
3301 } else if (sd->sensor == SEN_OV3610) {
3302 cam->cam_mode = ovfx2_ov3610_mode;
3303 cam->nmodes = ARRAY_SIZE(ovfx2_ov3610_mode);
7491f785 3304 } else if (sd->sif) {
635118d5
HG		 3305 cam->cam_mode = ov519_sif_mode;
3306 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3307 }
3308 break;
a511ba94 3309 case BRIDGE_W9968CF:
79b35902 3310 if (sd->sif)
7491f785 3311 cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode) - 1;
a511ba94
HG		 3312
3313 /* w9968cf needs initialisation once the sensor is known */
f8f20188 3314 w9968cf_init(sd);
a511ba94 3315 break;
6a7eba24 3316 }
83db7688
JFM		 3317
3318 gspca_dev->ctrl_dis = ctrl_dis[sd->sensor];
02ab18b0 3319
4202f71c
JFM		 3320 /* initialize the sensor */
3321 switch (sd->sensor) {
635118d5 3322 case SEN_OV2610:
f8f20188
JFM		 3323 write_i2c_regvals(sd, norm_2610, ARRAY_SIZE(norm_2610));
3324
635118d5 3325 /* Enable autogain, autoexpo, awb, bandfilter */
f8f20188 3326 i2c_w_mask(sd, 0x13, 0x27, 0x27);
635118d5
HG		 3327 break;
3328 case SEN_OV3610:
f8f20188
JFM		 3329 write_i2c_regvals(sd, norm_3620b, ARRAY_SIZE(norm_3620b));
3330
635118d5 3331 /* Enable autogain, autoexpo, awb, bandfilter */
f8f20188 3332 i2c_w_mask(sd, 0x13, 0x27, 0x27);
635118d5 3333 break;
4202f71c 3334 case SEN_OV6620:
f8f20188 3335 write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20));
4202f71c
JFM		 3336 break;
3337 case SEN_OV6630:
7d971373 3338 case SEN_OV66308AF:
62833acd
JFM		 3339 sd->ctrls[CONTRAST].def = 200;
3340 /* The default is too low for the ov6630 */
f8f20188 3341 write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30));
4202f71c
JFM		 3342 break;
3343 default:
3344/* case SEN_OV7610: */
3345/* case SEN_OV76BE: */
f8f20188
JFM		 3346 write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610));
3347 i2c_w_mask(sd, 0x0e, 0x00, 0x40);
4202f71c
JFM		 3348 break;
3349 case SEN_OV7620:
859cc470 3350 case SEN_OV7620AE:
f8f20188 3351 write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620));
4202f71c
JFM		 3352 break;
3353 case SEN_OV7640:
035d3a3d 3354 case SEN_OV7648:
f8f20188 3355 write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640));
4202f71c 3356 break;
42e142f6
JFM		 3357 case SEN_OV7660:
3358 i2c_w(sd, OV7670_R12_COM7, OV7670_COM7_RESET);
3359 msleep(14);
3360 reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
3361 write_regvals(sd, init_519_ov7660,
3362 ARRAY_SIZE(init_519_ov7660));
3363 write_i2c_regvals(sd, norm_7660, ARRAY_SIZE(norm_7660));
3364 sd->gspca_dev.curr_mode = 1; /* 640x480 */
3365 sd->frame_rate = 15;
3366 ov519_set_mode(sd);
3367 ov519_set_fr(sd);
3368 sd->ctrls[COLORS].max = 4; /* 0..4 */
3369 sd->ctrls[COLORS].val =
3370 sd->ctrls[COLORS].def = 2;
3371 setcolors(gspca_dev);
3372 sd->ctrls[CONTRAST].max = 6; /* 0..6 */
3373 sd->ctrls[CONTRAST].val =
3374 sd->ctrls[CONTRAST].def = 3;
3375 setcontrast(gspca_dev);
3376 sd->ctrls[BRIGHTNESS].max = 6; /* 0..6 */
3377 sd->ctrls[BRIGHTNESS].val =
3378 sd->ctrls[BRIGHTNESS].def = 3;
3379 setbrightness(gspca_dev);
3380 sd_reset_snapshot(gspca_dev);
3381 ov51x_restart(sd);
3382 ov51x_stop(sd); /* not in win traces */
3383 ov51x_led_control(sd, 0);
3384 break;
4202f71c 3385 case SEN_OV7670:
62833acd
JFM		 3386 sd->ctrls[FREQ].max = 3; /* auto */
3387 sd->ctrls[FREQ].def = 3;
f8f20188 3388 write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670));
4202f71c
JFM		 3389 break;
3390 case SEN_OV8610:
f8f20188 3391 write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610));
4202f71c
JFM		 3392 break;
3393 }
f8f20188 3394 return gspca_dev->usb_err;
7491f785
JFM		 3395error:
3396 PDEBUG(D_ERR, "OV519 Config failed");
3397 return -EINVAL;
6a7eba24
JFM		 3398}
3399
1876bb92
HG		 3400/* Set up the OV511/OV511+ with the given image parameters.
3401 *
3402 * Do not put any sensor-specific code in here (including I2C I/O functions)
3403 */
f8f20188 3404static void ov511_mode_init_regs(struct sd *sd)
1876bb92
HG		 3405{
3406 int hsegs, vsegs, packet_size, fps, needed;
3407 int interlaced = 0;
3408 struct usb_host_interface *alt;
3409 struct usb_interface *intf;
3410
3411 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3412 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3413 if (!alt) {
0b656321 3414 err("Couldn't get altsetting");
f8f20188
JFM		 3415 sd->gspca_dev.usb_err = -EIO;
3416 return;
1876bb92
HG		 3417 }
3418
3419 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3420 reg_w(sd, R51x_FIFO_PSIZE, packet_size >> 5);
3421
3422 reg_w(sd, R511_CAM_UV_EN, 0x01);
3423 reg_w(sd, R511_SNAP_UV_EN, 0x01);
3424 reg_w(sd, R511_SNAP_OPTS, 0x03);
3425
3426 /* Here I'm assuming that snapshot size == image size.
3427 * I hope that's always true. --claudio
3428 */
3429 hsegs = (sd->gspca_dev.width >> 3) - 1;
3430 vsegs = (sd->gspca_dev.height >> 3) - 1;
3431
3432 reg_w(sd, R511_CAM_PXCNT, hsegs);
3433 reg_w(sd, R511_CAM_LNCNT, vsegs);
3434 reg_w(sd, R511_CAM_PXDIV, 0x00);
3435 reg_w(sd, R511_CAM_LNDIV, 0x00);
3436
3437 /* YUV420, low pass filter on */
3438 reg_w(sd, R511_CAM_OPTS, 0x03);
3439
3440 /* Snapshot additions */
3441 reg_w(sd, R511_SNAP_PXCNT, hsegs);
3442 reg_w(sd, R511_SNAP_LNCNT, vsegs);
3443 reg_w(sd, R511_SNAP_PXDIV, 0x00);
3444 reg_w(sd, R511_SNAP_LNDIV, 0x00);
3445
3446 /******** Set the framerate ********/
3447 if (frame_rate > 0)
3448 sd->frame_rate = frame_rate;
3449
3450 switch (sd->sensor) {
3451 case SEN_OV6620:
3452 /* No framerate control, doesn't like higher rates yet */
3453 sd->clockdiv = 3;
3454 break;
3455
3456 /* Note once the FIXME's in mode_init_ov_sensor_regs() are fixed
3457 for more sensors we need to do this for them too */
3458 case SEN_OV7620:
859cc470 3459 case SEN_OV7620AE:
1876bb92 3460 case SEN_OV7640:
035d3a3d 3461 case SEN_OV7648:
b282d873 3462 case SEN_OV76BE:
1876bb92
HG		 3463 if (sd->gspca_dev.width == 320)
3464 interlaced = 1;
3465 /* Fall through */
3466 case SEN_OV6630:
1876bb92
HG		 3467 case SEN_OV7610:
3468 case SEN_OV7670:
3469 switch (sd->frame_rate) {
3470 case 30:
3471 case 25:
3472 /* Not enough bandwidth to do 640x480 @ 30 fps */
3473 if (sd->gspca_dev.width != 640) {
3474 sd->clockdiv = 0;
3475 break;
3476 }
3477 /* Fall through for 640x480 case */
3478 default:
3479/* case 20: */
3480/* case 15: */
3481 sd->clockdiv = 1;
3482 break;
3483 case 10:
3484 sd->clockdiv = 2;
3485 break;
3486 case 5:
3487 sd->clockdiv = 5;
3488 break;
3489 }
3490 if (interlaced) {
3491 sd->clockdiv = (sd->clockdiv + 1) * 2 - 1;
3492 /* Higher then 10 does not work */
3493 if (sd->clockdiv > 10)
3494 sd->clockdiv = 10;
3495 }
3496 break;
3497
3498 case SEN_OV8610:
3499 /* No framerate control ?? */
3500 sd->clockdiv = 0;
3501 break;
3502 }
3503
3504 /* Check if we have enough bandwidth to disable compression */
3505 fps = (interlaced ? 60 : 30) / (sd->clockdiv + 1) + 1;
3506 needed = fps * sd->gspca_dev.width * sd->gspca_dev.height * 3 / 2;
3507 /* 1400 is a conservative estimate of the max nr of isoc packets/sec */
3508 if (needed > 1400 * packet_size) {
3509 /* Enable Y and UV quantization and compression */
3510 reg_w(sd, R511_COMP_EN, 0x07);
3511 reg_w(sd, R511_COMP_LUT_EN, 0x03);
3512 } else {
3513 reg_w(sd, R511_COMP_EN, 0x06);
3514 reg_w(sd, R511_COMP_LUT_EN, 0x00);
3515 }
3516
3517 reg_w(sd, R51x_SYS_RESET, OV511_RESET_OMNICE);
3518 reg_w(sd, R51x_SYS_RESET, 0);
1876bb92
HG		 3519}
3520
49809d6a
HG		 3521/* Sets up the OV518/OV518+ with the given image parameters
3522 *
3523 * OV518 needs a completely different approach, until we can figure out what
3524 * the individual registers do. Also, only 15 FPS is supported now.
3525 *
3526 * Do not put any sensor-specific code in here (including I2C I/O functions)
3527 */
f8f20188 3528static void ov518_mode_init_regs(struct sd *sd)
49809d6a 3529{
b282d873
HG		 3530 int hsegs, vsegs, packet_size;
3531 struct usb_host_interface *alt;
3532 struct usb_interface *intf;
3533
3534 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3535 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3536 if (!alt) {
0b656321 3537 err("Couldn't get altsetting");
f8f20188
JFM		 3538 sd->gspca_dev.usb_err = -EIO;
3539 return;
b282d873
HG		 3540 }
3541
3542 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3543 ov518_reg_w32(sd, R51x_FIFO_PSIZE, packet_size & ~7, 2);
49809d6a
HG		 3544
3545 /******** Set the mode ********/
49809d6a
HG		 3546 reg_w(sd, 0x2b, 0);
3547 reg_w(sd, 0x2c, 0);
3548 reg_w(sd, 0x2d, 0);
3549 reg_w(sd, 0x2e, 0);
3550 reg_w(sd, 0x3b, 0);
3551 reg_w(sd, 0x3c, 0);
3552 reg_w(sd, 0x3d, 0);
3553 reg_w(sd, 0x3e, 0);
3554
3555 if (sd->bridge == BRIDGE_OV518) {
3556 /* Set 8-bit (YVYU) input format */
3557 reg_w_mask(sd, 0x20, 0x08, 0x08);
3558
3559 /* Set 12-bit (4:2:0) output format */
3560 reg_w_mask(sd, 0x28, 0x80, 0xf0);
3561 reg_w_mask(sd, 0x38, 0x80, 0xf0);
3562 } else {
3563 reg_w(sd, 0x28, 0x80);
3564 reg_w(sd, 0x38, 0x80);
3565 }
3566
3567 hsegs = sd->gspca_dev.width / 16;
3568 vsegs = sd->gspca_dev.height / 4;
3569
3570 reg_w(sd, 0x29, hsegs);
3571 reg_w(sd, 0x2a, vsegs);
3572
3573 reg_w(sd, 0x39, hsegs);
3574 reg_w(sd, 0x3a, vsegs);
3575
3576 /* Windows driver does this here; who knows why */
3577 reg_w(sd, 0x2f, 0x80);
3578
87bae740 3579 /******** Set the framerate ********/
b282d873 3580 sd->clockdiv = 1;
49809d6a
HG		 3581
3582 /* Mode independent, but framerate dependent, regs */
b282d873
HG		 3583 /* 0x51: Clock divider; Only works on some cams which use 2 crystals */
3584 reg_w(sd, 0x51, 0x04);
49809d6a
HG		 3585 reg_w(sd, 0x22, 0x18);
3586 reg_w(sd, 0x23, 0xff);
3587
b282d873
HG		 3588 if (sd->bridge == BRIDGE_OV518PLUS) {
3589 switch (sd->sensor) {
859cc470 3590 case SEN_OV7620AE:
b282d873
HG		 3591 if (sd->gspca_dev.width == 320) {
3592 reg_w(sd, 0x20, 0x00);
3593 reg_w(sd, 0x21, 0x19);
3594 } else {
3595 reg_w(sd, 0x20, 0x60);
3596 reg_w(sd, 0x21, 0x1f);
3597 }
3598 break;
859cc470
HG		 3599 case SEN_OV7620:
3600 reg_w(sd, 0x20, 0x00);
3601 reg_w(sd, 0x21, 0x19);
3602 break;
b282d873
HG		 3603 default:
3604 reg_w(sd, 0x21, 0x19);
3605 }
3606 } else
49809d6a
HG		 3607 reg_w(sd, 0x71, 0x17); /* Compression-related? */
3608
3609 /* FIXME: Sensor-specific */
3610 /* Bit 5 is what matters here. Of course, it is "reserved" */
3611 i2c_w(sd, 0x54, 0x23);
3612
3613 reg_w(sd, 0x2f, 0x80);
3614
3615 if (sd->bridge == BRIDGE_OV518PLUS) {
3616 reg_w(sd, 0x24, 0x94);
3617 reg_w(sd, 0x25, 0x90);
3618 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3619 ov518_reg_w32(sd, 0xc6, 540, 2); /* 21ch */
3620 ov518_reg_w32(sd, 0xc7, 540, 2); /* 21ch */
3621 ov518_reg_w32(sd, 0xc8, 108, 2); /* 6ch */
3622 ov518_reg_w32(sd, 0xca, 131098, 3); /* 2001ah */
3623 ov518_reg_w32(sd, 0xcb, 532, 2); /* 214h */
3624 ov518_reg_w32(sd, 0xcc, 2400, 2); /* 960h */
3625 ov518_reg_w32(sd, 0xcd, 32, 2); /* 20h */
3626 ov518_reg_w32(sd, 0xce, 608, 2); /* 260h */
3627 } else {
3628 reg_w(sd, 0x24, 0x9f);
3629 reg_w(sd, 0x25, 0x90);
3630 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3631 ov518_reg_w32(sd, 0xc6, 381, 2); /* 17dh */
3632 ov518_reg_w32(sd, 0xc7, 381, 2); /* 17dh */
3633 ov518_reg_w32(sd, 0xc8, 128, 2); /* 80h */
3634 ov518_reg_w32(sd, 0xca, 183331, 3); /* 2cc23h */
3635 ov518_reg_w32(sd, 0xcb, 746, 2); /* 2eah */
3636 ov518_reg_w32(sd, 0xcc, 1750, 2); /* 6d6h */
3637 ov518_reg_w32(sd, 0xcd, 45, 2); /* 2dh */
3638 ov518_reg_w32(sd, 0xce, 851, 2); /* 353h */
3639 }
3640
3641 reg_w(sd, 0x2f, 0x80);
49809d6a
HG		 3642}
3643
6a7eba24
JFM		 3644/* Sets up the OV519 with the given image parameters
3645 *
3646 * OV519 needs a completely different approach, until we can figure out what
3647 * the individual registers do.
3648 *
3649 * Do not put any sensor-specific code in here (including I2C I/O functions)
3650 */
f8f20188 3651static void ov519_mode_init_regs(struct sd *sd)
6a7eba24 3652{
a5ae2062 3653 static const struct ov_regvals mode_init_519_ov7670[] = {
6a7eba24
JFM		 3654 { 0x5d, 0x03 }, /* Turn off suspend mode */
3655 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
21867803 3656 { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
6a7eba24
JFM		 3657 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3658 { 0xa3, 0x18 },
3659 { 0xa4, 0x04 },
3660 { 0xa5, 0x28 },
3661 { 0x37, 0x00 }, /* SetUsbInit */
3662 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3663 /* Enable both fields, YUV Input, disable defect comp (why?) */
3664 { 0x20, 0x0c },
3665 { 0x21, 0x38 },
3666 { 0x22, 0x1d },
3667 { 0x17, 0x50 }, /* undocumented */
3668 { 0x37, 0x00 }, /* undocumented */
3669 { 0x40, 0xff }, /* I2C timeout counter */
3670 { 0x46, 0x00 }, /* I2C clock prescaler */
3671 { 0x59, 0x04 }, /* new from windrv 090403 */
3672 { 0xff, 0x00 }, /* undocumented */
3673 /* windows reads 0x55 at this point, why? */
3674 };
3675
a5ae2062 3676 static const struct ov_regvals mode_init_519[] = {
6a7eba24
JFM		 3677 { 0x5d, 0x03 }, /* Turn off suspend mode */
3678 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
21867803 3679 { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
6a7eba24
JFM		 3680 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3681 { 0xa3, 0x18 },
3682 { 0xa4, 0x04 },
3683 { 0xa5, 0x28 },
3684 { 0x37, 0x00 }, /* SetUsbInit */
3685 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3686 /* Enable both fields, YUV Input, disable defect comp (why?) */
3687 { 0x22, 0x1d },
3688 { 0x17, 0x50 }, /* undocumented */
3689 { 0x37, 0x00 }, /* undocumented */
3690 { 0x40, 0xff }, /* I2C timeout counter */
3691 { 0x46, 0x00 }, /* I2C clock prescaler */
3692 { 0x59, 0x04 }, /* new from windrv 090403 */
3693 { 0xff, 0x00 }, /* undocumented */
3694 /* windows reads 0x55 at this point, why? */
3695 };
3696
6a7eba24 3697 /******** Set the mode ********/
42e142f6
JFM		 3698 switch (sd->sensor) {
3699 default:
f8f20188 3700 write_regvals(sd, mode_init_519, ARRAY_SIZE(mode_init_519));
035d3a3d
HG		 3701 if (sd->sensor == SEN_OV7640 ||
3702 sd->sensor == SEN_OV7648) {
594f5b8b 3703 /* Select 8-bit input mode */
ac40b1fa 3704 reg_w_mask(sd, OV519_R20_DFR, 0x10, 0x10);
594f5b8b 3705 }
42e142f6
JFM		 3706 break;
3707 case SEN_OV7660:
3708 return; /* done by ov519_set_mode/fr() */
3709 case SEN_OV7670:
f8f20188
JFM		 3710 write_regvals(sd, mode_init_519_ov7670,
3711 ARRAY_SIZE(mode_init_519_ov7670));
42e142f6 3712 break;
6a7eba24
JFM		 3713 }
3714
ac40b1fa
JFM		 3715 reg_w(sd, OV519_R10_H_SIZE, sd->gspca_dev.width >> 4);
3716 reg_w(sd, OV519_R11_V_SIZE, sd->gspca_dev.height >> 3);
80142efa
HG		 3717 if (sd->sensor == SEN_OV7670 &&
3718 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3719 reg_w(sd, OV519_R12_X_OFFSETL, 0x04);
035d3a3d
HG		 3720 else if (sd->sensor == SEN_OV7648 &&
3721 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3722 reg_w(sd, OV519_R12_X_OFFSETL, 0x01);
80142efa
HG		 3723 else
3724 reg_w(sd, OV519_R12_X_OFFSETL, 0x00);
ac40b1fa
JFM		 3725 reg_w(sd, OV519_R13_X_OFFSETH, 0x00);
3726 reg_w(sd, OV519_R14_Y_OFFSETL, 0x00);
3727 reg_w(sd, OV519_R15_Y_OFFSETH, 0x00);
3728 reg_w(sd, OV519_R16_DIVIDER, 0x00);
3729 reg_w(sd, OV519_R25_FORMAT, 0x03); /* YUV422 */
6a7eba24
JFM		 3730 reg_w(sd, 0x26, 0x00); /* Undocumented */
3731
3732 /******** Set the framerate ********/
3733 if (frame_rate > 0)
3734 sd->frame_rate = frame_rate;
3735
3736/* FIXME: These are only valid at the max resolution. */
3737 sd->clockdiv = 0;
594f5b8b
JFM		 3738 switch (sd->sensor) {
3739 case SEN_OV7640:
035d3a3d 3740 case SEN_OV7648:
6a7eba24 3741 switch (sd->frame_rate) {
53e74515
JFM		 3742 default:
3743/* case 30: */
6a7eba24
JFM		 3744 reg_w(sd, 0xa4, 0x0c);
3745 reg_w(sd, 0x23, 0xff);
3746 break;
3747 case 25:
3748 reg_w(sd, 0xa4, 0x0c);
3749 reg_w(sd, 0x23, 0x1f);
3750 break;
3751 case 20:
3752 reg_w(sd, 0xa4, 0x0c);
3753 reg_w(sd, 0x23, 0x1b);
3754 break;
53e74515 3755 case 15:
6a7eba24
JFM		 3756 reg_w(sd, 0xa4, 0x04);
3757 reg_w(sd, 0x23, 0xff);
3758 sd->clockdiv = 1;
3759 break;
3760 case 10:
3761 reg_w(sd, 0xa4, 0x04);
3762 reg_w(sd, 0x23, 0x1f);
3763 sd->clockdiv = 1;
3764 break;
3765 case 5:
3766 reg_w(sd, 0xa4, 0x04);
3767 reg_w(sd, 0x23, 0x1b);
3768 sd->clockdiv = 1;
3769 break;
3770 }
594f5b8b
JFM		 3771 break;
3772 case SEN_OV8610:
6a7eba24
JFM		 3773 switch (sd->frame_rate) {
3774 default: /* 15 fps */
3775/* case 15: */
3776 reg_w(sd, 0xa4, 0x06);
3777 reg_w(sd, 0x23, 0xff);
3778 break;
3779 case 10:
3780 reg_w(sd, 0xa4, 0x06);
3781 reg_w(sd, 0x23, 0x1f);
3782 break;
3783 case 5:
3784 reg_w(sd, 0xa4, 0x06);
3785 reg_w(sd, 0x23, 0x1b);
3786 break;
3787 }
594f5b8b
JFM		 3788 break;
3789 case SEN_OV7670: /* guesses, based on 7640 */
6a7eba24
JFM		 3790 PDEBUG(D_STREAM, "Setting framerate to %d fps",
3791 (sd->frame_rate == 0) ? 15 : sd->frame_rate);
594f5b8b 3792 reg_w(sd, 0xa4, 0x10);
6a7eba24
JFM		 3793 switch (sd->frame_rate) {
3794 case 30:
6a7eba24
JFM		 3795 reg_w(sd, 0x23, 0xff);
3796 break;
3797 case 20:
6a7eba24
JFM		 3798 reg_w(sd, 0x23, 0x1b);
3799 break;
594f5b8b
JFM		 3800 default:
3801/* case 15: */
6a7eba24
JFM		 3802 reg_w(sd, 0x23, 0xff);
3803 sd->clockdiv = 1;
3804 break;
3805 }
594f5b8b 3806 break;
6a7eba24 3807 }
6a7eba24
JFM		 3808}
3809
f8f20188 3810static void mode_init_ov_sensor_regs(struct sd *sd)
6a7eba24 3811{
594f5b8b 3812 struct gspca_dev *gspca_dev;
ebbb5c3e 3813 int qvga, xstart, xend, ystart, yend;
9d1593a8 3814 u8 v;
594f5b8b
JFM		 3815
3816 gspca_dev = &sd->gspca_dev;
87bae740 3817 qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
6a7eba24
JFM		 3818
3819 /******** Mode (VGA/QVGA) and sensor specific regs ********/
3820 switch (sd->sensor) {
635118d5
HG		 3821 case SEN_OV2610:
3822 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3823 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3824 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3825 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3826 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
3827 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
3828 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
f8f20188 3829 return;
ebbb5c3e 3830 case SEN_OV3610:
635118d5
HG		 3831 if (qvga) {
3832 xstart = (1040 - gspca_dev->width) / 2 + (0x1f << 4);
b46aaa02 3833 ystart = (776 - gspca_dev->height) / 2;
635118d5 3834 } else {
b46aaa02 3835 xstart = (2076 - gspca_dev->width) / 2 + (0x10 << 4);
635118d5
HG		 3836 ystart = (1544 - gspca_dev->height) / 2;
3837 }
3838 xend = xstart + gspca_dev->width;
3839 yend = ystart + gspca_dev->height;
3840 /* Writing to the COMH register resets the other windowing regs
3841 to their default values, so we must do this first. */
3842 i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0xf0);
3843 i2c_w_mask(sd, 0x32,
3844 (((xend >> 1) & 7) << 3) | ((xstart >> 1) & 7),
3845 0x3f);
3846 i2c_w_mask(sd, 0x03,
3847 (((yend >> 1) & 3) << 2) | ((ystart >> 1) & 3),
3848 0x0f);
3849 i2c_w(sd, 0x17, xstart >> 4);
3850 i2c_w(sd, 0x18, xend >> 4);
3851 i2c_w(sd, 0x19, ystart >> 3);
3852 i2c_w(sd, 0x1a, yend >> 3);
f8f20188 3853 return;
6a7eba24
JFM		 3854 case SEN_OV8610:
3855 /* For OV8610 qvga means qsvga */
3856 i2c_w_mask(sd, OV7610_REG_COM_C, qvga ? (1 << 5) : 0, 1 << 5);
ebbb5c3e
HG		 3857 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3858 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3859 i2c_w_mask(sd, 0x2d, 0x00, 0x40); /* from windrv 090403 */
3860 i2c_w_mask(sd, 0x28, 0x20, 0x20); /* progressive mode on */
6a7eba24
JFM		 3861 break;
3862 case SEN_OV7610:
3863 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
780e3121 3864 i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
ebbb5c3e
HG		 3865 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3866 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3867 break;
3868 case SEN_OV7620:
859cc470 3869 case SEN_OV7620AE:
b282d873 3870 case SEN_OV76BE:
6a7eba24
JFM		 3871 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3872 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3873 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3874 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3875 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
b282d873 3876 i2c_w_mask(sd, 0x67, qvga ? 0xb0 : 0x90, 0xf0);
6a7eba24 3877 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e
HG		 3878 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3879 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3880 if (sd->sensor == SEN_OV76BE)
3881 i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
6a7eba24 3882 break;
6a7eba24 3883 case SEN_OV7640:
035d3a3d 3884 case SEN_OV7648:
6a7eba24
JFM		 3885 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3886 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
8d0082fa
HG		 3887 /* Setting this undocumented bit in qvga mode removes a very
3888 annoying vertical shaking of the image */
035d3a3d 3889 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
8d0082fa 3890 /* Unknown */
035d3a3d 3891 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
8d0082fa 3892 /* Allow higher automatic gain (to allow higher framerates) */
035d3a3d 3893 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3894 i2c_w_mask(sd, 0x12, 0x04, 0x04); /* AWB: 1 */
6a7eba24
JFM		 3895 break;
3896 case SEN_OV7670:
3897 /* set COM7_FMT_VGA or COM7_FMT_QVGA
3898 * do we need to set anything else?
3899 * HSTART etc are set in set_ov_sensor_window itself */
21867803 3900 i2c_w_mask(sd, OV7670_R12_COM7,
6a7eba24
JFM		 3901 qvga ? OV7670_COM7_FMT_QVGA : OV7670_COM7_FMT_VGA,
3902 OV7670_COM7_FMT_MASK);
ebbb5c3e 3903 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
21867803 3904 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_AWB,
ebbb5c3e
HG		 3905 OV7670_COM8_AWB);
3906 if (qvga) { /* QVGA from ov7670.c by
3907 * Jonathan Corbet */
3908 xstart = 164;
3909 xend = 28;
3910 ystart = 14;
3911 yend = 494;
3912 } else { /* VGA */
3913 xstart = 158;
3914 xend = 14;
3915 ystart = 10;
3916 yend = 490;
3917 }
3918 /* OV7670 hardware window registers are split across
3919 * multiple locations */
21867803
JFM		 3920 i2c_w(sd, OV7670_R17_HSTART, xstart >> 3);
3921 i2c_w(sd, OV7670_R18_HSTOP, xend >> 3);
3922 v = i2c_r(sd, OV7670_R32_HREF);
ebbb5c3e
HG		 3923 v = (v & 0xc0) | ((xend & 0x7) << 3) | (xstart & 0x07);
3924 msleep(10); /* need to sleep between read and write to
3925 * same reg! */
21867803 3926 i2c_w(sd, OV7670_R32_HREF, v);
ebbb5c3e 3927
21867803
JFM		 3928 i2c_w(sd, OV7670_R19_VSTART, ystart >> 2);
3929 i2c_w(sd, OV7670_R1A_VSTOP, yend >> 2);
3930 v = i2c_r(sd, OV7670_R03_VREF);
ebbb5c3e
HG		 3931 v = (v & 0xc0) | ((yend & 0x3) << 2) | (ystart & 0x03);
3932 msleep(10); /* need to sleep between read and write to
3933 * same reg! */
21867803 3934 i2c_w(sd, OV7670_R03_VREF, v);
6a7eba24
JFM		 3935 break;
3936 case SEN_OV6620:
ebbb5c3e
HG		 3937 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3938 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3939 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3940 break;
6a7eba24 3941 case SEN_OV6630:
7d971373 3942 case SEN_OV66308AF:
6a7eba24 3943 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3944 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3945 break;
3946 default:
f8f20188 3947 return;
6a7eba24
JFM		 3948 }
3949
6a7eba24 3950 /******** Clock programming ********/
ae49c404 3951 i2c_w(sd, 0x11, sd->clockdiv);
6a7eba24
JFM		 3952}
3953
42e142f6 3954/* this function works for bridge ov519 and sensors ov7660 and ov7670 only */
62833acd 3955static void sethvflip(struct gspca_dev *gspca_dev)
0cd6759d 3956{
62833acd
JFM		 3957 struct sd *sd = (struct sd *) gspca_dev;
3958
0cd6759d 3959 if (sd->gspca_dev.streaming)
5927abcb 3960 reg_w(sd, OV519_R51_RESET1, 0x0f); /* block stream */
21867803 3961 i2c_w_mask(sd, OV7670_R1E_MVFP,
62833acd
JFM		 3962 OV7670_MVFP_MIRROR * sd->ctrls[HFLIP].val
3963 | OV7670_MVFP_VFLIP * sd->ctrls[VFLIP].val,
594f5b8b 3964 OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP);
0cd6759d 3965 if (sd->gspca_dev.streaming)
5927abcb 3966 reg_w(sd, OV519_R51_RESET1, 0x00); /* restart stream */
0cd6759d
JFM		 3967}
3968
f8f20188 3969static void set_ov_sensor_window(struct sd *sd)
6a7eba24 3970{
594f5b8b 3971 struct gspca_dev *gspca_dev;
124cc9c0 3972 int qvga, crop;
6a7eba24 3973 int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;
6a7eba24 3974
635118d5 3975 /* mode setup is fully handled in mode_init_ov_sensor_regs for these */
42e142f6
JFM		 3976 switch (sd->sensor) {
3977 case SEN_OV2610:
3978 case SEN_OV3610:
3979 case SEN_OV7670:
f8f20188
JFM		 3980 mode_init_ov_sensor_regs(sd);
3981 return;
42e142f6
JFM		 3982 case SEN_OV7660:
3983 ov519_set_mode(sd);
3984 ov519_set_fr(sd);
3985 return;
f8f20188 3986 }
42e142f6 3987
594f5b8b 3988 gspca_dev = &sd->gspca_dev;
87bae740
JFM		 3989 qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
3990 crop = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 2;
594f5b8b 3991
6a7eba24
JFM		 3992 /* The different sensor ICs handle setting up of window differently.
3993 * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */
3994 switch (sd->sensor) {
3995 case SEN_OV8610:
3996 hwsbase = 0x1e;
3997 hwebase = 0x1e;
3998 vwsbase = 0x02;
3999 vwebase = 0x02;
4000 break;
4001 case SEN_OV7610:
4002 case SEN_OV76BE:
4003 hwsbase = 0x38;
4004 hwebase = 0x3a;
4005 vwsbase = vwebase = 0x05;
4006 break;
4007 case SEN_OV6620:
4008 case SEN_OV6630:
7d971373 4009 case SEN_OV66308AF:
6a7eba24
JFM		 4010 hwsbase = 0x38;
4011 hwebase = 0x3a;
4012 vwsbase = 0x05;
4013 vwebase = 0x06;
7d971373 4014 if (sd->sensor == SEN_OV66308AF && qvga)
49809d6a 4015 /* HDG: this fixes U and V getting swapped */
7d971373 4016 hwsbase++;
124cc9c0
HG		 4017 if (crop) {
4018 hwsbase += 8;
4019 hwebase += 8;
4020 vwsbase += 11;
4021 vwebase += 11;
4022 }
6a7eba24
JFM		 4023 break;
4024 case SEN_OV7620:
859cc470 4025 case SEN_OV7620AE:
6a7eba24
JFM		 4026 hwsbase = 0x2f; /* From 7620.SET (spec is wrong) */
4027 hwebase = 0x2f;
4028 vwsbase = vwebase = 0x05;
4029 break;
4030 case SEN_OV7640:
035d3a3d 4031 case SEN_OV7648:
6a7eba24
JFM		 4032 hwsbase = 0x1a;
4033 hwebase = 0x1a;
4034 vwsbase = vwebase = 0x03;
4035 break;
6a7eba24 4036 default:
f8f20188 4037 return;
6a7eba24
JFM		 4038 }
4039
4040 switch (sd->sensor) {
4041 case SEN_OV6620:
4042 case SEN_OV6630:
7d971373 4043 case SEN_OV66308AF:
594f5b8b 4044 if (qvga) { /* QCIF */
6a7eba24
JFM		 4045 hwscale = 0;
4046 vwscale = 0;
4047 } else { /* CIF */
4048 hwscale = 1;
4049 vwscale = 1; /* The datasheet says 0;
4050 * it's wrong */
4051 }
4052 break;
4053 case SEN_OV8610:
594f5b8b 4054 if (qvga) { /* QSVGA */
6a7eba24
JFM		 4055 hwscale = 1;
4056 vwscale = 1;
4057 } else { /* SVGA */
4058 hwscale = 2;
4059 vwscale = 2;
4060 }
4061 break;
4062 default: /* SEN_OV7xx0 */
594f5b8b 4063 if (qvga) { /* QVGA */
6a7eba24
JFM		 4064 hwscale = 1;
4065 vwscale = 0;
4066 } else { /* VGA */
4067 hwscale = 2;
4068 vwscale = 1;
4069 }
4070 }
4071
f8f20188 4072 mode_init_ov_sensor_regs(sd);
6a7eba24 4073
ebbb5c3e 4074 i2c_w(sd, 0x17, hwsbase);
a511ba94 4075 i2c_w(sd, 0x18, hwebase + (sd->sensor_width >> hwscale));
ebbb5c3e 4076 i2c_w(sd, 0x19, vwsbase);
a511ba94 4077 i2c_w(sd, 0x1a, vwebase + (sd->sensor_height >> vwscale));
6a7eba24
JFM		 4078}
4079
6a7eba24 4080/* -- start the camera -- */
72ab97ce 4081static int sd_start(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 4082{
4083 struct sd *sd = (struct sd *) gspca_dev;
6a7eba24 4084
a511ba94
HG		 4085 /* Default for most bridges, allow bridge_mode_init_regs to override */
4086 sd->sensor_width = sd->gspca_dev.width;
4087 sd->sensor_height = sd->gspca_dev.height;
4088
49809d6a 4089 switch (sd->bridge) {
1876bb92
HG		 4090 case BRIDGE_OV511:
4091 case BRIDGE_OV511PLUS:
f8f20188 4092 ov511_mode_init_regs(sd);
1876bb92 4093 break;
49809d6a
HG		 4094 case BRIDGE_OV518:
4095 case BRIDGE_OV518PLUS:
f8f20188 4096 ov518_mode_init_regs(sd);
49809d6a
HG		 4097 break;
4098 case BRIDGE_OV519:
f8f20188 4099 ov519_mode_init_regs(sd);
49809d6a 4100 break;
b46aaa02 4101 /* case BRIDGE_OVFX2: nothing to do */
a511ba94 4102 case BRIDGE_W9968CF:
f8f20188 4103 w9968cf_mode_init_regs(sd);
a511ba94 4104 break;
49809d6a 4105 }
49809d6a 4106
f8f20188 4107 set_ov_sensor_window(sd);
6a7eba24 4108
e2817029
JFM		 4109 if (!(sd->gspca_dev.ctrl_dis & (1 << CONTRAST)))
4110 setcontrast(gspca_dev);
4111 if (!(sd->gspca_dev.ctrl_dis & (1 << BRIGHTNESS)))
4112 setbrightness(gspca_dev);
4113 if (!(sd->gspca_dev.ctrl_dis & (1 << COLORS)))
4114 setcolors(gspca_dev);
4115 if (!(sd->gspca_dev.ctrl_dis & ((1 << HFLIP) | (1 << VFLIP))))
4116 sethvflip(gspca_dev);
4117 if (!(sd->gspca_dev.ctrl_dis & (1 << AUTOBRIGHT)))
4118 setautobright(gspca_dev);
4119 if (!(sd->gspca_dev.ctrl_dis & (1 << FREQ)))
4120 setfreq_i(sd);
49809d6a 4121
417a4d26
HG		 4122 /* Force clear snapshot state in case the snapshot button was
4123 pressed while we weren't streaming */
4124 sd->snapshot_needs_reset = 1;
4125 sd_reset_snapshot(gspca_dev);
417a4d26 4126
d6b6d7ae
HG		 4127 sd->first_frame = 3;
4128
f8f20188 4129 ov51x_restart(sd);
6a7eba24 4130 ov51x_led_control(sd, 1);
f8f20188 4131 return gspca_dev->usb_err;
6a7eba24
JFM		 4132}
4133
4134static void sd_stopN(struct gspca_dev *gspca_dev)
4135{
ac40b1fa
JFM		 4136 struct sd *sd = (struct sd *) gspca_dev;
4137
4138 ov51x_stop(sd);
4139 ov51x_led_control(sd, 0);
6a7eba24
JFM		 4140}
4141
79b35902
HG		 4142static void sd_stop0(struct gspca_dev *gspca_dev)
4143{
4144 struct sd *sd = (struct sd *) gspca_dev;
4145
d65174c0
JFM		 4146 if (!sd->gspca_dev.present)
4147 return;
79b35902
HG		 4148 if (sd->bridge == BRIDGE_W9968CF)
4149 w9968cf_stop0(sd);
614d0691 4150
14653e64 4151#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
614d0691
HG		 4152 /* If the last button state is pressed, release it now! */
4153 if (sd->snapshot_pressed) {
4154 input_report_key(gspca_dev->input_dev, KEY_CAMERA, 0);
4155 input_sync(gspca_dev->input_dev);
4156 sd->snapshot_pressed = 0;
4157 }
4158#endif
b4e96ea3
JFM		 4159 if (sd->bridge == BRIDGE_OV519)
4160 reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
79b35902
HG		 4161}
4162
92e232ac
HG		 4163static void ov51x_handle_button(struct gspca_dev *gspca_dev, u8 state)
4164{
4165 struct sd *sd = (struct sd *) gspca_dev;
4166
4167 if (sd->snapshot_pressed != state) {
2856643e 4168#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
92e232ac
HG		 4169 input_report_key(gspca_dev->input_dev, KEY_CAMERA, state);
4170 input_sync(gspca_dev->input_dev);
4171#endif
4172 if (state)
4173 sd->snapshot_needs_reset = 1;
4174
4175 sd->snapshot_pressed = state;
4176 } else {
88e8d20a
HG		 4177 /* On the ov511 / ov519 we need to reset the button state
4178 multiple times, as resetting does not work as long as the
4179 button stays pressed */
4180 switch (sd->bridge) {
4181 case BRIDGE_OV511:
4182 case BRIDGE_OV511PLUS:
4183 case BRIDGE_OV519:
4184 if (state)
4185 sd->snapshot_needs_reset = 1;
4186 break;
4187 }
92e232ac
HG		 4188 }
4189}
4190
1876bb92 4191static void ov511_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b
JFM		 4192 u8 *in, /* isoc packet */
4193 int len) /* iso packet length */
1876bb92
HG		 4194{
4195 struct sd *sd = (struct sd *) gspca_dev;
4196
4197 /* SOF/EOF packets have 1st to 8th bytes zeroed and the 9th
4198 * byte non-zero. The EOF packet has image width/height in the
4199 * 10th and 11th bytes. The 9th byte is given as follows:
4200 *
4201 * bit 7: EOF
4202 * 6: compression enabled
4203 * 5: 422/420/400 modes
4204 * 4: 422/420/400 modes
4205 * 3: 1
4206 * 2: snapshot button on
4207 * 1: snapshot frame
4208 * 0: even/odd field
4209 */
4210 if (!(in[0] | in[1] | in[2] | in[3] | in[4] | in[5] | in[6] | in[7]) &&
4211 (in[8] & 0x08)) {
88e8d20a 4212 ov51x_handle_button(gspca_dev, (in[8] >> 2) & 1);
1876bb92
HG		 4213 if (in[8] & 0x80) {
4214 /* Frame end */
4215 if ((in[9] + 1) * 8 != gspca_dev->width ||
4216 (in[10] + 1) * 8 != gspca_dev->height) {
4217 PDEBUG(D_ERR, "Invalid frame size, got: %dx%d,"
4218 " requested: %dx%d\n",
4219 (in[9] + 1) * 8, (in[10] + 1) * 8,
4220 gspca_dev->width, gspca_dev->height);
4221 gspca_dev->last_packet_type = DISCARD_PACKET;
4222 return;
4223 }
4224 /* Add 11 byte footer to frame, might be usefull */
76dd272b 4225 gspca_frame_add(gspca_dev, LAST_PACKET, in, 11);
1876bb92
HG		 4226 return;
4227 } else {
4228 /* Frame start */
76dd272b 4229 gspca_frame_add(gspca_dev, FIRST_PACKET, in, 0);
1876bb92
HG		 4230 sd->packet_nr = 0;
4231 }
4232 }
4233
4234 /* Ignore the packet number */
4235 len--;
4236
4237 /* intermediate packet */
76dd272b 4238 gspca_frame_add(gspca_dev, INTER_PACKET, in, len);
1876bb92
HG		 4239}
4240
49809d6a 4241static void ov518_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4242 u8 *data, /* isoc packet */
49809d6a
HG		 4243 int len) /* iso packet length */
4244{
92918a53 4245 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 4246
4247 /* A false positive here is likely, until OVT gives me
4248 * the definitive SOF/EOF format */
4249 if ((!(data[0] | data[1] | data[2] | data[3] | data[5])) && data[6]) {
92e232ac 4250 ov51x_handle_button(gspca_dev, (data[6] >> 1) & 1);
76dd272b
JFM		 4251 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
4252 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
92918a53
HG		 4253 sd->packet_nr = 0;
4254 }
4255
4256 if (gspca_dev->last_packet_type == DISCARD_PACKET)
4257 return;
4258
4259 /* Does this device use packet numbers ? */
4260 if (len & 7) {
4261 len--;
4262 if (sd->packet_nr == data[len])
4263 sd->packet_nr++;
4264 /* The last few packets of the frame (which are all 0's
4265 except that they may contain part of the footer), are
4266 numbered 0 */
4267 else if (sd->packet_nr == 0 || data[len]) {
4268 PDEBUG(D_ERR, "Invalid packet nr: %d (expect: %d)",
4269 (int)data[len], (int)sd->packet_nr);
4270 gspca_dev->last_packet_type = DISCARD_PACKET;
4271 return;
4272 }
49809d6a
HG		 4273 }
4274
4275 /* intermediate packet */
76dd272b 4276 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
49809d6a
HG		 4277}
4278
4279static void ov519_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4280 u8 *data, /* isoc packet */
6a7eba24
JFM		 4281 int len) /* iso packet length */
4282{
4283 /* Header of ov519 is 16 bytes:
4284 * Byte Value Description
4285 * 0 0xff magic
4286 * 1 0xff magic
4287 * 2 0xff magic
4288 * 3 0xXX 0x50 = SOF, 0x51 = EOF
4289 * 9 0xXX 0x01 initial frame without data,
4290 * 0x00 standard frame with image
4291 * 14 Lo in EOF: length of image data / 8
4292 * 15 Hi
4293 */
4294
4295 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff) {
4296 switch (data[3]) {
4297 case 0x50: /* start of frame */
417a4d26
HG		 4298 /* Don't check the button state here, as the state
4299 usually (always ?) changes at EOF and checking it
4300 here leads to unnecessary snapshot state resets. */
6a7eba24
JFM		 4301#define HDRSZ 16
4302 data += HDRSZ;
4303 len -= HDRSZ;
4304#undef HDRSZ
4305 if (data[0] == 0xff || data[1] == 0xd8)
76dd272b 4306 gspca_frame_add(gspca_dev, FIRST_PACKET,
6a7eba24
JFM		 4307 data, len);
4308 else
4309 gspca_dev->last_packet_type = DISCARD_PACKET;
4310 return;
4311 case 0x51: /* end of frame */
92e232ac 4312 ov51x_handle_button(gspca_dev, data[11] & 1);
6a7eba24
JFM		 4313 if (data[9] != 0)
4314 gspca_dev->last_packet_type = DISCARD_PACKET;
76dd272b
JFM		 4315 gspca_frame_add(gspca_dev, LAST_PACKET,
4316 NULL, 0);
6a7eba24
JFM		 4317 return;
4318 }
4319 }
4320
4321 /* intermediate packet */
76dd272b 4322 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
6a7eba24
JFM		 4323}
4324
b46aaa02 4325static void ovfx2_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4326 u8 *data, /* isoc packet */
b46aaa02
HG		 4327 int len) /* iso packet length */
4328{
d6b6d7ae 4329 struct sd *sd = (struct sd *) gspca_dev;
d6b6d7ae
HG		 4330
4331 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
4332
b46aaa02
HG		 4333 /* A short read signals EOF */
4334 if (len < OVFX2_BULK_SIZE) {
d6b6d7ae
HG		 4335 /* If the frame is short, and it is one of the first ones
4336 the sensor and bridge are still syncing, so drop it. */
4337 if (sd->first_frame) {
4338 sd->first_frame--;
b192ca98
JFM		 4339 if (gspca_dev->image_len <
4340 sd->gspca_dev.width * sd->gspca_dev.height)
d6b6d7ae
HG		 4341 gspca_dev->last_packet_type = DISCARD_PACKET;
4342 }
4343 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
76dd272b 4344 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
b46aaa02 4345 }
b46aaa02
HG		 4346}
4347
49809d6a 4348static void sd_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4349 u8 *data, /* isoc packet */
49809d6a
HG		 4350 int len) /* iso packet length */
4351{
4352 struct sd *sd = (struct sd *) gspca_dev;
4353
4354 switch (sd->bridge) {
4355 case BRIDGE_OV511:
4356 case BRIDGE_OV511PLUS:
76dd272b 4357 ov511_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4358 break;
4359 case BRIDGE_OV518:
4360 case BRIDGE_OV518PLUS:
76dd272b 4361 ov518_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4362 break;
4363 case BRIDGE_OV519:
76dd272b 4364 ov519_pkt_scan(gspca_dev, data, len);
49809d6a 4365 break;
b46aaa02 4366 case BRIDGE_OVFX2:
76dd272b 4367 ovfx2_pkt_scan(gspca_dev, data, len);
b46aaa02 4368 break;
a511ba94 4369 case BRIDGE_W9968CF:
76dd272b 4370 w9968cf_pkt_scan(gspca_dev, data, len);
a511ba94 4371 break;
49809d6a
HG		 4372 }
4373}
4374
6a7eba24
JFM		 4375/* -- management routines -- */
4376
4377static void setbrightness(struct gspca_dev *gspca_dev)
4378{
4379 struct sd *sd = (struct sd *) gspca_dev;
4380 int val;
42e142f6
JFM		 4381 static const struct ov_i2c_regvals brit_7660[][7] = {
4382 {{0x0f, 0x6a}, {0x24, 0x40}, {0x25, 0x2b}, {0x26, 0x90},
4383 {0x27, 0xe0}, {0x28, 0xe0}, {0x2c, 0xe0}},
4384 {{0x0f, 0x6a}, {0x24, 0x50}, {0x25, 0x40}, {0x26, 0xa1},
4385 {0x27, 0xc0}, {0x28, 0xc0}, {0x2c, 0xc0}},
4386 {{0x0f, 0x6a}, {0x24, 0x68}, {0x25, 0x58}, {0x26, 0xc2},
4387 {0x27, 0xa0}, {0x28, 0xa0}, {0x2c, 0xa0}},
4388 {{0x0f, 0x6a}, {0x24, 0x70}, {0x25, 0x68}, {0x26, 0xd3},
4389 {0x27, 0x80}, {0x28, 0x80}, {0x2c, 0x80}},
4390 {{0x0f, 0x6a}, {0x24, 0x80}, {0x25, 0x70}, {0x26, 0xd3},
4391 {0x27, 0x20}, {0x28, 0x20}, {0x2c, 0x20}},
4392 {{0x0f, 0x6a}, {0x24, 0x88}, {0x25, 0x78}, {0x26, 0xd3},
4393 {0x27, 0x40}, {0x28, 0x40}, {0x2c, 0x40}},
4394 {{0x0f, 0x6a}, {0x24, 0x90}, {0x25, 0x80}, {0x26, 0xd4},
4395 {0x27, 0x60}, {0x28, 0x60}, {0x2c, 0x60}}
4396 };
6a7eba24 4397
62833acd 4398 val = sd->ctrls[BRIGHTNESS].val;
6a7eba24
JFM		 4399 switch (sd->sensor) {
4400 case SEN_OV8610:
4401 case SEN_OV7610:
4402 case SEN_OV76BE:
4403 case SEN_OV6620:
4404 case SEN_OV6630:
7d971373 4405 case SEN_OV66308AF:
6a7eba24 4406 case SEN_OV7640:
035d3a3d 4407 case SEN_OV7648:
6a7eba24
JFM		 4408 i2c_w(sd, OV7610_REG_BRT, val);
4409 break;
4410 case SEN_OV7620:
859cc470 4411 case SEN_OV7620AE:
6a7eba24 4412 /* 7620 doesn't like manual changes when in auto mode */
62833acd 4413 if (!sd->ctrls[AUTOBRIGHT].val)
6a7eba24
JFM		 4414 i2c_w(sd, OV7610_REG_BRT, val);
4415 break;
42e142f6
JFM		 4416 case SEN_OV7660:
4417 write_i2c_regvals(sd, brit_7660[val],
4418 ARRAY_SIZE(brit_7660[0]));
4419 break;
6a7eba24 4420 case SEN_OV7670:
594f5b8b 4421/*win trace
21867803
JFM		 4422 * i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_AEC); */
4423 i2c_w(sd, OV7670_R55_BRIGHT, ov7670_abs_to_sm(val));
6a7eba24
JFM		 4424 break;
4425 }
6a7eba24
JFM		 4426}
4427
4428static void setcontrast(struct gspca_dev *gspca_dev)
4429{
4430 struct sd *sd = (struct sd *) gspca_dev;
4431 int val;
42e142f6
JFM		 4432 static const struct ov_i2c_regvals contrast_7660[][31] = {
4433 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0xa0},
4434 {0x70, 0x58}, {0x71, 0x38}, {0x72, 0x30}, {0x73, 0x30},
4435 {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x24}, {0x77, 0x24},
4436 {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x34},
4437 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x65},
4438 {0x80, 0x70}, {0x81, 0x77}, {0x82, 0x7d}, {0x83, 0x83},
4439 {0x84, 0x88}, {0x85, 0x8d}, {0x86, 0x96}, {0x87, 0x9f},
4440 {0x88, 0xb0}, {0x89, 0xc4}, {0x8a, 0xd9}},
4441 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0x94},
4442 {0x70, 0x58}, {0x71, 0x40}, {0x72, 0x30}, {0x73, 0x30},
4443 {0x74, 0x30}, {0x75, 0x30}, {0x76, 0x2c}, {0x77, 0x24},
4444 {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x31},
4445 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x62},
4446 {0x80, 0x6d}, {0x81, 0x75}, {0x82, 0x7b}, {0x83, 0x81},
4447 {0x84, 0x87}, {0x85, 0x8d}, {0x86, 0x98}, {0x87, 0xa1},
4448 {0x88, 0xb2}, {0x89, 0xc6}, {0x8a, 0xdb}},
4449 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x84},
4450 {0x70, 0x58}, {0x71, 0x48}, {0x72, 0x40}, {0x73, 0x40},
4451 {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x28}, {0x77, 0x24},
4452 {0x78, 0x26}, {0x79, 0x28}, {0x7a, 0x28}, {0x7b, 0x34},
4453 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x5d},
4454 {0x80, 0x68}, {0x81, 0x71}, {0x82, 0x79}, {0x83, 0x81},
4455 {0x84, 0x86}, {0x85, 0x8b}, {0x86, 0x95}, {0x87, 0x9e},
4456 {0x88, 0xb1}, {0x89, 0xc5}, {0x8a, 0xd9}},
4457 {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x70},
4458 {0x70, 0x58}, {0x71, 0x58}, {0x72, 0x48}, {0x73, 0x48},
4459 {0x74, 0x38}, {0x75, 0x40}, {0x76, 0x34}, {0x77, 0x34},
4460 {0x78, 0x2e}, {0x79, 0x28}, {0x7a, 0x24}, {0x7b, 0x22},
4461 {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x58},
4462 {0x80, 0x63}, {0x81, 0x6e}, {0x82, 0x77}, {0x83, 0x80},
4463 {0x84, 0x87}, {0x85, 0x8f}, {0x86, 0x9c}, {0x87, 0xa9},
4464 {0x88, 0xc0}, {0x89, 0xd4}, {0x8a, 0xe6}},
4465 {{0x6c, 0xa0}, {0x6d, 0xf0}, {0x6e, 0x90}, {0x6f, 0x80},
4466 {0x70, 0x70}, {0x71, 0x80}, {0x72, 0x60}, {0x73, 0x60},
4467 {0x74, 0x58}, {0x75, 0x60}, {0x76, 0x4c}, {0x77, 0x38},
4468 {0x78, 0x38}, {0x79, 0x2a}, {0x7a, 0x20}, {0x7b, 0x0e},
4469 {0x7c, 0x0a}, {0x7d, 0x14}, {0x7e, 0x26}, {0x7f, 0x46},
4470 {0x80, 0x54}, {0x81, 0x64}, {0x82, 0x70}, {0x83, 0x7c},
4471 {0x84, 0x87}, {0x85, 0x93}, {0x86, 0xa6}, {0x87, 0xb4},
4472 {0x88, 0xd0}, {0x89, 0xe5}, {0x8a, 0xf5}},
4473 {{0x6c, 0x60}, {0x6d, 0x80}, {0x6e, 0x60}, {0x6f, 0x80},
4474 {0x70, 0x80}, {0x71, 0x80}, {0x72, 0x88}, {0x73, 0x30},
4475 {0x74, 0x70}, {0x75, 0x68}, {0x76, 0x64}, {0x77, 0x50},
4476 {0x78, 0x3c}, {0x79, 0x22}, {0x7a, 0x10}, {0x7b, 0x08},
4477 {0x7c, 0x06}, {0x7d, 0x0e}, {0x7e, 0x1a}, {0x7f, 0x3a},
4478 {0x80, 0x4a}, {0x81, 0x5a}, {0x82, 0x6b}, {0x83, 0x7b},
4479 {0x84, 0x89}, {0x85, 0x96}, {0x86, 0xaf}, {0x87, 0xc3},
4480 {0x88, 0xe1}, {0x89, 0xf2}, {0x8a, 0xfa}},
4481 {{0x6c, 0x20}, {0x6d, 0x40}, {0x6e, 0x20}, {0x6f, 0x60},
4482 {0x70, 0x88}, {0x71, 0xc8}, {0x72, 0xc0}, {0x73, 0xb8},
4483 {0x74, 0xa8}, {0x75, 0xb8}, {0x76, 0x80}, {0x77, 0x5c},
4484 {0x78, 0x26}, {0x79, 0x10}, {0x7a, 0x08}, {0x7b, 0x04},
4485 {0x7c, 0x02}, {0x7d, 0x06}, {0x7e, 0x0a}, {0x7f, 0x22},
4486 {0x80, 0x33}, {0x81, 0x4c}, {0x82, 0x64}, {0x83, 0x7b},
4487 {0x84, 0x90}, {0x85, 0xa7}, {0x86, 0xc7}, {0x87, 0xde},
4488 {0x88, 0xf1}, {0x89, 0xf9}, {0x8a, 0xfd}},
4489 };
6a7eba24 4490
62833acd 4491 val = sd->ctrls[CONTRAST].val;
6a7eba24
JFM		 4492 switch (sd->sensor) {
4493 case SEN_OV7610:
4494 case SEN_OV6620:
4495 i2c_w(sd, OV7610_REG_CNT, val);
4496 break;
4497 case SEN_OV6630:
7d971373 4498 case SEN_OV66308AF:
6a7eba24 4499 i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f);
49809d6a 4500 break;
6a7eba24 4501 case SEN_OV8610: {
9d1593a8 4502 static const u8 ctab[] = {
6a7eba24
JFM		 4503 0x03, 0x09, 0x0b, 0x0f, 0x53, 0x6f, 0x35, 0x7f
4504 };
4505
4506 /* Use Y gamma control instead. Bit 0 enables it. */
4507 i2c_w(sd, 0x64, ctab[val >> 5]);
4508 break;
4509 }
859cc470
HG		 4510 case SEN_OV7620:
4511 case SEN_OV7620AE: {
9d1593a8 4512 static const u8 ctab[] = {
6a7eba24
JFM		 4513 0x01, 0x05, 0x09, 0x11, 0x15, 0x35, 0x37, 0x57,
4514 0x5b, 0xa5, 0xa7, 0xc7, 0xc9, 0xcf, 0xef, 0xff
4515 };
4516
4517 /* Use Y gamma control instead. Bit 0 enables it. */
4518 i2c_w(sd, 0x64, ctab[val >> 4]);
4519 break;
4520 }
42e142f6
JFM		 4521 case SEN_OV7660:
4522 write_i2c_regvals(sd, contrast_7660[val],
4523 ARRAY_SIZE(contrast_7660[0]));
4524 break;
6a7eba24
JFM		 4525 case SEN_OV7670:
4526 /* check that this isn't just the same as ov7610 */
21867803 4527 i2c_w(sd, OV7670_R56_CONTRAS, val >> 1);
6a7eba24
JFM		 4528 break;
4529 }
6a7eba24
JFM		 4530}
4531
4532static void setcolors(struct gspca_dev *gspca_dev)
4533{
4534 struct sd *sd = (struct sd *) gspca_dev;
4535 int val;
42e142f6
JFM		 4536 static const struct ov_i2c_regvals colors_7660[][6] = {
4537 {{0x4f, 0x28}, {0x50, 0x2a}, {0x51, 0x02}, {0x52, 0x0a},
4538 {0x53, 0x19}, {0x54, 0x23}},
4539 {{0x4f, 0x47}, {0x50, 0x4a}, {0x51, 0x03}, {0x52, 0x11},
4540 {0x53, 0x2c}, {0x54, 0x3e}},
4541 {{0x4f, 0x66}, {0x50, 0x6b}, {0x51, 0x05}, {0x52, 0x19},
4542 {0x53, 0x40}, {0x54, 0x59}},
4543 {{0x4f, 0x84}, {0x50, 0x8b}, {0x51, 0x06}, {0x52, 0x20},
4544 {0x53, 0x53}, {0x54, 0x73}},
4545 {{0x4f, 0xa3}, {0x50, 0xab}, {0x51, 0x08}, {0x52, 0x28},
4546 {0x53, 0x66}, {0x54, 0x8e}},
4547 };
6a7eba24 4548
62833acd 4549 val = sd->ctrls[COLORS].val;
6a7eba24
JFM		 4550 switch (sd->sensor) {
4551 case SEN_OV8610:
4552 case SEN_OV7610:
4553 case SEN_OV76BE:
4554 case SEN_OV6620:
4555 case SEN_OV6630:
7d971373 4556 case SEN_OV66308AF:
6a7eba24
JFM		 4557 i2c_w(sd, OV7610_REG_SAT, val);
4558 break;
4559 case SEN_OV7620:
859cc470 4560 case SEN_OV7620AE:
6a7eba24
JFM		 4561 /* Use UV gamma control instead. Bits 0 & 7 are reserved. */
4562/* rc = ov_i2c_write(sd->dev, 0x62, (val >> 9) & 0x7e);
4563 if (rc < 0)
4564 goto out; */
4565 i2c_w(sd, OV7610_REG_SAT, val);
4566 break;
4567 case SEN_OV7640:
035d3a3d 4568 case SEN_OV7648:
6a7eba24
JFM		 4569 i2c_w(sd, OV7610_REG_SAT, val & 0xf0);
4570 break;
42e142f6
JFM		 4571 case SEN_OV7660:
4572 write_i2c_regvals(sd, colors_7660[val],
4573 ARRAY_SIZE(colors_7660[0]));
4574 break;
6a7eba24
JFM		 4575 case SEN_OV7670:
4576 /* supported later once I work out how to do it
4577 * transparently fail now! */
4578 /* set REG_COM13 values for UV sat auto mode */
4579 break;
4580 }
6a7eba24
JFM		 4581}
4582
62833acd 4583static void setautobright(struct gspca_dev *gspca_dev)
02ab18b0 4584{
62833acd
JFM		 4585 struct sd *sd = (struct sd *) gspca_dev;
4586
62833acd 4587 i2c_w_mask(sd, 0x2d, sd->ctrls[AUTOBRIGHT].val ? 0x10 : 0x00, 0x10);
02ab18b0
HG		 4588}
4589
62833acd 4590static void setfreq_i(struct sd *sd)
02ab18b0 4591{
42e142f6
JFM		 4592 if (sd->sensor == SEN_OV7660
4593 || sd->sensor == SEN_OV7670) {
62833acd 4594 switch (sd->ctrls[FREQ].val) {
02ab18b0 4595 case 0: /* Banding filter disabled */
21867803 4596 i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_BFILT);
02ab18b0
HG		 4597 break;
4598 case 1: /* 50 hz */
21867803 4599 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
02ab18b0 4600 OV7670_COM8_BFILT);
21867803 4601 i2c_w_mask(sd, OV7670_R3B_COM11, 0x08, 0x18);
02ab18b0
HG		 4602 break;
4603 case 2: /* 60 hz */
21867803 4604 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
02ab18b0 4605 OV7670_COM8_BFILT);
21867803 4606 i2c_w_mask(sd, OV7670_R3B_COM11, 0x00, 0x18);
02ab18b0 4607 break;
21867803
JFM		 4608 case 3: /* Auto hz - ov7670 only */
4609 i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
02ab18b0 4610 OV7670_COM8_BFILT);
21867803 4611 i2c_w_mask(sd, OV7670_R3B_COM11, OV7670_COM11_HZAUTO,
02ab18b0
HG		 4612 0x18);
4613 break;
4614 }
4615 } else {
62833acd 4616 switch (sd->ctrls[FREQ].val) {
02ab18b0
HG		 4617 case 0: /* Banding filter disabled */
4618 i2c_w_mask(sd, 0x2d, 0x00, 0x04);
4619 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4620 break;
4621 case 1: /* 50 hz (filter on and framerate adj) */
4622 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4623 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4624 /* 20 fps -> 16.667 fps */
4625 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4626 sd->sensor == SEN_OV6630 ||
4627 sd->sensor == SEN_OV66308AF)
02ab18b0
HG		 4628 i2c_w(sd, 0x2b, 0x5e);
4629 else
4630 i2c_w(sd, 0x2b, 0xac);
4631 break;
4632 case 2: /* 60 hz (filter on, ...) */
4633 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4634 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4635 sd->sensor == SEN_OV6630 ||
4636 sd->sensor == SEN_OV66308AF) {
02ab18b0
HG		 4637 /* 20 fps -> 15 fps */
4638 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4639 i2c_w(sd, 0x2b, 0xa8);
4640 } else {
4641 /* no framerate adj. */
4642 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4643 }
4644 break;
4645 }
4646 }
4647}
62833acd 4648static void setfreq(struct gspca_dev *gspca_dev)
02ab18b0
HG		 4649{
4650 struct sd *sd = (struct sd *) gspca_dev;
4651
62833acd 4652 setfreq_i(sd);
02ab18b0 4653
62833acd
JFM		 4654 /* Ugly but necessary */
4655 if (sd->bridge == BRIDGE_W9968CF)
4656 w9968cf_set_crop_window(sd);
02ab18b0
HG		 4657}
4658
4659static int sd_querymenu(struct gspca_dev *gspca_dev,
4660 struct v4l2_querymenu *menu)
4661{
4662 struct sd *sd = (struct sd *) gspca_dev;
4663
4664 switch (menu->id) {
4665 case V4L2_CID_POWER_LINE_FREQUENCY:
4666 switch (menu->index) {
4667 case 0: /* V4L2_CID_POWER_LINE_FREQUENCY_DISABLED */
4668 strcpy((char *) menu->name, "NoFliker");
4669 return 0;
4670 case 1: /* V4L2_CID_POWER_LINE_FREQUENCY_50HZ */
4671 strcpy((char *) menu->name, "50 Hz");
4672 return 0;
4673 case 2: /* V4L2_CID_POWER_LINE_FREQUENCY_60HZ */
4674 strcpy((char *) menu->name, "60 Hz");
4675 return 0;
4676 case 3:
4677 if (sd->sensor != SEN_OV7670)
4678 return -EINVAL;
4679
4680 strcpy((char *) menu->name, "Automatic");
4681 return 0;
4682 }
4683 break;
4684 }
4685 return -EINVAL;
4686}
4687
79b35902
HG		 4688static int sd_get_jcomp(struct gspca_dev *gspca_dev,
4689 struct v4l2_jpegcompression *jcomp)
4690{
4691 struct sd *sd = (struct sd *) gspca_dev;
4692
4693 if (sd->bridge != BRIDGE_W9968CF)
4694 return -EINVAL;
4695
4696 memset(jcomp, 0, sizeof *jcomp);
4697 jcomp->quality = sd->quality;
4698 jcomp->jpeg_markers = V4L2_JPEG_MARKER_DHT | V4L2_JPEG_MARKER_DQT |
4699 V4L2_JPEG_MARKER_DRI;
4700 return 0;
4701}
4702
4703static int sd_set_jcomp(struct gspca_dev *gspca_dev,
4704 struct v4l2_jpegcompression *jcomp)
4705{
4706 struct sd *sd = (struct sd *) gspca_dev;
4707
4708 if (sd->bridge != BRIDGE_W9968CF)
4709 return -EINVAL;
4710
4711 if (gspca_dev->streaming)
4712 return -EBUSY;
4713
4714 if (jcomp->quality < QUALITY_MIN)
4715 sd->quality = QUALITY_MIN;
4716 else if (jcomp->quality > QUALITY_MAX)
4717 sd->quality = QUALITY_MAX;
4718 else
4719 sd->quality = jcomp->quality;
4720
4721 /* Return resulting jcomp params to app */
4722 sd_get_jcomp(gspca_dev, jcomp);
4723
4724 return 0;
4725}
4726
6a7eba24 4727/* sub-driver description */
a5ae2062 4728static const struct sd_desc sd_desc = {
6a7eba24
JFM		 4729 .name = MODULE_NAME,
4730 .ctrls = sd_ctrls,
4731 .nctrls = ARRAY_SIZE(sd_ctrls),
4732 .config = sd_config,
012d6b02 4733 .init = sd_init,
6a7eba24
JFM		 4734 .start = sd_start,
4735 .stopN = sd_stopN,
79b35902 4736 .stop0 = sd_stop0,
6a7eba24 4737 .pkt_scan = sd_pkt_scan,
417a4d26 4738 .dq_callback = sd_reset_snapshot,
02ab18b0 4739 .querymenu = sd_querymenu,
79b35902
HG		 4740 .get_jcomp = sd_get_jcomp,
4741 .set_jcomp = sd_set_jcomp,
2856643e 4742#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
417a4d26
HG		 4743 .other_input = 1,
4744#endif
6a7eba24
JFM		 4745};
4746
4747/* -- module initialisation -- */
95c967c1 4748static const struct usb_device_id device_table[] = {
a511ba94 4749 {USB_DEVICE(0x041e, 0x4003), .driver_info = BRIDGE_W9968CF },
49809d6a
HG		 4750 {USB_DEVICE(0x041e, 0x4052), .driver_info = BRIDGE_OV519 },
4751 {USB_DEVICE(0x041e, 0x405f), .driver_info = BRIDGE_OV519 },
4752 {USB_DEVICE(0x041e, 0x4060), .driver_info = BRIDGE_OV519 },
4753 {USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
9e4d8258 4754 {USB_DEVICE(0x041e, 0x4064),
87bae740 4755 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
518c8df7 4756 {USB_DEVICE(0x041e, 0x4067), .driver_info = BRIDGE_OV519 },
9e4d8258 4757 {USB_DEVICE(0x041e, 0x4068),
87bae740 4758 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
49809d6a
HG		 4759 {USB_DEVICE(0x045e, 0x028c), .driver_info = BRIDGE_OV519 },
4760 {USB_DEVICE(0x054c, 0x0154), .driver_info = BRIDGE_OV519 },
98184f78 4761 {USB_DEVICE(0x054c, 0x0155),
87bae740 4762 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
1876bb92 4763 {USB_DEVICE(0x05a9, 0x0511), .driver_info = BRIDGE_OV511 },
49809d6a
HG		 4764 {USB_DEVICE(0x05a9, 0x0518), .driver_info = BRIDGE_OV518 },
4765 {USB_DEVICE(0x05a9, 0x0519), .driver_info = BRIDGE_OV519 },
4766 {USB_DEVICE(0x05a9, 0x0530), .driver_info = BRIDGE_OV519 },
b46aaa02 4767 {USB_DEVICE(0x05a9, 0x2800), .driver_info = BRIDGE_OVFX2 },
49809d6a
HG		 4768 {USB_DEVICE(0x05a9, 0x4519), .driver_info = BRIDGE_OV519 },
4769 {USB_DEVICE(0x05a9, 0x8519), .driver_info = BRIDGE_OV519 },
1876bb92 4770 {USB_DEVICE(0x05a9, 0xa511), .driver_info = BRIDGE_OV511PLUS },
49809d6a 4771 {USB_DEVICE(0x05a9, 0xa518), .driver_info = BRIDGE_OV518PLUS },
1876bb92 4772 {USB_DEVICE(0x0813, 0x0002), .driver_info = BRIDGE_OV511PLUS },
b46aaa02
HG		 4773 {USB_DEVICE(0x0b62, 0x0059), .driver_info = BRIDGE_OVFX2 },
4774 {USB_DEVICE(0x0e96, 0xc001), .driver_info = BRIDGE_OVFX2 },
a511ba94 4775 {USB_DEVICE(0x1046, 0x9967), .driver_info = BRIDGE_W9968CF },
87bae740 4776 {USB_DEVICE(0x8020, 0xef04), .driver_info = BRIDGE_OVFX2 },
6a7eba24
JFM		 4777 {}
4778};
ac40b1fa 4779
6a7eba24
JFM		 4780MODULE_DEVICE_TABLE(usb, device_table);
4781
4782/* -- device connect -- */
4783static int sd_probe(struct usb_interface *intf,
4784 const struct usb_device_id *id)
4785{
4786 return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
4787 THIS_MODULE);
4788}
4789
4790static struct usb_driver sd_driver = {
4791 .name = MODULE_NAME,
4792 .id_table = device_table,
4793 .probe = sd_probe,
4794 .disconnect = gspca_disconnect,
6a709749
JFM		 4795#ifdef CONFIG_PM
4796 .suspend = gspca_suspend,
4797 .resume = gspca_resume,
4798#endif
6a7eba24
JFM		 4799};
4800
4801/* -- module insert / remove -- */
4802static int __init sd_mod_init(void)
4803{
54826437 4804 return usb_register(&sd_driver);
6a7eba24
JFM		 4805}
4806static void __exit sd_mod_exit(void)
4807{
4808 usb_deregister(&sd_driver);
6a7eba24
JFM		 4809}
4810
4811module_init(sd_mod_init);
4812module_exit(sd_mod_exit);
4813
4814module_param(frame_rate, int, 0644);
4815MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)");
Linux 6.x block layer and io_uring tree(s)