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V4L/DVB (9737): sms1xxx: enable LNA control on Hauppauge WinTV MiniCard
[linux-2.6-block.git] / drivers / media / video / em28xx / em28xx-core.c
CommitLineData
a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
a6c2ba28 27#include <linux/usb.h>
28#include <linux/vmalloc.h>
29
f7abcd38 30#include "em28xx.h"
a6c2ba28 31
32/* #define ENABLE_DEBUG_ISOC_FRAMES */
33
ff699e6b 34static unsigned int core_debug;
a6c2ba28 35module_param(core_debug,int,0644);
36MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
37
3acf2809 38#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 39 if (core_debug) \
40 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 41 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 42
ff699e6b 43static unsigned int reg_debug;
a6c2ba28 44module_param(reg_debug,int,0644);
45MODULE_PARM_DESC(reg_debug,"enable debug messages [URB reg]");
46
3acf2809 47#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 48 if (reg_debug) \
49 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 50 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 51
3acf2809 52static int alt = EM28XX_PINOUT;
a6c2ba28 53module_param(alt, int, 0644);
54MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
55
579f72e4
AT		 56/* FIXME */
57#define em28xx_isocdbg(fmt, arg...) do {\
58 if (core_debug) \
59 printk(KERN_INFO "%s %s :"fmt, \
60 dev->name, __func__ , ##arg); } while (0)
61
a6c2ba28 62/*
3acf2809 63 * em28xx_read_reg_req()
a6c2ba28 64 * reads data from the usb device specifying bRequest
65 */
3acf2809 66int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28 67 char *buf, int len)
68{
69 int ret, byte;
70
9f38724a 71 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 72 return -ENODEV;
73
74 if (len > URB_MAX_CTRL_SIZE)
75 return -EINVAL;
9f38724a 76
3acf2809 77 em28xx_regdbg("req=%02x, reg=%02x ", req, reg);
a6c2ba28 78
f2a2e491 79 mutex_lock(&dev->ctrl_urb_lock);
a6c2ba28 80 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
81 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 82 0x0000, reg, dev->urb_buf, len, HZ);
83 if (ret < 0) {
84 if (reg_debug)
85 printk(" failed!\n");
f2a2e491 86 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 87 return ret;
88 }
89
90 if (len)
91 memcpy(buf, dev->urb_buf, len);
a6c2ba28 92
f2a2e491
MCC		 93 mutex_unlock(&dev->ctrl_urb_lock);
94
6ea54d93 95 if (reg_debug) {
c4a98793 96 printk("%02x values: ", ret);
6ea54d93 97 for (byte = 0; byte < len; byte++)
82ac4f87 98 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 99 printk("\n");
a6c2ba28 100 }
101
102 return ret;
103}
104
105/*
3acf2809 106 * em28xx_read_reg_req()
a6c2ba28 107 * reads data from the usb device specifying bRequest
108 */
3acf2809 109int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 110{
111 u8 val;
112 int ret;
113
9f38724a
MR		 114 if (dev->state & DEV_DISCONNECTED)
115 return(-ENODEV);
116
3acf2809 117 em28xx_regdbg("req=%02x, reg=%02x:", req, reg);
a6c2ba28 118
f2a2e491 119 mutex_lock(&dev->ctrl_urb_lock);
a6c2ba28 120 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
121 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 122 0x0000, reg, dev->urb_buf, 1, HZ);
f2a2e491
MCC		 123 val = dev->urb_buf[0];
124 mutex_unlock(&dev->ctrl_urb_lock);
125
c4a98793
MCC		 126 if (ret < 0) {
127 printk(" failed!\n");
128 return ret;
129 }
a6c2ba28 130
c4a98793
MCC		 131 if (reg_debug)
132 printk("%02x\n", (unsigned char) val);
a6c2ba28 133
134 return val;
135}
136
3acf2809 137int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 138{
3acf2809 139 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28 140}
141
142/*
3acf2809 143 * em28xx_write_regs_req()
a6c2ba28 144 * sends data to the usb device, specifying bRequest
145 */
3acf2809 146int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28 147 int len)
148{
149 int ret;
150
9f38724a 151 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 152 return -ENODEV;
153
c4a98793 154 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 155 return -EINVAL;
9f38724a 156
3acf2809 157 em28xx_regdbg("req=%02x reg=%02x:", req, reg);
a6c2ba28 158 if (reg_debug) {
159 int i;
160 for (i = 0; i < len; ++i)
82ac4f87
MCC		 161 printk(" %02x", (unsigned char)buf[i]);
162 printk("\n");
a6c2ba28 163 }
164
f2a2e491 165 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 166 memcpy(dev->urb_buf, buf, len);
a6c2ba28 167 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), req,
168 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 169 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 170 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 171
89b329ef
MCC		 172 if (dev->wait_after_write)
173 msleep(dev->wait_after_write);
174
a6c2ba28 175 return ret;
176}
177
3acf2809 178int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 179{
c67ec53f
MCC		 180 int rc;
181
182 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
183
184 /* Stores GPO/GPIO values at the cache, if changed
185 Only write values should be stored, since input on a GPIO
186 register will return the input bits.
187 Not sure what happens on reading GPO register.
188 */
189 if (rc >= 0) {
6a1acc3b 190 if (reg == dev->reg_gpo_num)
c67ec53f 191 dev->reg_gpo = buf[0];
6a1acc3b 192 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 193 dev->reg_gpio = buf[0];
194 }
195
196 return rc;
a6c2ba28 197}
198
b6972489
DH		 199/* Write a single register */
200int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
201{
202 return em28xx_write_regs(dev, reg, &val, 1);
203}
204
a6c2ba28 205/*
3acf2809 206 * em28xx_write_reg_bits()
a6c2ba28 207 * sets only some bits (specified by bitmask) of a register, by first reading
208 * the actual value
209 */
532fe652 210static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28 211 u8 bitmask)
212{
213 int oldval;
214 u8 newval;
6ea54d93 215
c67ec53f 216 /* Uses cache for gpo/gpio registers */
6a1acc3b 217 if (reg == dev->reg_gpo_num)
c67ec53f 218 oldval = dev->reg_gpo;
6a1acc3b 219 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 220 oldval = dev->reg_gpio;
221 else
222 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 223
224 if (oldval < 0)
a6c2ba28 225 return oldval;
6ea54d93 226
a6c2ba28 227 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 228
3acf2809 229 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28 230}
231
35643943
MCC		 232/*
233 * em28xx_is_ac97_ready()
234 * Checks if ac97 is ready
235 */
236static int em28xx_is_ac97_ready(struct em28xx *dev)
237{
238 int ret, i;
239
240 /* Wait up to 50 ms for AC97 command to complete */
241 for (i = 0; i < 10; i++, msleep(5)) {
242 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
243 if (ret < 0)
244 return ret;
245
246 if (!(ret & 0x01))
247 return 0;
248 }
249
250 em28xx_warn("AC97 command still being executed: not handled properly!\n");
251 return -EBUSY;
252}
253
254/*
255 * em28xx_read_ac97()
256 * write a 16 bit value to the specified AC97 address (LSB first!)
257 */
258static int em28xx_read_ac97(struct em28xx *dev, u8 reg)
259{
260 int ret;
261 u8 addr = (reg & 0x7f) | 0x80;
262 u16 val;
263
264 ret = em28xx_is_ac97_ready(dev);
265 if (ret < 0)
266 return ret;
267
268 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
269 if (ret < 0)
270 return ret;
271
272 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
273 (u8 *)&val, sizeof(val));
274
275 if (ret < 0)
276 return ret;
277 return le16_to_cpu(val);
278}
279
a6c2ba28 280/*
3acf2809 281 * em28xx_write_ac97()
a6c2ba28 282 * write a 16 bit value to the specified AC97 address (LSB first!)
283 */
35643943 284static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 285{
35643943 286 int ret;
a6c2ba28 287 u8 addr = reg & 0x7f;
35643943
MCC		 288 __le16 value;
289
290 value = cpu_to_le16(val);
291
292 ret = em28xx_is_ac97_ready(dev);
293 if (ret < 0)
294 return ret;
6ea54d93 295
35643943 296 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 297 if (ret < 0)
a6c2ba28 298 return ret;
6ea54d93 299
41facaa4 300 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 301 if (ret < 0)
a6c2ba28 302 return ret;
00b8730f 303
35643943
MCC		 304 return 0;
305}
6ea54d93 306
e879b8eb
MCC		 307struct em28xx_vol_table {
308 enum em28xx_amux mux;
5faff789
MCC		 309 u8 reg;
310};
311
e879b8eb 312static struct em28xx_vol_table inputs[] = {
5faff789
MCC		 313 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
314 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
315 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
316 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
317 { EM28XX_AMUX_CD, AC97_CD_VOL },
318 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
319 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
320};
321
322static int set_ac97_input(struct em28xx *dev)
35643943 323{
5faff789
MCC		 324 int ret, i;
325 enum em28xx_amux amux = dev->ctl_ainput;
35643943 326
5faff789
MCC		 327 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
328 em28xx should point to LINE IN, while AC97 should use VIDEO
329 */
330 if (amux == EM28XX_AMUX_VIDEO2)
f1990a9c 331 amux = EM28XX_AMUX_VIDEO;
35643943 332
5faff789
MCC		 333 /* Mute all entres but the one that were selected */
334 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
e879b8eb 335 if (amux == inputs[i].mux)
5faff789
MCC		 336 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
337 else
338 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
35643943 339
5faff789
MCC		 340 if (ret < 0)
341 em28xx_warn("couldn't setup AC97 register %d\n",
342 inputs[i].reg);
343 }
344 return 0;
a6c2ba28 345}
346
00b8730f 347static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 348{
1685a6fe 349 int ret;
539c96d0
MCC		 350 u8 input;
351
505b6d0b 352 if (dev->board.is_em2800) {
5faff789 353 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
539c96d0 354 input = EM2800_AUDIO_SRC_TUNER;
5faff789
MCC		 355 else
356 input = EM2800_AUDIO_SRC_LINE;
539c96d0 357
41facaa4 358 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 359 if (ret < 0)
360 return ret;
361 }
362
505b6d0b 363 if (dev->board.has_msp34xx)
539c96d0
MCC		 364 input = EM28XX_AUDIO_SRC_TUNER;
365 else {
366 switch (dev->ctl_ainput) {
367 case EM28XX_AMUX_VIDEO:
368 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 369 break;
35643943 370 default:
539c96d0 371 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 372 break;
373 }
374 }
375
41facaa4 376 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 377 if (ret < 0)
378 return ret;
00b8730f 379 msleep(5);
539c96d0 380
35643943
MCC		 381 switch (dev->audio_mode.ac97) {
382 case EM28XX_NO_AC97:
383 break;
5faff789
MCC		 384 default:
385 ret = set_ac97_input(dev);
35643943 386 }
539c96d0 387
5faff789 388 return ret;
539c96d0
MCC		 389}
390
e879b8eb
MCC		 391struct em28xx_vol_table outputs[] = {
392 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
393 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
394 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
395 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
396 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
35ae6f04
MCC		 397};
398
3acf2809 399int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 400{
35ae6f04 401 int ret, i;
a2070c66 402 u8 xclk;
539c96d0 403
35643943
MCC		 404 if (!dev->audio_mode.has_audio)
405 return 0;
539c96d0 406
5faff789
MCC		 407 /* It is assumed that all devices use master volume for output.
408 It would be possible to use also line output.
409 */
35643943 410 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
35ae6f04
MCC		 411 /* Mute all outputs */
412 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
e879b8eb 413 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
35ae6f04
MCC		 414 if (ret < 0)
415 em28xx_warn("couldn't setup AC97 register %d\n",
e879b8eb 416 outputs[i].reg);
35ae6f04 417 }
35643943 418 }
539c96d0 419
505b6d0b 420 xclk = dev->board.xclk & 0x7f;
3abee53e
MCC		 421 if (!dev->mute)
422 xclk |= 0x80;
423
a2070c66 424 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
539c96d0
MCC		 425 if (ret < 0)
426 return ret;
3abee53e 427 msleep(10);
539c96d0
MCC		 428
429 /* Selects the proper audio input */
430 ret = em28xx_set_audio_source(dev);
a6c2ba28 431
35643943
MCC		 432 /* Sets volume */
433 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
434 int vol;
435
436 /* LSB: left channel - both channels with the same level */
437 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
438
439 /* Mute device, if needed */
440 if (dev->mute)
441 vol |= 0x8000;
442
443 /* Sets volume */
e879b8eb
MCC		 444 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
445 if (dev->ctl_aoutput & outputs[i].mux)
446 ret = em28xx_write_ac97(dev, outputs[i].reg,
447 vol);
448 if (ret < 0)
449 em28xx_warn("couldn't setup AC97 register %d\n",
450 outputs[i].reg);
451 }
35643943 452 }
00b8730f 453
539c96d0
MCC		 454 return ret;
455}
456EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 457
35643943
MCC		 458int em28xx_audio_setup(struct em28xx *dev)
459{
460 int vid1, vid2, feat, cfg;
16c7bcad 461 u32 vid;
35643943
MCC		 462
463 if (dev->chip_id == CHIP_ID_EM2874) {
464 /* Digital only device - don't load any alsa module */
465 dev->audio_mode.has_audio = 0;
466 dev->has_audio_class = 0;
467 dev->has_alsa_audio = 0;
468 return 0;
469 }
470
471 /* If device doesn't support Usb Audio Class, use vendor class */
472 if (!dev->has_audio_class)
473 dev->has_alsa_audio = 1;
474
475 dev->audio_mode.has_audio = 1;
476
477 /* See how this device is configured */
478 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
479 if (cfg < 0)
480 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
481 else
482 em28xx_info("Config register raw data: 0x%02x\n", cfg);
483
484 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
485 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
486 em28xx_info("I2S Audio (3 sample rates)\n");
487 dev->audio_mode.i2s_3rates = 1;
488 }
489 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
490 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
491 em28xx_info("I2S Audio (5 sample rates)\n");
492 dev->audio_mode.i2s_5rates = 1;
493 }
494
495 if (!(cfg & EM28XX_CHIPCFG_AC97)) {
496 dev->audio_mode.ac97 = EM28XX_NO_AC97;
497 goto init_audio;
498 }
499
500 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
501
502 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
503 if (vid1 < 0) {
504 /* Device likely doesn't support AC97 */
505 em28xx_warn("AC97 chip type couldn't be determined\n");
506 goto init_audio;
507 }
508
509 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
510 if (vid2 < 0)
511 goto init_audio;
512
16c7bcad
MCC		 513 vid = vid1 << 16 | vid2;
514
515 dev->audio_mode.ac97_vendor_id = vid;
516 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 517
518 feat = em28xx_read_ac97(dev, AC97_RESET);
519 if (feat < 0)
520 goto init_audio;
521
522 dev->audio_mode.ac97_feat = feat;
523 em28xx_warn("AC97 features = 0x%04x\n", feat);
524
16c7bcad
MCC		 525 /* Try to identify what audio processor we have */
526 if ((vid == 0xffffffff) && (feat == 0x6a90))
35643943 527 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
209acc02
MCC		 528 else if ((vid >> 8) == 0x838476)
529 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
35643943
MCC		 530
531init_audio:
532 /* Reports detected AC97 processor */
533 switch (dev->audio_mode.ac97) {
534 case EM28XX_NO_AC97:
535 em28xx_info("No AC97 audio processor\n");
536 break;
537 case EM28XX_AC97_EM202:
538 em28xx_info("Empia 202 AC97 audio processor detected\n");
539 break;
209acc02
MCC		 540 case EM28XX_AC97_SIGMATEL:
541 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
542 dev->audio_mode.ac97_vendor_id & 0xff);
543 break;
35643943
MCC		 544 case EM28XX_AC97_OTHER:
545 em28xx_warn("Unknown AC97 audio processor detected!\n");
546 break;
547 default:
548 break;
549 }
550
551 return em28xx_audio_analog_set(dev);
552}
553EXPORT_SYMBOL_GPL(em28xx_audio_setup);
554
3acf2809 555int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 556{
2a29a0d7
MCC		 557 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
558 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
559 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
560 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
561 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
562 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
563
564 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
565 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
566 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
567 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
568 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
569 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
570 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
a6c2ba28 571}
572
3acf2809 573int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 574{
ee6e3a86 575 int rc;
ebef13d4
DH		 576
577 if (dev->chip_id == CHIP_ID_EM2874) {
578 /* The Transport Stream Enable Register moved in em2874 */
579 if (!start) {
580 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
581 0x00,
582 EM2874_TS1_CAPTURE_ENABLE);
583 return rc;
584 }
585
586 /* Enable Transport Stream */
587 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
588 EM2874_TS1_CAPTURE_ENABLE,
589 EM2874_TS1_CAPTURE_ENABLE);
590 return rc;
591 }
592
593
a6c2ba28 594 /* FIXME: which is the best order? */
595 /* video registers are sampled by VREF */
41facaa4 596 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 597 start ? 0x10 : 0x00, 0x10);
598 if (rc < 0)
599 return rc;
600
601 if (!start) {
602 /* disable video capture */
2a29a0d7 603 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
102a0b08 604 return rc;
ee6e3a86
MCC		 605 }
606
a6c2ba28 607 /* enable video capture */
2a29a0d7 608 rc = em28xx_write_reg(dev, 0x48, 0x00);
102a0b08 609
ee6e3a86 610 if (dev->mode == EM28XX_ANALOG_MODE)
2a29a0d7 611 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
ee6e3a86 612 else
2a29a0d7 613 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
ee6e3a86 614
6ea54d93 615 msleep(6);
ee6e3a86
MCC		 616
617 return rc;
a6c2ba28 618}
619
3acf2809 620int em28xx_outfmt_set_yuv422(struct em28xx *dev)
a6c2ba28 621{
2a29a0d7
MCC		 622 em28xx_write_reg(dev, EM28XX_R27_OUTFMT, 0x34);
623 em28xx_write_reg(dev, EM28XX_R10_VINMODE, 0x10);
624 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, 0x11);
a6c2ba28 625}
626
adcb0fa2
AB		 627static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
628 u8 ymin, u8 ymax)
a6c2ba28 629{
6ea54d93
DSL		 630 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
631 xmin, ymin, xmax, ymax);
a6c2ba28 632
41facaa4
MCC		 633 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
634 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
635 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
636 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28 637}
638
adcb0fa2 639static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28 640 u16 width, u16 height)
641{
642 u8 cwidth = width;
643 u8 cheight = height;
644 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
645
6ea54d93
DSL		 646 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
647 (width | (overflow & 2) << 7),
a6c2ba28 648 (height | (overflow & 1) << 8));
649
41facaa4
MCC		 650 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
651 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
652 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
653 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
654 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28 655}
656
adcb0fa2 657static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 658{
52c02fcd
SS		 659 u8 mode;
660 /* the em2800 scaler only supports scaling down to 50% */
505b6d0b 661 if (dev->board.is_em2800)
52c02fcd
SS		 662 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
663 else {
664 u8 buf[2];
665 buf[0] = h;
666 buf[1] = h >> 8;
41facaa4 667 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
52c02fcd
SS		 668 buf[0] = v;
669 buf[1] = v >> 8;
41facaa4 670 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 671 /* it seems that both H and V scalers must be active
672 to work correctly */
52c02fcd 673 mode = (h || v)? 0x30: 0x00;
74458e6c 674 }
41facaa4 675 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28 676}
677
678/* FIXME: this only function read values from dev */
3acf2809 679int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28 680{
681 int width, height;
682 width = norm_maxw(dev);
683 height = norm_maxh(dev) >> 1;
684
3acf2809
MCC		 685 em28xx_outfmt_set_yuv422(dev);
686 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
687 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
688 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28 689}
690
3acf2809 691int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28 692{
693 int errCode, prev_alt = dev->alt;
3687e1e6 694 int i;
44dc733c 695 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 696
2c4a07b2 697 /* When image size is bigger than a certain value,
3687e1e6
MCC		 698 the frame size should be increased, otherwise, only
699 green screen will be received.
700 */
44dc733c 701 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 702 min_pkt_size *= 2;
703
2c4a07b2
SS		 704 for (i = 0; i < dev->num_alt; i++) {
705 /* stop when the selected alt setting offers enough bandwidth */
706 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
707 dev->alt = i;
3687e1e6 708 break;
2c4a07b2
SS		 709 /* otherwise make sure that we end up with the maximum bandwidth
710 because the min_pkt_size equation might be wrong...
711 */
712 } else if (dev->alt_max_pkt_size[i] >
713 dev->alt_max_pkt_size[dev->alt])
714 dev->alt = i;
715 }
a6c2ba28 716
717 if (dev->alt != prev_alt) {
3687e1e6
MCC		 718 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
719 min_pkt_size, dev->alt);
a6c2ba28 720 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 721 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
722 dev->alt, dev->max_pkt_size);
a6c2ba28 723 errCode = usb_set_interface(dev->udev, 0, dev->alt);
724 if (errCode < 0) {
6ea54d93 725 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 726 dev->alt, errCode);
a6c2ba28 727 return errCode;
728 }
729 }
730 return 0;
731}
579f72e4 732
c67ec53f
MCC		 733int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
734{
735 int rc = 0;
736
737 if (!gpio)
738 return rc;
739
2fe3e2ee
MCC		 740 if (dev->mode != EM28XX_SUSPEND) {
741 em28xx_write_reg(dev, 0x48, 0x00);
742 if (dev->mode == EM28XX_ANALOG_MODE)
743 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
744 else
745 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
746 msleep(6);
747 }
c67ec53f
MCC		 748
749 /* Send GPIO reset sequences specified at board entry */
750 while (gpio->sleep >= 0) {
751 if (gpio->reg >= 0) {
752 rc = em28xx_write_reg_bits(dev,
753 gpio->reg,
754 gpio->val,
755 gpio->mask);
756 if (rc < 0)
757 return rc;
758 }
759 if (gpio->sleep > 0)
760 msleep(gpio->sleep);
761
762 gpio++;
763 }
764 return rc;
765}
766
767int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
768{
769 if (dev->mode == set_mode)
770 return 0;
771
2fe3e2ee 772 if (set_mode == EM28XX_SUSPEND) {
c67ec53f 773 dev->mode = set_mode;
2fe3e2ee
MCC		 774
775 /* FIXME: add suspend support for ac97 */
776
777 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
c67ec53f
MCC		 778 }
779
780 dev->mode = set_mode;
781
782 if (dev->mode == EM28XX_DIGITAL_MODE)
f502e861 783 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
c67ec53f 784 else
f502e861 785 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
c67ec53f
MCC		 786}
787EXPORT_SYMBOL_GPL(em28xx_set_mode);
788
579f72e4
AT		 789/* ------------------------------------------------------------------
790 URB control
791 ------------------------------------------------------------------*/
792
793/*
794 * IRQ callback, called by URB callback
795 */
796static void em28xx_irq_callback(struct urb *urb)
797{
798 struct em28xx_dmaqueue *dma_q = urb->context;
799 struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
800 int rc, i;
801
802 /* Copy data from URB */
803 spin_lock(&dev->slock);
804 rc = dev->isoc_ctl.isoc_copy(dev, urb);
805 spin_unlock(&dev->slock);
806
807 /* Reset urb buffers */
808 for (i = 0; i < urb->number_of_packets; i++) {
809 urb->iso_frame_desc[i].status = 0;
810 urb->iso_frame_desc[i].actual_length = 0;
811 }
812 urb->status = 0;
813
814 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
815 if (urb->status) {
4269a8ee
DH		 816 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
817 urb->status);
579f72e4
AT		 818 }
819}
820
821/*
822 * Stop and Deallocate URBs
823 */
824void em28xx_uninit_isoc(struct em28xx *dev)
825{
826 struct urb *urb;
827 int i;
828
829 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
830
831 dev->isoc_ctl.nfields = -1;
832 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
833 urb = dev->isoc_ctl.urb[i];
834 if (urb) {
835 usb_kill_urb(urb);
836 usb_unlink_urb(urb);
837 if (dev->isoc_ctl.transfer_buffer[i]) {
838 usb_buffer_free(dev->udev,
6ea54d93
DSL		 839 urb->transfer_buffer_length,
840 dev->isoc_ctl.transfer_buffer[i],
841 urb->transfer_dma);
579f72e4
AT		 842 }
843 usb_free_urb(urb);
844 dev->isoc_ctl.urb[i] = NULL;
845 }
846 dev->isoc_ctl.transfer_buffer[i] = NULL;
847 }
848
849 kfree(dev->isoc_ctl.urb);
850 kfree(dev->isoc_ctl.transfer_buffer);
851
852 dev->isoc_ctl.urb = NULL;
853 dev->isoc_ctl.transfer_buffer = NULL;
854 dev->isoc_ctl.num_bufs = 0;
855
856 em28xx_capture_start(dev, 0);
857}
858EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
859
860/*
861 * Allocate URBs and start IRQ
862 */
863int em28xx_init_isoc(struct em28xx *dev, int max_packets,
864 int num_bufs, int max_pkt_size,
c67ec53f 865 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
579f72e4
AT		 866{
867 struct em28xx_dmaqueue *dma_q = &dev->vidq;
868 int i;
869 int sb_size, pipe;
870 struct urb *urb;
871 int j, k;
872 int rc;
873
874 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
875
876 /* De-allocates all pending stuff */
877 em28xx_uninit_isoc(dev);
878
879 dev->isoc_ctl.isoc_copy = isoc_copy;
880 dev->isoc_ctl.num_bufs = num_bufs;
881
882 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
883 if (!dev->isoc_ctl.urb) {
884 em28xx_errdev("cannot alloc memory for usb buffers\n");
885 return -ENOMEM;
886 }
887
888 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
889 GFP_KERNEL);
094f9b4b 890 if (!dev->isoc_ctl.transfer_buffer) {
579f72e4
AT		 891 em28xx_errdev("cannot allocate memory for usbtransfer\n");
892 kfree(dev->isoc_ctl.urb);
893 return -ENOMEM;
894 }
895
896 dev->isoc_ctl.max_pkt_size = max_pkt_size;
897 dev->isoc_ctl.buf = NULL;
898
899 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
900
901 /* allocate urbs and transfer buffers */
902 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
903 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
904 if (!urb) {
905 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
906 em28xx_uninit_isoc(dev);
907 return -ENOMEM;
908 }
909 dev->isoc_ctl.urb[i] = urb;
910
911 dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
912 sb_size, GFP_KERNEL, &urb->transfer_dma);
913 if (!dev->isoc_ctl.transfer_buffer[i]) {
914 em28xx_err("unable to allocate %i bytes for transfer"
915 " buffer %i%s\n",
916 sb_size, i,
917 in_interrupt()?" while in int":"");
918 em28xx_uninit_isoc(dev);
919 return -ENOMEM;
920 }
921 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
922
923 /* FIXME: this is a hack - should be
924 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
925 should also be using 'desc.bInterval'
926 */
6ea54d93 927 pipe = usb_rcvisocpipe(dev->udev,
c67ec53f 928 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
6ea54d93 929
579f72e4
AT		 930 usb_fill_int_urb(urb, dev->udev, pipe,
931 dev->isoc_ctl.transfer_buffer[i], sb_size,
932 em28xx_irq_callback, dma_q, 1);
933
934 urb->number_of_packets = max_packets;
935 urb->transfer_flags = URB_ISO_ASAP;
936
937 k = 0;
938 for (j = 0; j < max_packets; j++) {
939 urb->iso_frame_desc[j].offset = k;
940 urb->iso_frame_desc[j].length =
941 dev->isoc_ctl.max_pkt_size;
942 k += dev->isoc_ctl.max_pkt_size;
943 }
944 }
945
946 init_waitqueue_head(&dma_q->wq);
947
c67ec53f 948 em28xx_capture_start(dev, 1);
579f72e4
AT		 949
950 /* submit urbs and enables IRQ */
951 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
952 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
953 if (rc) {
954 em28xx_err("submit of urb %i failed (error=%i)\n", i,
955 rc);
956 em28xx_uninit_isoc(dev);
957 return rc;
958 }
959 }
960
961 return 0;
962}
963EXPORT_SYMBOL_GPL(em28xx_init_isoc);
Linux 6.x block layer and io_uring tree(s)