projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
V4L/DVB (10833): em28xx: enable Compro VideoMate ForYou sound
[linux-2.6-block.git] / drivers / media / video / em28xx / em28xx-core.c
CommitLineData
a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
a6c2ba28 27#include <linux/usb.h>
28#include <linux/vmalloc.h>
1a23f81b 29#include <media/v4l2-common.h>
a6c2ba28 30
f7abcd38 31#include "em28xx.h"
a6c2ba28 32
33/* #define ENABLE_DEBUG_ISOC_FRAMES */
34
ff699e6b 35static unsigned int core_debug;
a1a6ee74
NS		 36module_param(core_debug, int, 0644);
37MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
a6c2ba28 38
3acf2809 39#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 40 if (core_debug) \
41 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 42 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 43
ff699e6b 44static unsigned int reg_debug;
a1a6ee74
NS		 45module_param(reg_debug, int, 0644);
46MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
a6c2ba28 47
3acf2809 48#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 49 if (reg_debug) \
50 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 51 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 52
3acf2809 53static int alt = EM28XX_PINOUT;
a6c2ba28 54module_param(alt, int, 0644);
55MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
56
579f72e4
AT		 57/* FIXME */
58#define em28xx_isocdbg(fmt, arg...) do {\
59 if (core_debug) \
60 printk(KERN_INFO "%s %s :"fmt, \
61 dev->name, __func__ , ##arg); } while (0)
62
a6c2ba28 63/*
3acf2809 64 * em28xx_read_reg_req()
a6c2ba28 65 * reads data from the usb device specifying bRequest
66 */
3acf2809 67int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28 68 char *buf, int len)
69{
9e5d6760
MCC		 70 int ret;
71 int pipe = usb_rcvctrlpipe(dev->udev, 0);
a6c2ba28 72
9f38724a 73 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 74 return -ENODEV;
75
76 if (len > URB_MAX_CTRL_SIZE)
77 return -EINVAL;
9f38724a 78
9e5d6760 79 if (reg_debug) {
a1a6ee74 80 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 81 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
82 pipe,
83 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
84 req, 0, 0,
85 reg & 0xff, reg >> 8,
86 len & 0xff, len >> 8);
87 }
a6c2ba28 88
f2a2e491 89 mutex_lock(&dev->ctrl_urb_lock);
9e5d6760 90 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 91 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 92 0x0000, reg, dev->urb_buf, len, HZ);
93 if (ret < 0) {
94 if (reg_debug)
95 printk(" failed!\n");
f2a2e491 96 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 97 return ret;
98 }
99
100 if (len)
101 memcpy(buf, dev->urb_buf, len);
a6c2ba28 102
f2a2e491
MCC		 103 mutex_unlock(&dev->ctrl_urb_lock);
104
6ea54d93 105 if (reg_debug) {
9e5d6760
MCC		 106 int byte;
107
108 printk("<<<");
6ea54d93 109 for (byte = 0; byte < len; byte++)
82ac4f87 110 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 111 printk("\n");
a6c2ba28 112 }
113
114 return ret;
115}
116
117/*
3acf2809 118 * em28xx_read_reg_req()
a6c2ba28 119 * reads data from the usb device specifying bRequest
120 */
3acf2809 121int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 122{
a6c2ba28 123 int ret;
9e5d6760 124 u8 val;
a6c2ba28 125
9e5d6760
MCC		 126 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
127 if (ret < 0)
c4a98793 128 return ret;
a6c2ba28 129
130 return val;
131}
132
3acf2809 133int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 134{
3acf2809 135 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28 136}
137
138/*
3acf2809 139 * em28xx_write_regs_req()
a6c2ba28 140 * sends data to the usb device, specifying bRequest
141 */
3acf2809 142int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28 143 int len)
144{
145 int ret;
9e5d6760 146 int pipe = usb_sndctrlpipe(dev->udev, 0);
a6c2ba28 147
9f38724a 148 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 149 return -ENODEV;
150
c4a98793 151 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 152 return -EINVAL;
9f38724a 153
a6c2ba28 154 if (reg_debug) {
9e5d6760
MCC		 155 int byte;
156
a1a6ee74 157 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 158 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
159 pipe,
160 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
161 req, 0, 0,
162 reg & 0xff, reg >> 8,
163 len & 0xff, len >> 8);
164
165 for (byte = 0; byte < len; byte++)
166 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 167 printk("\n");
a6c2ba28 168 }
169
f2a2e491 170 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 171 memcpy(dev->urb_buf, buf, len);
9e5d6760 172 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 173 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 174 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 175 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 176
89b329ef
MCC		 177 if (dev->wait_after_write)
178 msleep(dev->wait_after_write);
179
a6c2ba28 180 return ret;
181}
182
3acf2809 183int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 184{
c67ec53f
MCC		 185 int rc;
186
187 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
188
189 /* Stores GPO/GPIO values at the cache, if changed
190 Only write values should be stored, since input on a GPIO
191 register will return the input bits.
192 Not sure what happens on reading GPO register.
193 */
194 if (rc >= 0) {
6a1acc3b 195 if (reg == dev->reg_gpo_num)
c67ec53f 196 dev->reg_gpo = buf[0];
6a1acc3b 197 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 198 dev->reg_gpio = buf[0];
199 }
200
201 return rc;
a6c2ba28 202}
203
b6972489
DH		 204/* Write a single register */
205int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
206{
207 return em28xx_write_regs(dev, reg, &val, 1);
208}
209
a6c2ba28 210/*
3acf2809 211 * em28xx_write_reg_bits()
a6c2ba28 212 * sets only some bits (specified by bitmask) of a register, by first reading
213 * the actual value
214 */
532fe652 215static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28 216 u8 bitmask)
217{
218 int oldval;
219 u8 newval;
6ea54d93 220
c67ec53f 221 /* Uses cache for gpo/gpio registers */
6a1acc3b 222 if (reg == dev->reg_gpo_num)
c67ec53f 223 oldval = dev->reg_gpo;
6a1acc3b 224 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 225 oldval = dev->reg_gpio;
226 else
227 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 228
229 if (oldval < 0)
a6c2ba28 230 return oldval;
6ea54d93 231
a6c2ba28 232 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 233
3acf2809 234 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28 235}
236
35643943
MCC		 237/*
238 * em28xx_is_ac97_ready()
239 * Checks if ac97 is ready
240 */
241static int em28xx_is_ac97_ready(struct em28xx *dev)
242{
243 int ret, i;
244
245 /* Wait up to 50 ms for AC97 command to complete */
246 for (i = 0; i < 10; i++, msleep(5)) {
247 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
248 if (ret < 0)
249 return ret;
250
251 if (!(ret & 0x01))
252 return 0;
253 }
254
255 em28xx_warn("AC97 command still being executed: not handled properly!\n");
256 return -EBUSY;
257}
258
259/*
260 * em28xx_read_ac97()
261 * write a 16 bit value to the specified AC97 address (LSB first!)
262 */
531c98e7 263int em28xx_read_ac97(struct em28xx *dev, u8 reg)
35643943
MCC		 264{
265 int ret;
266 u8 addr = (reg & 0x7f) | 0x80;
267 u16 val;
268
269 ret = em28xx_is_ac97_ready(dev);
270 if (ret < 0)
271 return ret;
272
273 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
274 if (ret < 0)
275 return ret;
276
277 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
278 (u8 *)&val, sizeof(val));
279
280 if (ret < 0)
281 return ret;
282 return le16_to_cpu(val);
283}
284
a6c2ba28 285/*
3acf2809 286 * em28xx_write_ac97()
a6c2ba28 287 * write a 16 bit value to the specified AC97 address (LSB first!)
288 */
531c98e7 289int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 290{
35643943 291 int ret;
a6c2ba28 292 u8 addr = reg & 0x7f;
35643943
MCC		 293 __le16 value;
294
295 value = cpu_to_le16(val);
296
297 ret = em28xx_is_ac97_ready(dev);
298 if (ret < 0)
299 return ret;
6ea54d93 300
35643943 301 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 302 if (ret < 0)
a6c2ba28 303 return ret;
6ea54d93 304
41facaa4 305 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 306 if (ret < 0)
a6c2ba28 307 return ret;
00b8730f 308
35643943
MCC		 309 return 0;
310}
6ea54d93 311
e879b8eb
MCC		 312struct em28xx_vol_table {
313 enum em28xx_amux mux;
5faff789
MCC		 314 u8 reg;
315};
316
e879b8eb 317static struct em28xx_vol_table inputs[] = {
5faff789
MCC		 318 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
319 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
320 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
321 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
322 { EM28XX_AMUX_CD, AC97_CD_VOL },
323 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
324 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
325};
326
327static int set_ac97_input(struct em28xx *dev)
35643943 328{
5faff789
MCC		 329 int ret, i;
330 enum em28xx_amux amux = dev->ctl_ainput;
35643943 331
5faff789
MCC		 332 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
333 em28xx should point to LINE IN, while AC97 should use VIDEO
334 */
335 if (amux == EM28XX_AMUX_VIDEO2)
f1990a9c 336 amux = EM28XX_AMUX_VIDEO;
35643943 337
5faff789
MCC		 338 /* Mute all entres but the one that were selected */
339 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
e879b8eb 340 if (amux == inputs[i].mux)
5faff789
MCC		 341 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
342 else
343 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
35643943 344
5faff789
MCC		 345 if (ret < 0)
346 em28xx_warn("couldn't setup AC97 register %d\n",
347 inputs[i].reg);
348 }
349 return 0;
a6c2ba28 350}
351
00b8730f 352static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 353{
1685a6fe 354 int ret;
539c96d0
MCC		 355 u8 input;
356
505b6d0b 357 if (dev->board.is_em2800) {
5faff789 358 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
539c96d0 359 input = EM2800_AUDIO_SRC_TUNER;
5faff789
MCC		 360 else
361 input = EM2800_AUDIO_SRC_LINE;
539c96d0 362
41facaa4 363 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 364 if (ret < 0)
365 return ret;
366 }
367
505b6d0b 368 if (dev->board.has_msp34xx)
539c96d0
MCC		 369 input = EM28XX_AUDIO_SRC_TUNER;
370 else {
371 switch (dev->ctl_ainput) {
372 case EM28XX_AMUX_VIDEO:
373 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 374 break;
35643943 375 default:
539c96d0 376 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 377 break;
378 }
379 }
380
2bd1d9eb
VW		 381 if (dev->board.mute_gpio && dev->mute)
382 em28xx_gpio_set(dev, dev->board.mute_gpio);
383 else
384 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
385
41facaa4 386 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 387 if (ret < 0)
388 return ret;
00b8730f 389 msleep(5);
539c96d0 390
35643943
MCC		 391 switch (dev->audio_mode.ac97) {
392 case EM28XX_NO_AC97:
393 break;
5faff789
MCC		 394 default:
395 ret = set_ac97_input(dev);
35643943 396 }
539c96d0 397
5faff789 398 return ret;
539c96d0
MCC		 399}
400
26cdc76b 401static const struct em28xx_vol_table outputs[] = {
e879b8eb
MCC		 402 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
403 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
404 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
405 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
406 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
35ae6f04
MCC		 407};
408
3acf2809 409int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 410{
35ae6f04 411 int ret, i;
a2070c66 412 u8 xclk;
539c96d0 413
35643943
MCC		 414 if (!dev->audio_mode.has_audio)
415 return 0;
539c96d0 416
5faff789
MCC		 417 /* It is assumed that all devices use master volume for output.
418 It would be possible to use also line output.
419 */
35643943 420 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
35ae6f04
MCC		 421 /* Mute all outputs */
422 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
e879b8eb 423 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
35ae6f04
MCC		 424 if (ret < 0)
425 em28xx_warn("couldn't setup AC97 register %d\n",
e879b8eb 426 outputs[i].reg);
35ae6f04 427 }
35643943 428 }
539c96d0 429
505b6d0b 430 xclk = dev->board.xclk & 0x7f;
3abee53e 431 if (!dev->mute)
8ed06fd4 432 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
3abee53e 433
a2070c66 434 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
539c96d0
MCC		 435 if (ret < 0)
436 return ret;
3abee53e 437 msleep(10);
539c96d0
MCC		 438
439 /* Selects the proper audio input */
440 ret = em28xx_set_audio_source(dev);
a6c2ba28 441
35643943
MCC		 442 /* Sets volume */
443 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
444 int vol;
445
7e4b15e4
RK		 446 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
447 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
448 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
449
35643943
MCC		 450 /* LSB: left channel - both channels with the same level */
451 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
452
453 /* Mute device, if needed */
454 if (dev->mute)
455 vol |= 0x8000;
456
457 /* Sets volume */
e879b8eb
MCC		 458 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
459 if (dev->ctl_aoutput & outputs[i].mux)
460 ret = em28xx_write_ac97(dev, outputs[i].reg,
461 vol);
462 if (ret < 0)
463 em28xx_warn("couldn't setup AC97 register %d\n",
464 outputs[i].reg);
465 }
8866f9cf
MCC		 466
467 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
468 int sel = ac97_return_record_select(dev->ctl_aoutput);
469
a1a6ee74
NS		 470 /* Use the same input for both left and right
471 channels */
8866f9cf
MCC		 472 sel |= (sel << 8);
473
474 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
475 }
35643943 476 }
00b8730f 477
539c96d0
MCC		 478 return ret;
479}
480EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 481
35643943
MCC		 482int em28xx_audio_setup(struct em28xx *dev)
483{
484 int vid1, vid2, feat, cfg;
16c7bcad 485 u32 vid;
35643943 486
62f3e69b 487 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
35643943
MCC		 488 /* Digital only device - don't load any alsa module */
489 dev->audio_mode.has_audio = 0;
490 dev->has_audio_class = 0;
491 dev->has_alsa_audio = 0;
492 return 0;
493 }
494
495 /* If device doesn't support Usb Audio Class, use vendor class */
496 if (!dev->has_audio_class)
497 dev->has_alsa_audio = 1;
498
499 dev->audio_mode.has_audio = 1;
500
501 /* See how this device is configured */
502 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
503 if (cfg < 0)
504 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
505 else
506 em28xx_info("Config register raw data: 0x%02x\n", cfg);
507
508 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
509 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
510 em28xx_info("I2S Audio (3 sample rates)\n");
511 dev->audio_mode.i2s_3rates = 1;
512 }
513 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
514 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
515 em28xx_info("I2S Audio (5 sample rates)\n");
516 dev->audio_mode.i2s_5rates = 1;
517 }
518
de84830e
DH		 519 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
520 /* Skip the code that does AC97 vendor detection */
35643943
MCC		 521 dev->audio_mode.ac97 = EM28XX_NO_AC97;
522 goto init_audio;
523 }
524
525 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
526
527 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
528 if (vid1 < 0) {
529 /* Device likely doesn't support AC97 */
530 em28xx_warn("AC97 chip type couldn't be determined\n");
531 goto init_audio;
532 }
533
534 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
535 if (vid2 < 0)
536 goto init_audio;
537
16c7bcad
MCC		 538 vid = vid1 << 16 | vid2;
539
540 dev->audio_mode.ac97_vendor_id = vid;
541 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 542
543 feat = em28xx_read_ac97(dev, AC97_RESET);
544 if (feat < 0)
545 goto init_audio;
546
547 dev->audio_mode.ac97_feat = feat;
548 em28xx_warn("AC97 features = 0x%04x\n", feat);
549
16c7bcad
MCC		 550 /* Try to identify what audio processor we have */
551 if ((vid == 0xffffffff) && (feat == 0x6a90))
35643943 552 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
209acc02
MCC		 553 else if ((vid >> 8) == 0x838476)
554 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
35643943
MCC		 555
556init_audio:
557 /* Reports detected AC97 processor */
558 switch (dev->audio_mode.ac97) {
559 case EM28XX_NO_AC97:
560 em28xx_info("No AC97 audio processor\n");
561 break;
562 case EM28XX_AC97_EM202:
563 em28xx_info("Empia 202 AC97 audio processor detected\n");
564 break;
209acc02
MCC		 565 case EM28XX_AC97_SIGMATEL:
566 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
567 dev->audio_mode.ac97_vendor_id & 0xff);
568 break;
35643943
MCC		 569 case EM28XX_AC97_OTHER:
570 em28xx_warn("Unknown AC97 audio processor detected!\n");
571 break;
572 default:
573 break;
574 }
575
576 return em28xx_audio_analog_set(dev);
577}
578EXPORT_SYMBOL_GPL(em28xx_audio_setup);
579
3acf2809 580int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 581{
2a29a0d7
MCC		 582 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
583 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
584 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
585 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
586 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
587 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
588
589 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
590 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
591 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
592 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
593 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
594 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
595 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
a6c2ba28 596}
597
3acf2809 598int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 599{
ee6e3a86 600 int rc;
ebef13d4
DH		 601
602 if (dev->chip_id == CHIP_ID_EM2874) {
603 /* The Transport Stream Enable Register moved in em2874 */
604 if (!start) {
605 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
606 0x00,
607 EM2874_TS1_CAPTURE_ENABLE);
608 return rc;
609 }
610
611 /* Enable Transport Stream */
612 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
613 EM2874_TS1_CAPTURE_ENABLE,
614 EM2874_TS1_CAPTURE_ENABLE);
615 return rc;
616 }
617
618
a6c2ba28 619 /* FIXME: which is the best order? */
620 /* video registers are sampled by VREF */
41facaa4 621 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 622 start ? 0x10 : 0x00, 0x10);
623 if (rc < 0)
624 return rc;
625
626 if (!start) {
627 /* disable video capture */
2a29a0d7 628 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
102a0b08 629 return rc;
ee6e3a86
MCC		 630 }
631
a6c2ba28 632 /* enable video capture */
2a29a0d7 633 rc = em28xx_write_reg(dev, 0x48, 0x00);
102a0b08 634
ee6e3a86 635 if (dev->mode == EM28XX_ANALOG_MODE)
2a29a0d7 636 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
ee6e3a86 637 else
2a29a0d7 638 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
ee6e3a86 639
6ea54d93 640 msleep(6);
ee6e3a86
MCC		 641
642 return rc;
a6c2ba28 643}
644
bddcf633 645int em28xx_set_outfmt(struct em28xx *dev)
a6c2ba28 646{
bddcf633
MCC		 647 int ret;
648
649 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
650 dev->format->reg | 0x20, 0x3f);
651 if (ret < 0)
652 return ret;
653
654 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, 0x10);
655 if (ret < 0)
656 return ret;
657
2a29a0d7 658 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, 0x11);
a6c2ba28 659}
660
adcb0fa2
AB		 661static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
662 u8 ymin, u8 ymax)
a6c2ba28 663{
6ea54d93
DSL		 664 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
665 xmin, ymin, xmax, ymax);
a6c2ba28 666
41facaa4
MCC		 667 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
668 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
669 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
670 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28 671}
672
adcb0fa2 673static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28 674 u16 width, u16 height)
675{
676 u8 cwidth = width;
677 u8 cheight = height;
678 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
679
6ea54d93
DSL		 680 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
681 (width | (overflow & 2) << 7),
a6c2ba28 682 (height | (overflow & 1) << 8));
683
41facaa4
MCC		 684 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
685 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
686 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
687 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
688 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28 689}
690
adcb0fa2 691static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 692{
52c02fcd
SS		 693 u8 mode;
694 /* the em2800 scaler only supports scaling down to 50% */
505b6d0b 695 if (dev->board.is_em2800)
52c02fcd
SS		 696 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
697 else {
698 u8 buf[2];
699 buf[0] = h;
700 buf[1] = h >> 8;
41facaa4 701 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
52c02fcd
SS		 702 buf[0] = v;
703 buf[1] = v >> 8;
41facaa4 704 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 705 /* it seems that both H and V scalers must be active
706 to work correctly */
a1a6ee74 707 mode = (h || v) ? 0x30 : 0x00;
74458e6c 708 }
41facaa4 709 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28 710}
711
712/* FIXME: this only function read values from dev */
3acf2809 713int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28 714{
715 int width, height;
716 width = norm_maxw(dev);
717 height = norm_maxh(dev) >> 1;
718
bddcf633 719 em28xx_set_outfmt(dev);
3acf2809
MCC		 720 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
721 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
722 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28 723}
724
3acf2809 725int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28 726{
727 int errCode, prev_alt = dev->alt;
3687e1e6 728 int i;
44dc733c 729 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 730
2c4a07b2 731 /* When image size is bigger than a certain value,
3687e1e6
MCC		 732 the frame size should be increased, otherwise, only
733 green screen will be received.
734 */
44dc733c 735 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 736 min_pkt_size *= 2;
737
2c4a07b2
SS		 738 for (i = 0; i < dev->num_alt; i++) {
739 /* stop when the selected alt setting offers enough bandwidth */
740 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
741 dev->alt = i;
3687e1e6 742 break;
2c4a07b2
SS		 743 /* otherwise make sure that we end up with the maximum bandwidth
744 because the min_pkt_size equation might be wrong...
745 */
746 } else if (dev->alt_max_pkt_size[i] >
747 dev->alt_max_pkt_size[dev->alt])
748 dev->alt = i;
749 }
a6c2ba28 750
751 if (dev->alt != prev_alt) {
3687e1e6
MCC		 752 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
753 min_pkt_size, dev->alt);
a6c2ba28 754 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 755 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
756 dev->alt, dev->max_pkt_size);
a6c2ba28 757 errCode = usb_set_interface(dev->udev, 0, dev->alt);
758 if (errCode < 0) {
6ea54d93 759 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 760 dev->alt, errCode);
a6c2ba28 761 return errCode;
762 }
763 }
764 return 0;
765}
579f72e4 766
c67ec53f
MCC		 767int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
768{
769 int rc = 0;
770
771 if (!gpio)
772 return rc;
773
2fe3e2ee
MCC		 774 if (dev->mode != EM28XX_SUSPEND) {
775 em28xx_write_reg(dev, 0x48, 0x00);
776 if (dev->mode == EM28XX_ANALOG_MODE)
777 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
778 else
779 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
780 msleep(6);
781 }
c67ec53f
MCC		 782
783 /* Send GPIO reset sequences specified at board entry */
784 while (gpio->sleep >= 0) {
785 if (gpio->reg >= 0) {
786 rc = em28xx_write_reg_bits(dev,
787 gpio->reg,
788 gpio->val,
789 gpio->mask);
790 if (rc < 0)
791 return rc;
792 }
793 if (gpio->sleep > 0)
794 msleep(gpio->sleep);
795
796 gpio++;
797 }
798 return rc;
799}
800
801int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
802{
803 if (dev->mode == set_mode)
804 return 0;
805
2fe3e2ee 806 if (set_mode == EM28XX_SUSPEND) {
c67ec53f 807 dev->mode = set_mode;
2fe3e2ee
MCC		 808
809 /* FIXME: add suspend support for ac97 */
810
811 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
c67ec53f
MCC		 812 }
813
814 dev->mode = set_mode;
815
816 if (dev->mode == EM28XX_DIGITAL_MODE)
f502e861 817 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
c67ec53f 818 else
f502e861 819 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
c67ec53f
MCC		 820}
821EXPORT_SYMBOL_GPL(em28xx_set_mode);
822
579f72e4
AT		 823/* ------------------------------------------------------------------
824 URB control
825 ------------------------------------------------------------------*/
826
827/*
828 * IRQ callback, called by URB callback
829 */
830static void em28xx_irq_callback(struct urb *urb)
831{
832 struct em28xx_dmaqueue *dma_q = urb->context;
833 struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
834 int rc, i;
835
aa5a1821
RK		 836 switch (urb->status) {
837 case 0: /* success */
838 case -ETIMEDOUT: /* NAK */
839 break;
840 case -ECONNRESET: /* kill */
841 case -ENOENT:
842 case -ESHUTDOWN:
843 return;
844 default: /* error */
845 em28xx_isocdbg("urb completition error %d.\n", urb->status);
846 break;
847 }
848
579f72e4
AT		 849 /* Copy data from URB */
850 spin_lock(&dev->slock);
851 rc = dev->isoc_ctl.isoc_copy(dev, urb);
852 spin_unlock(&dev->slock);
853
854 /* Reset urb buffers */
855 for (i = 0; i < urb->number_of_packets; i++) {
856 urb->iso_frame_desc[i].status = 0;
857 urb->iso_frame_desc[i].actual_length = 0;
858 }
859 urb->status = 0;
860
861 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
862 if (urb->status) {
4269a8ee
DH		 863 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
864 urb->status);
579f72e4
AT		 865 }
866}
867
868/*
869 * Stop and Deallocate URBs
870 */
871void em28xx_uninit_isoc(struct em28xx *dev)
872{
873 struct urb *urb;
874 int i;
875
876 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
877
878 dev->isoc_ctl.nfields = -1;
879 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
880 urb = dev->isoc_ctl.urb[i];
881 if (urb) {
9c06210b
RK		 882 if (!irqs_disabled())
883 usb_kill_urb(urb);
884 else
885 usb_unlink_urb(urb);
886
579f72e4
AT		 887 if (dev->isoc_ctl.transfer_buffer[i]) {
888 usb_buffer_free(dev->udev,
6ea54d93
DSL		 889 urb->transfer_buffer_length,
890 dev->isoc_ctl.transfer_buffer[i],
891 urb->transfer_dma);
579f72e4
AT		 892 }
893 usb_free_urb(urb);
894 dev->isoc_ctl.urb[i] = NULL;
895 }
896 dev->isoc_ctl.transfer_buffer[i] = NULL;
897 }
898
899 kfree(dev->isoc_ctl.urb);
900 kfree(dev->isoc_ctl.transfer_buffer);
901
902 dev->isoc_ctl.urb = NULL;
903 dev->isoc_ctl.transfer_buffer = NULL;
904 dev->isoc_ctl.num_bufs = 0;
905
906 em28xx_capture_start(dev, 0);
907}
908EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
909
910/*
911 * Allocate URBs and start IRQ
912 */
913int em28xx_init_isoc(struct em28xx *dev, int max_packets,
914 int num_bufs, int max_pkt_size,
c67ec53f 915 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
579f72e4
AT		 916{
917 struct em28xx_dmaqueue *dma_q = &dev->vidq;
918 int i;
919 int sb_size, pipe;
920 struct urb *urb;
921 int j, k;
922 int rc;
923
924 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
925
926 /* De-allocates all pending stuff */
927 em28xx_uninit_isoc(dev);
928
929 dev->isoc_ctl.isoc_copy = isoc_copy;
930 dev->isoc_ctl.num_bufs = num_bufs;
931
932 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
933 if (!dev->isoc_ctl.urb) {
934 em28xx_errdev("cannot alloc memory for usb buffers\n");
935 return -ENOMEM;
936 }
937
938 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
939 GFP_KERNEL);
094f9b4b 940 if (!dev->isoc_ctl.transfer_buffer) {
579f72e4
AT		 941 em28xx_errdev("cannot allocate memory for usbtransfer\n");
942 kfree(dev->isoc_ctl.urb);
943 return -ENOMEM;
944 }
945
946 dev->isoc_ctl.max_pkt_size = max_pkt_size;
947 dev->isoc_ctl.buf = NULL;
948
949 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
950
951 /* allocate urbs and transfer buffers */
952 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
953 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
954 if (!urb) {
955 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
956 em28xx_uninit_isoc(dev);
957 return -ENOMEM;
958 }
959 dev->isoc_ctl.urb[i] = urb;
960
961 dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
962 sb_size, GFP_KERNEL, &urb->transfer_dma);
963 if (!dev->isoc_ctl.transfer_buffer[i]) {
964 em28xx_err("unable to allocate %i bytes for transfer"
965 " buffer %i%s\n",
966 sb_size, i,
a1a6ee74 967 in_interrupt() ? " while in int" : "");
579f72e4
AT		 968 em28xx_uninit_isoc(dev);
969 return -ENOMEM;
970 }
971 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
972
973 /* FIXME: this is a hack - should be
974 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
975 should also be using 'desc.bInterval'
976 */
6ea54d93 977 pipe = usb_rcvisocpipe(dev->udev,
c67ec53f 978 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
6ea54d93 979
579f72e4
AT		 980 usb_fill_int_urb(urb, dev->udev, pipe,
981 dev->isoc_ctl.transfer_buffer[i], sb_size,
982 em28xx_irq_callback, dma_q, 1);
983
984 urb->number_of_packets = max_packets;
985 urb->transfer_flags = URB_ISO_ASAP;
986
987 k = 0;
988 for (j = 0; j < max_packets; j++) {
989 urb->iso_frame_desc[j].offset = k;
990 urb->iso_frame_desc[j].length =
991 dev->isoc_ctl.max_pkt_size;
992 k += dev->isoc_ctl.max_pkt_size;
993 }
994 }
995
996 init_waitqueue_head(&dma_q->wq);
997
c67ec53f 998 em28xx_capture_start(dev, 1);
579f72e4
AT		 999
1000 /* submit urbs and enables IRQ */
1001 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1002 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
1003 if (rc) {
1004 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1005 rc);
1006 em28xx_uninit_isoc(dev);
1007 return rc;
1008 }
1009 }
1010
1011 return 0;
1012}
1013EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1a23f81b
MCC		 1014
1015/*
1016 * em28xx_wake_i2c()
1017 * configure i2c attached devices
1018 */
1019void em28xx_wake_i2c(struct em28xx *dev)
1020{
1021 struct v4l2_routing route;
1022 int zero = 0;
1023
1024 route.input = INPUT(dev->ctl_input)->vmux;
1025 route.output = 0;
1026 em28xx_i2c_call_clients(dev, VIDIOC_INT_RESET, &zero);
1027 em28xx_i2c_call_clients(dev, VIDIOC_INT_S_VIDEO_ROUTING, &route);
1028 em28xx_i2c_call_clients(dev, VIDIOC_STREAMON, NULL);
1029}
1030
1031/*
1032 * Device control list
1033 */
1034
1035static LIST_HEAD(em28xx_devlist);
1036static DEFINE_MUTEX(em28xx_devlist_mutex);
1037
bec43661 1038struct em28xx *em28xx_get_device(int minor,
1a23f81b
MCC		 1039 enum v4l2_buf_type *fh_type,
1040 int *has_radio)
1041{
1042 struct em28xx *h, *dev = NULL;
1a23f81b
MCC		 1043
1044 *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1045 *has_radio = 0;
1046
1047 mutex_lock(&em28xx_devlist_mutex);
1048 list_for_each_entry(h, &em28xx_devlist, devlist) {
1049 if (h->vdev->minor == minor)
1050 dev = h;
1051 if (h->vbi_dev->minor == minor) {
1052 dev = h;
1053 *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
1054 }
1055 if (h->radio_dev &&
1056 h->radio_dev->minor == minor) {
1057 dev = h;
1058 *has_radio = 1;
1059 }
1060 }
1061 mutex_unlock(&em28xx_devlist_mutex);
1062
1063 return dev;
1064}
1065
1066/*
1067 * em28xx_realease_resources()
1068 * unregisters the v4l2,i2c and usb devices
1069 * called when the device gets disconected or at module unload
1070*/
1071void em28xx_remove_from_devlist(struct em28xx *dev)
1072{
1073 mutex_lock(&em28xx_devlist_mutex);
1074 list_del(&dev->devlist);
1075 mutex_unlock(&em28xx_devlist_mutex);
1076};
1077
1078void em28xx_add_into_devlist(struct em28xx *dev)
1079{
1080 mutex_lock(&em28xx_devlist_mutex);
1081 list_add_tail(&dev->devlist, &em28xx_devlist);
1082 mutex_unlock(&em28xx_devlist_mutex);
1083};
1084
1085/*
1086 * Extension interface
1087 */
1088
1089static LIST_HEAD(em28xx_extension_devlist);
1090static DEFINE_MUTEX(em28xx_extension_devlist_lock);
1091
1092int em28xx_register_extension(struct em28xx_ops *ops)
1093{
1094 struct em28xx *dev = NULL;
1095
1096 mutex_lock(&em28xx_devlist_mutex);
1097 mutex_lock(&em28xx_extension_devlist_lock);
1098 list_add_tail(&ops->next, &em28xx_extension_devlist);
1099 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1100 if (dev)
1101 ops->init(dev);
1102 }
1103 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1104 mutex_unlock(&em28xx_extension_devlist_lock);
1105 mutex_unlock(&em28xx_devlist_mutex);
1106 return 0;
1107}
1108EXPORT_SYMBOL(em28xx_register_extension);
1109
1110void em28xx_unregister_extension(struct em28xx_ops *ops)
1111{
1112 struct em28xx *dev = NULL;
1113
1114 mutex_lock(&em28xx_devlist_mutex);
1115 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1116 if (dev)
1117 ops->fini(dev);
1118 }
1119
1120 mutex_lock(&em28xx_extension_devlist_lock);
1121 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1122 list_del(&ops->next);
1123 mutex_unlock(&em28xx_extension_devlist_lock);
1124 mutex_unlock(&em28xx_devlist_mutex);
1125}
1126EXPORT_SYMBOL(em28xx_unregister_extension);
1127
1128void em28xx_init_extension(struct em28xx *dev)
1129{
1130 struct em28xx_ops *ops = NULL;
1131
1132 mutex_lock(&em28xx_extension_devlist_lock);
1133 if (!list_empty(&em28xx_extension_devlist)) {
1134 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1135 if (ops->init)
1136 ops->init(dev);
1137 }
1138 }
1139 mutex_unlock(&em28xx_extension_devlist_lock);
1140}
1141
1142void em28xx_close_extension(struct em28xx *dev)
1143{
1144 struct em28xx_ops *ops = NULL;
1145
1146 mutex_lock(&em28xx_extension_devlist_lock);
1147 if (!list_empty(&em28xx_extension_devlist)) {
1148 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1149 if (ops->fini)
1150 ops->fini(dev);
1151 }
1152 }
1153 mutex_unlock(&em28xx_extension_devlist_lock);
1154}
Linux 6.x block layer and io_uring tree(s)