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V4L/DVB (9652): em28xx: merge AC97 vendor id's into a single var
[linux-2.6-block.git] / drivers / media / video / em28xx / em28xx-core.c
CommitLineData
a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
a6c2ba28 27#include <linux/usb.h>
28#include <linux/vmalloc.h>
29
f7abcd38 30#include "em28xx.h"
a6c2ba28 31
32/* #define ENABLE_DEBUG_ISOC_FRAMES */
33
ff699e6b 34static unsigned int core_debug;
a6c2ba28 35module_param(core_debug,int,0644);
36MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
37
3acf2809 38#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 39 if (core_debug) \
40 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 41 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 42
ff699e6b 43static unsigned int reg_debug;
a6c2ba28 44module_param(reg_debug,int,0644);
45MODULE_PARM_DESC(reg_debug,"enable debug messages [URB reg]");
46
3acf2809 47#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 48 if (reg_debug) \
49 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 50 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 51
3acf2809 52static int alt = EM28XX_PINOUT;
a6c2ba28 53module_param(alt, int, 0644);
54MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
55
579f72e4
AT		 56/* FIXME */
57#define em28xx_isocdbg(fmt, arg...) do {\
58 if (core_debug) \
59 printk(KERN_INFO "%s %s :"fmt, \
60 dev->name, __func__ , ##arg); } while (0)
61
a6c2ba28 62/*
3acf2809 63 * em28xx_read_reg_req()
a6c2ba28 64 * reads data from the usb device specifying bRequest
65 */
3acf2809 66int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28 67 char *buf, int len)
68{
69 int ret, byte;
70
9f38724a 71 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 72 return -ENODEV;
73
74 if (len > URB_MAX_CTRL_SIZE)
75 return -EINVAL;
9f38724a 76
3acf2809 77 em28xx_regdbg("req=%02x, reg=%02x ", req, reg);
a6c2ba28 78
f2a2e491 79 mutex_lock(&dev->ctrl_urb_lock);
a6c2ba28 80 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
81 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 82 0x0000, reg, dev->urb_buf, len, HZ);
83 if (ret < 0) {
84 if (reg_debug)
85 printk(" failed!\n");
f2a2e491 86 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 87 return ret;
88 }
89
90 if (len)
91 memcpy(buf, dev->urb_buf, len);
a6c2ba28 92
f2a2e491
MCC		 93 mutex_unlock(&dev->ctrl_urb_lock);
94
6ea54d93 95 if (reg_debug) {
c4a98793 96 printk("%02x values: ", ret);
6ea54d93 97 for (byte = 0; byte < len; byte++)
82ac4f87 98 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 99 printk("\n");
a6c2ba28 100 }
101
102 return ret;
103}
104
105/*
3acf2809 106 * em28xx_read_reg_req()
a6c2ba28 107 * reads data from the usb device specifying bRequest
108 */
3acf2809 109int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 110{
111 u8 val;
112 int ret;
113
9f38724a
MR		 114 if (dev->state & DEV_DISCONNECTED)
115 return(-ENODEV);
116
3acf2809 117 em28xx_regdbg("req=%02x, reg=%02x:", req, reg);
a6c2ba28 118
f2a2e491 119 mutex_lock(&dev->ctrl_urb_lock);
a6c2ba28 120 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
121 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 122 0x0000, reg, dev->urb_buf, 1, HZ);
f2a2e491
MCC		 123 val = dev->urb_buf[0];
124 mutex_unlock(&dev->ctrl_urb_lock);
125
c4a98793
MCC		 126 if (ret < 0) {
127 printk(" failed!\n");
128 return ret;
129 }
a6c2ba28 130
c4a98793
MCC		 131 if (reg_debug)
132 printk("%02x\n", (unsigned char) val);
a6c2ba28 133
134 return val;
135}
136
3acf2809 137int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 138{
3acf2809 139 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28 140}
141
142/*
3acf2809 143 * em28xx_write_regs_req()
a6c2ba28 144 * sends data to the usb device, specifying bRequest
145 */
3acf2809 146int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28 147 int len)
148{
149 int ret;
150
9f38724a 151 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 152 return -ENODEV;
153
c4a98793 154 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 155 return -EINVAL;
9f38724a 156
3acf2809 157 em28xx_regdbg("req=%02x reg=%02x:", req, reg);
a6c2ba28 158 if (reg_debug) {
159 int i;
160 for (i = 0; i < len; ++i)
82ac4f87
MCC		 161 printk(" %02x", (unsigned char)buf[i]);
162 printk("\n");
a6c2ba28 163 }
164
f2a2e491 165 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 166 memcpy(dev->urb_buf, buf, len);
a6c2ba28 167 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), req,
168 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 169 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 170 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 171
89b329ef
MCC		 172 if (dev->wait_after_write)
173 msleep(dev->wait_after_write);
174
a6c2ba28 175 return ret;
176}
177
3acf2809 178int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 179{
c67ec53f
MCC		 180 int rc;
181
182 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
183
184 /* Stores GPO/GPIO values at the cache, if changed
185 Only write values should be stored, since input on a GPIO
186 register will return the input bits.
187 Not sure what happens on reading GPO register.
188 */
189 if (rc >= 0) {
6a1acc3b 190 if (reg == dev->reg_gpo_num)
c67ec53f 191 dev->reg_gpo = buf[0];
6a1acc3b 192 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 193 dev->reg_gpio = buf[0];
194 }
195
196 return rc;
a6c2ba28 197}
198
199/*
3acf2809 200 * em28xx_write_reg_bits()
a6c2ba28 201 * sets only some bits (specified by bitmask) of a register, by first reading
202 * the actual value
203 */
532fe652 204static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28 205 u8 bitmask)
206{
207 int oldval;
208 u8 newval;
6ea54d93 209
c67ec53f 210 /* Uses cache for gpo/gpio registers */
6a1acc3b 211 if (reg == dev->reg_gpo_num)
c67ec53f 212 oldval = dev->reg_gpo;
6a1acc3b 213 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 214 oldval = dev->reg_gpio;
215 else
216 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 217
218 if (oldval < 0)
a6c2ba28 219 return oldval;
6ea54d93 220
a6c2ba28 221 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 222
3acf2809 223 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28 224}
225
35643943
MCC		 226/*
227 * em28xx_is_ac97_ready()
228 * Checks if ac97 is ready
229 */
230static int em28xx_is_ac97_ready(struct em28xx *dev)
231{
232 int ret, i;
233
234 /* Wait up to 50 ms for AC97 command to complete */
235 for (i = 0; i < 10; i++, msleep(5)) {
236 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
237 if (ret < 0)
238 return ret;
239
240 if (!(ret & 0x01))
241 return 0;
242 }
243
244 em28xx_warn("AC97 command still being executed: not handled properly!\n");
245 return -EBUSY;
246}
247
248/*
249 * em28xx_read_ac97()
250 * write a 16 bit value to the specified AC97 address (LSB first!)
251 */
252static int em28xx_read_ac97(struct em28xx *dev, u8 reg)
253{
254 int ret;
255 u8 addr = (reg & 0x7f) | 0x80;
256 u16 val;
257
258 ret = em28xx_is_ac97_ready(dev);
259 if (ret < 0)
260 return ret;
261
262 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
263 if (ret < 0)
264 return ret;
265
266 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
267 (u8 *)&val, sizeof(val));
268
269 if (ret < 0)
270 return ret;
271 return le16_to_cpu(val);
272}
273
a6c2ba28 274/*
3acf2809 275 * em28xx_write_ac97()
a6c2ba28 276 * write a 16 bit value to the specified AC97 address (LSB first!)
277 */
35643943 278static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 279{
35643943 280 int ret;
a6c2ba28 281 u8 addr = reg & 0x7f;
35643943
MCC		 282 __le16 value;
283
284 value = cpu_to_le16(val);
285
286 ret = em28xx_is_ac97_ready(dev);
287 if (ret < 0)
288 return ret;
6ea54d93 289
35643943 290 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 291 if (ret < 0)
a6c2ba28 292 return ret;
6ea54d93 293
41facaa4 294 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 295 if (ret < 0)
a6c2ba28 296 return ret;
00b8730f 297
35643943
MCC		 298 return 0;
299}
6ea54d93 300
35643943
MCC		 301static int set_ac97_em202_input(struct em28xx *dev)
302{
303 int ret;
304 u16 enable = 0x0808; /* 12 dB attenuation Left/Right */
305 u16 disable = 0x8808; /* bit 15 - mute volumme */
306 u16 video, line;
307
308 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO) {
309 video = enable;
310 line = disable;
311 } else {
312 video = disable;
313 line = enable;
a6c2ba28 314 }
35643943
MCC		 315
316 /* Sets em202 AC97 mixer registers */
317 ret = em28xx_write_ac97(dev, AC97_VIDEO_VOL, video);
318 if (ret < 0)
319 return ret;
320
321 ret = em28xx_write_ac97(dev, AC97_LINEIN_VOL, line);
322
323 return ret;
a6c2ba28 324}
325
00b8730f 326static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 327{
1685a6fe 328 int ret;
539c96d0
MCC		 329 u8 input;
330
331 if (dev->is_em2800) {
332 if (dev->ctl_ainput)
333 input = EM2800_AUDIO_SRC_LINE;
334 else
335 input = EM2800_AUDIO_SRC_TUNER;
336
41facaa4 337 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 338 if (ret < 0)
339 return ret;
340 }
341
342 if (dev->has_msp34xx)
343 input = EM28XX_AUDIO_SRC_TUNER;
344 else {
345 switch (dev->ctl_ainput) {
346 case EM28XX_AMUX_VIDEO:
347 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 348 break;
35643943 349 default:
539c96d0 350 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 351 break;
352 }
353 }
354
41facaa4 355 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 356 if (ret < 0)
357 return ret;
00b8730f 358 msleep(5);
539c96d0 359
35643943
MCC		 360 switch (dev->audio_mode.ac97) {
361 case EM28XX_NO_AC97:
362 break;
363 case EM28XX_AC97_OTHER:
364 /* We don't know how to handle this chip.
365 Let's hope it is close enough to em202 to work
366 */
367 case EM28XX_AC97_EM202:
368 ret = set_ac97_em202_input(dev);
369 break;
370 }
539c96d0 371
35643943 372 return 0;
539c96d0
MCC		 373}
374
3acf2809 375int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 376{
539c96d0 377 int ret;
3abee53e 378 u8 xclk = 0x07;
539c96d0 379
35643943
MCC		 380 if (!dev->audio_mode.has_audio)
381 return 0;
539c96d0 382
35643943
MCC		 383 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
384 /* Mute */
385 ret = em28xx_write_ac97(dev, AC97_MASTER_VOL, 0x8000);
00b8730f 386
35643943
MCC		 387 if (ret < 0)
388 return ret;
389 }
539c96d0 390
3abee53e
MCC		 391 if (dev->has_12mhz_i2s)
392 xclk |= 0x20;
393
394 if (!dev->mute)
395 xclk |= 0x80;
396
41facaa4 397 ret = em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, xclk, 0xa7);
539c96d0
MCC		 398 if (ret < 0)
399 return ret;
3abee53e 400 msleep(10);
539c96d0
MCC		 401
402 /* Selects the proper audio input */
403 ret = em28xx_set_audio_source(dev);
a6c2ba28 404
35643943
MCC		 405 /* Sets volume */
406 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
407 int vol;
408
409 /* LSB: left channel - both channels with the same level */
410 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
411
412 /* Mute device, if needed */
413 if (dev->mute)
414 vol |= 0x8000;
415
416 /* Sets volume */
417 ret = em28xx_write_ac97(dev, AC97_MASTER_VOL, vol);
418 }
00b8730f 419
539c96d0
MCC		 420 return ret;
421}
422EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 423
35643943
MCC		 424int em28xx_audio_setup(struct em28xx *dev)
425{
426 int vid1, vid2, feat, cfg;
16c7bcad 427 u32 vid;
35643943
MCC		 428
429 if (dev->chip_id == CHIP_ID_EM2874) {
430 /* Digital only device - don't load any alsa module */
431 dev->audio_mode.has_audio = 0;
432 dev->has_audio_class = 0;
433 dev->has_alsa_audio = 0;
434 return 0;
435 }
436
437 /* If device doesn't support Usb Audio Class, use vendor class */
438 if (!dev->has_audio_class)
439 dev->has_alsa_audio = 1;
440
441 dev->audio_mode.has_audio = 1;
442
443 /* See how this device is configured */
444 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
445 if (cfg < 0)
446 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
447 else
448 em28xx_info("Config register raw data: 0x%02x\n", cfg);
449
450 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
451 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
452 em28xx_info("I2S Audio (3 sample rates)\n");
453 dev->audio_mode.i2s_3rates = 1;
454 }
455 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
456 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
457 em28xx_info("I2S Audio (5 sample rates)\n");
458 dev->audio_mode.i2s_5rates = 1;
459 }
460
461 if (!(cfg & EM28XX_CHIPCFG_AC97)) {
462 dev->audio_mode.ac97 = EM28XX_NO_AC97;
463 goto init_audio;
464 }
465
466 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
467
468 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
469 if (vid1 < 0) {
470 /* Device likely doesn't support AC97 */
471 em28xx_warn("AC97 chip type couldn't be determined\n");
472 goto init_audio;
473 }
474
475 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
476 if (vid2 < 0)
477 goto init_audio;
478
16c7bcad
MCC		 479 vid = vid1 << 16 | vid2;
480
481 dev->audio_mode.ac97_vendor_id = vid;
482 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 483
484 feat = em28xx_read_ac97(dev, AC97_RESET);
485 if (feat < 0)
486 goto init_audio;
487
488 dev->audio_mode.ac97_feat = feat;
489 em28xx_warn("AC97 features = 0x%04x\n", feat);
490
16c7bcad
MCC		 491 /* Try to identify what audio processor we have */
492 if ((vid == 0xffffffff) && (feat == 0x6a90))
35643943
MCC		 493 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
494
495init_audio:
496 /* Reports detected AC97 processor */
497 switch (dev->audio_mode.ac97) {
498 case EM28XX_NO_AC97:
499 em28xx_info("No AC97 audio processor\n");
500 break;
501 case EM28XX_AC97_EM202:
502 em28xx_info("Empia 202 AC97 audio processor detected\n");
503 break;
504 case EM28XX_AC97_OTHER:
505 em28xx_warn("Unknown AC97 audio processor detected!\n");
506 break;
507 default:
508 break;
509 }
510
511 return em28xx_audio_analog_set(dev);
512}
513EXPORT_SYMBOL_GPL(em28xx_audio_setup);
514
3acf2809 515int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 516{
41facaa4
MCC		 517 em28xx_write_regs(dev, EM28XX_R20_YGAIN, "\x10", 1); /* contrast */
518 em28xx_write_regs(dev, EM28XX_R21_YOFFSET, "\x00", 1); /* brightness */
519 em28xx_write_regs(dev, EM28XX_R22_UVGAIN, "\x10", 1); /* saturation */
520 em28xx_write_regs(dev, EM28XX_R23_UOFFSET, "\x00", 1);
521 em28xx_write_regs(dev, EM28XX_R24_VOFFSET, "\x00", 1);
522 em28xx_write_regs(dev, EM28XX_R25_SHARPNESS, "\x00", 1);
523
524 em28xx_write_regs(dev, EM28XX_R14_GAMMA, "\x20", 1);
525 em28xx_write_regs(dev, EM28XX_R15_RGAIN, "\x20", 1);
526 em28xx_write_regs(dev, EM28XX_R16_GGAIN, "\x20", 1);
527 em28xx_write_regs(dev, EM28XX_R17_BGAIN, "\x20", 1);
528 em28xx_write_regs(dev, EM28XX_R18_ROFFSET, "\x00", 1);
529 em28xx_write_regs(dev, EM28XX_R19_GOFFSET, "\x00", 1);
530 return em28xx_write_regs(dev, EM28XX_R1A_BOFFSET, "\x00", 1);
a6c2ba28 531}
532
3acf2809 533int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 534{
ee6e3a86 535 int rc;
ebef13d4
DH		 536
537 if (dev->chip_id == CHIP_ID_EM2874) {
538 /* The Transport Stream Enable Register moved in em2874 */
539 if (!start) {
540 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
541 0x00,
542 EM2874_TS1_CAPTURE_ENABLE);
543 return rc;
544 }
545
546 /* Enable Transport Stream */
547 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
548 EM2874_TS1_CAPTURE_ENABLE,
549 EM2874_TS1_CAPTURE_ENABLE);
550 return rc;
551 }
552
553
a6c2ba28 554 /* FIXME: which is the best order? */
555 /* video registers are sampled by VREF */
41facaa4 556 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 557 start ? 0x10 : 0x00, 0x10);
558 if (rc < 0)
559 return rc;
560
561 if (!start) {
562 /* disable video capture */
41facaa4 563 rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x27", 1);
102a0b08 564 return rc;
ee6e3a86
MCC		 565 }
566
a6c2ba28 567 /* enable video capture */
ee6e3a86 568 rc = em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
102a0b08 569
ee6e3a86 570 if (dev->mode == EM28XX_ANALOG_MODE)
41facaa4 571 rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x67", 1);
ee6e3a86 572 else
41facaa4 573 rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x37", 1);
ee6e3a86 574
6ea54d93 575 msleep(6);
ee6e3a86
MCC		 576
577 return rc;
a6c2ba28 578}
579
3acf2809 580int em28xx_outfmt_set_yuv422(struct em28xx *dev)
a6c2ba28 581{
41facaa4
MCC		 582 em28xx_write_regs(dev, EM28XX_R27_OUTFMT, "\x34", 1);
583 em28xx_write_regs(dev, EM28XX_R10_VINMODE, "\x10", 1);
584 return em28xx_write_regs(dev, EM28XX_R11_VINCTRL, "\x11", 1);
a6c2ba28 585}
586
adcb0fa2
AB		 587static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
588 u8 ymin, u8 ymax)
a6c2ba28 589{
6ea54d93
DSL		 590 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
591 xmin, ymin, xmax, ymax);
a6c2ba28 592
41facaa4
MCC		 593 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
594 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
595 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
596 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28 597}
598
adcb0fa2 599static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28 600 u16 width, u16 height)
601{
602 u8 cwidth = width;
603 u8 cheight = height;
604 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
605
6ea54d93
DSL		 606 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
607 (width | (overflow & 2) << 7),
a6c2ba28 608 (height | (overflow & 1) << 8));
609
41facaa4
MCC		 610 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
611 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
612 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
613 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
614 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28 615}
616
adcb0fa2 617static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 618{
52c02fcd
SS		 619 u8 mode;
620 /* the em2800 scaler only supports scaling down to 50% */
6ea54d93 621 if (dev->is_em2800)
52c02fcd
SS		 622 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
623 else {
624 u8 buf[2];
625 buf[0] = h;
626 buf[1] = h >> 8;
41facaa4 627 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
52c02fcd
SS		 628 buf[0] = v;
629 buf[1] = v >> 8;
41facaa4 630 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 631 /* it seems that both H and V scalers must be active
632 to work correctly */
52c02fcd 633 mode = (h || v)? 0x30: 0x00;
74458e6c 634 }
41facaa4 635 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28 636}
637
638/* FIXME: this only function read values from dev */
3acf2809 639int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28 640{
641 int width, height;
642 width = norm_maxw(dev);
643 height = norm_maxh(dev) >> 1;
644
3acf2809
MCC		 645 em28xx_outfmt_set_yuv422(dev);
646 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
647 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
648 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28 649}
650
3acf2809 651int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28 652{
653 int errCode, prev_alt = dev->alt;
3687e1e6 654 int i;
44dc733c 655 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 656
2c4a07b2 657 /* When image size is bigger than a certain value,
3687e1e6
MCC		 658 the frame size should be increased, otherwise, only
659 green screen will be received.
660 */
44dc733c 661 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 662 min_pkt_size *= 2;
663
2c4a07b2
SS		 664 for (i = 0; i < dev->num_alt; i++) {
665 /* stop when the selected alt setting offers enough bandwidth */
666 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
667 dev->alt = i;
3687e1e6 668 break;
2c4a07b2
SS		 669 /* otherwise make sure that we end up with the maximum bandwidth
670 because the min_pkt_size equation might be wrong...
671 */
672 } else if (dev->alt_max_pkt_size[i] >
673 dev->alt_max_pkt_size[dev->alt])
674 dev->alt = i;
675 }
a6c2ba28 676
677 if (dev->alt != prev_alt) {
3687e1e6
MCC		 678 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
679 min_pkt_size, dev->alt);
a6c2ba28 680 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 681 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
682 dev->alt, dev->max_pkt_size);
a6c2ba28 683 errCode = usb_set_interface(dev->udev, 0, dev->alt);
684 if (errCode < 0) {
6ea54d93 685 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 686 dev->alt, errCode);
a6c2ba28 687 return errCode;
688 }
689 }
690 return 0;
691}
579f72e4 692
c67ec53f
MCC		 693int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
694{
695 int rc = 0;
696
697 if (!gpio)
698 return rc;
699
700 dev->em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
701 if (dev->mode == EM28XX_ANALOG_MODE)
702 dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x67", 1);
703 else
704 dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x37", 1);
705 msleep(6);
706
707 /* Send GPIO reset sequences specified at board entry */
708 while (gpio->sleep >= 0) {
709 if (gpio->reg >= 0) {
710 rc = em28xx_write_reg_bits(dev,
711 gpio->reg,
712 gpio->val,
713 gpio->mask);
714 if (rc < 0)
715 return rc;
716 }
717 if (gpio->sleep > 0)
718 msleep(gpio->sleep);
719
720 gpio++;
721 }
722 return rc;
723}
724
725int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
726{
727 if (dev->mode == set_mode)
728 return 0;
729
730 if (set_mode == EM28XX_MODE_UNDEFINED) {
731 dev->mode = set_mode;
732 return 0;
733 }
734
735 dev->mode = set_mode;
736
737 if (dev->mode == EM28XX_DIGITAL_MODE)
738 return em28xx_gpio_set(dev, dev->digital_gpio);
739 else
740 return em28xx_gpio_set(dev, dev->analog_gpio);
741}
742EXPORT_SYMBOL_GPL(em28xx_set_mode);
743
579f72e4
AT		 744/* ------------------------------------------------------------------
745 URB control
746 ------------------------------------------------------------------*/
747
748/*
749 * IRQ callback, called by URB callback
750 */
751static void em28xx_irq_callback(struct urb *urb)
752{
753 struct em28xx_dmaqueue *dma_q = urb->context;
754 struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
755 int rc, i;
756
757 /* Copy data from URB */
758 spin_lock(&dev->slock);
759 rc = dev->isoc_ctl.isoc_copy(dev, urb);
760 spin_unlock(&dev->slock);
761
762 /* Reset urb buffers */
763 for (i = 0; i < urb->number_of_packets; i++) {
764 urb->iso_frame_desc[i].status = 0;
765 urb->iso_frame_desc[i].actual_length = 0;
766 }
767 urb->status = 0;
768
769 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
770 if (urb->status) {
4269a8ee
DH		 771 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
772 urb->status);
579f72e4
AT		 773 }
774}
775
776/*
777 * Stop and Deallocate URBs
778 */
779void em28xx_uninit_isoc(struct em28xx *dev)
780{
781 struct urb *urb;
782 int i;
783
784 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
785
786 dev->isoc_ctl.nfields = -1;
787 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
788 urb = dev->isoc_ctl.urb[i];
789 if (urb) {
790 usb_kill_urb(urb);
791 usb_unlink_urb(urb);
792 if (dev->isoc_ctl.transfer_buffer[i]) {
793 usb_buffer_free(dev->udev,
6ea54d93
DSL		 794 urb->transfer_buffer_length,
795 dev->isoc_ctl.transfer_buffer[i],
796 urb->transfer_dma);
579f72e4
AT		 797 }
798 usb_free_urb(urb);
799 dev->isoc_ctl.urb[i] = NULL;
800 }
801 dev->isoc_ctl.transfer_buffer[i] = NULL;
802 }
803
804 kfree(dev->isoc_ctl.urb);
805 kfree(dev->isoc_ctl.transfer_buffer);
806
807 dev->isoc_ctl.urb = NULL;
808 dev->isoc_ctl.transfer_buffer = NULL;
809 dev->isoc_ctl.num_bufs = 0;
810
811 em28xx_capture_start(dev, 0);
812}
813EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
814
815/*
816 * Allocate URBs and start IRQ
817 */
818int em28xx_init_isoc(struct em28xx *dev, int max_packets,
819 int num_bufs, int max_pkt_size,
c67ec53f 820 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
579f72e4
AT		 821{
822 struct em28xx_dmaqueue *dma_q = &dev->vidq;
823 int i;
824 int sb_size, pipe;
825 struct urb *urb;
826 int j, k;
827 int rc;
828
829 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
830
831 /* De-allocates all pending stuff */
832 em28xx_uninit_isoc(dev);
833
834 dev->isoc_ctl.isoc_copy = isoc_copy;
835 dev->isoc_ctl.num_bufs = num_bufs;
836
837 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
838 if (!dev->isoc_ctl.urb) {
839 em28xx_errdev("cannot alloc memory for usb buffers\n");
840 return -ENOMEM;
841 }
842
843 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
844 GFP_KERNEL);
094f9b4b 845 if (!dev->isoc_ctl.transfer_buffer) {
579f72e4
AT		 846 em28xx_errdev("cannot allocate memory for usbtransfer\n");
847 kfree(dev->isoc_ctl.urb);
848 return -ENOMEM;
849 }
850
851 dev->isoc_ctl.max_pkt_size = max_pkt_size;
852 dev->isoc_ctl.buf = NULL;
853
854 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
855
856 /* allocate urbs and transfer buffers */
857 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
858 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
859 if (!urb) {
860 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
861 em28xx_uninit_isoc(dev);
862 return -ENOMEM;
863 }
864 dev->isoc_ctl.urb[i] = urb;
865
866 dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
867 sb_size, GFP_KERNEL, &urb->transfer_dma);
868 if (!dev->isoc_ctl.transfer_buffer[i]) {
869 em28xx_err("unable to allocate %i bytes for transfer"
870 " buffer %i%s\n",
871 sb_size, i,
872 in_interrupt()?" while in int":"");
873 em28xx_uninit_isoc(dev);
874 return -ENOMEM;
875 }
876 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
877
878 /* FIXME: this is a hack - should be
879 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
880 should also be using 'desc.bInterval'
881 */
6ea54d93 882 pipe = usb_rcvisocpipe(dev->udev,
c67ec53f 883 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
6ea54d93 884
579f72e4
AT		 885 usb_fill_int_urb(urb, dev->udev, pipe,
886 dev->isoc_ctl.transfer_buffer[i], sb_size,
887 em28xx_irq_callback, dma_q, 1);
888
889 urb->number_of_packets = max_packets;
890 urb->transfer_flags = URB_ISO_ASAP;
891
892 k = 0;
893 for (j = 0; j < max_packets; j++) {
894 urb->iso_frame_desc[j].offset = k;
895 urb->iso_frame_desc[j].length =
896 dev->isoc_ctl.max_pkt_size;
897 k += dev->isoc_ctl.max_pkt_size;
898 }
899 }
900
901 init_waitqueue_head(&dma_q->wq);
902
c67ec53f 903 em28xx_capture_start(dev, 1);
579f72e4
AT		 904
905 /* submit urbs and enables IRQ */
906 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
907 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
908 if (rc) {
909 em28xx_err("submit of urb %i failed (error=%i)\n", i,
910 rc);
911 em28xx_uninit_isoc(dev);
912 return rc;
913 }
914 }
915
916 return 0;
917}
918EXPORT_SYMBOL_GPL(em28xx_init_isoc);
Linux 6.x block layer and io_uring tree(s)