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[media] em28xx: Don't initialize a var if won't be using it
[linux-2.6-block.git] / drivers / media / video / em28xx / em28xx-core.c
CommitLineData
a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
5a0e3ad6 27#include <linux/slab.h>
a6c2ba28 28#include <linux/usb.h>
29#include <linux/vmalloc.h>
1a23f81b 30#include <media/v4l2-common.h>
a6c2ba28 31
f7abcd38 32#include "em28xx.h"
a6c2ba28 33
34/* #define ENABLE_DEBUG_ISOC_FRAMES */
35
ff699e6b 36static unsigned int core_debug;
a1a6ee74
NS		 37module_param(core_debug, int, 0644);
38MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
a6c2ba28 39
3acf2809 40#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 41 if (core_debug) \
42 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 43 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 44
ff699e6b 45static unsigned int reg_debug;
a1a6ee74
NS		 46module_param(reg_debug, int, 0644);
47MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
a6c2ba28 48
3acf2809 49#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 50 if (reg_debug) \
51 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 52 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 53
fc099f0e 54static int alt;
a6c2ba28 55module_param(alt, int, 0644);
56MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
57
da52a55c
DH		 58static unsigned int disable_vbi;
59module_param(disable_vbi, int, 0644);
60MODULE_PARM_DESC(disable_vbi, "disable vbi support");
61
579f72e4
AT		 62/* FIXME */
63#define em28xx_isocdbg(fmt, arg...) do {\
64 if (core_debug) \
65 printk(KERN_INFO "%s %s :"fmt, \
66 dev->name, __func__ , ##arg); } while (0)
67
a6c2ba28 68/*
3acf2809 69 * em28xx_read_reg_req()
a6c2ba28 70 * reads data from the usb device specifying bRequest
71 */
3acf2809 72int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28 73 char *buf, int len)
74{
9e5d6760
MCC		 75 int ret;
76 int pipe = usb_rcvctrlpipe(dev->udev, 0);
a6c2ba28 77
9f38724a 78 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 79 return -ENODEV;
80
81 if (len > URB_MAX_CTRL_SIZE)
82 return -EINVAL;
9f38724a 83
9e5d6760 84 if (reg_debug) {
a1a6ee74 85 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 86 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
87 pipe,
88 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
89 req, 0, 0,
90 reg & 0xff, reg >> 8,
91 len & 0xff, len >> 8);
92 }
a6c2ba28 93
f2a2e491 94 mutex_lock(&dev->ctrl_urb_lock);
9e5d6760 95 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 96 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 97 0x0000, reg, dev->urb_buf, len, HZ);
98 if (ret < 0) {
99 if (reg_debug)
100 printk(" failed!\n");
f2a2e491 101 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 102 return ret;
103 }
104
105 if (len)
106 memcpy(buf, dev->urb_buf, len);
a6c2ba28 107
f2a2e491
MCC		 108 mutex_unlock(&dev->ctrl_urb_lock);
109
6ea54d93 110 if (reg_debug) {
9e5d6760
MCC		 111 int byte;
112
113 printk("<<<");
6ea54d93 114 for (byte = 0; byte < len; byte++)
82ac4f87 115 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 116 printk("\n");
a6c2ba28 117 }
118
119 return ret;
120}
121
122/*
3acf2809 123 * em28xx_read_reg_req()
a6c2ba28 124 * reads data from the usb device specifying bRequest
125 */
3acf2809 126int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 127{
a6c2ba28 128 int ret;
9e5d6760 129 u8 val;
a6c2ba28 130
9e5d6760
MCC		 131 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
132 if (ret < 0)
c4a98793 133 return ret;
a6c2ba28 134
135 return val;
136}
137
3acf2809 138int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 139{
3acf2809 140 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28 141}
142
143/*
3acf2809 144 * em28xx_write_regs_req()
a6c2ba28 145 * sends data to the usb device, specifying bRequest
146 */
3acf2809 147int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28 148 int len)
149{
150 int ret;
9e5d6760 151 int pipe = usb_sndctrlpipe(dev->udev, 0);
a6c2ba28 152
9f38724a 153 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 154 return -ENODEV;
155
c4a98793 156 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 157 return -EINVAL;
9f38724a 158
a6c2ba28 159 if (reg_debug) {
9e5d6760
MCC		 160 int byte;
161
a1a6ee74 162 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 163 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
164 pipe,
165 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
166 req, 0, 0,
167 reg & 0xff, reg >> 8,
168 len & 0xff, len >> 8);
169
170 for (byte = 0; byte < len; byte++)
171 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 172 printk("\n");
a6c2ba28 173 }
174
f2a2e491 175 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 176 memcpy(dev->urb_buf, buf, len);
9e5d6760 177 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 178 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 179 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 180 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 181
89b329ef
MCC		 182 if (dev->wait_after_write)
183 msleep(dev->wait_after_write);
184
a6c2ba28 185 return ret;
186}
187
3acf2809 188int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 189{
c67ec53f
MCC		 190 int rc;
191
192 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
193
194 /* Stores GPO/GPIO values at the cache, if changed
195 Only write values should be stored, since input on a GPIO
196 register will return the input bits.
197 Not sure what happens on reading GPO register.
198 */
199 if (rc >= 0) {
6a1acc3b 200 if (reg == dev->reg_gpo_num)
c67ec53f 201 dev->reg_gpo = buf[0];
6a1acc3b 202 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 203 dev->reg_gpio = buf[0];
204 }
205
206 return rc;
a6c2ba28 207}
208
b6972489
DH		 209/* Write a single register */
210int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
211{
212 return em28xx_write_regs(dev, reg, &val, 1);
213}
214
a6c2ba28 215/*
3acf2809 216 * em28xx_write_reg_bits()
a6c2ba28 217 * sets only some bits (specified by bitmask) of a register, by first reading
218 * the actual value
219 */
1bad429e 220int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28 221 u8 bitmask)
222{
223 int oldval;
224 u8 newval;
6ea54d93 225
c67ec53f 226 /* Uses cache for gpo/gpio registers */
6a1acc3b 227 if (reg == dev->reg_gpo_num)
c67ec53f 228 oldval = dev->reg_gpo;
6a1acc3b 229 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 230 oldval = dev->reg_gpio;
231 else
232 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 233
234 if (oldval < 0)
a6c2ba28 235 return oldval;
6ea54d93 236
a6c2ba28 237 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 238
3acf2809 239 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28 240}
241
35643943
MCC		 242/*
243 * em28xx_is_ac97_ready()
244 * Checks if ac97 is ready
245 */
246static int em28xx_is_ac97_ready(struct em28xx *dev)
247{
248 int ret, i;
249
250 /* Wait up to 50 ms for AC97 command to complete */
251 for (i = 0; i < 10; i++, msleep(5)) {
252 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
253 if (ret < 0)
254 return ret;
255
256 if (!(ret & 0x01))
257 return 0;
258 }
259
260 em28xx_warn("AC97 command still being executed: not handled properly!\n");
261 return -EBUSY;
262}
263
264/*
265 * em28xx_read_ac97()
266 * write a 16 bit value to the specified AC97 address (LSB first!)
267 */
531c98e7 268int em28xx_read_ac97(struct em28xx *dev, u8 reg)
35643943
MCC		 269{
270 int ret;
271 u8 addr = (reg & 0x7f) | 0x80;
272 u16 val;
273
274 ret = em28xx_is_ac97_ready(dev);
275 if (ret < 0)
276 return ret;
277
278 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
279 if (ret < 0)
280 return ret;
281
282 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
283 (u8 *)&val, sizeof(val));
284
285 if (ret < 0)
286 return ret;
287 return le16_to_cpu(val);
288}
289
a6c2ba28 290/*
3acf2809 291 * em28xx_write_ac97()
a6c2ba28 292 * write a 16 bit value to the specified AC97 address (LSB first!)
293 */
531c98e7 294int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 295{
35643943 296 int ret;
a6c2ba28 297 u8 addr = reg & 0x7f;
35643943
MCC		 298 __le16 value;
299
300 value = cpu_to_le16(val);
301
302 ret = em28xx_is_ac97_ready(dev);
303 if (ret < 0)
304 return ret;
6ea54d93 305
35643943 306 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 307 if (ret < 0)
a6c2ba28 308 return ret;
6ea54d93 309
41facaa4 310 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 311 if (ret < 0)
a6c2ba28 312 return ret;
00b8730f 313
35643943
MCC		 314 return 0;
315}
6ea54d93 316
e879b8eb
MCC		 317struct em28xx_vol_table {
318 enum em28xx_amux mux;
5faff789
MCC		 319 u8 reg;
320};
321
e879b8eb 322static struct em28xx_vol_table inputs[] = {
5faff789
MCC		 323 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
324 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
325 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
326 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
327 { EM28XX_AMUX_CD, AC97_CD_VOL },
328 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
329 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
330};
331
332static int set_ac97_input(struct em28xx *dev)
35643943 333{
5faff789
MCC		 334 int ret, i;
335 enum em28xx_amux amux = dev->ctl_ainput;
35643943 336
5faff789
MCC		 337 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
338 em28xx should point to LINE IN, while AC97 should use VIDEO
339 */
340 if (amux == EM28XX_AMUX_VIDEO2)
f1990a9c 341 amux = EM28XX_AMUX_VIDEO;
35643943 342
5faff789
MCC		 343 /* Mute all entres but the one that were selected */
344 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
e879b8eb 345 if (amux == inputs[i].mux)
5faff789
MCC		 346 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
347 else
348 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
35643943 349
5faff789
MCC		 350 if (ret < 0)
351 em28xx_warn("couldn't setup AC97 register %d\n",
352 inputs[i].reg);
353 }
354 return 0;
a6c2ba28 355}
356
00b8730f 357static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 358{
1685a6fe 359 int ret;
539c96d0
MCC		 360 u8 input;
361
505b6d0b 362 if (dev->board.is_em2800) {
5faff789 363 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
539c96d0 364 input = EM2800_AUDIO_SRC_TUNER;
5faff789
MCC		 365 else
366 input = EM2800_AUDIO_SRC_LINE;
539c96d0 367
41facaa4 368 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 369 if (ret < 0)
370 return ret;
371 }
372
505b6d0b 373 if (dev->board.has_msp34xx)
539c96d0
MCC		 374 input = EM28XX_AUDIO_SRC_TUNER;
375 else {
376 switch (dev->ctl_ainput) {
377 case EM28XX_AMUX_VIDEO:
378 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 379 break;
35643943 380 default:
539c96d0 381 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 382 break;
383 }
384 }
385
2bd1d9eb
VW		 386 if (dev->board.mute_gpio && dev->mute)
387 em28xx_gpio_set(dev, dev->board.mute_gpio);
388 else
389 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
390
41facaa4 391 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 392 if (ret < 0)
393 return ret;
00b8730f 394 msleep(5);
539c96d0 395
35643943
MCC		 396 switch (dev->audio_mode.ac97) {
397 case EM28XX_NO_AC97:
398 break;
5faff789
MCC		 399 default:
400 ret = set_ac97_input(dev);
35643943 401 }
539c96d0 402
5faff789 403 return ret;
539c96d0
MCC		 404}
405
26cdc76b 406static const struct em28xx_vol_table outputs[] = {
e879b8eb
MCC		 407 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
408 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
409 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
410 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
411 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
35ae6f04
MCC		 412};
413
3acf2809 414int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 415{
35ae6f04 416 int ret, i;
a2070c66 417 u8 xclk;
539c96d0 418
35643943
MCC		 419 if (!dev->audio_mode.has_audio)
420 return 0;
539c96d0 421
5faff789
MCC		 422 /* It is assumed that all devices use master volume for output.
423 It would be possible to use also line output.
424 */
35643943 425 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
35ae6f04
MCC		 426 /* Mute all outputs */
427 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
e879b8eb 428 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
35ae6f04
MCC		 429 if (ret < 0)
430 em28xx_warn("couldn't setup AC97 register %d\n",
e879b8eb 431 outputs[i].reg);
35ae6f04 432 }
35643943 433 }
539c96d0 434
505b6d0b 435 xclk = dev->board.xclk & 0x7f;
3abee53e 436 if (!dev->mute)
8ed06fd4 437 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
3abee53e 438
a2070c66 439 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
539c96d0
MCC		 440 if (ret < 0)
441 return ret;
3abee53e 442 msleep(10);
539c96d0
MCC		 443
444 /* Selects the proper audio input */
445 ret = em28xx_set_audio_source(dev);
a6c2ba28 446
35643943
MCC		 447 /* Sets volume */
448 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
449 int vol;
450
7e4b15e4
RK		 451 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
452 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
453 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
454
35643943
MCC		 455 /* LSB: left channel - both channels with the same level */
456 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
457
458 /* Mute device, if needed */
459 if (dev->mute)
460 vol |= 0x8000;
461
462 /* Sets volume */
e879b8eb
MCC		 463 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
464 if (dev->ctl_aoutput & outputs[i].mux)
465 ret = em28xx_write_ac97(dev, outputs[i].reg,
466 vol);
467 if (ret < 0)
468 em28xx_warn("couldn't setup AC97 register %d\n",
469 outputs[i].reg);
470 }
8866f9cf
MCC		 471
472 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
473 int sel = ac97_return_record_select(dev->ctl_aoutput);
474
a1a6ee74
NS		 475 /* Use the same input for both left and right
476 channels */
8866f9cf
MCC		 477 sel |= (sel << 8);
478
479 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
480 }
35643943 481 }
00b8730f 482
539c96d0
MCC		 483 return ret;
484}
485EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 486
35643943
MCC		 487int em28xx_audio_setup(struct em28xx *dev)
488{
489 int vid1, vid2, feat, cfg;
16c7bcad 490 u32 vid;
35643943 491
2892bd0d
SK		 492 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874
493 || dev->chip_id == CHIP_ID_EM28174) {
35643943
MCC		 494 /* Digital only device - don't load any alsa module */
495 dev->audio_mode.has_audio = 0;
496 dev->has_audio_class = 0;
497 dev->has_alsa_audio = 0;
498 return 0;
499 }
500
501 /* If device doesn't support Usb Audio Class, use vendor class */
502 if (!dev->has_audio_class)
503 dev->has_alsa_audio = 1;
504
505 dev->audio_mode.has_audio = 1;
506
507 /* See how this device is configured */
508 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
1cdc6392
DH		 509 em28xx_info("Config register raw data: 0x%02x\n", cfg);
510 if (cfg < 0) {
511 /* Register read error? */
35643943 512 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
1cdc6392
DH		 513 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
514 /* The device doesn't have vendor audio at all */
515 dev->has_alsa_audio = 0;
516 dev->audio_mode.has_audio = 0;
517 return 0;
518 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
519 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
35643943
MCC		 520 em28xx_info("I2S Audio (3 sample rates)\n");
521 dev->audio_mode.i2s_3rates = 1;
1cdc6392
DH		 522 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
523 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
35643943
MCC		 524 em28xx_info("I2S Audio (5 sample rates)\n");
525 dev->audio_mode.i2s_5rates = 1;
526 }
527
de84830e
DH		 528 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
529 /* Skip the code that does AC97 vendor detection */
35643943
MCC		 530 dev->audio_mode.ac97 = EM28XX_NO_AC97;
531 goto init_audio;
532 }
533
534 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
535
536 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
537 if (vid1 < 0) {
0731160a
MCC		 538 /*
539 * Device likely doesn't support AC97
540 * Note: (some) em2800 devices without eeprom reports 0x91 on
541 * CHIPCFG register, even not having an AC97 chip
542 */
35643943 543 em28xx_warn("AC97 chip type couldn't be determined\n");
0731160a
MCC		 544 dev->audio_mode.ac97 = EM28XX_NO_AC97;
545 dev->has_alsa_audio = 0;
546 dev->audio_mode.has_audio = 0;
35643943
MCC		 547 goto init_audio;
548 }
549
550 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
551 if (vid2 < 0)
552 goto init_audio;
553
16c7bcad
MCC		 554 vid = vid1 << 16 | vid2;
555
556 dev->audio_mode.ac97_vendor_id = vid;
557 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 558
559 feat = em28xx_read_ac97(dev, AC97_RESET);
560 if (feat < 0)
561 goto init_audio;
562
563 dev->audio_mode.ac97_feat = feat;
564 em28xx_warn("AC97 features = 0x%04x\n", feat);
565
16c7bcad
MCC		 566 /* Try to identify what audio processor we have */
567 if ((vid == 0xffffffff) && (feat == 0x6a90))
35643943 568 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
209acc02
MCC		 569 else if ((vid >> 8) == 0x838476)
570 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
35643943
MCC		 571
572init_audio:
573 /* Reports detected AC97 processor */
574 switch (dev->audio_mode.ac97) {
575 case EM28XX_NO_AC97:
576 em28xx_info("No AC97 audio processor\n");
577 break;
578 case EM28XX_AC97_EM202:
579 em28xx_info("Empia 202 AC97 audio processor detected\n");
580 break;
209acc02
MCC		 581 case EM28XX_AC97_SIGMATEL:
582 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
583 dev->audio_mode.ac97_vendor_id & 0xff);
584 break;
35643943
MCC		 585 case EM28XX_AC97_OTHER:
586 em28xx_warn("Unknown AC97 audio processor detected!\n");
587 break;
588 default:
589 break;
590 }
591
592 return em28xx_audio_analog_set(dev);
593}
594EXPORT_SYMBOL_GPL(em28xx_audio_setup);
595
3acf2809 596int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 597{
2a29a0d7
MCC		 598 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
599 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
600 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
601 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
602 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
603 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
604
605 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
606 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
607 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
608 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
609 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
610 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
611 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
a6c2ba28 612}
613
3acf2809 614int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 615{
ee6e3a86 616 int rc;
ebef13d4 617
bc022694 618 if (dev->chip_id == CHIP_ID_EM2874 || dev->chip_id == CHIP_ID_EM28174) {
ebef13d4
DH		 619 /* The Transport Stream Enable Register moved in em2874 */
620 if (!start) {
621 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
622 0x00,
623 EM2874_TS1_CAPTURE_ENABLE);
624 return rc;
625 }
626
627 /* Enable Transport Stream */
628 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
629 EM2874_TS1_CAPTURE_ENABLE,
630 EM2874_TS1_CAPTURE_ENABLE);
631 return rc;
632 }
633
634
a6c2ba28 635 /* FIXME: which is the best order? */
636 /* video registers are sampled by VREF */
41facaa4 637 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 638 start ? 0x10 : 0x00, 0x10);
639 if (rc < 0)
640 return rc;
641
642 if (!start) {
643 /* disable video capture */
2a29a0d7 644 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
102a0b08 645 return rc;
ee6e3a86
MCC		 646 }
647
d7612c86
MCC		 648 if (dev->board.is_webcam)
649 rc = em28xx_write_reg(dev, 0x13, 0x0c);
650
a6c2ba28 651 /* enable video capture */
2a29a0d7 652 rc = em28xx_write_reg(dev, 0x48, 0x00);
102a0b08 653
ee6e3a86 654 if (dev->mode == EM28XX_ANALOG_MODE)
2a29a0d7 655 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
ee6e3a86 656 else
2a29a0d7 657 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
ee6e3a86 658
6ea54d93 659 msleep(6);
ee6e3a86
MCC		 660
661 return rc;
a6c2ba28 662}
663
da52a55c
DH		 664int em28xx_vbi_supported(struct em28xx *dev)
665{
666 /* Modprobe option to manually disable */
667 if (disable_vbi == 1)
668 return 0;
669
670 if (dev->chip_id == CHIP_ID_EM2860 ||
671 dev->chip_id == CHIP_ID_EM2883)
672 return 1;
673
674 /* Version of em28xx that does not support VBI */
675 return 0;
676}
677
bddcf633 678int em28xx_set_outfmt(struct em28xx *dev)
a6c2ba28 679{
bddcf633 680 int ret;
da52a55c 681 u8 vinctrl;
bddcf633
MCC		 682
683 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
579d3152 684 dev->format->reg | 0x20, 0xff);
bddcf633 685 if (ret < 0)
02e7804b 686 return ret;
bddcf633 687
579d3152 688 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
bddcf633
MCC		 689 if (ret < 0)
690 return ret;
691
da52a55c
DH		 692 vinctrl = dev->vinctl;
693 if (em28xx_vbi_supported(dev) == 1) {
694 vinctrl |= EM28XX_VINCTRL_VBI_RAW;
695 em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
66d9cbad
DH		 696 em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
697 em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
698 if (dev->norm & V4L2_STD_525_60) {
699 /* NTSC */
700 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
701 } else if (dev->norm & V4L2_STD_625_50) {
702 /* PAL */
703 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
704 }
da52a55c
DH		 705 }
706
707 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
a6c2ba28 708}
709
adcb0fa2
AB		 710static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
711 u8 ymin, u8 ymax)
a6c2ba28 712{
6ea54d93
DSL		 713 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
714 xmin, ymin, xmax, ymax);
a6c2ba28 715
41facaa4
MCC		 716 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
717 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
718 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
719 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28 720}
721
adcb0fa2 722static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28 723 u16 width, u16 height)
724{
725 u8 cwidth = width;
726 u8 cheight = height;
727 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
728
6ea54d93
DSL		 729 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
730 (width | (overflow & 2) << 7),
a6c2ba28 731 (height | (overflow & 1) << 8));
732
41facaa4
MCC		 733 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
734 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
735 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
736 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
737 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28 738}
739
adcb0fa2 740static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 741{
52c02fcd
SS		 742 u8 mode;
743 /* the em2800 scaler only supports scaling down to 50% */
02e7804b 744
55699964 745 if (dev->board.is_em2800) {
52c02fcd 746 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
02e7804b 747 } else {
52c02fcd 748 u8 buf[2];
02e7804b 749
52c02fcd
SS		 750 buf[0] = h;
751 buf[1] = h >> 8;
41facaa4 752 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
02e7804b 753
52c02fcd
SS		 754 buf[0] = v;
755 buf[1] = v >> 8;
41facaa4 756 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 757 /* it seems that both H and V scalers must be active
758 to work correctly */
a1a6ee74 759 mode = (h || v) ? 0x30 : 0x00;
74458e6c 760 }
41facaa4 761 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28 762}
763
764/* FIXME: this only function read values from dev */
3acf2809 765int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28 766{
767 int width, height;
768 width = norm_maxw(dev);
c2a6b54a
MCC		 769 height = norm_maxh(dev);
770
66d9cbad
DH		 771 /* Properly setup VBI */
772 dev->vbi_width = 720;
773 if (dev->norm & V4L2_STD_525_60)
774 dev->vbi_height = 12;
775 else
776 dev->vbi_height = 18;
777
c2a6b54a
MCC		 778 if (!dev->progressive)
779 height >>= norm_maxh(dev);
a6c2ba28 780
bddcf633 781 em28xx_set_outfmt(dev);
02e7804b
MCC		 782
783
3acf2809 784 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
da52a55c 785
1744feab
DH		 786 /* If we don't set the start position to 2 in VBI mode, we end up
787 with line 20/21 being YUYV encoded instead of being in 8-bit
788 greyscale. The core of the issue is that line 21 (and line 23 for
789 PAL WSS) are inside of active video region, and as a result they
790 get the pixelformatting associated with that area. So by cropping
791 it out, we end up with the same format as the rest of the VBI
792 region */
da52a55c 793 if (em28xx_vbi_supported(dev) == 1)
1744feab 794 em28xx_capture_area_set(dev, 0, 2, width >> 2, height >> 2);
da52a55c
DH		 795 else
796 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
02e7804b 797
3acf2809 798 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28 799}
800
3acf2809 801int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28 802{
803 int errCode, prev_alt = dev->alt;
3687e1e6 804 int i;
44dc733c 805 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 806
fc099f0e
MCC		 807 /*
808 * alt = 0 is used only for control messages, so, only values
809 * greater than 0 can be used for streaming.
810 */
811 if (alt && alt < dev->num_alt) {
812 em28xx_coredbg("alternate forced to %d\n", dev->alt);
813 dev->alt = alt;
814 goto set_alt;
815 }
816
2c4a07b2 817 /* When image size is bigger than a certain value,
3687e1e6
MCC		 818 the frame size should be increased, otherwise, only
819 green screen will be received.
820 */
44dc733c 821 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 822 min_pkt_size *= 2;
823
2c4a07b2
SS		 824 for (i = 0; i < dev->num_alt; i++) {
825 /* stop when the selected alt setting offers enough bandwidth */
826 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
827 dev->alt = i;
3687e1e6 828 break;
2c4a07b2
SS		 829 /* otherwise make sure that we end up with the maximum bandwidth
830 because the min_pkt_size equation might be wrong...
831 */
832 } else if (dev->alt_max_pkt_size[i] >
833 dev->alt_max_pkt_size[dev->alt])
834 dev->alt = i;
835 }
a6c2ba28 836
fc099f0e 837set_alt:
a6c2ba28 838 if (dev->alt != prev_alt) {
3687e1e6
MCC		 839 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
840 min_pkt_size, dev->alt);
a6c2ba28 841 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 842 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
843 dev->alt, dev->max_pkt_size);
a6c2ba28 844 errCode = usb_set_interface(dev->udev, 0, dev->alt);
845 if (errCode < 0) {
6ea54d93 846 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 847 dev->alt, errCode);
a6c2ba28 848 return errCode;
849 }
850 }
851 return 0;
852}
579f72e4 853
c67ec53f
MCC		 854int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
855{
856 int rc = 0;
857
858 if (!gpio)
859 return rc;
860
2fe3e2ee
MCC		 861 if (dev->mode != EM28XX_SUSPEND) {
862 em28xx_write_reg(dev, 0x48, 0x00);
863 if (dev->mode == EM28XX_ANALOG_MODE)
864 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
865 else
866 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
867 msleep(6);
868 }
c67ec53f
MCC		 869
870 /* Send GPIO reset sequences specified at board entry */
871 while (gpio->sleep >= 0) {
872 if (gpio->reg >= 0) {
873 rc = em28xx_write_reg_bits(dev,
874 gpio->reg,
875 gpio->val,
876 gpio->mask);
877 if (rc < 0)
878 return rc;
879 }
880 if (gpio->sleep > 0)
881 msleep(gpio->sleep);
882
883 gpio++;
884 }
885 return rc;
886}
887
888int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
889{
890 if (dev->mode == set_mode)
891 return 0;
892
2fe3e2ee 893 if (set_mode == EM28XX_SUSPEND) {
c67ec53f 894 dev->mode = set_mode;
2fe3e2ee
MCC		 895
896 /* FIXME: add suspend support for ac97 */
897
898 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
c67ec53f
MCC		 899 }
900
901 dev->mode = set_mode;
902
903 if (dev->mode == EM28XX_DIGITAL_MODE)
f502e861 904 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
c67ec53f 905 else
f502e861 906 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
c67ec53f
MCC		 907}
908EXPORT_SYMBOL_GPL(em28xx_set_mode);
909
579f72e4
AT		 910/* ------------------------------------------------------------------
911 URB control
912 ------------------------------------------------------------------*/
913
914/*
915 * IRQ callback, called by URB callback
916 */
917static void em28xx_irq_callback(struct urb *urb)
918{
da52a55c 919 struct em28xx *dev = urb->context;
00d2e7ad 920 int i;
579f72e4 921
aa5a1821
RK		 922 switch (urb->status) {
923 case 0: /* success */
924 case -ETIMEDOUT: /* NAK */
925 break;
926 case -ECONNRESET: /* kill */
927 case -ENOENT:
928 case -ESHUTDOWN:
929 return;
930 default: /* error */
931 em28xx_isocdbg("urb completition error %d.\n", urb->status);
932 break;
933 }
934
579f72e4
AT		 935 /* Copy data from URB */
936 spin_lock(&dev->slock);
00d2e7ad 937 dev->isoc_ctl.isoc_copy(dev, urb);
579f72e4
AT		 938 spin_unlock(&dev->slock);
939
940 /* Reset urb buffers */
941 for (i = 0; i < urb->number_of_packets; i++) {
942 urb->iso_frame_desc[i].status = 0;
943 urb->iso_frame_desc[i].actual_length = 0;
944 }
945 urb->status = 0;
946
947 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
948 if (urb->status) {
4269a8ee
DH		 949 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
950 urb->status);
579f72e4
AT		 951 }
952}
953
954/*
955 * Stop and Deallocate URBs
956 */
957void em28xx_uninit_isoc(struct em28xx *dev)
958{
959 struct urb *urb;
960 int i;
961
962 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
963
964 dev->isoc_ctl.nfields = -1;
965 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
966 urb = dev->isoc_ctl.urb[i];
967 if (urb) {
9c06210b
RK		 968 if (!irqs_disabled())
969 usb_kill_urb(urb);
970 else
971 usb_unlink_urb(urb);
972
579f72e4 973 if (dev->isoc_ctl.transfer_buffer[i]) {
997ea58e 974 usb_free_coherent(dev->udev,
6ea54d93
DSL		 975 urb->transfer_buffer_length,
976 dev->isoc_ctl.transfer_buffer[i],
977 urb->transfer_dma);
579f72e4
AT		 978 }
979 usb_free_urb(urb);
980 dev->isoc_ctl.urb[i] = NULL;
981 }
982 dev->isoc_ctl.transfer_buffer[i] = NULL;
983 }
984
985 kfree(dev->isoc_ctl.urb);
986 kfree(dev->isoc_ctl.transfer_buffer);
987
988 dev->isoc_ctl.urb = NULL;
989 dev->isoc_ctl.transfer_buffer = NULL;
990 dev->isoc_ctl.num_bufs = 0;
991
992 em28xx_capture_start(dev, 0);
993}
994EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
995
996/*
997 * Allocate URBs and start IRQ
998 */
999int em28xx_init_isoc(struct em28xx *dev, int max_packets,
1000 int num_bufs, int max_pkt_size,
c67ec53f 1001 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
579f72e4
AT		 1002{
1003 struct em28xx_dmaqueue *dma_q = &dev->vidq;
28abf083 1004 struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
579f72e4
AT		 1005 int i;
1006 int sb_size, pipe;
1007 struct urb *urb;
1008 int j, k;
1009 int rc;
1010
1011 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
1012
1013 /* De-allocates all pending stuff */
1014 em28xx_uninit_isoc(dev);
1015
1016 dev->isoc_ctl.isoc_copy = isoc_copy;
1017 dev->isoc_ctl.num_bufs = num_bufs;
1018
1019 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
1020 if (!dev->isoc_ctl.urb) {
1021 em28xx_errdev("cannot alloc memory for usb buffers\n");
1022 return -ENOMEM;
1023 }
1024
1025 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
1026 GFP_KERNEL);
094f9b4b 1027 if (!dev->isoc_ctl.transfer_buffer) {
42ef4632 1028 em28xx_errdev("cannot allocate memory for usb transfer\n");
579f72e4
AT		 1029 kfree(dev->isoc_ctl.urb);
1030 return -ENOMEM;
1031 }
1032
1033 dev->isoc_ctl.max_pkt_size = max_pkt_size;
28abf083
DH		 1034 dev->isoc_ctl.vid_buf = NULL;
1035 dev->isoc_ctl.vbi_buf = NULL;
579f72e4
AT		 1036
1037 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
1038
1039 /* allocate urbs and transfer buffers */
1040 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1041 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
1042 if (!urb) {
1043 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
1044 em28xx_uninit_isoc(dev);
1045 return -ENOMEM;
1046 }
1047 dev->isoc_ctl.urb[i] = urb;
1048
997ea58e 1049 dev->isoc_ctl.transfer_buffer[i] = usb_alloc_coherent(dev->udev,
579f72e4
AT		 1050 sb_size, GFP_KERNEL, &urb->transfer_dma);
1051 if (!dev->isoc_ctl.transfer_buffer[i]) {
1052 em28xx_err("unable to allocate %i bytes for transfer"
1053 " buffer %i%s\n",
1054 sb_size, i,
a1a6ee74 1055 in_interrupt() ? " while in int" : "");
579f72e4
AT		 1056 em28xx_uninit_isoc(dev);
1057 return -ENOMEM;
1058 }
1059 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
1060
1061 /* FIXME: this is a hack - should be
1062 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
1063 should also be using 'desc.bInterval'
1064 */
6ea54d93 1065 pipe = usb_rcvisocpipe(dev->udev,
c67ec53f 1066 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
6ea54d93 1067
579f72e4
AT		 1068 usb_fill_int_urb(urb, dev->udev, pipe,
1069 dev->isoc_ctl.transfer_buffer[i], sb_size,
da52a55c 1070 em28xx_irq_callback, dev, 1);
579f72e4
AT		 1071
1072 urb->number_of_packets = max_packets;
9a4f8201 1073 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
579f72e4
AT		 1074
1075 k = 0;
1076 for (j = 0; j < max_packets; j++) {
1077 urb->iso_frame_desc[j].offset = k;
1078 urb->iso_frame_desc[j].length =
1079 dev->isoc_ctl.max_pkt_size;
1080 k += dev->isoc_ctl.max_pkt_size;
1081 }
1082 }
1083
1084 init_waitqueue_head(&dma_q->wq);
28abf083 1085 init_waitqueue_head(&vbi_dma_q->wq);
579f72e4 1086
c67ec53f 1087 em28xx_capture_start(dev, 1);
579f72e4
AT		 1088
1089 /* submit urbs and enables IRQ */
1090 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1091 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
1092 if (rc) {
1093 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1094 rc);
1095 em28xx_uninit_isoc(dev);
1096 return rc;
1097 }
1098 }
1099
1100 return 0;
1101}
1102EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1a23f81b 1103
d18e2fda
DH		 1104/* Determine the packet size for the DVB stream for the given device
1105 (underlying value programmed into the eeprom) */
1106int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
1107{
1108 unsigned int chip_cfg2;
1109 unsigned int packet_size = 564;
1110
1111 if (dev->chip_id == CHIP_ID_EM2874) {
1112 /* FIXME - for now assume 564 like it was before, but the
1113 em2874 code should be added to return the proper value... */
1114 packet_size = 564;
bc022694
AP		 1115 } else if (dev->chip_id == CHIP_ID_EM28174) {
1116 /* FIXME same as em2874. 564 was enough for 22 Mbit DVB-T
1117 but too much for 44 Mbit DVB-C. */
1118 packet_size = 752;
d18e2fda
DH		 1119 } else {
1120 /* TS max packet size stored in bits 1-0 of R01 */
1121 chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
1122 switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
1123 case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
1124 packet_size = 188;
1125 break;
1126 case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
1127 packet_size = 376;
1128 break;
1129 case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
1130 packet_size = 564;
1131 break;
1132 case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
1133 packet_size = 752;
1134 break;
1135 }
1136 }
1137
1138 em28xx_coredbg("dvb max packet size=%d\n", packet_size);
1139 return packet_size;
1140}
1141EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
1142
1a23f81b
MCC		 1143/*
1144 * em28xx_wake_i2c()
1145 * configure i2c attached devices
1146 */
1147void em28xx_wake_i2c(struct em28xx *dev)
1148{
5325b427
HV		 1149 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1150 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1151 INPUT(dev->ctl_input)->vmux, 0, 0);
f2cf250a 1152 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1a23f81b
MCC		 1153}
1154
1155/*
1156 * Device control list
1157 */
1158
1159static LIST_HEAD(em28xx_devlist);
1160static DEFINE_MUTEX(em28xx_devlist_mutex);
1161
1a23f81b
MCC		 1162/*
1163 * em28xx_realease_resources()
1164 * unregisters the v4l2,i2c and usb devices
1165 * called when the device gets disconected or at module unload
1166*/
1167void em28xx_remove_from_devlist(struct em28xx *dev)
1168{
1169 mutex_lock(&em28xx_devlist_mutex);
1170 list_del(&dev->devlist);
1171 mutex_unlock(&em28xx_devlist_mutex);
1172};
1173
1174void em28xx_add_into_devlist(struct em28xx *dev)
1175{
1176 mutex_lock(&em28xx_devlist_mutex);
1177 list_add_tail(&dev->devlist, &em28xx_devlist);
1178 mutex_unlock(&em28xx_devlist_mutex);
1179};
1180
1181/*
1182 * Extension interface
1183 */
1184
1185static LIST_HEAD(em28xx_extension_devlist);
1a23f81b
MCC		 1186
1187int em28xx_register_extension(struct em28xx_ops *ops)
1188{
1189 struct em28xx *dev = NULL;
1190
1191 mutex_lock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1192 list_add_tail(&ops->next, &em28xx_extension_devlist);
1193 list_for_each_entry(dev, &em28xx_devlist, devlist) {
517521e4 1194 ops->init(dev);
1a23f81b
MCC		 1195 }
1196 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1a23f81b
MCC		 1197 mutex_unlock(&em28xx_devlist_mutex);
1198 return 0;
1199}
1200EXPORT_SYMBOL(em28xx_register_extension);
1201
1202void em28xx_unregister_extension(struct em28xx_ops *ops)
1203{
1204 struct em28xx *dev = NULL;
1205
1206 mutex_lock(&em28xx_devlist_mutex);
1207 list_for_each_entry(dev, &em28xx_devlist, devlist) {
517521e4 1208 ops->fini(dev);
1a23f81b 1209 }
1a23f81b
MCC		 1210 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1211 list_del(&ops->next);
1a23f81b
MCC		 1212 mutex_unlock(&em28xx_devlist_mutex);
1213}
1214EXPORT_SYMBOL(em28xx_unregister_extension);
1215
1216void em28xx_init_extension(struct em28xx *dev)
1217{
1218 struct em28xx_ops *ops = NULL;
1219
5013318c 1220 mutex_lock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1221 if (!list_empty(&em28xx_extension_devlist)) {
1222 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1223 if (ops->init)
1224 ops->init(dev);
1225 }
1226 }
5013318c 1227 mutex_unlock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1228}
1229
1230void em28xx_close_extension(struct em28xx *dev)
1231{
1232 struct em28xx_ops *ops = NULL;
1233
5013318c 1234 mutex_lock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1235 if (!list_empty(&em28xx_extension_devlist)) {
1236 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1237 if (ops->fini)
1238 ops->fini(dev);
1239 }
1240 }
5013318c 1241 mutex_unlock(&em28xx_devlist_mutex);
1a23f81b 1242}
Linux 6.x block layer and io_uring tree(s)