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52fd3dda AW |
1 | /* |
2 | * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores | |
3 | * | |
4 | * Integrated Consumer Infrared Controller | |
5 | * | |
6 | * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version 2 | |
11 | * of the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
21 | * 02110-1301, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/slab.h> | |
25 | #include <linux/kfifo.h> | |
26 | #include <media/cx25840.h> | |
6bda9644 | 27 | #include <media/rc-core.h> |
52fd3dda AW |
28 | |
29 | #include "cx25840-core.h" | |
30 | ||
31 | static unsigned int ir_debug; | |
32 | module_param(ir_debug, int, 0644); | |
33 | MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages"); | |
34 | ||
35 | #define CX25840_IR_REG_BASE 0x200 | |
36 | ||
37 | #define CX25840_IR_CNTRL_REG 0x200 | |
38 | #define CNTRL_WIN_3_3 0x00000000 | |
39 | #define CNTRL_WIN_4_3 0x00000001 | |
40 | #define CNTRL_WIN_3_4 0x00000002 | |
41 | #define CNTRL_WIN_4_4 0x00000003 | |
42 | #define CNTRL_WIN 0x00000003 | |
43 | #define CNTRL_EDG_NONE 0x00000000 | |
44 | #define CNTRL_EDG_FALL 0x00000004 | |
45 | #define CNTRL_EDG_RISE 0x00000008 | |
46 | #define CNTRL_EDG_BOTH 0x0000000C | |
47 | #define CNTRL_EDG 0x0000000C | |
48 | #define CNTRL_DMD 0x00000010 | |
49 | #define CNTRL_MOD 0x00000020 | |
50 | #define CNTRL_RFE 0x00000040 | |
51 | #define CNTRL_TFE 0x00000080 | |
52 | #define CNTRL_RXE 0x00000100 | |
53 | #define CNTRL_TXE 0x00000200 | |
54 | #define CNTRL_RIC 0x00000400 | |
55 | #define CNTRL_TIC 0x00000800 | |
56 | #define CNTRL_CPL 0x00001000 | |
57 | #define CNTRL_LBM 0x00002000 | |
58 | #define CNTRL_R 0x00004000 | |
59 | ||
60 | #define CX25840_IR_TXCLK_REG 0x204 | |
61 | #define TXCLK_TCD 0x0000FFFF | |
62 | ||
63 | #define CX25840_IR_RXCLK_REG 0x208 | |
64 | #define RXCLK_RCD 0x0000FFFF | |
65 | ||
66 | #define CX25840_IR_CDUTY_REG 0x20C | |
67 | #define CDUTY_CDC 0x0000000F | |
68 | ||
69 | #define CX25840_IR_STATS_REG 0x210 | |
70 | #define STATS_RTO 0x00000001 | |
71 | #define STATS_ROR 0x00000002 | |
72 | #define STATS_RBY 0x00000004 | |
73 | #define STATS_TBY 0x00000008 | |
74 | #define STATS_RSR 0x00000010 | |
75 | #define STATS_TSR 0x00000020 | |
76 | ||
77 | #define CX25840_IR_IRQEN_REG 0x214 | |
78 | #define IRQEN_RTE 0x00000001 | |
79 | #define IRQEN_ROE 0x00000002 | |
80 | #define IRQEN_RSE 0x00000010 | |
81 | #define IRQEN_TSE 0x00000020 | |
82 | #define IRQEN_MSK 0x00000033 | |
83 | ||
84 | #define CX25840_IR_FILTR_REG 0x218 | |
85 | #define FILTR_LPF 0x0000FFFF | |
86 | ||
87 | #define CX25840_IR_FIFO_REG 0x23C | |
88 | #define FIFO_RXTX 0x0000FFFF | |
89 | #define FIFO_RXTX_LVL 0x00010000 | |
90 | #define FIFO_RXTX_RTO 0x0001FFFF | |
91 | #define FIFO_RX_NDV 0x00020000 | |
92 | #define FIFO_RX_DEPTH 8 | |
93 | #define FIFO_TX_DEPTH 8 | |
94 | ||
95 | #define CX25840_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */ | |
96 | #define CX25840_IR_REFCLK_FREQ (CX25840_VIDCLK_FREQ / 2) | |
97 | ||
c02e0d12 AW |
98 | /* |
99 | * We use this union internally for convenience, but callers to tx_write | |
100 | * and rx_read will be expecting records of type struct ir_raw_event. | |
101 | * Always ensure the size of this union is dictated by struct ir_raw_event. | |
102 | */ | |
103 | union cx25840_ir_fifo_rec { | |
104 | u32 hw_fifo_data; | |
105 | struct ir_raw_event ir_core_data; | |
106 | }; | |
107 | ||
108 | #define CX25840_IR_RX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec)) | |
109 | #define CX25840_IR_TX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec)) | |
52fd3dda AW |
110 | |
111 | struct cx25840_ir_state { | |
112 | struct i2c_client *c; | |
113 | ||
114 | struct v4l2_subdev_ir_parameters rx_params; | |
115 | struct mutex rx_params_lock; /* protects Rx parameter settings cache */ | |
116 | atomic_t rxclk_divider; | |
117 | atomic_t rx_invert; | |
118 | ||
119 | struct kfifo rx_kfifo; | |
120 | spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */ | |
121 | ||
122 | struct v4l2_subdev_ir_parameters tx_params; | |
123 | struct mutex tx_params_lock; /* protects Tx parameter settings cache */ | |
124 | atomic_t txclk_divider; | |
125 | }; | |
126 | ||
127 | static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd) | |
128 | { | |
129 | struct cx25840_state *state = to_state(sd); | |
130 | return state ? state->ir_state : NULL; | |
131 | } | |
132 | ||
133 | ||
134 | /* | |
135 | * Rx and Tx Clock Divider register computations | |
136 | * | |
137 | * Note the largest clock divider value of 0xffff corresponds to: | |
138 | * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns | |
139 | * which fits in 21 bits, so we'll use unsigned int for time arguments. | |
140 | */ | |
141 | static inline u16 count_to_clock_divider(unsigned int d) | |
142 | { | |
143 | if (d > RXCLK_RCD + 1) | |
144 | d = RXCLK_RCD; | |
145 | else if (d < 2) | |
146 | d = 1; | |
147 | else | |
148 | d--; | |
149 | return (u16) d; | |
150 | } | |
151 | ||
152 | static inline u16 ns_to_clock_divider(unsigned int ns) | |
153 | { | |
154 | return count_to_clock_divider( | |
155 | DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000)); | |
156 | } | |
157 | ||
158 | static inline unsigned int clock_divider_to_ns(unsigned int divider) | |
159 | { | |
160 | /* Period of the Rx or Tx clock in ns */ | |
161 | return DIV_ROUND_CLOSEST((divider + 1) * 1000, | |
162 | CX25840_IR_REFCLK_FREQ / 1000000); | |
163 | } | |
164 | ||
165 | static inline u16 carrier_freq_to_clock_divider(unsigned int freq) | |
166 | { | |
167 | return count_to_clock_divider( | |
168 | DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16)); | |
169 | } | |
170 | ||
171 | static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) | |
172 | { | |
173 | return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); | |
174 | } | |
175 | ||
176 | static inline u16 freq_to_clock_divider(unsigned int freq, | |
177 | unsigned int rollovers) | |
178 | { | |
179 | return count_to_clock_divider( | |
180 | DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers)); | |
181 | } | |
182 | ||
183 | static inline unsigned int clock_divider_to_freq(unsigned int divider, | |
184 | unsigned int rollovers) | |
185 | { | |
186 | return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, | |
187 | (divider + 1) * rollovers); | |
188 | } | |
189 | ||
190 | /* | |
191 | * Low Pass Filter register calculations | |
192 | * | |
193 | * Note the largest count value of 0xffff corresponds to: | |
194 | * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns | |
195 | * which fits in 21 bits, so we'll use unsigned int for time arguments. | |
196 | */ | |
197 | static inline u16 count_to_lpf_count(unsigned int d) | |
198 | { | |
199 | if (d > FILTR_LPF) | |
200 | d = FILTR_LPF; | |
201 | else if (d < 4) | |
202 | d = 0; | |
203 | return (u16) d; | |
204 | } | |
205 | ||
206 | static inline u16 ns_to_lpf_count(unsigned int ns) | |
207 | { | |
208 | return count_to_lpf_count( | |
209 | DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000)); | |
210 | } | |
211 | ||
212 | static inline unsigned int lpf_count_to_ns(unsigned int count) | |
213 | { | |
214 | /* Duration of the Low Pass Filter rejection window in ns */ | |
215 | return DIV_ROUND_CLOSEST(count * 1000, | |
216 | CX25840_IR_REFCLK_FREQ / 1000000); | |
217 | } | |
218 | ||
219 | static inline unsigned int lpf_count_to_us(unsigned int count) | |
220 | { | |
221 | /* Duration of the Low Pass Filter rejection window in us */ | |
222 | return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000); | |
223 | } | |
224 | ||
225 | /* | |
226 | * FIFO register pulse width count compuations | |
227 | */ | |
228 | static u32 clock_divider_to_resolution(u16 divider) | |
229 | { | |
230 | /* | |
231 | * Resolution is the duration of 1 tick of the readable portion of | |
232 | * of the pulse width counter as read from the FIFO. The two lsb's are | |
233 | * not readable, hence the << 2. This function returns ns. | |
234 | */ | |
235 | return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, | |
236 | CX25840_IR_REFCLK_FREQ / 1000000); | |
237 | } | |
238 | ||
239 | static u64 pulse_width_count_to_ns(u16 count, u16 divider) | |
240 | { | |
241 | u64 n; | |
242 | u32 rem; | |
243 | ||
244 | /* | |
245 | * The 2 lsb's of the pulse width timer count are not readable, hence | |
246 | * the (count << 2) | 0x3 | |
247 | */ | |
248 | n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ | |
249 | rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */ | |
250 | if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2) | |
251 | n++; | |
252 | return n; | |
253 | } | |
254 | ||
255 | #if 0 | |
256 | /* Keep as we will need this for Transmit functionality */ | |
257 | static u16 ns_to_pulse_width_count(u32 ns, u16 divider) | |
258 | { | |
259 | u64 n; | |
260 | u32 d; | |
261 | u32 rem; | |
262 | ||
263 | /* | |
264 | * The 2 lsb's of the pulse width timer count are not accessable, hence | |
265 | * the (1 << 2) | |
266 | */ | |
267 | n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */ | |
268 | d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */ | |
269 | rem = do_div(n, d); | |
270 | if (rem >= d / 2) | |
271 | n++; | |
272 | ||
273 | if (n > FIFO_RXTX) | |
274 | n = FIFO_RXTX; | |
275 | else if (n == 0) | |
276 | n = 1; | |
277 | return (u16) n; | |
278 | } | |
279 | ||
280 | #endif | |
281 | static unsigned int pulse_width_count_to_us(u16 count, u16 divider) | |
282 | { | |
283 | u64 n; | |
284 | u32 rem; | |
285 | ||
286 | /* | |
287 | * The 2 lsb's of the pulse width timer count are not readable, hence | |
288 | * the (count << 2) | 0x3 | |
289 | */ | |
290 | n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ | |
291 | rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */ | |
292 | if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2) | |
293 | n++; | |
294 | return (unsigned int) n; | |
295 | } | |
296 | ||
297 | /* | |
298 | * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts | |
299 | * | |
300 | * The total pulse clock count is an 18 bit pulse width timer count as the most | |
301 | * significant part and (up to) 16 bit clock divider count as a modulus. | |
302 | * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse | |
303 | * width timer count's least significant bit. | |
304 | */ | |
305 | static u64 ns_to_pulse_clocks(u32 ns) | |
306 | { | |
307 | u64 clocks; | |
308 | u32 rem; | |
309 | clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ | |
310 | rem = do_div(clocks, 1000); /* /1000 = cycles */ | |
311 | if (rem >= 1000 / 2) | |
312 | clocks++; | |
313 | return clocks; | |
314 | } | |
315 | ||
316 | static u16 pulse_clocks_to_clock_divider(u64 count) | |
317 | { | |
318 | u32 rem; | |
319 | ||
320 | rem = do_div(count, (FIFO_RXTX << 2) | 0x3); | |
321 | ||
322 | /* net result needs to be rounded down and decremented by 1 */ | |
323 | if (count > RXCLK_RCD + 1) | |
324 | count = RXCLK_RCD; | |
325 | else if (count < 2) | |
326 | count = 1; | |
327 | else | |
328 | count--; | |
329 | return (u16) count; | |
330 | } | |
331 | ||
332 | /* | |
333 | * IR Control Register helpers | |
334 | */ | |
335 | enum tx_fifo_watermark { | |
336 | TX_FIFO_HALF_EMPTY = 0, | |
337 | TX_FIFO_EMPTY = CNTRL_TIC, | |
338 | }; | |
339 | ||
340 | enum rx_fifo_watermark { | |
341 | RX_FIFO_HALF_FULL = 0, | |
342 | RX_FIFO_NOT_EMPTY = CNTRL_RIC, | |
343 | }; | |
344 | ||
345 | static inline void control_tx_irq_watermark(struct i2c_client *c, | |
346 | enum tx_fifo_watermark level) | |
347 | { | |
348 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level); | |
349 | } | |
350 | ||
351 | static inline void control_rx_irq_watermark(struct i2c_client *c, | |
352 | enum rx_fifo_watermark level) | |
353 | { | |
354 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level); | |
355 | } | |
356 | ||
357 | static inline void control_tx_enable(struct i2c_client *c, bool enable) | |
358 | { | |
359 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE), | |
360 | enable ? (CNTRL_TXE | CNTRL_TFE) : 0); | |
361 | } | |
362 | ||
363 | static inline void control_rx_enable(struct i2c_client *c, bool enable) | |
364 | { | |
365 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE), | |
366 | enable ? (CNTRL_RXE | CNTRL_RFE) : 0); | |
367 | } | |
368 | ||
369 | static inline void control_tx_modulation_enable(struct i2c_client *c, | |
370 | bool enable) | |
371 | { | |
372 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD, | |
373 | enable ? CNTRL_MOD : 0); | |
374 | } | |
375 | ||
376 | static inline void control_rx_demodulation_enable(struct i2c_client *c, | |
377 | bool enable) | |
378 | { | |
379 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD, | |
380 | enable ? CNTRL_DMD : 0); | |
381 | } | |
382 | ||
383 | static inline void control_rx_s_edge_detection(struct i2c_client *c, | |
384 | u32 edge_types) | |
385 | { | |
386 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH, | |
387 | edge_types & CNTRL_EDG_BOTH); | |
388 | } | |
389 | ||
390 | static void control_rx_s_carrier_window(struct i2c_client *c, | |
391 | unsigned int carrier, | |
392 | unsigned int *carrier_range_low, | |
393 | unsigned int *carrier_range_high) | |
394 | { | |
395 | u32 v; | |
396 | unsigned int c16 = carrier * 16; | |
397 | ||
398 | if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) { | |
399 | v = CNTRL_WIN_3_4; | |
400 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4); | |
401 | } else { | |
402 | v = CNTRL_WIN_3_3; | |
403 | *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3); | |
404 | } | |
405 | ||
406 | if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) { | |
407 | v |= CNTRL_WIN_4_3; | |
408 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4); | |
409 | } else { | |
410 | v |= CNTRL_WIN_3_3; | |
411 | *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3); | |
412 | } | |
413 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v); | |
414 | } | |
415 | ||
416 | static inline void control_tx_polarity_invert(struct i2c_client *c, | |
417 | bool invert) | |
418 | { | |
419 | cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL, | |
420 | invert ? CNTRL_CPL : 0); | |
421 | } | |
422 | ||
423 | /* | |
424 | * IR Rx & Tx Clock Register helpers | |
425 | */ | |
426 | static unsigned int txclk_tx_s_carrier(struct i2c_client *c, | |
427 | unsigned int freq, | |
428 | u16 *divider) | |
429 | { | |
430 | *divider = carrier_freq_to_clock_divider(freq); | |
431 | cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider); | |
432 | return clock_divider_to_carrier_freq(*divider); | |
433 | } | |
434 | ||
435 | static unsigned int rxclk_rx_s_carrier(struct i2c_client *c, | |
436 | unsigned int freq, | |
437 | u16 *divider) | |
438 | { | |
439 | *divider = carrier_freq_to_clock_divider(freq); | |
440 | cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider); | |
441 | return clock_divider_to_carrier_freq(*divider); | |
442 | } | |
443 | ||
444 | static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns, | |
445 | u16 *divider) | |
446 | { | |
447 | u64 pulse_clocks; | |
448 | ||
c02e0d12 AW |
449 | if (ns > IR_MAX_DURATION) |
450 | ns = IR_MAX_DURATION; | |
52fd3dda AW |
451 | pulse_clocks = ns_to_pulse_clocks(ns); |
452 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); | |
453 | cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider); | |
454 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); | |
455 | } | |
456 | ||
457 | static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns, | |
458 | u16 *divider) | |
459 | { | |
460 | u64 pulse_clocks; | |
461 | ||
c02e0d12 AW |
462 | if (ns > IR_MAX_DURATION) |
463 | ns = IR_MAX_DURATION; | |
52fd3dda AW |
464 | pulse_clocks = ns_to_pulse_clocks(ns); |
465 | *divider = pulse_clocks_to_clock_divider(pulse_clocks); | |
466 | cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider); | |
467 | return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider); | |
468 | } | |
469 | ||
470 | /* | |
471 | * IR Tx Carrier Duty Cycle register helpers | |
472 | */ | |
473 | static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c, | |
474 | unsigned int duty_cycle) | |
475 | { | |
476 | u32 n; | |
477 | n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */ | |
478 | if (n != 0) | |
479 | n--; | |
480 | if (n > 15) | |
481 | n = 15; | |
482 | cx25840_write4(c, CX25840_IR_CDUTY_REG, n); | |
483 | return DIV_ROUND_CLOSEST((n + 1) * 100, 16); | |
484 | } | |
485 | ||
486 | /* | |
487 | * IR Filter Register helpers | |
488 | */ | |
489 | static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns) | |
490 | { | |
491 | u32 count = ns_to_lpf_count(min_width_ns); | |
492 | cx25840_write4(c, CX25840_IR_FILTR_REG, count); | |
493 | return lpf_count_to_ns(count); | |
494 | } | |
495 | ||
496 | /* | |
497 | * IR IRQ Enable Register helpers | |
498 | */ | |
499 | static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask) | |
500 | { | |
501 | struct cx25840_state *state = to_state(sd); | |
502 | ||
503 | if (is_cx23885(state) || is_cx23887(state)) | |
504 | mask ^= IRQEN_MSK; | |
505 | mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); | |
506 | cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, | |
507 | ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); | |
508 | } | |
509 | ||
510 | static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask) | |
511 | { | |
512 | struct cx25840_state *state = to_state(sd); | |
513 | ||
514 | if (is_cx23885(state) || is_cx23887(state)) | |
515 | mask ^= IRQEN_MSK; | |
516 | mask &= IRQEN_TSE; | |
517 | cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask); | |
518 | } | |
519 | ||
520 | /* | |
521 | * V4L2 Subdevice IR Ops | |
522 | */ | |
523 | int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled) | |
524 | { | |
525 | struct cx25840_state *state = to_state(sd); | |
526 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
527 | struct i2c_client *c = NULL; | |
528 | unsigned long flags; | |
529 | ||
c02e0d12 AW |
530 | union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH]; |
531 | unsigned int i, j, k; | |
52fd3dda AW |
532 | u32 events, v; |
533 | int tsr, rsr, rto, ror, tse, rse, rte, roe, kror; | |
534 | u32 cntrl, irqen, stats; | |
535 | ||
536 | *handled = false; | |
537 | if (ir_state == NULL) | |
538 | return -ENODEV; | |
539 | ||
540 | c = ir_state->c; | |
541 | ||
542 | /* Only support the IR controller for the CX2388[57] AV Core for now */ | |
543 | if (!(is_cx23885(state) || is_cx23887(state))) | |
544 | return -ENODEV; | |
545 | ||
546 | cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG); | |
547 | irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG); | |
548 | if (is_cx23885(state) || is_cx23887(state)) | |
549 | irqen ^= IRQEN_MSK; | |
550 | stats = cx25840_read4(c, CX25840_IR_STATS_REG); | |
551 | ||
552 | tsr = stats & STATS_TSR; /* Tx FIFO Service Request */ | |
553 | rsr = stats & STATS_RSR; /* Rx FIFO Service Request */ | |
554 | rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */ | |
555 | ror = stats & STATS_ROR; /* Rx FIFO Over Run */ | |
556 | ||
557 | tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ | |
558 | rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ | |
559 | rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ | |
560 | roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ | |
561 | ||
562 | v4l2_dbg(2, ir_debug, sd, "IR IRQ Status: %s %s %s %s %s %s\n", | |
563 | tsr ? "tsr" : " ", rsr ? "rsr" : " ", | |
564 | rto ? "rto" : " ", ror ? "ror" : " ", | |
565 | stats & STATS_TBY ? "tby" : " ", | |
566 | stats & STATS_RBY ? "rby" : " "); | |
567 | ||
568 | v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n", | |
569 | tse ? "tse" : " ", rse ? "rse" : " ", | |
570 | rte ? "rte" : " ", roe ? "roe" : " "); | |
571 | ||
572 | /* | |
573 | * Transmitter interrupt service | |
574 | */ | |
575 | if (tse && tsr) { | |
576 | /* | |
577 | * TODO: | |
578 | * Check the watermark threshold setting | |
579 | * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo | |
580 | * Push the data to the hardware FIFO. | |
581 | * If there was nothing more to send in the tx_kfifo, disable | |
582 | * the TSR IRQ and notify the v4l2_device. | |
583 | * If there was something in the tx_kfifo, check the tx_kfifo | |
584 | * level and notify the v4l2_device, if it is low. | |
585 | */ | |
586 | /* For now, inhibit TSR interrupt until Tx is implemented */ | |
587 | irqenable_tx(sd, 0); | |
588 | events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ; | |
589 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events); | |
590 | *handled = true; | |
591 | } | |
592 | ||
593 | /* | |
594 | * Receiver interrupt service | |
595 | */ | |
596 | kror = 0; | |
597 | if ((rse && rsr) || (rte && rto)) { | |
598 | /* | |
599 | * Receive data on RSR to clear the STATS_RSR. | |
600 | * Receive data on RTO, since we may not have yet hit the RSR | |
601 | * watermark when we receive the RTO. | |
602 | */ | |
603 | for (i = 0, v = FIFO_RX_NDV; | |
604 | (v & FIFO_RX_NDV) && !kror; i = 0) { | |
605 | for (j = 0; | |
606 | (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) { | |
607 | v = cx25840_read4(c, CX25840_IR_FIFO_REG); | |
c02e0d12 AW |
608 | rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV; |
609 | i++; | |
52fd3dda AW |
610 | } |
611 | if (i == 0) | |
612 | break; | |
c02e0d12 | 613 | j = i * sizeof(union cx25840_ir_fifo_rec); |
52fd3dda AW |
614 | k = kfifo_in_locked(&ir_state->rx_kfifo, |
615 | (unsigned char *) rx_data, j, | |
616 | &ir_state->rx_kfifo_lock); | |
617 | if (k != j) | |
618 | kror++; /* rx_kfifo over run */ | |
619 | } | |
620 | *handled = true; | |
621 | } | |
622 | ||
623 | events = 0; | |
624 | v = 0; | |
625 | if (kror) { | |
626 | events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN; | |
627 | v4l2_err(sd, "IR receiver software FIFO overrun\n"); | |
628 | } | |
629 | if (roe && ror) { | |
630 | /* | |
631 | * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear | |
632 | * the Rx FIFO Over Run status (STATS_ROR) | |
633 | */ | |
634 | v |= CNTRL_RFE; | |
635 | events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN; | |
636 | v4l2_err(sd, "IR receiver hardware FIFO overrun\n"); | |
637 | } | |
638 | if (rte && rto) { | |
639 | /* | |
640 | * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear | |
641 | * the Rx Pulse Width Timer Time Out (STATS_RTO) | |
642 | */ | |
643 | v |= CNTRL_RXE; | |
644 | events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; | |
645 | } | |
646 | if (v) { | |
647 | /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ | |
648 | cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v); | |
649 | cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl); | |
650 | *handled = true; | |
651 | } | |
652 | spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags); | |
653 | if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2) | |
654 | events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; | |
655 | spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags); | |
656 | ||
657 | if (events) | |
658 | v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events); | |
659 | return 0; | |
660 | } | |
661 | ||
662 | /* Receiver */ | |
663 | static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count, | |
664 | ssize_t *num) | |
665 | { | |
666 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
667 | bool invert; | |
668 | u16 divider; | |
669 | unsigned int i, n; | |
c02e0d12 AW |
670 | union cx25840_ir_fifo_rec *p; |
671 | unsigned u, v; | |
52fd3dda AW |
672 | |
673 | if (ir_state == NULL) | |
674 | return -ENODEV; | |
675 | ||
676 | invert = (bool) atomic_read(&ir_state->rx_invert); | |
677 | divider = (u16) atomic_read(&ir_state->rxclk_divider); | |
678 | ||
c02e0d12 AW |
679 | n = count / sizeof(union cx25840_ir_fifo_rec) |
680 | * sizeof(union cx25840_ir_fifo_rec); | |
52fd3dda AW |
681 | if (n == 0) { |
682 | *num = 0; | |
683 | return 0; | |
684 | } | |
685 | ||
686 | n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n, | |
687 | &ir_state->rx_kfifo_lock); | |
688 | ||
c02e0d12 AW |
689 | n /= sizeof(union cx25840_ir_fifo_rec); |
690 | *num = n * sizeof(union cx25840_ir_fifo_rec); | |
52fd3dda | 691 | |
c02e0d12 | 692 | for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) { |
2560d94e | 693 | |
c02e0d12 | 694 | if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) { |
2560d94e AW |
695 | /* Assume RTO was because of no IR light input */ |
696 | u = 0; | |
52fd3dda | 697 | v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n"); |
2560d94e | 698 | } else { |
c02e0d12 | 699 | u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0; |
2560d94e | 700 | if (invert) |
c02e0d12 | 701 | u = u ? 0 : 1; |
52fd3dda AW |
702 | } |
703 | ||
c02e0d12 AW |
704 | v = (unsigned) pulse_width_count_to_ns( |
705 | (u16) (p->hw_fifo_data & FIFO_RXTX), divider); | |
706 | if (v > IR_MAX_DURATION) | |
707 | v = IR_MAX_DURATION; | |
52fd3dda | 708 | |
dc697984 | 709 | init_ir_raw_event(&p->ir_core_data); |
c02e0d12 AW |
710 | p->ir_core_data.pulse = u; |
711 | p->ir_core_data.duration = v; | |
52fd3dda AW |
712 | |
713 | v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s\n", | |
714 | v, u ? "mark" : "space"); | |
715 | } | |
716 | return 0; | |
717 | } | |
718 | ||
719 | static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd, | |
720 | struct v4l2_subdev_ir_parameters *p) | |
721 | { | |
722 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
723 | ||
724 | if (ir_state == NULL) | |
725 | return -ENODEV; | |
726 | ||
727 | mutex_lock(&ir_state->rx_params_lock); | |
728 | memcpy(p, &ir_state->rx_params, | |
729 | sizeof(struct v4l2_subdev_ir_parameters)); | |
730 | mutex_unlock(&ir_state->rx_params_lock); | |
731 | return 0; | |
732 | } | |
733 | ||
734 | static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd) | |
735 | { | |
736 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
737 | struct i2c_client *c; | |
738 | ||
739 | if (ir_state == NULL) | |
740 | return -ENODEV; | |
741 | ||
742 | c = ir_state->c; | |
743 | mutex_lock(&ir_state->rx_params_lock); | |
744 | ||
745 | /* Disable or slow down all IR Rx circuits and counters */ | |
746 | irqenable_rx(sd, 0); | |
747 | control_rx_enable(c, false); | |
748 | control_rx_demodulation_enable(c, false); | |
749 | control_rx_s_edge_detection(c, CNTRL_EDG_NONE); | |
750 | filter_rx_s_min_width(c, 0); | |
751 | cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD); | |
752 | ||
753 | ir_state->rx_params.shutdown = true; | |
754 | ||
755 | mutex_unlock(&ir_state->rx_params_lock); | |
756 | return 0; | |
757 | } | |
758 | ||
759 | static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd, | |
760 | struct v4l2_subdev_ir_parameters *p) | |
761 | { | |
762 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
763 | struct i2c_client *c; | |
764 | struct v4l2_subdev_ir_parameters *o; | |
765 | u16 rxclk_divider; | |
766 | ||
767 | if (ir_state == NULL) | |
768 | return -ENODEV; | |
769 | ||
770 | if (p->shutdown) | |
771 | return cx25840_ir_rx_shutdown(sd); | |
772 | ||
773 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) | |
774 | return -ENOSYS; | |
775 | ||
776 | c = ir_state->c; | |
777 | o = &ir_state->rx_params; | |
778 | ||
779 | mutex_lock(&ir_state->rx_params_lock); | |
780 | ||
781 | o->shutdown = p->shutdown; | |
782 | ||
783 | p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; | |
784 | o->mode = p->mode; | |
785 | ||
c02e0d12 | 786 | p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec); |
52fd3dda AW |
787 | o->bytes_per_data_element = p->bytes_per_data_element; |
788 | ||
789 | /* Before we tweak the hardware, we have to disable the receiver */ | |
790 | irqenable_rx(sd, 0); | |
791 | control_rx_enable(c, false); | |
792 | ||
793 | control_rx_demodulation_enable(c, p->modulation); | |
794 | o->modulation = p->modulation; | |
795 | ||
796 | if (p->modulation) { | |
797 | p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq, | |
798 | &rxclk_divider); | |
799 | ||
800 | o->carrier_freq = p->carrier_freq; | |
801 | ||
802 | p->duty_cycle = 50; | |
803 | o->duty_cycle = p->duty_cycle; | |
804 | ||
805 | control_rx_s_carrier_window(c, p->carrier_freq, | |
806 | &p->carrier_range_lower, | |
807 | &p->carrier_range_upper); | |
808 | o->carrier_range_lower = p->carrier_range_lower; | |
809 | o->carrier_range_upper = p->carrier_range_upper; | |
ceb152ad AW |
810 | |
811 | p->max_pulse_width = | |
812 | (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); | |
52fd3dda AW |
813 | } else { |
814 | p->max_pulse_width = | |
815 | rxclk_rx_s_max_pulse_width(c, p->max_pulse_width, | |
816 | &rxclk_divider); | |
52fd3dda | 817 | } |
ceb152ad | 818 | o->max_pulse_width = p->max_pulse_width; |
52fd3dda AW |
819 | atomic_set(&ir_state->rxclk_divider, rxclk_divider); |
820 | ||
821 | p->noise_filter_min_width = | |
822 | filter_rx_s_min_width(c, p->noise_filter_min_width); | |
823 | o->noise_filter_min_width = p->noise_filter_min_width; | |
824 | ||
825 | p->resolution = clock_divider_to_resolution(rxclk_divider); | |
826 | o->resolution = p->resolution; | |
827 | ||
828 | /* FIXME - make this dependent on resolution for better performance */ | |
829 | control_rx_irq_watermark(c, RX_FIFO_HALF_FULL); | |
830 | ||
831 | control_rx_s_edge_detection(c, CNTRL_EDG_BOTH); | |
832 | ||
833 | o->invert_level = p->invert_level; | |
834 | atomic_set(&ir_state->rx_invert, p->invert_level); | |
835 | ||
836 | o->interrupt_enable = p->interrupt_enable; | |
837 | o->enable = p->enable; | |
838 | if (p->enable) { | |
839 | unsigned long flags; | |
840 | ||
841 | spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags); | |
842 | kfifo_reset(&ir_state->rx_kfifo); | |
843 | spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags); | |
844 | if (p->interrupt_enable) | |
845 | irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE); | |
846 | control_rx_enable(c, p->enable); | |
847 | } | |
848 | ||
849 | mutex_unlock(&ir_state->rx_params_lock); | |
850 | return 0; | |
851 | } | |
852 | ||
853 | /* Transmitter */ | |
854 | static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count, | |
855 | ssize_t *num) | |
856 | { | |
857 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
858 | struct i2c_client *c; | |
859 | ||
860 | if (ir_state == NULL) | |
861 | return -ENODEV; | |
862 | ||
863 | c = ir_state->c; | |
864 | #if 0 | |
865 | /* | |
866 | * FIXME - the code below is an incomplete and untested sketch of what | |
867 | * may need to be done. The critical part is to get 4 (or 8) pulses | |
868 | * from the tx_kfifo, or converted from ns to the proper units from the | |
869 | * input, and push them off to the hardware Tx FIFO right away, if the | |
870 | * HW TX fifo needs service. The rest can be pushed to the tx_kfifo in | |
871 | * a less critical timeframe. Also watch out for overruning the | |
872 | * tx_kfifo - don't let it happen and let the caller know not all his | |
873 | * pulses were written. | |
874 | */ | |
875 | u32 *ns_pulse = (u32 *) buf; | |
876 | unsigned int n; | |
877 | u32 fifo_pulse[FIFO_TX_DEPTH]; | |
878 | u32 mark; | |
879 | ||
880 | /* Compute how much we can fit in the tx kfifo */ | |
881 | n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo); | |
882 | n = min(n, (unsigned int) count); | |
883 | n /= sizeof(u32); | |
884 | ||
885 | /* FIXME - turn on Tx Fifo service interrupt | |
886 | * check hardware fifo level, and other stuff | |
887 | */ | |
888 | for (i = 0; i < n; ) { | |
889 | for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) { | |
d69e85b6 | 890 | mark = ns_pulse[i] & LEVEL_MASK; |
52fd3dda AW |
891 | fifo_pulse[j] = ns_to_pulse_width_count( |
892 | ns_pulse[i] & | |
d69e85b6 | 893 | ~LEVEL_MASK, |
52fd3dda AW |
894 | ir_state->txclk_divider); |
895 | if (mark) | |
896 | fifo_pulse[j] &= FIFO_RXTX_LVL; | |
897 | i++; | |
898 | } | |
899 | kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse, | |
900 | j * sizeof(u32)); | |
901 | } | |
902 | *num = n * sizeof(u32); | |
903 | #else | |
904 | /* For now enable the Tx FIFO Service interrupt & pretend we did work */ | |
905 | irqenable_tx(sd, IRQEN_TSE); | |
906 | *num = count; | |
907 | #endif | |
908 | return 0; | |
909 | } | |
910 | ||
911 | static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd, | |
912 | struct v4l2_subdev_ir_parameters *p) | |
913 | { | |
914 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
915 | ||
916 | if (ir_state == NULL) | |
917 | return -ENODEV; | |
918 | ||
919 | mutex_lock(&ir_state->tx_params_lock); | |
920 | memcpy(p, &ir_state->tx_params, | |
921 | sizeof(struct v4l2_subdev_ir_parameters)); | |
922 | mutex_unlock(&ir_state->tx_params_lock); | |
923 | return 0; | |
924 | } | |
925 | ||
926 | static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd) | |
927 | { | |
928 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
929 | struct i2c_client *c; | |
930 | ||
931 | if (ir_state == NULL) | |
932 | return -ENODEV; | |
933 | ||
934 | c = ir_state->c; | |
935 | mutex_lock(&ir_state->tx_params_lock); | |
936 | ||
937 | /* Disable or slow down all IR Tx circuits and counters */ | |
938 | irqenable_tx(sd, 0); | |
939 | control_tx_enable(c, false); | |
940 | control_tx_modulation_enable(c, false); | |
941 | cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD); | |
942 | ||
943 | ir_state->tx_params.shutdown = true; | |
944 | ||
945 | mutex_unlock(&ir_state->tx_params_lock); | |
946 | return 0; | |
947 | } | |
948 | ||
949 | static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd, | |
950 | struct v4l2_subdev_ir_parameters *p) | |
951 | { | |
952 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
953 | struct i2c_client *c; | |
954 | struct v4l2_subdev_ir_parameters *o; | |
955 | u16 txclk_divider; | |
956 | ||
957 | if (ir_state == NULL) | |
958 | return -ENODEV; | |
959 | ||
960 | if (p->shutdown) | |
961 | return cx25840_ir_tx_shutdown(sd); | |
962 | ||
963 | if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH) | |
964 | return -ENOSYS; | |
965 | ||
966 | c = ir_state->c; | |
967 | o = &ir_state->tx_params; | |
968 | mutex_lock(&ir_state->tx_params_lock); | |
969 | ||
970 | o->shutdown = p->shutdown; | |
971 | ||
972 | p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH; | |
973 | o->mode = p->mode; | |
974 | ||
c02e0d12 | 975 | p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec); |
52fd3dda AW |
976 | o->bytes_per_data_element = p->bytes_per_data_element; |
977 | ||
978 | /* Before we tweak the hardware, we have to disable the transmitter */ | |
979 | irqenable_tx(sd, 0); | |
980 | control_tx_enable(c, false); | |
981 | ||
982 | control_tx_modulation_enable(c, p->modulation); | |
983 | o->modulation = p->modulation; | |
984 | ||
985 | if (p->modulation) { | |
986 | p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq, | |
987 | &txclk_divider); | |
988 | o->carrier_freq = p->carrier_freq; | |
989 | ||
990 | p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle); | |
991 | o->duty_cycle = p->duty_cycle; | |
ceb152ad AW |
992 | |
993 | p->max_pulse_width = | |
994 | (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); | |
52fd3dda AW |
995 | } else { |
996 | p->max_pulse_width = | |
997 | txclk_tx_s_max_pulse_width(c, p->max_pulse_width, | |
998 | &txclk_divider); | |
52fd3dda | 999 | } |
ceb152ad | 1000 | o->max_pulse_width = p->max_pulse_width; |
52fd3dda AW |
1001 | atomic_set(&ir_state->txclk_divider, txclk_divider); |
1002 | ||
1003 | p->resolution = clock_divider_to_resolution(txclk_divider); | |
1004 | o->resolution = p->resolution; | |
1005 | ||
1006 | /* FIXME - make this dependent on resolution for better performance */ | |
1007 | control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY); | |
1008 | ||
1009 | control_tx_polarity_invert(c, p->invert_carrier_sense); | |
1010 | o->invert_carrier_sense = p->invert_carrier_sense; | |
1011 | ||
1012 | /* | |
1013 | * FIXME: we don't have hardware help for IO pin level inversion | |
1014 | * here like we have on the CX23888. | |
1015 | * Act on this with some mix of logical inversion of data levels, | |
1016 | * carrier polarity, and carrier duty cycle. | |
1017 | */ | |
1018 | o->invert_level = p->invert_level; | |
1019 | ||
1020 | o->interrupt_enable = p->interrupt_enable; | |
1021 | o->enable = p->enable; | |
1022 | if (p->enable) { | |
1023 | /* reset tx_fifo here */ | |
1024 | if (p->interrupt_enable) | |
1025 | irqenable_tx(sd, IRQEN_TSE); | |
1026 | control_tx_enable(c, p->enable); | |
1027 | } | |
1028 | ||
1029 | mutex_unlock(&ir_state->tx_params_lock); | |
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | ||
1034 | /* | |
1035 | * V4L2 Subdevice Core Ops support | |
1036 | */ | |
1037 | int cx25840_ir_log_status(struct v4l2_subdev *sd) | |
1038 | { | |
1039 | struct cx25840_state *state = to_state(sd); | |
1040 | struct i2c_client *c = state->c; | |
1041 | char *s; | |
1042 | int i, j; | |
1043 | u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr; | |
1044 | ||
1045 | /* The CX23888 chip doesn't have an IR controller on the A/V core */ | |
1046 | if (is_cx23888(state)) | |
1047 | return 0; | |
1048 | ||
1049 | cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG); | |
1050 | txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD; | |
1051 | rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD; | |
1052 | cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC; | |
1053 | stats = cx25840_read4(c, CX25840_IR_STATS_REG); | |
1054 | irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG); | |
1055 | if (is_cx23885(state) || is_cx23887(state)) | |
1056 | irqen ^= IRQEN_MSK; | |
1057 | filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF; | |
1058 | ||
1059 | v4l2_info(sd, "IR Receiver:\n"); | |
1060 | v4l2_info(sd, "\tEnabled: %s\n", | |
1061 | cntrl & CNTRL_RXE ? "yes" : "no"); | |
1062 | v4l2_info(sd, "\tDemodulation from a carrier: %s\n", | |
1063 | cntrl & CNTRL_DMD ? "enabled" : "disabled"); | |
1064 | v4l2_info(sd, "\tFIFO: %s\n", | |
1065 | cntrl & CNTRL_RFE ? "enabled" : "disabled"); | |
1066 | switch (cntrl & CNTRL_EDG) { | |
1067 | case CNTRL_EDG_NONE: | |
1068 | s = "disabled"; | |
1069 | break; | |
1070 | case CNTRL_EDG_FALL: | |
1071 | s = "falling edge"; | |
1072 | break; | |
1073 | case CNTRL_EDG_RISE: | |
1074 | s = "rising edge"; | |
1075 | break; | |
1076 | case CNTRL_EDG_BOTH: | |
1077 | s = "rising & falling edges"; | |
1078 | break; | |
1079 | default: | |
1080 | s = "??? edge"; | |
1081 | break; | |
1082 | } | |
1083 | v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s); | |
1084 | v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n", | |
1085 | cntrl & CNTRL_R ? "not loaded" : "overflow marker"); | |
1086 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", | |
1087 | cntrl & CNTRL_RIC ? "not empty" : "half full or greater"); | |
1088 | v4l2_info(sd, "\tLoopback mode: %s\n", | |
1089 | cntrl & CNTRL_LBM ? "loopback active" : "normal receive"); | |
1090 | if (cntrl & CNTRL_DMD) { | |
1091 | v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n", | |
1092 | clock_divider_to_carrier_freq(rxclk)); | |
1093 | switch (cntrl & CNTRL_WIN) { | |
1094 | case CNTRL_WIN_3_3: | |
1095 | i = 3; | |
1096 | j = 3; | |
1097 | break; | |
1098 | case CNTRL_WIN_4_3: | |
1099 | i = 4; | |
1100 | j = 3; | |
1101 | break; | |
1102 | case CNTRL_WIN_3_4: | |
1103 | i = 3; | |
1104 | j = 4; | |
1105 | break; | |
1106 | case CNTRL_WIN_4_4: | |
1107 | i = 4; | |
1108 | j = 4; | |
1109 | break; | |
1110 | default: | |
1111 | i = 0; | |
1112 | j = 0; | |
1113 | break; | |
1114 | } | |
1115 | v4l2_info(sd, "\tNext carrier edge window: 16 clocks " | |
1116 | "-%1d/+%1d, %u to %u Hz\n", i, j, | |
1117 | clock_divider_to_freq(rxclk, 16 + j), | |
1118 | clock_divider_to_freq(rxclk, 16 - i)); | |
52fd3dda | 1119 | } |
ceb152ad AW |
1120 | v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", |
1121 | pulse_width_count_to_us(FIFO_RXTX, rxclk), | |
1122 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); | |
52fd3dda AW |
1123 | v4l2_info(sd, "\tLow pass filter: %s\n", |
1124 | filtr ? "enabled" : "disabled"); | |
1125 | if (filtr) | |
1126 | v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, " | |
1127 | "%u ns\n", | |
1128 | lpf_count_to_us(filtr), | |
1129 | lpf_count_to_ns(filtr)); | |
1130 | v4l2_info(sd, "\tPulse width timer timed-out: %s\n", | |
1131 | stats & STATS_RTO ? "yes" : "no"); | |
1132 | v4l2_info(sd, "\tPulse width timer time-out intr: %s\n", | |
1133 | irqen & IRQEN_RTE ? "enabled" : "disabled"); | |
1134 | v4l2_info(sd, "\tFIFO overrun: %s\n", | |
1135 | stats & STATS_ROR ? "yes" : "no"); | |
1136 | v4l2_info(sd, "\tFIFO overrun interrupt: %s\n", | |
1137 | irqen & IRQEN_ROE ? "enabled" : "disabled"); | |
1138 | v4l2_info(sd, "\tBusy: %s\n", | |
1139 | stats & STATS_RBY ? "yes" : "no"); | |
1140 | v4l2_info(sd, "\tFIFO service requested: %s\n", | |
1141 | stats & STATS_RSR ? "yes" : "no"); | |
1142 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", | |
1143 | irqen & IRQEN_RSE ? "enabled" : "disabled"); | |
1144 | ||
1145 | v4l2_info(sd, "IR Transmitter:\n"); | |
1146 | v4l2_info(sd, "\tEnabled: %s\n", | |
1147 | cntrl & CNTRL_TXE ? "yes" : "no"); | |
1148 | v4l2_info(sd, "\tModulation onto a carrier: %s\n", | |
1149 | cntrl & CNTRL_MOD ? "enabled" : "disabled"); | |
1150 | v4l2_info(sd, "\tFIFO: %s\n", | |
1151 | cntrl & CNTRL_TFE ? "enabled" : "disabled"); | |
1152 | v4l2_info(sd, "\tFIFO interrupt watermark: %s\n", | |
1153 | cntrl & CNTRL_TIC ? "not empty" : "half full or less"); | |
1154 | v4l2_info(sd, "\tCarrier polarity: %s\n", | |
1155 | cntrl & CNTRL_CPL ? "space:burst mark:noburst" | |
1156 | : "space:noburst mark:burst"); | |
1157 | if (cntrl & CNTRL_MOD) { | |
1158 | v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n", | |
1159 | clock_divider_to_carrier_freq(txclk)); | |
1160 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", | |
1161 | cduty + 1); | |
52fd3dda | 1162 | } |
ceb152ad AW |
1163 | v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", |
1164 | pulse_width_count_to_us(FIFO_RXTX, txclk), | |
1165 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); | |
52fd3dda AW |
1166 | v4l2_info(sd, "\tBusy: %s\n", |
1167 | stats & STATS_TBY ? "yes" : "no"); | |
1168 | v4l2_info(sd, "\tFIFO service requested: %s\n", | |
1169 | stats & STATS_TSR ? "yes" : "no"); | |
1170 | v4l2_info(sd, "\tFIFO service request interrupt: %s\n", | |
1171 | irqen & IRQEN_TSE ? "enabled" : "disabled"); | |
1172 | ||
1173 | return 0; | |
1174 | } | |
1175 | ||
1176 | ||
1177 | const struct v4l2_subdev_ir_ops cx25840_ir_ops = { | |
1178 | .rx_read = cx25840_ir_rx_read, | |
1179 | .rx_g_parameters = cx25840_ir_rx_g_parameters, | |
1180 | .rx_s_parameters = cx25840_ir_rx_s_parameters, | |
1181 | ||
1182 | .tx_write = cx25840_ir_tx_write, | |
1183 | .tx_g_parameters = cx25840_ir_tx_g_parameters, | |
1184 | .tx_s_parameters = cx25840_ir_tx_s_parameters, | |
1185 | }; | |
1186 | ||
1187 | ||
1188 | static const struct v4l2_subdev_ir_parameters default_rx_params = { | |
c02e0d12 | 1189 | .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec), |
52fd3dda AW |
1190 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, |
1191 | ||
1192 | .enable = false, | |
1193 | .interrupt_enable = false, | |
1194 | .shutdown = true, | |
1195 | ||
1196 | .modulation = true, | |
1197 | .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */ | |
1198 | ||
1199 | /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */ | |
1200 | /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */ | |
1201 | .noise_filter_min_width = 333333, /* ns */ | |
1202 | .carrier_range_lower = 35000, | |
1203 | .carrier_range_upper = 37000, | |
1204 | .invert_level = false, | |
1205 | }; | |
1206 | ||
1207 | static const struct v4l2_subdev_ir_parameters default_tx_params = { | |
c02e0d12 | 1208 | .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec), |
52fd3dda AW |
1209 | .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH, |
1210 | ||
1211 | .enable = false, | |
1212 | .interrupt_enable = false, | |
1213 | .shutdown = true, | |
1214 | ||
1215 | .modulation = true, | |
1216 | .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */ | |
1217 | .duty_cycle = 25, /* 25 % - RC-5 carrier */ | |
1218 | .invert_level = false, | |
1219 | .invert_carrier_sense = false, | |
1220 | }; | |
1221 | ||
1222 | int cx25840_ir_probe(struct v4l2_subdev *sd) | |
1223 | { | |
1224 | struct cx25840_state *state = to_state(sd); | |
1225 | struct cx25840_ir_state *ir_state; | |
1226 | struct v4l2_subdev_ir_parameters default_params; | |
1227 | ||
1228 | /* Only init the IR controller for the CX2388[57] AV Core for now */ | |
1229 | if (!(is_cx23885(state) || is_cx23887(state))) | |
1230 | return 0; | |
1231 | ||
1232 | ir_state = kzalloc(sizeof(struct cx25840_ir_state), GFP_KERNEL); | |
1233 | if (ir_state == NULL) | |
1234 | return -ENOMEM; | |
1235 | ||
1236 | spin_lock_init(&ir_state->rx_kfifo_lock); | |
1237 | if (kfifo_alloc(&ir_state->rx_kfifo, | |
1238 | CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL)) { | |
1239 | kfree(ir_state); | |
1240 | return -ENOMEM; | |
1241 | } | |
1242 | ||
1243 | ir_state->c = state->c; | |
1244 | state->ir_state = ir_state; | |
1245 | ||
1246 | /* Ensure no interrupts arrive yet */ | |
1247 | if (is_cx23885(state) || is_cx23887(state)) | |
1248 | cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK); | |
1249 | else | |
1250 | cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0); | |
1251 | ||
1252 | mutex_init(&ir_state->rx_params_lock); | |
1253 | memcpy(&default_params, &default_rx_params, | |
1254 | sizeof(struct v4l2_subdev_ir_parameters)); | |
1255 | v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params); | |
1256 | ||
1257 | mutex_init(&ir_state->tx_params_lock); | |
1258 | memcpy(&default_params, &default_tx_params, | |
1259 | sizeof(struct v4l2_subdev_ir_parameters)); | |
1260 | v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | int cx25840_ir_remove(struct v4l2_subdev *sd) | |
1266 | { | |
1267 | struct cx25840_state *state = to_state(sd); | |
1268 | struct cx25840_ir_state *ir_state = to_ir_state(sd); | |
1269 | ||
1270 | if (ir_state == NULL) | |
1271 | return -ENODEV; | |
1272 | ||
1273 | cx25840_ir_rx_shutdown(sd); | |
1274 | cx25840_ir_tx_shutdown(sd); | |
1275 | ||
1276 | kfifo_free(&ir_state->rx_kfifo); | |
1277 | kfree(ir_state); | |
1278 | state->ir_state = NULL; | |
1279 | return 0; | |
1280 | } |