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V4L/DVB (11769): cx23885: add ATSC/QAM tuning support for Hauppauge WinTV-HVR1275
[linux-2.6-block.git] / drivers / media / video / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/pci.h>
23#include <linux/i2c.h>
24#include <linux/i2c-algo-bit.h>
25#include <linux/kdev_t.h>
26
c0714f6c 27#include <media/v4l2-device.h>
d19770e5
ST		 28#include <media/tuner.h>
29#include <media/tveeprom.h>
409d84f8
TP		 30#include <media/videobuf-dma-sg.h>
31#include <media/videobuf-dvb.h>
d19770e5
ST		 32
33#include "btcx-risc.h"
34#include "cx23885-reg.h"
b1b81f1d 35#include "media/cx2341x.h"
d19770e5
ST		 36
37#include <linux/version.h>
38#include <linux/mutex.h>
39
3ff4ad81 40#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
d19770e5
ST		 41
42#define UNSET (-1U)
43
44#define CX23885_MAXBOARDS 8
45
d19770e5
ST		 46/* Max number of inputs by card */
47#define MAX_CX23885_INPUT 8
7b888014
ST		 48#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
49#define RESOURCE_OVERLAY 1
50#define RESOURCE_VIDEO 2
51#define RESOURCE_VBI 4
d19770e5 52
d19770e5
ST		 53#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
54
55#define CX23885_BOARD_NOAUTO UNSET
56#define CX23885_BOARD_UNKNOWN 0
57#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
58#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 59#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 60#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 61#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 62#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 63#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 64#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 65#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 66#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 67#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 68#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 69#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 70#define CX23885_BOARD_TBS_6920 14
579943f5 71#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 72#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 73#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 74#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 75#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
d19770e5 76
6f8bee9b
ST		 77#define GPIO_0 0x00000001
78#define GPIO_1 0x00000002
79#define GPIO_2 0x00000004
80#define GPIO_3 0x00000008
81#define GPIO_4 0x00000010
82#define GPIO_5 0x00000020
83#define GPIO_6 0x00000040
84#define GPIO_7 0x00000080
85#define GPIO_8 0x00000100
86#define GPIO_9 0x00000200
87
7b888014
ST		 88/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
89#define CX23885_NORMS (\
90 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
91 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
92 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
93 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
94
95struct cx23885_fmt {
96 char *name;
97 u32 fourcc; /* v4l2 format id */
98 int depth;
99 int flags;
100 u32 cxformat;
101};
102
103struct cx23885_ctrl {
104 struct v4l2_queryctrl v;
105 u32 off;
106 u32 reg;
107 u32 mask;
108 u32 shift;
109};
110
111struct cx23885_tvnorm {
112 char *name;
113 v4l2_std_id id;
114 u32 cxiformat;
115 u32 cxoformat;
116};
117
118struct cx23885_fh {
119 struct cx23885_dev *dev;
120 enum v4l2_buf_type type;
121 int radio;
122 u32 resources;
123
124 /* video overlay */
125 struct v4l2_window win;
126 struct v4l2_clip *clips;
127 unsigned int nclips;
128
129 /* video capture */
130 struct cx23885_fmt *fmt;
131 unsigned int width, height;
132
133 /* vbi capture */
134 struct videobuf_queue vidq;
135 struct videobuf_queue vbiq;
136
137 /* MPEG Encoder specifics ONLY */
138 struct videobuf_queue mpegq;
139 atomic_t v4l_reading;
140};
141
d19770e5
ST		 142enum cx23885_itype {
143 CX23885_VMUX_COMPOSITE1 = 1,
144 CX23885_VMUX_COMPOSITE2,
145 CX23885_VMUX_COMPOSITE3,
146 CX23885_VMUX_COMPOSITE4,
147 CX23885_VMUX_SVIDEO,
148 CX23885_VMUX_TELEVISION,
149 CX23885_VMUX_CABLE,
150 CX23885_VMUX_DVB,
151 CX23885_VMUX_DEBUG,
152 CX23885_RADIO,
153};
154
579f1163
ST		 155enum cx23885_src_sel_type {
156 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
157 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
158};
159
d19770e5
ST		 160/* buffer for one video frame */
161struct cx23885_buffer {
162 /* common v4l buffer stuff -- must be first */
163 struct videobuf_buffer vb;
164
165 /* cx23885 specific */
166 unsigned int bpl;
167 struct btcx_riscmem risc;
168 struct cx23885_fmt *fmt;
169 u32 count;
170};
171
172struct cx23885_input {
173 enum cx23885_itype type;
174 unsigned int vmux;
175 u32 gpio0, gpio1, gpio2, gpio3;
176};
177
661c7e44
ST		 178typedef enum {
179 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 180 CX23885_MPEG_DVB,
181 CX23885_ANALOG_VIDEO,
b1b81f1d 182 CX23885_MPEG_ENCODER,
661c7e44
ST		 183} port_t;
184
d19770e5
ST		 185struct cx23885_board {
186 char *name;
7b888014
ST		 187 port_t porta, portb, portc;
188 unsigned int tuner_type;
189 unsigned int radio_type;
190 unsigned char tuner_addr;
191 unsigned char radio_addr;
c7712613
ST		 192
193 /* Vendors can and do run the PCIe bridge at different
194 * clock rates, driven physically by crystals on the PCBs.
195 * The core has to accomodate this. This allows the user
196 * to add new boards with new frequencys. The value is
197 * expressed in Hz.
198 *
199 * The core framework will default this value based on
200 * current designs, but it can vary.
201 */
202 u32 clk_freq;
d19770e5 203 struct cx23885_input input[MAX_CX23885_INPUT];
5a23b076 204 int cimax; /* for NetUP */
d19770e5
ST		 205};
206
207struct cx23885_subid {
208 u16 subvendor;
209 u16 subdevice;
210 u32 card;
211};
212
213struct cx23885_i2c {
214 struct cx23885_dev *dev;
215
216 int nr;
217
218 /* i2c i/o */
219 struct i2c_adapter i2c_adap;
220 struct i2c_algo_bit_data i2c_algo;
221 struct i2c_client i2c_client;
222 u32 i2c_rc;
223
224 /* 885 registers used for raw addess */
225 u32 i2c_period;
226 u32 reg_ctrl;
227 u32 reg_stat;
228 u32 reg_addr;
229 u32 reg_rdata;
230 u32 reg_wdata;
231};
232
233struct cx23885_dmaqueue {
234 struct list_head active;
235 struct list_head queued;
236 struct timer_list timeout;
237 struct btcx_riscmem stopper;
238 u32 count;
239};
240
241struct cx23885_tsport {
242 struct cx23885_dev *dev;
243
244 int nr;
245 int sram_chno;
246
363c35fc 247 struct videobuf_dvb_frontends frontends;
d19770e5
ST		 248
249 /* dma queues */
250 struct cx23885_dmaqueue mpegq;
251 u32 ts_packet_size;
252 u32 ts_packet_count;
253
254 int width;
255 int height;
256
257 spinlock_t slock;
258
259 /* registers */
260 u32 reg_gpcnt;
261 u32 reg_gpcnt_ctl;
262 u32 reg_dma_ctl;
263 u32 reg_lngth;
264 u32 reg_hw_sop_ctrl;
265 u32 reg_gen_ctrl;
266 u32 reg_bd_pkt_status;
267 u32 reg_sop_status;
268 u32 reg_fifo_ovfl_stat;
269 u32 reg_vld_misc;
270 u32 reg_ts_clk_en;
271 u32 reg_ts_int_msk;
a6a3f140 272 u32 reg_ts_int_stat;
579f1163 273 u32 reg_src_sel;
d19770e5
ST		 274
275 /* Default register vals */
276 int pci_irqmask;
277 u32 dma_ctl_val;
278 u32 ts_int_msk_val;
279 u32 gen_ctrl_val;
280 u32 ts_clk_en_val;
579f1163 281 u32 src_sel_val;
b1b81f1d
ST		 282 u32 vld_misc_val;
283 u32 hw_sop_ctrl_val;
a739a7e4
ST		 284
285 /* Allow a single tsport to have multiple frontends */
286 u32 num_frontends;
5a23b076 287 void *port_priv;
d19770e5
ST		 288};
289
290struct cx23885_dev {
291 struct list_head devlist;
292 atomic_t refcount;
c0714f6c 293 struct v4l2_device v4l2_dev;
d19770e5
ST		 294
295 /* pci stuff */
296 struct pci_dev *pci;
297 unsigned char pci_rev, pci_lat;
298 int pci_bus, pci_slot;
299 u32 __iomem *lmmio;
300 u8 __iomem *bmmio;
d19770e5 301 int pci_irqmask;
0ac5881a 302 int hwrevision;
d19770e5 303
c7712613
ST		 304 /* This valud is board specific and is used to configure the
305 * AV core so we see nice clean and stable video and audio. */
306 u32 clk_freq;
307
44a6481d 308 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 309 struct cx23885_i2c i2c_bus[3];
310
311 int nr;
312 struct mutex lock;
313
314 /* board details */
315 unsigned int board;
316 char name[32];
317
a6a3f140 318 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 319
320 /* sram configuration */
321 struct sram_channel *sram_channels;
e133be0f
ST		 322
323 enum {
324 CX23885_BRIDGE_UNDEFINED = 0,
325 CX23885_BRIDGE_885 = 885,
326 CX23885_BRIDGE_887 = 887,
327 } bridge;
7b888014
ST		 328
329 /* Analog video */
330 u32 resources;
331 unsigned int input;
332 u32 tvaudio;
333 v4l2_std_id tvnorm;
334 unsigned int tuner_type;
335 unsigned char tuner_addr;
336 unsigned int radio_type;
337 unsigned char radio_addr;
338 unsigned int has_radio;
0d5a19f1 339 struct v4l2_subdev *sd_cx25840;
7b888014
ST		 340
341 /* V4l */
342 u32 freq;
343 struct video_device *video_dev;
344 struct video_device *vbi_dev;
345 struct video_device *radio_dev;
346
347 struct cx23885_dmaqueue vidq;
348 struct cx23885_dmaqueue vbiq;
349 spinlock_t slock;
b1b81f1d
ST		 350
351 /* MPEG Encoder ONLY settings */
352 u32 cx23417_mailbox;
353 struct cx2341x_mpeg_params mpeg_params;
354 struct video_device *v4l_device;
355 atomic_t v4l_reader_count;
356 struct cx23885_tvnorm encodernorm;
357
d19770e5
ST		 358};
359
c0714f6c
HV		 360static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
361{
362 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
363}
364
0d5a19f1
HV		 365#define call_all(dev, o, f, args...) \
366 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
367
7b888014
ST		 368extern struct list_head cx23885_devlist;
369
d19770e5
ST		 370#define SRAM_CH01 0 /* Video A */
371#define SRAM_CH02 1 /* VBI A */
372#define SRAM_CH03 2 /* Video B */
373#define SRAM_CH04 3 /* Transport via B */
374#define SRAM_CH05 4 /* VBI B */
375#define SRAM_CH06 5 /* Video C */
376#define SRAM_CH07 6 /* Transport via C */
377#define SRAM_CH08 7 /* Audio Internal A */
378#define SRAM_CH09 8 /* Audio Internal B */
379#define SRAM_CH10 9 /* Audio External */
380#define SRAM_CH11 10 /* COMB_3D_N */
381#define SRAM_CH12 11 /* Comb 3D N1 */
382#define SRAM_CH13 12 /* Comb 3D N2 */
383#define SRAM_CH14 13 /* MOE Vid */
384#define SRAM_CH15 14 /* MOE RSLT */
385
386struct sram_channel {
387 char *name;
388 u32 cmds_start;
389 u32 ctrl_start;
390 u32 cdt;
391 u32 fifo_start;;
392 u32 fifo_size;
393 u32 ptr1_reg;
394 u32 ptr2_reg;
395 u32 cnt1_reg;
396 u32 cnt2_reg;
397 u32 jumponly;
398};
399
400/* ----------------------------------------------------------- */
401
402#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 403#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 404
9c8ced51 405#define cx_andor(reg, mask, value) \
d19770e5
ST		 406 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
407 ((value) & (mask)), dev->lmmio+((reg)>>2))
408
9c8ced51
ST		 409#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
410#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 411
d19770e5 412/* ----------------------------------------------------------- */
7b888014
ST		 413/* cx23885-core.c */
414
415extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
416 struct sram_channel *ch,
417 unsigned int bpl, u32 risc);
418
419extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
420 struct sram_channel *ch);
d19770e5 421
7b888014
ST		 422extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
423 u32 reg, u32 mask, u32 value);
424
425extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
426 struct scatterlist *sglist,
427 unsigned int top_offset, unsigned int bottom_offset,
428 unsigned int bpl, unsigned int padding, unsigned int lines);
429
430void cx23885_cancel_buffers(struct cx23885_tsport *port);
431
432extern int cx23885_restart_queue(struct cx23885_tsport *port,
433 struct cx23885_dmaqueue *q);
434
435extern void cx23885_wakeup(struct cx23885_tsport *port,
436 struct cx23885_dmaqueue *q, u32 count);
437
6f8bee9b
ST		 438extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
439extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
440extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
441 int asoutput);
442
7b888014
ST		 443
444/* ----------------------------------------------------------- */
445/* cx23885-cards.c */
d19770e5
ST		 446extern struct cx23885_board cx23885_boards[];
447extern const unsigned int cx23885_bcount;
448
449extern struct cx23885_subid cx23885_subids[];
450extern const unsigned int cx23885_idcount;
451
9c8ced51
ST		 452extern int cx23885_tuner_callback(void *priv, int component,
453 int command, int arg);
d19770e5 454extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140
ST		 455extern int cx23885_ir_init(struct cx23885_dev *dev);
456extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5
ST		 457extern void cx23885_card_setup(struct cx23885_dev *dev);
458extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
459
460extern int cx23885_dvb_register(struct cx23885_tsport *port);
461extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
462
44a6481d
MK		 463extern int cx23885_buf_prepare(struct videobuf_queue *q,
464 struct cx23885_tsport *port,
465 struct cx23885_buffer *buf,
466 enum v4l2_field field);
44a6481d
MK		 467extern void cx23885_buf_queue(struct cx23885_tsport *port,
468 struct cx23885_buffer *buf);
469extern void cx23885_free_buffer(struct videobuf_queue *q,
470 struct cx23885_buffer *buf);
d19770e5
ST		 471
472/* ----------------------------------------------------------- */
7b888014
ST		 473/* cx23885-video.c */
474/* Video */
475extern int cx23885_video_register(struct cx23885_dev *dev);
476extern void cx23885_video_unregister(struct cx23885_dev *dev);
477extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
478
479/* ----------------------------------------------------------- */
480/* cx23885-vbi.c */
481extern int cx23885_vbi_fmt(struct file *file, void *priv,
482 struct v4l2_format *f);
483extern void cx23885_vbi_timeout(unsigned long data);
484extern struct videobuf_queue_ops cx23885_vbi_qops;
485
d19770e5
ST		 486/* cx23885-i2c.c */
487extern int cx23885_i2c_register(struct cx23885_i2c *bus);
488extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 489extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 490
b1b81f1d
ST		 491/* ----------------------------------------------------------- */
492/* cx23885-417.c */
493extern int cx23885_417_register(struct cx23885_dev *dev);
494extern void cx23885_417_unregister(struct cx23885_dev *dev);
495extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
496extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
497extern void cx23885_mc417_init(struct cx23885_dev *dev);
498extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
499extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
500
501
7b888014
ST		 502/* ----------------------------------------------------------- */
503/* tv norms */
504
505static inline unsigned int norm_maxw(v4l2_std_id norm)
506{
507 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
508}
509
510static inline unsigned int norm_maxh(v4l2_std_id norm)
511{
512 return (norm & V4L2_STD_625_50) ? 576 : 480;
513}
514
515static inline unsigned int norm_swidth(v4l2_std_id norm)
516{
517 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
518}
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