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V4L/DVB (6190): cx23885: GPIO fix for non HVR1800lp boards
[linux-block.git] / drivers / media / video / cx23885 / cx23885-core.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kmod.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <asm/div64.h>
32
33#include "cx23885.h"
34
35MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37MODULE_LICENSE("GPL");
38
39static unsigned int debug = 0;
40module_param(debug,int,0644);
41MODULE_PARM_DESC(debug,"enable debug messages");
42
43static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44module_param_array(card, int, NULL, 0444);
45MODULE_PARM_DESC(card,"card type");
46
47#define dprintk(level,fmt, arg...) if (debug >= level) \
48 printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
49
50static unsigned int cx23885_devcount;
51
52static DEFINE_MUTEX(devlist);
53static LIST_HEAD(cx23885_devlist);
54
55#define NO_SYNC_LINE (-1U)
56
57/*
58 * CX23885 Assumptions
59 * 1 line = 16 bytes of CDT
60 * cmds size = 80
61 * cdt size = 16 * linesize
62 * iqsize = 64
63 * maxlines = 6
64 *
65 * Address Space:
66 * 0x00000000 0x00008fff FIFO clusters
67 * 0x00010000 0x000104af Channel Management Data Structures
68 * 0x000104b0 0x000104ff Free
69 * 0x00010500 0x000108bf 15 channels * iqsize
70 * 0x000108c0 0x000108ff Free
71 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
72 * 15 channels * (iqsize + (maxlines * linesize))
73 * 0x00010ea0 0x00010xxx Free
74 */
75
76struct sram_channel cx23885_sram_channels[] = {
77 [SRAM_CH01] = {
78 .name = "test ch1",
79 .cmds_start = 0x10000,
80 .ctrl_start = 0x10500,
81 .cdt = 0x10900,
82 .fifo_start = 0x3000,
83 .fifo_size = 0x1000,
84 .ptr1_reg = DMA1_PTR1,
85 .ptr2_reg = DMA1_PTR2,
86 .cnt1_reg = DMA1_CNT1,
87 .cnt2_reg = DMA1_CNT2,
88 .jumponly = 1,
89 },
90 [SRAM_CH02] = {
91 .name = "ch2",
92 .cmds_start = 0x0,
93 .ctrl_start = 0x0,
94 .cdt = 0x0,
95 .fifo_start = 0x0,
96 .fifo_size = 0x0,
97 .ptr1_reg = DMA2_PTR1,
98 .ptr2_reg = DMA2_PTR2,
99 .cnt1_reg = DMA2_CNT1,
100 .cnt2_reg = DMA2_CNT2,
101 },
102 [SRAM_CH03] = {
103 .name = "ch3",
104 .cmds_start = 0x0,
105 .ctrl_start = 0x0,
106 .cdt = 0x0,
107 .fifo_start = 0x0,
108 .fifo_size = 0x0,
109 .ptr1_reg = DMA3_PTR1,
110 .ptr2_reg = DMA3_PTR2,
111 .cnt1_reg = DMA3_CNT1,
112 .cnt2_reg = DMA3_CNT2,
113 },
114 [SRAM_CH04] = {
115 .name = "ch4",
116 .cmds_start = 0x0,
117 .ctrl_start = 0x0,
118 .cdt = 0x0,
119 .fifo_start = 0x0,
120 .fifo_size = 0x0,
121 .ptr1_reg = DMA4_PTR1,
122 .ptr2_reg = DMA4_PTR2,
123 .cnt1_reg = DMA4_CNT1,
124 .cnt2_reg = DMA4_CNT2,
125 },
126 [SRAM_CH05] = {
127 .name = "ch5",
128 .cmds_start = 0x0,
129 .ctrl_start = 0x0,
130 .cdt = 0x0,
131 .fifo_start = 0x0,
132 .fifo_size = 0x0,
133 .ptr1_reg = DMA5_PTR1,
134 .ptr2_reg = DMA5_PTR2,
135 .cnt1_reg = DMA5_CNT1,
136 .cnt2_reg = DMA5_CNT2,
137 },
138 [SRAM_CH06] = {
139 .name = "TS2 C",
140 .cmds_start = 0x10140,
141 .ctrl_start = 0x10680,
142 .cdt = 0x10480,
143 .fifo_start = 0x6000,
144 .fifo_size = 0x1000,
145 .ptr1_reg = DMA5_PTR1,
146 .ptr2_reg = DMA5_PTR2,
147 .cnt1_reg = DMA5_CNT1,
148 .cnt2_reg = DMA5_CNT2,
149 },
150 [SRAM_CH07] = {
151 .name = "ch7",
152 .cmds_start = 0x0,
153 .ctrl_start = 0x0,
154 .cdt = 0x0,
155 .fifo_start = 0x0,
156 .fifo_size = 0x0,
157 .ptr1_reg = DMA6_PTR1,
158 .ptr2_reg = DMA6_PTR2,
159 .cnt1_reg = DMA6_CNT1,
160 .cnt2_reg = DMA6_CNT2,
161 },
162 [SRAM_CH08] = {
163 .name = "ch8",
164 .cmds_start = 0x0,
165 .ctrl_start = 0x0,
166 .cdt = 0x0,
167 .fifo_start = 0x0,
168 .fifo_size = 0x0,
169 .ptr1_reg = DMA7_PTR1,
170 .ptr2_reg = DMA7_PTR2,
171 .cnt1_reg = DMA7_CNT1,
172 .cnt2_reg = DMA7_CNT2,
173 },
174 [SRAM_CH09] = {
175 .name = "ch9",
176 .cmds_start = 0x0,
177 .ctrl_start = 0x0,
178 .cdt = 0x0,
179 .fifo_start = 0x0,
180 .fifo_size = 0x0,
181 .ptr1_reg = DMA8_PTR1,
182 .ptr2_reg = DMA8_PTR2,
183 .cnt1_reg = DMA8_CNT1,
184 .cnt2_reg = DMA8_CNT2,
185 },
186};
187
188/* FIXME, these allocations will change when
189 * analog arrives. The be reviewed.
190 * CX23887 Assumptions
191 * 1 line = 16 bytes of CDT
192 * cmds size = 80
193 * cdt size = 16 * linesize
194 * iqsize = 64
195 * maxlines = 6
196 *
197 * Address Space:
198 * 0x00000000 0x00008fff FIFO clusters
199 * 0x00010000 0x000104af Channel Management Data Structures
200 * 0x000104b0 0x000104ff Free
201 * 0x00010500 0x000108bf 15 channels * iqsize
202 * 0x000108c0 0x000108ff Free
203 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
204 * 15 channels * (iqsize + (maxlines * linesize))
205 * 0x00010ea0 0x00010xxx Free
206 */
207
208struct sram_channel cx23887_sram_channels[] = {
209 [SRAM_CH01] = {
210 .name = "test ch1",
211 .cmds_start = 0x0,
212 .ctrl_start = 0x0,
213 .cdt = 0x0,
214 .fifo_start = 0x0,
215 .fifo_size = 0x0,
216 .ptr1_reg = DMA1_PTR1,
217 .ptr2_reg = DMA1_PTR2,
218 .cnt1_reg = DMA1_CNT1,
219 .cnt2_reg = DMA1_CNT2,
220 },
221 [SRAM_CH02] = {
222 .name = "ch2",
223 .cmds_start = 0x0,
224 .ctrl_start = 0x0,
225 .cdt = 0x0,
226 .fifo_start = 0x0,
227 .fifo_size = 0x0,
228 .ptr1_reg = DMA2_PTR1,
229 .ptr2_reg = DMA2_PTR2,
230 .cnt1_reg = DMA2_CNT1,
231 .cnt2_reg = DMA2_CNT2,
232 },
233 [SRAM_CH03] = {
234 .name = "ch3",
235 .cmds_start = 0x0,
236 .ctrl_start = 0x0,
237 .cdt = 0x0,
238 .fifo_start = 0x0,
239 .fifo_size = 0x0,
240 .ptr1_reg = DMA3_PTR1,
241 .ptr2_reg = DMA3_PTR2,
242 .cnt1_reg = DMA3_CNT1,
243 .cnt2_reg = DMA3_CNT2,
244 },
245 [SRAM_CH04] = {
246 .name = "ch4",
247 .cmds_start = 0x0,
248 .ctrl_start = 0x0,
249 .cdt = 0x0,
250 .fifo_start = 0x0,
251 .fifo_size = 0x0,
252 .ptr1_reg = DMA4_PTR1,
253 .ptr2_reg = DMA4_PTR2,
254 .cnt1_reg = DMA4_CNT1,
255 .cnt2_reg = DMA4_CNT2,
256 },
257 [SRAM_CH05] = {
258 .name = "ch5",
259 .cmds_start = 0x0,
260 .ctrl_start = 0x0,
261 .cdt = 0x0,
262 .fifo_start = 0x0,
263 .fifo_size = 0x0,
264 .ptr1_reg = DMA5_PTR1,
265 .ptr2_reg = DMA5_PTR2,
266 .cnt1_reg = DMA5_CNT1,
267 .cnt2_reg = DMA5_CNT2,
268 },
269 [SRAM_CH06] = {
270 .name = "TS2 C",
271 .cmds_start = 0x10140,
272 .ctrl_start = 0x10680,
3bd40659 273 .cdt = 0x108d0,
d19770e5
ST		 274 .fifo_start = 0x6000,
275 .fifo_size = 0x1000,
276 .ptr1_reg = DMA5_PTR1,
277 .ptr2_reg = DMA5_PTR2,
278 .cnt1_reg = DMA5_CNT1,
279 .cnt2_reg = DMA5_CNT2,
280 },
281 [SRAM_CH07] = {
282 .name = "ch7",
283 .cmds_start = 0x0,
284 .ctrl_start = 0x0,
285 .cdt = 0x0,
286 .fifo_start = 0x0,
287 .fifo_size = 0x0,
288 .ptr1_reg = DMA6_PTR1,
289 .ptr2_reg = DMA6_PTR2,
290 .cnt1_reg = DMA6_CNT1,
291 .cnt2_reg = DMA6_CNT2,
292 },
293 [SRAM_CH08] = {
294 .name = "ch8",
295 .cmds_start = 0x0,
296 .ctrl_start = 0x0,
297 .cdt = 0x0,
298 .fifo_start = 0x0,
299 .fifo_size = 0x0,
300 .ptr1_reg = DMA7_PTR1,
301 .ptr2_reg = DMA7_PTR2,
302 .cnt1_reg = DMA7_CNT1,
303 .cnt2_reg = DMA7_CNT2,
304 },
305 [SRAM_CH09] = {
306 .name = "ch9",
307 .cmds_start = 0x0,
308 .ctrl_start = 0x0,
309 .cdt = 0x0,
310 .fifo_start = 0x0,
311 .fifo_size = 0x0,
312 .ptr1_reg = DMA8_PTR1,
313 .ptr2_reg = DMA8_PTR2,
314 .cnt1_reg = DMA8_CNT1,
315 .cnt2_reg = DMA8_CNT2,
316 },
317};
318
319static int cx23885_risc_decode(u32 risc)
320{
321 static char *instr[16] = {
322 [ RISC_SYNC >> 28 ] = "sync",
323 [ RISC_WRITE >> 28 ] = "write",
324 [ RISC_WRITEC >> 28 ] = "writec",
325 [ RISC_READ >> 28 ] = "read",
326 [ RISC_READC >> 28 ] = "readc",
327 [ RISC_JUMP >> 28 ] = "jump",
328 [ RISC_SKIP >> 28 ] = "skip",
329 [ RISC_WRITERM >> 28 ] = "writerm",
330 [ RISC_WRITECM >> 28 ] = "writecm",
331 [ RISC_WRITECR >> 28 ] = "writecr",
332 };
333 static int incr[16] = {
2df9a4c2
ST		 334 [ RISC_WRITE >> 28 ] = 3,
335 [ RISC_JUMP >> 28 ] = 3,
d19770e5
ST		 336 [ RISC_SKIP >> 28 ] = 1,
337 [ RISC_SYNC >> 28 ] = 1,
338 [ RISC_WRITERM >> 28 ] = 3,
339 [ RISC_WRITECM >> 28 ] = 3,
340 [ RISC_WRITECR >> 28 ] = 4,
341 };
342 static char *bits[] = {
343 "12", "13", "14", "resync",
344 "cnt0", "cnt1", "18", "19",
345 "20", "21", "22", "23",
346 "irq1", "irq2", "eol", "sol",
347 };
348 int i;
349
350 printk("0x%08x [ %s", risc,
351 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
44a6481d 352 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
d19770e5 353 if (risc & (1 << (i + 12)))
44a6481d 354 printk(" %s", bits[i]);
d19770e5
ST		 355 printk(" count=%d ]\n", risc & 0xfff);
356 return incr[risc >> 28] ? incr[risc >> 28] : 1;
357}
358
359void cx23885_wakeup(struct cx23885_tsport *port,
44a6481d 360 struct cx23885_dmaqueue *q, u32 count)
d19770e5
ST		 361{
362 struct cx23885_dev *dev = port->dev;
363 struct cx23885_buffer *buf;
364 int bc;
365
366 for (bc = 0;; bc++) {
367 if (list_empty(&q->active))
368 break;
369 buf = list_entry(q->active.next,
370 struct cx23885_buffer, vb.queue);
2e52f215 371
d19770e5
ST		 372 /* count comes from the hw and is is 16bit wide --
373 * this trick handles wrap-arounds correctly for
374 * up to 32767 buffers in flight... */
375 if ((s16) (count - buf->count) < 0)
376 break;
2e52f215 377
d19770e5 378 do_gettimeofday(&buf->vb.ts);
44a6481d 379 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
d19770e5
ST		 380 count, buf->count);
381 buf->vb.state = STATE_DONE;
382 list_del(&buf->vb.queue);
383 wake_up(&buf->vb.done);
384 }
385 if (list_empty(&q->active)) {
386 del_timer(&q->timeout);
387 } else {
44a6481d 388 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 389 }
390 if (bc != 1)
44a6481d
MK		 391 printk("%s: %d buffers handled (should be 1)\n",
392 __FUNCTION__, bc);
d19770e5
ST		 393}
394void cx23885_sram_channel_dump(struct cx23885_dev *dev,
44a6481d 395 struct sram_channel *ch);
d19770e5
ST		 396
397int cx23885_sram_channel_setup(struct cx23885_dev *dev,
44a6481d
MK		 398 struct sram_channel *ch,
399 unsigned int bpl, u32 risc)
d19770e5 400{
44a6481d 401 unsigned int i, lines;
d19770e5
ST		 402 u32 cdt;
403
404 if (ch->cmds_start == 0)
405 {
44a6481d
MK		 406 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
407 ch->name);
d19770e5
ST		 408 cx_write(ch->ptr1_reg, 0);
409 cx_write(ch->ptr2_reg, 0);
410 cx_write(ch->cnt2_reg, 0);
411 cx_write(ch->cnt1_reg, 0);
412 return 0;
413 } else {
44a6481d
MK		 414 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
415 ch->name);
d19770e5
ST		 416 }
417
418 bpl = (bpl + 7) & ~7; /* alignment */
419 cdt = ch->cdt;
420 lines = ch->fifo_size / bpl;
421 if (lines > 6)
422 lines = 6;
423 BUG_ON(lines < 2);
424
44a6481d
MK		 425 cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
426 cx_write(8 + 4, cpu_to_le32(8) );
427 cx_write(8 + 8, cpu_to_le32(0) );
d19770e5
ST		 428
429 /* write CDT */
430 for (i = 0; i < lines; i++) {
44a6481d
MK		 431 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
432 ch->fifo_start + bpl*i);
d19770e5
ST		 433 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
434 cx_write(cdt + 16*i + 4, 0);
435 cx_write(cdt + 16*i + 8, 0);
436 cx_write(cdt + 16*i + 12, 0);
437 }
438
439 /* write CMDS */
440 if (ch->jumponly)
441 cx_write(ch->cmds_start + 0, 8);
442 else
443 cx_write(ch->cmds_start + 0, risc);
444 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
445 cx_write(ch->cmds_start + 8, cdt);
446 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
447 cx_write(ch->cmds_start + 16, ch->ctrl_start);
448 if (ch->jumponly)
449 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
450 else
451 cx_write(ch->cmds_start + 20, 64 >> 2);
452 for (i = 24; i < 80; i += 4)
453 cx_write(ch->cmds_start + i, 0);
454
455 /* fill registers */
456 cx_write(ch->ptr1_reg, ch->fifo_start);
457 cx_write(ch->ptr2_reg, cdt);
458 cx_write(ch->cnt2_reg, (lines*16) >> 3);
459 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
460
e133be0f
ST		 461 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
462 dev->bridge,
d19770e5
ST		 463 ch->name,
464 bpl,
465 lines);
466
467 return 0;
468}
469
470void cx23885_sram_channel_dump(struct cx23885_dev *dev,
44a6481d 471 struct sram_channel *ch)
d19770e5
ST		 472{
473 static char *name[] = {
474 "init risc lo",
475 "init risc hi",
476 "cdt base",
477 "cdt size",
478 "iq base",
479 "iq size",
480 "risc pc lo",
481 "risc pc hi",
482 "iq wr ptr",
483 "iq rd ptr",
484 "cdt current",
485 "pci target lo",
486 "pci target hi",
487 "line / byte",
488 };
489 u32 risc;
44a6481d 490 unsigned int i, j, n;
d19770e5
ST		 491
492 printk("%s: %s - dma channel status dump\n",
493 dev->name, ch->name);
494 for (i = 0; i < ARRAY_SIZE(name); i++)
495 printk("%s: cmds: %-15s: 0x%08x\n",
496 dev->name, name[i],
497 cx_read(ch->cmds_start + 4*i));
498
499 for (i = 0; i < 4; i++) {
44a6481d 500 risc = cx_read(ch->cmds_start + 4 * (i + 14));
d19770e5
ST		 501 printk("%s: risc%d: ", dev->name, i);
502 cx23885_risc_decode(risc);
503 }
504 for (i = 0; i < (64 >> 2); i += n) {
44a6481d
MK		 505 risc = cx_read(ch->ctrl_start + 4 * i);
506 /* No consideration for bits 63-32 */
507
508 printk("%s: (0x%08x) iq %x: ", dev->name,
509 ch->ctrl_start + 4 * i, i);
d19770e5
ST		 510 n = cx23885_risc_decode(risc);
511 for (j = 1; j < n; j++) {
44a6481d 512 risc = cx_read(ch->ctrl_start + 4 * (i + j));
d19770e5
ST		 513 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
514 dev->name, i+j, risc, j);
515 }
516 }
517
518 printk("%s: fifo: 0x%08x -> 0x%x\n",
519 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
520 printk("%s: ctrl: 0x%08x -> 0x%x\n",
44a6481d 521 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
d19770e5
ST		 522 printk("%s: ptr1_reg: 0x%08x\n",
523 dev->name, cx_read(ch->ptr1_reg));
524 printk("%s: ptr2_reg: 0x%08x\n",
525 dev->name, cx_read(ch->ptr2_reg));
526 printk("%s: cnt1_reg: 0x%08x\n",
527 dev->name, cx_read(ch->cnt1_reg));
528 printk("%s: cnt2_reg: 0x%08x\n",
529 dev->name, cx_read(ch->cnt2_reg));
530}
531
44a6481d
MK		 532void cx23885_risc_disasm(struct cx23885_tsport *port,
533 struct btcx_riscmem *risc)
d19770e5
ST		 534{
535 struct cx23885_dev *dev = port->dev;
44a6481d 536 unsigned int i, j, n;
d19770e5
ST		 537
538 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
539 dev->name, risc->cpu, (unsigned long)risc->dma);
540 for (i = 0; i < (risc->size >> 2); i += n) {
541 printk("%s: %04d: ", dev->name, i);
542 n = cx23885_risc_decode(risc->cpu[i]);
543 for (j = 1; j < n; j++)
544 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
44a6481d 545 dev->name, i + j, risc->cpu[i + j], j);
d19770e5
ST		 546 if (risc->cpu[i] == RISC_JUMP)
547 break;
548 }
549}
550
551void cx23885_shutdown(struct cx23885_dev *dev)
552{
553 /* disable RISC controller */
554 cx_write(DEV_CNTRL2, 0);
555
556 /* Disable all IR activity */
557 cx_write(IR_CNTRL_REG, 0);
558
559 /* Disable Video A/B activity */
560 cx_write(VID_A_DMA_CTL, 0);
561 cx_write(VID_B_DMA_CTL, 0);
562 cx_write(VID_C_DMA_CTL, 0);
563
564 /* Disable Audio activity */
565 cx_write(AUD_INT_DMA_CTL, 0);
566 cx_write(AUD_EXT_DMA_CTL, 0);
567
568 /* Disable Serial port */
569 cx_write(UART_CTL, 0);
570
571 /* Disable Interrupts */
572 cx_write(PCI_INT_MSK, 0);
573 cx_write(VID_A_INT_MSK, 0);
574 cx_write(VID_B_INT_MSK, 0);
575 cx_write(VID_C_INT_MSK, 0);
576 cx_write(AUDIO_INT_INT_MSK, 0);
577 cx_write(AUDIO_EXT_INT_MSK, 0);
578
579}
580
581void cx23885_reset(struct cx23885_dev *dev)
582{
583 dprintk(1, "%s()\n", __FUNCTION__);
584
585 cx23885_shutdown(dev);
586
587 cx_write(PCI_INT_STAT, 0xffffffff);
588 cx_write(VID_A_INT_STAT, 0xffffffff);
589 cx_write(VID_B_INT_STAT, 0xffffffff);
590 cx_write(VID_C_INT_STAT, 0xffffffff);
591 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
592 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
593 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
594
595 mdelay(100);
596
d19770e5
ST		 597 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
598 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
599 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
600 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
601 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
602 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
603 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
604 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
605 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
606
d19770e5 607 switch(dev->board) {
a77743bc
ST		 608 case CX23885_BOARD_HAUPPAUGE_HVR1250:
609 /* GPIO-0 cx24227 demodulator reset */
610 dprintk( 1, "%s() Configuring HVR1250 GPIO's\n", __FUNCTION__);
611 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
612 break;
d19770e5
ST		 613 case CX23885_BOARD_HAUPPAUGE_HVR1800:
614 /* GPIO-0 656_CLK */
615 /* GPIO-1 656_D0 */
616 /* GPIO-2 8295A Reset */
617 /* GPIO-3-10 cx23417 data0-7 */
618 /* GPIO-11-14 cx23417 addr0-3 */
619 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
620 /* GPIO-19 IR_RX */
621 dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
622 // FIXME: Analog requires the tuner is brought out of reset
623 break;
624 }
625}
626
627
628static int cx23885_pci_quirks(struct cx23885_dev *dev)
629{
630 dprintk(1, "%s()\n", __FUNCTION__);
631
2df9a4c2
ST		 632 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
633 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
634 * occur on the cx23887 bridge.
635 */
4823e9ee 636 if(dev->bridge == CX23885_BRIDGE_885)
d19770e5 637 cx_clear(RDR_TLCTL0, 1 << 4);
4823e9ee 638
d19770e5
ST		 639 return 0;
640}
641
642static int get_resources(struct cx23885_dev *dev)
643{
644 if (request_mem_region(pci_resource_start(dev->pci,0),
44a6481d
MK		 645 pci_resource_len(dev->pci,0),
646 dev->name))
d19770e5
ST		 647 return 0;
648
649 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
650 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
651
652 return -EBUSY;
653}
654
655static void cx23885_timeout(unsigned long data);
656int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d 657 u32 reg, u32 mask, u32 value);
d19770e5
ST		 658
659static int cx23885_ir_init(struct cx23885_dev *dev)
660{
661 dprintk(1, "%s()\n", __FUNCTION__);
662
663 switch (dev->board) {
a77743bc 664 case CX23885_BOARD_HAUPPAUGE_HVR1250:
d19770e5
ST		 665 case CX23885_BOARD_HAUPPAUGE_HVR1800:
666 dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
667 break;
668 }
669
670 return 0;
671}
672
673static int cx23885_dev_setup(struct cx23885_dev *dev)
674{
675 int i;
676
677 mutex_init(&dev->lock);
678
679 atomic_inc(&dev->refcount);
680
681 dev->nr = cx23885_devcount++;
682 dev->pci_bus = dev->pci->bus->number;
683 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
684 dev->pci_irqmask = 0x001f00;
685
686 /* External Master 1 Bus */
687 dev->i2c_bus[0].nr = 0;
688 dev->i2c_bus[0].dev = dev;
689 dev->i2c_bus[0].reg_stat = I2C1_STAT;
690 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
691 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
692 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
693 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
694 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
695
696 /* External Master 2 Bus */
697 dev->i2c_bus[1].nr = 1;
698 dev->i2c_bus[1].dev = dev;
699 dev->i2c_bus[1].reg_stat = I2C2_STAT;
700 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
701 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
702 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
703 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
704 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
705
706 /* Internal Master 3 Bus */
707 dev->i2c_bus[2].nr = 2;
708 dev->i2c_bus[2].dev = dev;
709 dev->i2c_bus[2].reg_stat = I2C3_STAT;
710 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
a2129af5 711 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
d19770e5
ST		 712 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
713 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
714 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
715
716 /* Transport bus init dma queue */
717 spin_lock_init(&dev->ts2.slock);
718 dev->ts2.dev = dev;
719 dev->ts2.nr = 2;
720 dev->ts2.sram_chno = SRAM_CH06;
721 INIT_LIST_HEAD(&dev->ts2.mpegq.active);
722 INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
723 dev->ts2.mpegq.timeout.function = cx23885_timeout;
724 dev->ts2.mpegq.timeout.data = (unsigned long)&dev->ts2;
725 init_timer(&dev->ts2.mpegq.timeout);
726
727 dev->ts2.reg_gpcnt = VID_C_GPCNT;
728 dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
729 dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
730 dev->ts2.reg_lngth = VID_C_LNGTH;
731 dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
732 dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
733 dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
734 dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
735 dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
736 dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
737 dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
738 dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
739
740 // FIXME: Make this board specific
741 dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
742 dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
743 dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
744 dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
745 dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
746
44a6481d
MK		 747 cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
748 dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
d19770e5 749
44a6481d 750 sprintf(dev->name, "cx23885[%d]", dev->nr);
d19770e5
ST		 751
752 if (get_resources(dev) < 0) {
753 printk(KERN_ERR "CORE %s No more PCIe resources for "
44a6481d
MK		 754 "subsystem: %04x:%04x\n",
755 dev->name, dev->pci->subsystem_vendor,
756 dev->pci->subsystem_device);
d19770e5
ST		 757
758 cx23885_devcount--;
759 goto fail_free;
760 }
761
762 mutex_lock(&devlist);
763 list_add_tail(&dev->devlist, &cx23885_devlist);
764 mutex_unlock(&devlist);
765
766 /* PCIe stuff */
767 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
44a6481d 768 pci_resource_len(dev->pci,0));
d19770e5
ST		 769
770 dev->bmmio = (u8 __iomem *)dev->lmmio;
771
d19770e5
ST		 772 /* board config */
773 dev->board = UNSET;
774 if (card[dev->nr] < cx23885_bcount)
775 dev->board = card[dev->nr];
776 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
777 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
778 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
779 dev->board = cx23885_subids[i].card;
780 if (UNSET == dev->board) {
781 dev->board = CX23885_BOARD_UNKNOWN;
782 cx23885_card_list(dev);
783 }
784 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
44a6481d
MK		 785 dev->name, dev->pci->subsystem_vendor,
786 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
787 dev->board, card[dev->nr] == dev->board ?
788 "insmod option" : "autodetected");
d19770e5 789
e133be0f
ST		 790 /* Configure the internal memory */
791 if(dev->pci->device == 0x8880) {
792 dev->bridge = CX23885_BRIDGE_887;
d19770e5 793 dev->sram_channels = cx23887_sram_channels;
e133be0f
ST		 794 } else
795 if(dev->pci->device == 0x8852) {
796 dev->bridge = CX23885_BRIDGE_885;
797 dev->sram_channels = cx23885_sram_channels;
d19770e5 798 }
44a6481d
MK		 799 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
800 __FUNCTION__, dev->bridge);
d19770e5 801
4823e9ee
ST		 802 cx23885_pci_quirks(dev);
803
d19770e5
ST		 804 /* init hardware */
805 cx23885_reset(dev);
806
807 cx23885_i2c_register(&dev->i2c_bus[0]);
808 cx23885_i2c_register(&dev->i2c_bus[1]);
809 cx23885_i2c_register(&dev->i2c_bus[2]);
810 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
811
812 cx23885_card_setup(dev);
813 cx23885_ir_init(dev);
814
815 if (cx23885_dvb_register(&dev->ts2) < 0) {
44a6481d
MK		 816 printk(KERN_ERR "%s() Failed to register dvb adapters\n",
817 __FUNCTION__);
d19770e5
ST		 818 }
819
820 return 0;
821
822fail_free:
823 kfree(dev);
824 return -ENODEV;
825}
826
827void cx23885_dev_unregister(struct cx23885_dev *dev)
828{
829 release_mem_region(pci_resource_start(dev->pci,0),
830 pci_resource_len(dev->pci,0));
831
832 if (!atomic_dec_and_test(&dev->refcount))
833 return;
834
835 cx23885_dvb_unregister(&dev->ts2);
836 cx23885_i2c_unregister(&dev->i2c_bus[2]);
837 cx23885_i2c_unregister(&dev->i2c_bus[1]);
838 cx23885_i2c_unregister(&dev->i2c_bus[0]);
839
840 iounmap(dev->lmmio);
841}
842
843static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
44a6481d
MK		 844 unsigned int offset, u32 sync_line,
845 unsigned int bpl, unsigned int padding,
846 unsigned int lines)
d19770e5
ST		 847{
848 struct scatterlist *sg;
44a6481d 849 unsigned int line, todo;
d19770e5
ST		 850
851 /* sync instruction */
852 if (sync_line != NO_SYNC_LINE)
853 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
854
855 /* scan lines */
856 sg = sglist;
857 for (line = 0; line < lines; line++) {
858 while (offset && offset >= sg_dma_len(sg)) {
859 offset -= sg_dma_len(sg);
860 sg++;
861 }
862 if (bpl <= sg_dma_len(sg)-offset) {
863 /* fits into current chunk */
864 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
865 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
866 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
867 offset+=bpl;
868 } else {
869 /* scanline needs to be split */
870 todo = bpl;
871 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
872 (sg_dma_len(sg)-offset));
873 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
874 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
875 todo -= (sg_dma_len(sg)-offset);
876 offset = 0;
877 sg++;
878 while (todo > sg_dma_len(sg)) {
879 *(rp++)=cpu_to_le32(RISC_WRITE|
880 sg_dma_len(sg));
881 *(rp++)=cpu_to_le32(sg_dma_address(sg));
882 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
883 todo -= sg_dma_len(sg);
884 sg++;
885 }
886 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
887 *(rp++)=cpu_to_le32(sg_dma_address(sg));
888 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
889 offset += todo;
890 }
891 offset += padding;
892 }
893
894 return rp;
895}
896
897int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d
MK		 898 struct scatterlist *sglist, unsigned int top_offset,
899 unsigned int bottom_offset, unsigned int bpl,
900 unsigned int padding, unsigned int lines)
d19770e5 901{
44a6481d 902 u32 instructions, fields;
d19770e5
ST		 903 u32 *rp;
904 int rc;
905
906 fields = 0;
907 if (UNSET != top_offset)
908 fields++;
909 if (UNSET != bottom_offset)
910 fields++;
911
912 /* estimate risc mem: worst case is one write per page border +
913 one write per scan line + syncs + jump (all 2 dwords). Padding
914 can cause next bpl to start close to a page border. First DMA
915 region may be smaller than PAGE_SIZE */
916 /* write and jump need and extra dword */
917 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
918 instructions += 2;
d19770e5
ST		 919 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
920 return rc;
921
922 /* write risc instructions */
923 rp = risc->cpu;
924 if (UNSET != top_offset)
925 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
44a6481d 926 bpl, padding, lines);
d19770e5
ST		 927 if (UNSET != bottom_offset)
928 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
44a6481d 929 bpl, padding, lines);
d19770e5
ST		 930
931 /* save pointer to jmp instruction address */
932 risc->jmp = rp;
933 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
934 return 0;
935}
936
937int cx23885_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d
MK		 938 struct scatterlist *sglist, unsigned int bpl,
939 unsigned int lines)
d19770e5
ST		 940{
941 u32 instructions;
942 u32 *rp;
943 int rc;
944
945 /* estimate risc mem: worst case is one write per page border +
946 one write per scan line + syncs + jump (all 2 dwords). Here
947 there is no padding and no sync. First DMA region may be smaller
948 than PAGE_SIZE */
949 /* Jump and write need an extra dword */
950 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
951 instructions += 1;
952
d19770e5
ST		 953 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
954 return rc;
955
956 /* write risc instructions */
957 rp = risc->cpu;
958 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
959
960 /* save pointer to jmp instruction address */
961 risc->jmp = rp;
962 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
963 return 0;
964}
965
966int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d 967 u32 reg, u32 mask, u32 value)
d19770e5
ST		 968{
969 u32 *rp;
970 int rc;
971
972 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
973 return rc;
974
975 /* write risc instructions */
976 rp = risc->cpu;
d19770e5
ST		 977 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
978 *(rp++) = cpu_to_le32(reg);
979 *(rp++) = cpu_to_le32(value);
980 *(rp++) = cpu_to_le32(mask);
981 *(rp++) = cpu_to_le32(RISC_JUMP);
982 *(rp++) = cpu_to_le32(risc->dma);
983 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
984 return 0;
985}
986
987void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
988{
989 BUG_ON(in_interrupt());
44a6481d 990 videobuf_waiton(&buf->vb, 0, 0);
d19770e5
ST		 991 videobuf_dma_unmap(q, &buf->vb.dma);
992 videobuf_dma_free(&buf->vb.dma);
993 btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
994 buf->vb.state = STATE_NEEDS_INIT;
995}
996
997static int cx23885_start_dma(struct cx23885_tsport *port,
44a6481d
MK		 998 struct cx23885_dmaqueue *q,
999 struct cx23885_buffer *buf)
d19770e5
ST		 1000{
1001 struct cx23885_dev *dev = port->dev;
1002
1003 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
44a6481d 1004 buf->vb.width, buf->vb.height, buf->vb.field);
d19770e5 1005
d19770e5
ST		 1006 /* setup fifo + format */
1007 cx23885_sram_channel_setup(dev,
44a6481d
MK		 1008 &dev->sram_channels[ port->sram_chno ],
1009 port->ts_packet_size, buf->risc.dma);
3328e4fb 1010 if(debug > 5) {
d19770e5 1011 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
d19770e5 1012 cx23885_risc_disasm(port, &buf->risc);
3328e4fb 1013 }
d19770e5
ST		 1014
1015 /* write TS length to chip */
1016 cx_write(port->reg_lngth, buf->vb.width);
1017
1018 if (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) {
44a6481d
MK		 1019 printk( "%s() Failed. Unsupported value in .portc (0x%08x)\n",
1020 __FUNCTION__, cx23885_boards[dev->board].portc );
d19770e5
ST		 1021 return -EINVAL;
1022 }
1023
d19770e5
ST		 1024 udelay(100);
1025
1026 cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1027 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1028
d19770e5 1029 switch (dev->board) {
a77743bc 1030 case CX23885_BOARD_HAUPPAUGE_HVR1250:
d19770e5
ST		 1031 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1032 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1033 cx_write(port->reg_vld_misc, 0x00);
44a6481d
MK		 1034 dprintk(1, "%s() Configuring HVR1800/lp/1500 board\n",
1035 __FUNCTION__);
d19770e5
ST		 1036 break;
1037 default:
d19770e5
ST		 1038 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1039 }
1040
1041 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1042 udelay(100);
1043
1044 /* reset counter to zero */
1045 cx_write(port->reg_gpcnt_ctl, 3);
1046 q->count = 1;
1047
e133be0f 1048 switch(dev->bridge) {
d19770e5 1049 case CX23885_BRIDGE_885:
3bd40659 1050 case CX23885_BRIDGE_887:
d19770e5
ST		 1051 /* enable irqs */
1052 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1053 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1054 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1055 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1056 break;
d19770e5 1057 default:
d19770e5
ST		 1058 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1059 }
1060
d19770e5
ST		 1061 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1062
d19770e5
ST		 1063 return 0;
1064}
1065
1066static int cx23885_stop_dma(struct cx23885_tsport *port)
1067{
1068 struct cx23885_dev *dev = port->dev;
1069 dprintk(1, "%s()\n", __FUNCTION__);
1070
1071 /* Stop interrupts and DMA */
1072 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1073 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1074
1075 return 0;
1076}
1077
1078static int cx23885_restart_queue(struct cx23885_tsport *port,
1079 struct cx23885_dmaqueue *q)
1080{
1081 struct cx23885_dev *dev = port->dev;
1082 struct cx23885_buffer *buf;
1083 struct list_head *item;
1084
1085 dprintk(5, "%s()\n", __FUNCTION__);
1086 if (list_empty(&q->active))
1087 {
44a6481d
MK		 1088 struct cx23885_buffer *prev;
1089 prev = NULL;
d19770e5
ST		 1090
1091 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1092
44a6481d
MK		 1093 for (;;) {
1094 if (list_empty(&q->queued))
1095 return 0;
1096 buf = list_entry(q->queued.next, struct cx23885_buffer,
1097 vb.queue);
1098 if (NULL == prev) {
1099 list_del(&buf->vb.queue);
1100 list_add_tail(&buf->vb.queue, &q->active);
1101 cx23885_start_dma(port, q, buf);
1102 buf->vb.state = STATE_ACTIVE;
1103 buf->count = q->count++;
1104 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1105 dprintk(5, "[%p/%d] restart_queue - first active\n",
1106 buf, buf->vb.i);
1107
1108 } else if (prev->vb.width == buf->vb.width &&
1109 prev->vb.height == buf->vb.height &&
1110 prev->fmt == buf->fmt) {
1111 list_del(&buf->vb.queue);
1112 list_add_tail(&buf->vb.queue, &q->active);
1113 buf->vb.state = STATE_ACTIVE;
1114 buf->count = q->count++;
1115 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1116 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1117 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1118 buf, buf->vb.i);
1119 } else {
1120 return 0;
1121 }
1122 prev = buf;
1123 }
d19770e5
ST		 1124 return 0;
1125 }
1126
1127 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
44a6481d 1128 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
d19770e5
ST		 1129 buf, buf->vb.i);
1130 cx23885_start_dma(port, q, buf);
44a6481d 1131 list_for_each(item, &q->active) {
d19770e5
ST		 1132 buf = list_entry(item, struct cx23885_buffer, vb.queue);
1133 buf->count = q->count++;
1134 }
44a6481d 1135 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 1136 return 0;
1137}
1138
1139/* ------------------------------------------------------------------ */
1140
1141int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1142 struct cx23885_buffer *buf, enum v4l2_field field)
1143{
1144 struct cx23885_dev *dev = port->dev;
1145 int size = port->ts_packet_size * port->ts_packet_count;
1146 int rc;
1147
1148 dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1149 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1150 return -EINVAL;
1151
1152 if (STATE_NEEDS_INIT == buf->vb.state) {
1153 buf->vb.width = port->ts_packet_size;
1154 buf->vb.height = port->ts_packet_count;
1155 buf->vb.size = size;
1156 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1157
44a6481d 1158 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
d19770e5
ST		 1159 goto fail;
1160 cx23885_risc_databuffer(dev->pci, &buf->risc,
1161 buf->vb.dma.sglist,
1162 buf->vb.width, buf->vb.height);
1163 }
1164 buf->vb.state = STATE_PREPARED;
1165 return 0;
1166
1167 fail:
44a6481d 1168 cx23885_free_buffer(q, buf);
d19770e5
ST		 1169 return rc;
1170}
1171
1172void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1173{
1174 struct cx23885_buffer *prev;
1175 struct cx23885_dev *dev = port->dev;
1176 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1177
1178 /* add jump to stopper */
1179 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1180 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1181 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1182
1183 if (list_empty(&cx88q->active)) {
1184 dprintk( 1, "queue is empty - first active\n" );
44a6481d 1185 list_add_tail(&buf->vb.queue, &cx88q->active);
d19770e5
ST		 1186 cx23885_start_dma(port, cx88q, buf);
1187 buf->vb.state = STATE_ACTIVE;
1188 buf->count = cx88q->count++;
44a6481d
MK		 1189 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1190 dprintk(1, "[%p/%d] %s - first active\n",
d19770e5 1191 buf, buf->vb.i, __FUNCTION__);
d19770e5
ST		 1192 } else {
1193 dprintk( 1, "queue is not empty - append to active\n" );
44a6481d
MK		 1194 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1195 vb.queue);
1196 list_add_tail(&buf->vb.queue, &cx88q->active);
d19770e5
ST		 1197 buf->vb.state = STATE_ACTIVE;
1198 buf->count = cx88q->count++;
1199 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1200 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1201 dprintk( 1, "[%p/%d] %s - append to active\n",
44a6481d 1202 buf, buf->vb.i, __FUNCTION__);
d19770e5
ST		 1203 }
1204}
1205
1206/* ----------------------------------------------------------- */
1207
44a6481d
MK		 1208static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1209 int restart)
d19770e5
ST		 1210{
1211 struct cx23885_dev *dev = port->dev;
1212 struct cx23885_dmaqueue *q = &port->mpegq;
1213 struct cx23885_buffer *buf;
1214 unsigned long flags;
1215
44a6481d 1216 spin_lock_irqsave(&port->slock, flags);
d19770e5 1217 while (!list_empty(&q->active)) {
44a6481d
MK		 1218 buf = list_entry(q->active.next, struct cx23885_buffer,
1219 vb.queue);
d19770e5
ST		 1220 list_del(&buf->vb.queue);
1221 buf->vb.state = STATE_ERROR;
1222 wake_up(&buf->vb.done);
44a6481d 1223 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
d19770e5
ST		 1224 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1225 }
44a6481d 1226 if (restart) {
d19770e5
ST		 1227 dprintk(1, "restarting queue\n" );
1228 cx23885_restart_queue(port, q);
1229 }
44a6481d 1230 spin_unlock_irqrestore(&port->slock, flags);
d19770e5
ST		 1231}
1232
1233void cx23885_cancel_buffers(struct cx23885_tsport *port)
1234{
1235 struct cx23885_dev *dev = port->dev;
1236 struct cx23885_dmaqueue *q = &port->mpegq;
1237
44a6481d 1238 dprintk(1, "%s()\n", __FUNCTION__);
d19770e5
ST		 1239 del_timer_sync(&q->timeout);
1240 cx23885_stop_dma(port);
1241 do_cancel_buffers(port, "cancel", 0);
1242}
1243
1244static void cx23885_timeout(unsigned long data)
1245{
1246 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1247 struct cx23885_dev *dev = port->dev;
1248
1249 dprintk(1, "%s()\n",__FUNCTION__);
1250
1251 if (debug > 5)
d19770e5 1252 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
3328e4fb 1253
d19770e5
ST		 1254 cx23885_stop_dma(port);
1255 do_cancel_buffers(port, "timeout", 1);
1256}
1257
03121f05 1258static irqreturn_t cx23885_irq(int irq, void *dev_id)
d19770e5
ST		 1259{
1260 struct cx23885_dev *dev = dev_id;
1261 struct cx23885_tsport *port = &dev->ts2;
1262 u32 pci_status, pci_mask;
1263 u32 ts2_status, ts2_mask;
1264 int count = 0, handled = 0;
1265
1266 pci_status = cx_read(PCI_INT_STAT);
1267 pci_mask = cx_read(PCI_INT_MSK);
1268
1269 ts2_status = cx_read(VID_C_INT_STAT);
1270 ts2_mask = cx_read(VID_C_INT_MSK);
1271
1272 if ( (pci_status == 0) && (ts2_status == 0) )
1273 goto out;
1274
1275 count = cx_read(port->reg_gpcnt);
1276 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n", pci_status, pci_mask );
1277 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
1278
1279 if ( (pci_status & PCI_MSK_RISC_RD) ||
44a6481d
MK		 1280 (pci_status & PCI_MSK_RISC_WR) ||
1281 (pci_status & PCI_MSK_AL_RD) ||
1282 (pci_status & PCI_MSK_AL_WR) ||
1283 (pci_status & PCI_MSK_APB_DMA) ||
1284 (pci_status & PCI_MSK_VID_C) ||
1285 (pci_status & PCI_MSK_VID_B) ||
1286 (pci_status & PCI_MSK_VID_A) ||
1287 (pci_status & PCI_MSK_AUD_INT) ||
1288 (pci_status & PCI_MSK_AUD_EXT) )
d19770e5
ST		 1289 {
1290
1291 if (pci_status & PCI_MSK_RISC_RD)
1292 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1293 if (pci_status & PCI_MSK_RISC_WR)
1294 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1295 if (pci_status & PCI_MSK_AL_RD)
1296 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1297 if (pci_status & PCI_MSK_AL_WR)
1298 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1299 if (pci_status & PCI_MSK_APB_DMA)
1300 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1301 if (pci_status & PCI_MSK_VID_C)
1302 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1303 if (pci_status & PCI_MSK_VID_B)
1304 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1305 if (pci_status & PCI_MSK_VID_A)
1306 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1307 if (pci_status & PCI_MSK_AUD_INT)
1308 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1309 if (pci_status & PCI_MSK_AUD_EXT)
1310 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1311
1312 }
1313
1314 if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
44a6481d
MK		 1315 (ts2_status & VID_C_MSK_BAD_PKT) ||
1316 (ts2_status & VID_C_MSK_SYNC) ||
1317 (ts2_status & VID_C_MSK_OF))
d19770e5
ST		 1318 {
1319 if (ts2_status & VID_C_MSK_OPC_ERR)
1320 dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
1321 if (ts2_status & VID_C_MSK_BAD_PKT)
1322 dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
1323 if (ts2_status & VID_C_MSK_SYNC)
1324 dprintk(7, " (VID_C_MSK_SYNC 0x%08x)\n", VID_C_MSK_SYNC);
1325 if (ts2_status & VID_C_MSK_OF)
1326 dprintk(7, " (VID_C_MSK_OF 0x%08x)\n", VID_C_MSK_OF);
1327
1328 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1329
1330 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
d19770e5 1331 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
d19770e5
ST		 1332
1333 } else if (ts2_status & VID_C_MSK_RISCI1) {
1334
1335 dprintk(7, " (RISCI1 0x%08x)\n", VID_C_MSK_RISCI1);
1336
1337 spin_lock(&port->slock);
1338 count = cx_read(port->reg_gpcnt);
1339 cx23885_wakeup(port, &port->mpegq, count);
1340 spin_unlock(&port->slock);
1341
1342 } else if (ts2_status & VID_C_MSK_RISCI2) {
1343
1344 dprintk(7, " (RISCI2 0x%08x)\n", VID_C_MSK_RISCI2);
1345
1346 spin_lock(&port->slock);
1347 cx23885_restart_queue(port, &port->mpegq);
1348 spin_unlock(&port->slock);
1349
1350 }
1351
1352 cx_write(VID_C_INT_STAT, ts2_status);
1353 cx_write(PCI_INT_STAT, pci_status);
1354 handled = 1;
1355out:
1356 return IRQ_RETVAL(handled);
1357}
1358
1359static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
44a6481d 1360 const struct pci_device_id *pci_id)
d19770e5
ST		 1361{
1362 struct cx23885_dev *dev;
1363 int err;
1364
44a6481d 1365 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
d19770e5
ST		 1366 if (NULL == dev)
1367 return -ENOMEM;
1368
1369 /* pci init */
1370 dev->pci = pci_dev;
1371 if (pci_enable_device(pci_dev)) {
1372 err = -EIO;
1373 goto fail_free;
1374 }
1375
1376 if (cx23885_dev_setup(dev) < 0) {
1377 err = -EINVAL;
1378 goto fail_free;
1379 }
1380
1381 /* print pci info */
1382 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1383 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1384 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1385 "latency: %d, mmio: 0x%llx\n", dev->name,
1386 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1387 dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1388
1389 pci_set_master(pci_dev);
1390 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1391 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1392 err = -EIO;
1393 goto fail_irq;
1394 }
1395
44a6481d
MK		 1396 err = request_irq(pci_dev->irq, cx23885_irq,
1397 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
d19770e5
ST		 1398 if (err < 0) {
1399 printk(KERN_ERR "%s: can't get IRQ %d\n",
1400 dev->name, pci_dev->irq);
1401 goto fail_irq;
1402 }
1403
1404 pci_set_drvdata(pci_dev, dev);
1405 return 0;
1406
1407fail_irq:
1408 cx23885_dev_unregister(dev);
1409fail_free:
1410 kfree(dev);
1411 return err;
1412}
1413
1414static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1415{
1416 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1417
1418 cx23885_shutdown(dev);
1419
1420 pci_disable_device(pci_dev);
1421
1422 /* unregister stuff */
1423 free_irq(pci_dev->irq, dev);
1424 pci_set_drvdata(pci_dev, NULL);
1425
1426 mutex_lock(&devlist);
1427 list_del(&dev->devlist);
1428 mutex_unlock(&devlist);
1429
1430 cx23885_dev_unregister(dev);
1431 kfree(dev);
1432}
1433
1434static struct pci_device_id cx23885_pci_tbl[] = {
1435 {
1436 /* CX23885 */
1437 .vendor = 0x14f1,
1438 .device = 0x8852,
1439 .subvendor = PCI_ANY_ID,
1440 .subdevice = PCI_ANY_ID,
1441 },{
1442 /* CX23887 Rev 2 */
1443 .vendor = 0x14f1,
1444 .device = 0x8880,
1445 .subvendor = PCI_ANY_ID,
1446 .subdevice = PCI_ANY_ID,
1447 },{
1448 /* --- end of list --- */
1449 }
1450};
1451MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1452
1453static struct pci_driver cx23885_pci_driver = {
1454 .name = "cx23885",
1455 .id_table = cx23885_pci_tbl,
1456 .probe = cx23885_initdev,
1457 .remove = __devexit_p(cx23885_finidev),
1458 /* TODO */
1459 .suspend = NULL,
1460 .resume = NULL,
1461};
1462
1463static int cx23885_init(void)
1464{
1465 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
047646bf
ST		 1466 (CX23885_VERSION_CODE >> 16) & 0xff,
1467 (CX23885_VERSION_CODE >> 8) & 0xff,
1468 CX23885_VERSION_CODE & 0xff);
d19770e5
ST		 1469#ifdef SNAPSHOT
1470 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1471 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1472#endif
1473 return pci_register_driver(&cx23885_pci_driver);
1474}
1475
1476static void cx23885_fini(void)
1477{
1478 pci_unregister_driver(&cx23885_pci_driver);
1479}
1480
1481module_init(cx23885_init);
1482module_exit(cx23885_fini);
1483
1484/* ----------------------------------------------------------- */
1485/*
1486 * Local variables:
1487 * c-basic-offset: 8
1488 * End:
1489 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1490 */
Linux 6.x block layer and io_uring tree(s)