projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
V4L/DVB (6169): Removed unused function mt2131_set_gpo()
[linux-block.git] / drivers / media / video / cx23885 / cx23885-core.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kmod.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <asm/div64.h>
32
33#include "cx23885.h"
34
35MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37MODULE_LICENSE("GPL");
38
39static unsigned int debug = 0;
40module_param(debug,int,0644);
41MODULE_PARM_DESC(debug,"enable debug messages");
42
43static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44module_param_array(card, int, NULL, 0444);
45MODULE_PARM_DESC(card,"card type");
46
47#define dprintk(level,fmt, arg...) if (debug >= level) \
48 printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
49
50static unsigned int cx23885_devcount;
51
52static DEFINE_MUTEX(devlist);
53static LIST_HEAD(cx23885_devlist);
54
55#define NO_SYNC_LINE (-1U)
56
57/*
58 * CX23885 Assumptions
59 * 1 line = 16 bytes of CDT
60 * cmds size = 80
61 * cdt size = 16 * linesize
62 * iqsize = 64
63 * maxlines = 6
64 *
65 * Address Space:
66 * 0x00000000 0x00008fff FIFO clusters
67 * 0x00010000 0x000104af Channel Management Data Structures
68 * 0x000104b0 0x000104ff Free
69 * 0x00010500 0x000108bf 15 channels * iqsize
70 * 0x000108c0 0x000108ff Free
71 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
72 * 15 channels * (iqsize + (maxlines * linesize))
73 * 0x00010ea0 0x00010xxx Free
74 */
75
76struct sram_channel cx23885_sram_channels[] = {
77 [SRAM_CH01] = {
78 .name = "test ch1",
79 .cmds_start = 0x10000,
80 .ctrl_start = 0x10500,
81 .cdt = 0x10900,
82 .fifo_start = 0x3000,
83 .fifo_size = 0x1000,
84 .ptr1_reg = DMA1_PTR1,
85 .ptr2_reg = DMA1_PTR2,
86 .cnt1_reg = DMA1_CNT1,
87 .cnt2_reg = DMA1_CNT2,
88 .jumponly = 1,
89 },
90 [SRAM_CH02] = {
91 .name = "ch2",
92 .cmds_start = 0x0,
93 .ctrl_start = 0x0,
94 .cdt = 0x0,
95 .fifo_start = 0x0,
96 .fifo_size = 0x0,
97 .ptr1_reg = DMA2_PTR1,
98 .ptr2_reg = DMA2_PTR2,
99 .cnt1_reg = DMA2_CNT1,
100 .cnt2_reg = DMA2_CNT2,
101 },
102 [SRAM_CH03] = {
103 .name = "ch3",
104 .cmds_start = 0x0,
105 .ctrl_start = 0x0,
106 .cdt = 0x0,
107 .fifo_start = 0x0,
108 .fifo_size = 0x0,
109 .ptr1_reg = DMA3_PTR1,
110 .ptr2_reg = DMA3_PTR2,
111 .cnt1_reg = DMA3_CNT1,
112 .cnt2_reg = DMA3_CNT2,
113 },
114 [SRAM_CH04] = {
115 .name = "ch4",
116 .cmds_start = 0x0,
117 .ctrl_start = 0x0,
118 .cdt = 0x0,
119 .fifo_start = 0x0,
120 .fifo_size = 0x0,
121 .ptr1_reg = DMA4_PTR1,
122 .ptr2_reg = DMA4_PTR2,
123 .cnt1_reg = DMA4_CNT1,
124 .cnt2_reg = DMA4_CNT2,
125 },
126 [SRAM_CH05] = {
127 .name = "ch5",
128 .cmds_start = 0x0,
129 .ctrl_start = 0x0,
130 .cdt = 0x0,
131 .fifo_start = 0x0,
132 .fifo_size = 0x0,
133 .ptr1_reg = DMA5_PTR1,
134 .ptr2_reg = DMA5_PTR2,
135 .cnt1_reg = DMA5_CNT1,
136 .cnt2_reg = DMA5_CNT2,
137 },
138 [SRAM_CH06] = {
139 .name = "TS2 C",
140 .cmds_start = 0x10140,
141 .ctrl_start = 0x10680,
142 .cdt = 0x10480,
143 .fifo_start = 0x6000,
144 .fifo_size = 0x1000,
145 .ptr1_reg = DMA5_PTR1,
146 .ptr2_reg = DMA5_PTR2,
147 .cnt1_reg = DMA5_CNT1,
148 .cnt2_reg = DMA5_CNT2,
149 },
150 [SRAM_CH07] = {
151 .name = "ch7",
152 .cmds_start = 0x0,
153 .ctrl_start = 0x0,
154 .cdt = 0x0,
155 .fifo_start = 0x0,
156 .fifo_size = 0x0,
157 .ptr1_reg = DMA6_PTR1,
158 .ptr2_reg = DMA6_PTR2,
159 .cnt1_reg = DMA6_CNT1,
160 .cnt2_reg = DMA6_CNT2,
161 },
162 [SRAM_CH08] = {
163 .name = "ch8",
164 .cmds_start = 0x0,
165 .ctrl_start = 0x0,
166 .cdt = 0x0,
167 .fifo_start = 0x0,
168 .fifo_size = 0x0,
169 .ptr1_reg = DMA7_PTR1,
170 .ptr2_reg = DMA7_PTR2,
171 .cnt1_reg = DMA7_CNT1,
172 .cnt2_reg = DMA7_CNT2,
173 },
174 [SRAM_CH09] = {
175 .name = "ch9",
176 .cmds_start = 0x0,
177 .ctrl_start = 0x0,
178 .cdt = 0x0,
179 .fifo_start = 0x0,
180 .fifo_size = 0x0,
181 .ptr1_reg = DMA8_PTR1,
182 .ptr2_reg = DMA8_PTR2,
183 .cnt1_reg = DMA8_CNT1,
184 .cnt2_reg = DMA8_CNT2,
185 },
186};
187
188/* FIXME, these allocations will change when
189 * analog arrives. The be reviewed.
190 * CX23887 Assumptions
191 * 1 line = 16 bytes of CDT
192 * cmds size = 80
193 * cdt size = 16 * linesize
194 * iqsize = 64
195 * maxlines = 6
196 *
197 * Address Space:
198 * 0x00000000 0x00008fff FIFO clusters
199 * 0x00010000 0x000104af Channel Management Data Structures
200 * 0x000104b0 0x000104ff Free
201 * 0x00010500 0x000108bf 15 channels * iqsize
202 * 0x000108c0 0x000108ff Free
203 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
204 * 15 channels * (iqsize + (maxlines * linesize))
205 * 0x00010ea0 0x00010xxx Free
206 */
207
208struct sram_channel cx23887_sram_channels[] = {
209 [SRAM_CH01] = {
210 .name = "test ch1",
211 .cmds_start = 0x0,
212 .ctrl_start = 0x0,
213 .cdt = 0x0,
214 .fifo_start = 0x0,
215 .fifo_size = 0x0,
216 .ptr1_reg = DMA1_PTR1,
217 .ptr2_reg = DMA1_PTR2,
218 .cnt1_reg = DMA1_CNT1,
219 .cnt2_reg = DMA1_CNT2,
220 },
221 [SRAM_CH02] = {
222 .name = "ch2",
223 .cmds_start = 0x0,
224 .ctrl_start = 0x0,
225 .cdt = 0x0,
226 .fifo_start = 0x0,
227 .fifo_size = 0x0,
228 .ptr1_reg = DMA2_PTR1,
229 .ptr2_reg = DMA2_PTR2,
230 .cnt1_reg = DMA2_CNT1,
231 .cnt2_reg = DMA2_CNT2,
232 },
233 [SRAM_CH03] = {
234 .name = "ch3",
235 .cmds_start = 0x0,
236 .ctrl_start = 0x0,
237 .cdt = 0x0,
238 .fifo_start = 0x0,
239 .fifo_size = 0x0,
240 .ptr1_reg = DMA3_PTR1,
241 .ptr2_reg = DMA3_PTR2,
242 .cnt1_reg = DMA3_CNT1,
243 .cnt2_reg = DMA3_CNT2,
244 },
245 [SRAM_CH04] = {
246 .name = "ch4",
247 .cmds_start = 0x0,
248 .ctrl_start = 0x0,
249 .cdt = 0x0,
250 .fifo_start = 0x0,
251 .fifo_size = 0x0,
252 .ptr1_reg = DMA4_PTR1,
253 .ptr2_reg = DMA4_PTR2,
254 .cnt1_reg = DMA4_CNT1,
255 .cnt2_reg = DMA4_CNT2,
256 },
257 [SRAM_CH05] = {
258 .name = "ch5",
259 .cmds_start = 0x0,
260 .ctrl_start = 0x0,
261 .cdt = 0x0,
262 .fifo_start = 0x0,
263 .fifo_size = 0x0,
264 .ptr1_reg = DMA5_PTR1,
265 .ptr2_reg = DMA5_PTR2,
266 .cnt1_reg = DMA5_CNT1,
267 .cnt2_reg = DMA5_CNT2,
268 },
269 [SRAM_CH06] = {
270 .name = "TS2 C",
271 .cmds_start = 0x10140,
272 .ctrl_start = 0x10680,
3bd40659 273 .cdt = 0x108d0,
d19770e5
ST		 274 .fifo_start = 0x6000,
275 .fifo_size = 0x1000,
276 .ptr1_reg = DMA5_PTR1,
277 .ptr2_reg = DMA5_PTR2,
278 .cnt1_reg = DMA5_CNT1,
279 .cnt2_reg = DMA5_CNT2,
280 },
281 [SRAM_CH07] = {
282 .name = "ch7",
283 .cmds_start = 0x0,
284 .ctrl_start = 0x0,
285 .cdt = 0x0,
286 .fifo_start = 0x0,
287 .fifo_size = 0x0,
288 .ptr1_reg = DMA6_PTR1,
289 .ptr2_reg = DMA6_PTR2,
290 .cnt1_reg = DMA6_CNT1,
291 .cnt2_reg = DMA6_CNT2,
292 },
293 [SRAM_CH08] = {
294 .name = "ch8",
295 .cmds_start = 0x0,
296 .ctrl_start = 0x0,
297 .cdt = 0x0,
298 .fifo_start = 0x0,
299 .fifo_size = 0x0,
300 .ptr1_reg = DMA7_PTR1,
301 .ptr2_reg = DMA7_PTR2,
302 .cnt1_reg = DMA7_CNT1,
303 .cnt2_reg = DMA7_CNT2,
304 },
305 [SRAM_CH09] = {
306 .name = "ch9",
307 .cmds_start = 0x0,
308 .ctrl_start = 0x0,
309 .cdt = 0x0,
310 .fifo_start = 0x0,
311 .fifo_size = 0x0,
312 .ptr1_reg = DMA8_PTR1,
313 .ptr2_reg = DMA8_PTR2,
314 .cnt1_reg = DMA8_CNT1,
315 .cnt2_reg = DMA8_CNT2,
316 },
317};
318
319static int cx23885_risc_decode(u32 risc)
320{
321 static char *instr[16] = {
322 [ RISC_SYNC >> 28 ] = "sync",
323 [ RISC_WRITE >> 28 ] = "write",
324 [ RISC_WRITEC >> 28 ] = "writec",
325 [ RISC_READ >> 28 ] = "read",
326 [ RISC_READC >> 28 ] = "readc",
327 [ RISC_JUMP >> 28 ] = "jump",
328 [ RISC_SKIP >> 28 ] = "skip",
329 [ RISC_WRITERM >> 28 ] = "writerm",
330 [ RISC_WRITECM >> 28 ] = "writecm",
331 [ RISC_WRITECR >> 28 ] = "writecr",
332 };
333 static int incr[16] = {
334 [ RISC_WRITE >> 28 ] = 3, // 2
335 [ RISC_JUMP >> 28 ] = 3, // 2
336 [ RISC_SKIP >> 28 ] = 1,
337 [ RISC_SYNC >> 28 ] = 1,
338 [ RISC_WRITERM >> 28 ] = 3,
339 [ RISC_WRITECM >> 28 ] = 3,
340 [ RISC_WRITECR >> 28 ] = 4,
341 };
342 static char *bits[] = {
343 "12", "13", "14", "resync",
344 "cnt0", "cnt1", "18", "19",
345 "20", "21", "22", "23",
346 "irq1", "irq2", "eol", "sol",
347 };
348 int i;
349
350 printk("0x%08x [ %s", risc,
351 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
44a6481d 352 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
d19770e5 353 if (risc & (1 << (i + 12)))
44a6481d 354 printk(" %s", bits[i]);
d19770e5
ST		 355 printk(" count=%d ]\n", risc & 0xfff);
356 return incr[risc >> 28] ? incr[risc >> 28] : 1;
357}
358
359void cx23885_wakeup(struct cx23885_tsport *port,
44a6481d 360 struct cx23885_dmaqueue *q, u32 count)
d19770e5
ST		 361{
362 struct cx23885_dev *dev = port->dev;
363 struct cx23885_buffer *buf;
364 int bc;
365
366 for (bc = 0;; bc++) {
367 if (list_empty(&q->active))
368 break;
369 buf = list_entry(q->active.next,
370 struct cx23885_buffer, vb.queue);
371 /* count comes from the hw and is is 16bit wide --
372 * this trick handles wrap-arounds correctly for
373 * up to 32767 buffers in flight... */
374 if ((s16) (count - buf->count) < 0)
375 break;
376 do_gettimeofday(&buf->vb.ts);
44a6481d 377 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
d19770e5
ST		 378 count, buf->count);
379 buf->vb.state = STATE_DONE;
380 list_del(&buf->vb.queue);
381 wake_up(&buf->vb.done);
382 }
383 if (list_empty(&q->active)) {
384 del_timer(&q->timeout);
385 } else {
44a6481d 386 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 387 }
388 if (bc != 1)
44a6481d
MK		 389 printk("%s: %d buffers handled (should be 1)\n",
390 __FUNCTION__, bc);
d19770e5
ST		 391}
392void cx23885_sram_channel_dump(struct cx23885_dev *dev,
44a6481d 393 struct sram_channel *ch);
d19770e5
ST		 394
395int cx23885_sram_channel_setup(struct cx23885_dev *dev,
44a6481d
MK		 396 struct sram_channel *ch,
397 unsigned int bpl, u32 risc)
d19770e5 398{
44a6481d 399 unsigned int i, lines;
d19770e5
ST		 400 u32 cdt;
401
402 if (ch->cmds_start == 0)
403 {
44a6481d
MK		 404 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
405 ch->name);
d19770e5
ST		 406 cx_write(ch->ptr1_reg, 0);
407 cx_write(ch->ptr2_reg, 0);
408 cx_write(ch->cnt2_reg, 0);
409 cx_write(ch->cnt1_reg, 0);
410 return 0;
411 } else {
44a6481d
MK		 412 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
413 ch->name);
d19770e5
ST		 414 }
415
416 bpl = (bpl + 7) & ~7; /* alignment */
417 cdt = ch->cdt;
418 lines = ch->fifo_size / bpl;
419 if (lines > 6)
420 lines = 6;
421 BUG_ON(lines < 2);
422
44a6481d
MK		 423 cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
424 cx_write(8 + 4, cpu_to_le32(8) );
425 cx_write(8 + 8, cpu_to_le32(0) );
d19770e5
ST		 426
427 /* write CDT */
428 for (i = 0; i < lines; i++) {
44a6481d
MK		 429 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
430 ch->fifo_start + bpl*i);
d19770e5
ST		 431 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
432 cx_write(cdt + 16*i + 4, 0);
433 cx_write(cdt + 16*i + 8, 0);
434 cx_write(cdt + 16*i + 12, 0);
435 }
436
437 /* write CMDS */
438 if (ch->jumponly)
439 cx_write(ch->cmds_start + 0, 8);
440 else
441 cx_write(ch->cmds_start + 0, risc);
442 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
443 cx_write(ch->cmds_start + 8, cdt);
444 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
445 cx_write(ch->cmds_start + 16, ch->ctrl_start);
446 if (ch->jumponly)
447 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
448 else
449 cx_write(ch->cmds_start + 20, 64 >> 2);
450 for (i = 24; i < 80; i += 4)
451 cx_write(ch->cmds_start + i, 0);
452
453 /* fill registers */
454 cx_write(ch->ptr1_reg, ch->fifo_start);
455 cx_write(ch->ptr2_reg, cdt);
456 cx_write(ch->cnt2_reg, (lines*16) >> 3);
457 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
458
e133be0f
ST		 459 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
460 dev->bridge,
d19770e5
ST		 461 ch->name,
462 bpl,
463 lines);
464
465 return 0;
466}
467
468void cx23885_sram_channel_dump(struct cx23885_dev *dev,
44a6481d 469 struct sram_channel *ch)
d19770e5
ST		 470{
471 static char *name[] = {
472 "init risc lo",
473 "init risc hi",
474 "cdt base",
475 "cdt size",
476 "iq base",
477 "iq size",
478 "risc pc lo",
479 "risc pc hi",
480 "iq wr ptr",
481 "iq rd ptr",
482 "cdt current",
483 "pci target lo",
484 "pci target hi",
485 "line / byte",
486 };
487 u32 risc;
44a6481d 488 unsigned int i, j, n;
d19770e5
ST		 489
490 printk("%s: %s - dma channel status dump\n",
491 dev->name, ch->name);
492 for (i = 0; i < ARRAY_SIZE(name); i++)
493 printk("%s: cmds: %-15s: 0x%08x\n",
494 dev->name, name[i],
495 cx_read(ch->cmds_start + 4*i));
496
497 for (i = 0; i < 4; i++) {
44a6481d 498 risc = cx_read(ch->cmds_start + 4 * (i + 14));
d19770e5
ST		 499 printk("%s: risc%d: ", dev->name, i);
500 cx23885_risc_decode(risc);
501 }
502 for (i = 0; i < (64 >> 2); i += n) {
44a6481d
MK		 503 risc = cx_read(ch->ctrl_start + 4 * i);
504 /* No consideration for bits 63-32 */
505
506 printk("%s: (0x%08x) iq %x: ", dev->name,
507 ch->ctrl_start + 4 * i, i);
d19770e5
ST		 508 n = cx23885_risc_decode(risc);
509 for (j = 1; j < n; j++) {
44a6481d 510 risc = cx_read(ch->ctrl_start + 4 * (i + j));
d19770e5
ST		 511 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
512 dev->name, i+j, risc, j);
513 }
514 }
515
516 printk("%s: fifo: 0x%08x -> 0x%x\n",
517 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
518 printk("%s: ctrl: 0x%08x -> 0x%x\n",
44a6481d 519 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
d19770e5
ST		 520 printk("%s: ptr1_reg: 0x%08x\n",
521 dev->name, cx_read(ch->ptr1_reg));
522 printk("%s: ptr2_reg: 0x%08x\n",
523 dev->name, cx_read(ch->ptr2_reg));
524 printk("%s: cnt1_reg: 0x%08x\n",
525 dev->name, cx_read(ch->cnt1_reg));
526 printk("%s: cnt2_reg: 0x%08x\n",
527 dev->name, cx_read(ch->cnt2_reg));
528}
529
44a6481d
MK		 530void cx23885_risc_disasm(struct cx23885_tsport *port,
531 struct btcx_riscmem *risc)
d19770e5
ST		 532{
533 struct cx23885_dev *dev = port->dev;
44a6481d 534 unsigned int i, j, n;
d19770e5
ST		 535
536 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
537 dev->name, risc->cpu, (unsigned long)risc->dma);
538 for (i = 0; i < (risc->size >> 2); i += n) {
539 printk("%s: %04d: ", dev->name, i);
540 n = cx23885_risc_decode(risc->cpu[i]);
541 for (j = 1; j < n; j++)
542 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
44a6481d 543 dev->name, i + j, risc->cpu[i + j], j);
d19770e5
ST		 544 if (risc->cpu[i] == RISC_JUMP)
545 break;
546 }
547}
548
549void cx23885_shutdown(struct cx23885_dev *dev)
550{
551 /* disable RISC controller */
552 cx_write(DEV_CNTRL2, 0);
553
554 /* Disable all IR activity */
555 cx_write(IR_CNTRL_REG, 0);
556
557 /* Disable Video A/B activity */
558 cx_write(VID_A_DMA_CTL, 0);
559 cx_write(VID_B_DMA_CTL, 0);
560 cx_write(VID_C_DMA_CTL, 0);
561
562 /* Disable Audio activity */
563 cx_write(AUD_INT_DMA_CTL, 0);
564 cx_write(AUD_EXT_DMA_CTL, 0);
565
566 /* Disable Serial port */
567 cx_write(UART_CTL, 0);
568
569 /* Disable Interrupts */
570 cx_write(PCI_INT_MSK, 0);
571 cx_write(VID_A_INT_MSK, 0);
572 cx_write(VID_B_INT_MSK, 0);
573 cx_write(VID_C_INT_MSK, 0);
574 cx_write(AUDIO_INT_INT_MSK, 0);
575 cx_write(AUDIO_EXT_INT_MSK, 0);
576
577}
578
579void cx23885_reset(struct cx23885_dev *dev)
580{
581 dprintk(1, "%s()\n", __FUNCTION__);
582
583 cx23885_shutdown(dev);
584
585 cx_write(PCI_INT_STAT, 0xffffffff);
586 cx_write(VID_A_INT_STAT, 0xffffffff);
587 cx_write(VID_B_INT_STAT, 0xffffffff);
588 cx_write(VID_C_INT_STAT, 0xffffffff);
589 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
590 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
591 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
592
593 mdelay(100);
594
d19770e5
ST		 595 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
596 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
597 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
598 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
599 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
600 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
601 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
602 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
603 cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
604
d19770e5 605 switch(dev->board) {
a77743bc
ST		 606 case CX23885_BOARD_HAUPPAUGE_HVR1250:
607 /* GPIO-0 cx24227 demodulator reset */
608 dprintk( 1, "%s() Configuring HVR1250 GPIO's\n", __FUNCTION__);
609 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
610 break;
d19770e5
ST		 611 case CX23885_BOARD_HAUPPAUGE_HVR1800:
612 /* GPIO-0 656_CLK */
613 /* GPIO-1 656_D0 */
614 /* GPIO-2 8295A Reset */
615 /* GPIO-3-10 cx23417 data0-7 */
616 /* GPIO-11-14 cx23417 addr0-3 */
617 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
618 /* GPIO-19 IR_RX */
619 dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
620 // FIXME: Analog requires the tuner is brought out of reset
621 break;
622 }
623}
624
625
626static int cx23885_pci_quirks(struct cx23885_dev *dev)
627{
628 dprintk(1, "%s()\n", __FUNCTION__);
629
4823e9ee 630 if(dev->bridge == CX23885_BRIDGE_885)
d19770e5 631 cx_clear(RDR_TLCTL0, 1 << 4);
4823e9ee 632
d19770e5
ST		 633 return 0;
634}
635
636static int get_resources(struct cx23885_dev *dev)
637{
638 if (request_mem_region(pci_resource_start(dev->pci,0),
44a6481d
MK		 639 pci_resource_len(dev->pci,0),
640 dev->name))
d19770e5
ST		 641 return 0;
642
643 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
644 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
645
646 return -EBUSY;
647}
648
649static void cx23885_timeout(unsigned long data);
650int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d 651 u32 reg, u32 mask, u32 value);
d19770e5
ST		 652
653static int cx23885_ir_init(struct cx23885_dev *dev)
654{
655 dprintk(1, "%s()\n", __FUNCTION__);
656
657 switch (dev->board) {
a77743bc 658 case CX23885_BOARD_HAUPPAUGE_HVR1250:
d19770e5
ST		 659 case CX23885_BOARD_HAUPPAUGE_HVR1800:
660 dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
661 break;
662 }
663
664 return 0;
665}
666
667static int cx23885_dev_setup(struct cx23885_dev *dev)
668{
669 int i;
670
671 mutex_init(&dev->lock);
672
673 atomic_inc(&dev->refcount);
674
675 dev->nr = cx23885_devcount++;
676 dev->pci_bus = dev->pci->bus->number;
677 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
678 dev->pci_irqmask = 0x001f00;
679
680 /* External Master 1 Bus */
681 dev->i2c_bus[0].nr = 0;
682 dev->i2c_bus[0].dev = dev;
683 dev->i2c_bus[0].reg_stat = I2C1_STAT;
684 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
685 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
686 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
687 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
688 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
689
690 /* External Master 2 Bus */
691 dev->i2c_bus[1].nr = 1;
692 dev->i2c_bus[1].dev = dev;
693 dev->i2c_bus[1].reg_stat = I2C2_STAT;
694 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
695 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
696 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
697 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
698 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
699
700 /* Internal Master 3 Bus */
701 dev->i2c_bus[2].nr = 2;
702 dev->i2c_bus[2].dev = dev;
703 dev->i2c_bus[2].reg_stat = I2C3_STAT;
704 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
a2129af5 705 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
d19770e5
ST		 706 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
707 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
708 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
709
710 /* Transport bus init dma queue */
711 spin_lock_init(&dev->ts2.slock);
712 dev->ts2.dev = dev;
713 dev->ts2.nr = 2;
714 dev->ts2.sram_chno = SRAM_CH06;
715 INIT_LIST_HEAD(&dev->ts2.mpegq.active);
716 INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
717 dev->ts2.mpegq.timeout.function = cx23885_timeout;
718 dev->ts2.mpegq.timeout.data = (unsigned long)&dev->ts2;
719 init_timer(&dev->ts2.mpegq.timeout);
720
721 dev->ts2.reg_gpcnt = VID_C_GPCNT;
722 dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
723 dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
724 dev->ts2.reg_lngth = VID_C_LNGTH;
725 dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
726 dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
727 dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
728 dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
729 dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
730 dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
731 dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
732 dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
733
734 // FIXME: Make this board specific
735 dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
736 dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
737 dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
738 dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
739 dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
740
44a6481d
MK		 741 cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
742 dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
d19770e5 743
44a6481d 744 sprintf(dev->name, "cx23885[%d]", dev->nr);
d19770e5
ST		 745
746 if (get_resources(dev) < 0) {
747 printk(KERN_ERR "CORE %s No more PCIe resources for "
44a6481d
MK		 748 "subsystem: %04x:%04x\n",
749 dev->name, dev->pci->subsystem_vendor,
750 dev->pci->subsystem_device);
d19770e5
ST		 751
752 cx23885_devcount--;
753 goto fail_free;
754 }
755
756 mutex_lock(&devlist);
757 list_add_tail(&dev->devlist, &cx23885_devlist);
758 mutex_unlock(&devlist);
759
760 /* PCIe stuff */
761 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
44a6481d 762 pci_resource_len(dev->pci,0));
d19770e5
ST		 763
764 dev->bmmio = (u8 __iomem *)dev->lmmio;
765
d19770e5
ST		 766 /* board config */
767 dev->board = UNSET;
768 if (card[dev->nr] < cx23885_bcount)
769 dev->board = card[dev->nr];
770 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
771 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
772 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
773 dev->board = cx23885_subids[i].card;
774 if (UNSET == dev->board) {
775 dev->board = CX23885_BOARD_UNKNOWN;
776 cx23885_card_list(dev);
777 }
778 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
44a6481d
MK		 779 dev->name, dev->pci->subsystem_vendor,
780 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
781 dev->board, card[dev->nr] == dev->board ?
782 "insmod option" : "autodetected");
d19770e5 783
e133be0f
ST		 784 /* Configure the internal memory */
785 if(dev->pci->device == 0x8880) {
786 dev->bridge = CX23885_BRIDGE_887;
d19770e5 787 dev->sram_channels = cx23887_sram_channels;
e133be0f
ST		 788 } else
789 if(dev->pci->device == 0x8852) {
790 dev->bridge = CX23885_BRIDGE_885;
791 dev->sram_channels = cx23885_sram_channels;
d19770e5 792 }
44a6481d
MK		 793 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
794 __FUNCTION__, dev->bridge);
d19770e5 795
4823e9ee
ST		 796 cx23885_pci_quirks(dev);
797
d19770e5
ST		 798 /* init hardware */
799 cx23885_reset(dev);
800
801 cx23885_i2c_register(&dev->i2c_bus[0]);
802 cx23885_i2c_register(&dev->i2c_bus[1]);
803 cx23885_i2c_register(&dev->i2c_bus[2]);
804 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
805
806 cx23885_card_setup(dev);
807 cx23885_ir_init(dev);
808
809 if (cx23885_dvb_register(&dev->ts2) < 0) {
44a6481d
MK		 810 printk(KERN_ERR "%s() Failed to register dvb adapters\n",
811 __FUNCTION__);
d19770e5
ST		 812 }
813
814 return 0;
815
816fail_free:
817 kfree(dev);
818 return -ENODEV;
819}
820
821void cx23885_dev_unregister(struct cx23885_dev *dev)
822{
823 release_mem_region(pci_resource_start(dev->pci,0),
824 pci_resource_len(dev->pci,0));
825
826 if (!atomic_dec_and_test(&dev->refcount))
827 return;
828
829 cx23885_dvb_unregister(&dev->ts2);
830 cx23885_i2c_unregister(&dev->i2c_bus[2]);
831 cx23885_i2c_unregister(&dev->i2c_bus[1]);
832 cx23885_i2c_unregister(&dev->i2c_bus[0]);
833
834 iounmap(dev->lmmio);
835}
836
837static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
44a6481d
MK		 838 unsigned int offset, u32 sync_line,
839 unsigned int bpl, unsigned int padding,
840 unsigned int lines)
d19770e5
ST		 841{
842 struct scatterlist *sg;
44a6481d 843 unsigned int line, todo;
d19770e5
ST		 844
845 /* sync instruction */
846 if (sync_line != NO_SYNC_LINE)
847 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
848
849 /* scan lines */
850 sg = sglist;
851 for (line = 0; line < lines; line++) {
852 while (offset && offset >= sg_dma_len(sg)) {
853 offset -= sg_dma_len(sg);
854 sg++;
855 }
856 if (bpl <= sg_dma_len(sg)-offset) {
857 /* fits into current chunk */
858 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
859 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
860 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
861 offset+=bpl;
862 } else {
863 /* scanline needs to be split */
864 todo = bpl;
865 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
866 (sg_dma_len(sg)-offset));
867 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
868 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
869 todo -= (sg_dma_len(sg)-offset);
870 offset = 0;
871 sg++;
872 while (todo > sg_dma_len(sg)) {
873 *(rp++)=cpu_to_le32(RISC_WRITE|
874 sg_dma_len(sg));
875 *(rp++)=cpu_to_le32(sg_dma_address(sg));
876 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
877 todo -= sg_dma_len(sg);
878 sg++;
879 }
880 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
881 *(rp++)=cpu_to_le32(sg_dma_address(sg));
882 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
883 offset += todo;
884 }
885 offset += padding;
886 }
887
888 return rp;
889}
890
891int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d
MK		 892 struct scatterlist *sglist, unsigned int top_offset,
893 unsigned int bottom_offset, unsigned int bpl,
894 unsigned int padding, unsigned int lines)
d19770e5 895{
44a6481d 896 u32 instructions, fields;
d19770e5
ST		 897 u32 *rp;
898 int rc;
899
900 fields = 0;
901 if (UNSET != top_offset)
902 fields++;
903 if (UNSET != bottom_offset)
904 fields++;
905
906 /* estimate risc mem: worst case is one write per page border +
907 one write per scan line + syncs + jump (all 2 dwords). Padding
908 can cause next bpl to start close to a page border. First DMA
909 region may be smaller than PAGE_SIZE */
910 /* write and jump need and extra dword */
911 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
912 instructions += 2;
913 //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
914 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
915 return rc;
916
917 /* write risc instructions */
918 rp = risc->cpu;
919 if (UNSET != top_offset)
920 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
44a6481d 921 bpl, padding, lines);
d19770e5
ST		 922 if (UNSET != bottom_offset)
923 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
44a6481d 924 bpl, padding, lines);
d19770e5
ST		 925
926 /* save pointer to jmp instruction address */
927 risc->jmp = rp;
928 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
929 return 0;
930}
931
932int cx23885_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d
MK		 933 struct scatterlist *sglist, unsigned int bpl,
934 unsigned int lines)
d19770e5
ST		 935{
936 u32 instructions;
937 u32 *rp;
938 int rc;
939
940 /* estimate risc mem: worst case is one write per page border +
941 one write per scan line + syncs + jump (all 2 dwords). Here
942 there is no padding and no sync. First DMA region may be smaller
943 than PAGE_SIZE */
944 /* Jump and write need an extra dword */
945 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
946 instructions += 1;
947
948 //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
949 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
950 return rc;
951
952 /* write risc instructions */
953 rp = risc->cpu;
954 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
955
956 /* save pointer to jmp instruction address */
957 risc->jmp = rp;
958 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
959 return 0;
960}
961
962int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
44a6481d 963 u32 reg, u32 mask, u32 value)
d19770e5
ST		 964{
965 u32 *rp;
966 int rc;
967
968 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
969 return rc;
970
971 /* write risc instructions */
972 rp = risc->cpu;
973 //*(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2 | RISC_IMM);
974 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
975 *(rp++) = cpu_to_le32(reg);
976 *(rp++) = cpu_to_le32(value);
977 *(rp++) = cpu_to_le32(mask);
978 *(rp++) = cpu_to_le32(RISC_JUMP);
979 *(rp++) = cpu_to_le32(risc->dma);
980 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
981 return 0;
982}
983
984void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
985{
986 BUG_ON(in_interrupt());
44a6481d 987 videobuf_waiton(&buf->vb, 0, 0);
d19770e5
ST		 988 videobuf_dma_unmap(q, &buf->vb.dma);
989 videobuf_dma_free(&buf->vb.dma);
990 btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
991 buf->vb.state = STATE_NEEDS_INIT;
992}
993
994static int cx23885_start_dma(struct cx23885_tsport *port,
44a6481d
MK		 995 struct cx23885_dmaqueue *q,
996 struct cx23885_buffer *buf)
d19770e5
ST		 997{
998 struct cx23885_dev *dev = port->dev;
999
1000 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
44a6481d 1001 buf->vb.width, buf->vb.height, buf->vb.field);
d19770e5 1002
d19770e5
ST		 1003 /* setup fifo + format */
1004 cx23885_sram_channel_setup(dev,
44a6481d
MK		 1005 &dev->sram_channels[ port->sram_chno ],
1006 port->ts_packet_size, buf->risc.dma);
3328e4fb 1007 if(debug > 5) {
d19770e5 1008 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
d19770e5 1009 cx23885_risc_disasm(port, &buf->risc);
3328e4fb 1010 }
d19770e5
ST		 1011
1012 /* write TS length to chip */
1013 cx_write(port->reg_lngth, buf->vb.width);
1014
1015 if (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) {
44a6481d
MK		 1016 printk( "%s() Failed. Unsupported value in .portc (0x%08x)\n",
1017 __FUNCTION__, cx23885_boards[dev->board].portc );
d19770e5
ST		 1018 return -EINVAL;
1019 }
1020
1021 // FIXME: review the need for these two lines
1022 dprintk( 1, "%s() doing .dvb\n", __FUNCTION__);
1023 udelay(100);
1024
1025 cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1026 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1027
1028 // FIXME: review the need for this
1029 cx_write(GPIO2, 0x00);
1030
1031 switch (dev->board) {
a77743bc 1032 case CX23885_BOARD_HAUPPAUGE_HVR1250:
d19770e5
ST		 1033 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1034 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1035 cx_write(port->reg_vld_misc, 0x00);
44a6481d
MK		 1036 dprintk(1, "%s() Configuring HVR1800/lp/1500 board\n",
1037 __FUNCTION__);
d19770e5
ST		 1038 break;
1039 default:
1040 // FIXME
1041 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1042 }
1043
1044 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1045 udelay(100);
1046
1047 /* reset counter to zero */
1048 cx_write(port->reg_gpcnt_ctl, 3);
1049 q->count = 1;
1050
e133be0f 1051 switch(dev->bridge) {
d19770e5 1052 case CX23885_BRIDGE_885:
3bd40659 1053 case CX23885_BRIDGE_887:
d19770e5
ST		 1054 /* enable irqs */
1055 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1056 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1057 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1058 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1059 break;
d19770e5
ST		 1060 default:
1061 // FIXME: generate a sensible switch-default message
1062 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1063 }
1064
1065 dprintk(1, "%s() Register Dump\n", __FUNCTION__);
1066 dprintk(1, "%s() set port ts_int_msk, now %x\n", __FUNCTION__, cx_read(port->reg_ts_int_msk) );
1067 dprintk(1, "%s() DEV_CNTRL2 0x%08x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1068 dprintk(1, "%s() PCI_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(PCI_INT_MSK) );
1069 dprintk(1, "%s() VID_A_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(VID_A_INT_MSK) );
1070 dprintk(1, "%s() VID_B_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(VID_B_INT_MSK) );
1071 dprintk(1, "%s() VID_C_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSK) );
1072 dprintk(1, "%s() VID_A_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(VID_A_DMA_CTL) );
1073 dprintk(1, "%s() VID_B_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(VID_B_DMA_CTL) );
1074 dprintk(1, "%s() VID_C_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1075 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_INT_INT_MSK) );
1076 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_INT_DMA_CTL) );
1077 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_EXT_INT_MSK) );
1078 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_EXT_DMA_CTL) );
1079
1080 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1081
1082 dprintk(1, "%s() set dev_cntrl2, now %x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
1083 dprintk(1, "%s() VID_C_DMA_CTL , now %x\n", __FUNCTION__, cx_read(port->reg_dma_ctl) );
1084 dprintk(1, "%s() VID_C_DMA_CTL , now %x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
1085 dprintk(1, "%s() PAD_CTRL %x\n", __FUNCTION__, cx_read(PAD_CTRL) );
1086 dprintk(1, "%s() GPIO2 %x\n", __FUNCTION__, cx_read(GPIO2) );
1087 dprintk(1, "%s() VID_C_LN_LNGTH , now %x\n", __FUNCTION__, cx_read(port->reg_lngth) );
1088 dprintk(1, "%s() VID_C_HW_SOP_CTL, now %x\n", __FUNCTION__, cx_read(port->reg_hw_sop_ctrl) );
1089 dprintk(1, "%s() VID_C_GEN_CTL , now %x\n", __FUNCTION__, cx_read(port->reg_gen_ctrl) );
1090 dprintk(1, "%s() VID_C_SOP_STATUS, now %x\n", __FUNCTION__, cx_read(VID_C_SOP_STATUS) );
1091 dprintk(1, "%s() VID_C_TS_CLK_EN , now %x\n", __FUNCTION__, cx_read(VID_C_TS_CLK_EN) );
1092 dprintk(1, "%s() VID_C_FIFO_OVLST, now %x\n", __FUNCTION__, cx_read(VID_C_FIFO_OVFL_STAT) );
1093 dprintk(1, "%s() VID_C_INT_MSTAT , now 0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSTAT) );
1094 return 0;
1095}
1096
1097static int cx23885_stop_dma(struct cx23885_tsport *port)
1098{
1099 struct cx23885_dev *dev = port->dev;
1100 dprintk(1, "%s()\n", __FUNCTION__);
1101
1102 /* Stop interrupts and DMA */
1103 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1104 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1105
1106 return 0;
1107}
1108
1109static int cx23885_restart_queue(struct cx23885_tsport *port,
1110 struct cx23885_dmaqueue *q)
1111{
1112 struct cx23885_dev *dev = port->dev;
1113 struct cx23885_buffer *buf;
1114 struct list_head *item;
1115
1116 dprintk(5, "%s()\n", __FUNCTION__);
1117 if (list_empty(&q->active))
1118 {
44a6481d
MK		 1119 struct cx23885_buffer *prev;
1120 prev = NULL;
d19770e5
ST		 1121
1122 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1123
44a6481d
MK		 1124 for (;;) {
1125 if (list_empty(&q->queued))
1126 return 0;
1127 buf = list_entry(q->queued.next, struct cx23885_buffer,
1128 vb.queue);
1129 if (NULL == prev) {
1130 list_del(&buf->vb.queue);
1131 list_add_tail(&buf->vb.queue, &q->active);
1132 cx23885_start_dma(port, q, buf);
1133 buf->vb.state = STATE_ACTIVE;
1134 buf->count = q->count++;
1135 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1136 dprintk(5, "[%p/%d] restart_queue - first active\n",
1137 buf, buf->vb.i);
1138
1139 } else if (prev->vb.width == buf->vb.width &&
1140 prev->vb.height == buf->vb.height &&
1141 prev->fmt == buf->fmt) {
1142 list_del(&buf->vb.queue);
1143 list_add_tail(&buf->vb.queue, &q->active);
1144 buf->vb.state = STATE_ACTIVE;
1145 buf->count = q->count++;
1146 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1147 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1148 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1149 buf, buf->vb.i);
1150 } else {
1151 return 0;
1152 }
1153 prev = buf;
1154 }
d19770e5
ST		 1155 return 0;
1156 }
1157
1158 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
44a6481d 1159 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
d19770e5
ST		 1160 buf, buf->vb.i);
1161 cx23885_start_dma(port, q, buf);
44a6481d 1162 list_for_each(item, &q->active) {
d19770e5
ST		 1163 buf = list_entry(item, struct cx23885_buffer, vb.queue);
1164 buf->count = q->count++;
1165 }
44a6481d 1166 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 1167 return 0;
1168}
1169
1170/* ------------------------------------------------------------------ */
1171
1172int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1173 struct cx23885_buffer *buf, enum v4l2_field field)
1174{
1175 struct cx23885_dev *dev = port->dev;
1176 int size = port->ts_packet_size * port->ts_packet_count;
1177 int rc;
1178
1179 dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1180 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1181 return -EINVAL;
1182
1183 if (STATE_NEEDS_INIT == buf->vb.state) {
1184 buf->vb.width = port->ts_packet_size;
1185 buf->vb.height = port->ts_packet_count;
1186 buf->vb.size = size;
1187 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1188
44a6481d 1189 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
d19770e5
ST		 1190 goto fail;
1191 cx23885_risc_databuffer(dev->pci, &buf->risc,
1192 buf->vb.dma.sglist,
1193 buf->vb.width, buf->vb.height);
1194 }
1195 buf->vb.state = STATE_PREPARED;
1196 return 0;
1197
1198 fail:
44a6481d 1199 cx23885_free_buffer(q, buf);
d19770e5
ST		 1200 return rc;
1201}
1202
1203void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1204{
1205 struct cx23885_buffer *prev;
1206 struct cx23885_dev *dev = port->dev;
1207 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1208
1209 /* add jump to stopper */
1210 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1211 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1212 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1213
1214 if (list_empty(&cx88q->active)) {
1215 dprintk( 1, "queue is empty - first active\n" );
44a6481d 1216 list_add_tail(&buf->vb.queue, &cx88q->active);
d19770e5
ST		 1217 cx23885_start_dma(port, cx88q, buf);
1218 buf->vb.state = STATE_ACTIVE;
1219 buf->count = cx88q->count++;
44a6481d
MK		 1220 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1221 dprintk(1, "[%p/%d] %s - first active\n",
d19770e5
ST		 1222 buf, buf->vb.i, __FUNCTION__);
1223
1224 } else {
1225 dprintk( 1, "queue is not empty - append to active\n" );
44a6481d
MK		 1226 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1227 vb.queue);
1228 list_add_tail(&buf->vb.queue, &cx88q->active);
d19770e5
ST		 1229 buf->vb.state = STATE_ACTIVE;
1230 buf->count = cx88q->count++;
1231 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1232 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1233 dprintk( 1, "[%p/%d] %s - append to active\n",
44a6481d 1234 buf, buf->vb.i, __FUNCTION__);
d19770e5
ST		 1235 }
1236}
1237
1238/* ----------------------------------------------------------- */
1239
44a6481d
MK		 1240static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1241 int restart)
d19770e5
ST		 1242{
1243 struct cx23885_dev *dev = port->dev;
1244 struct cx23885_dmaqueue *q = &port->mpegq;
1245 struct cx23885_buffer *buf;
1246 unsigned long flags;
1247
44a6481d 1248 spin_lock_irqsave(&port->slock, flags);
d19770e5 1249 while (!list_empty(&q->active)) {
44a6481d
MK		 1250 buf = list_entry(q->active.next, struct cx23885_buffer,
1251 vb.queue);
d19770e5
ST		 1252 list_del(&buf->vb.queue);
1253 buf->vb.state = STATE_ERROR;
1254 wake_up(&buf->vb.done);
44a6481d 1255 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
d19770e5
ST		 1256 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1257 }
44a6481d 1258 if (restart) {
d19770e5
ST		 1259 dprintk(1, "restarting queue\n" );
1260 cx23885_restart_queue(port, q);
1261 }
44a6481d 1262 spin_unlock_irqrestore(&port->slock, flags);
d19770e5
ST		 1263}
1264
1265void cx23885_cancel_buffers(struct cx23885_tsport *port)
1266{
1267 struct cx23885_dev *dev = port->dev;
1268 struct cx23885_dmaqueue *q = &port->mpegq;
1269
44a6481d 1270 dprintk(1, "%s()\n", __FUNCTION__);
d19770e5
ST		 1271 del_timer_sync(&q->timeout);
1272 cx23885_stop_dma(port);
1273 do_cancel_buffers(port, "cancel", 0);
1274}
1275
1276static void cx23885_timeout(unsigned long data)
1277{
1278 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1279 struct cx23885_dev *dev = port->dev;
1280
1281 dprintk(1, "%s()\n",__FUNCTION__);
1282
1283 if (debug > 5)
d19770e5 1284 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
3328e4fb 1285
d19770e5
ST		 1286 cx23885_stop_dma(port);
1287 do_cancel_buffers(port, "timeout", 1);
1288}
1289
1290#define PCI_MSK_APB_DMA (1 << 12)
1291#define PCI_MSK_AL_WR (1 << 11)
1292#define PCI_MSK_AL_RD (1 << 10)
1293#define PCI_MSK_RISC_WR (1 << 9)
1294#define PCI_MSK_RISC_RD (1 << 8)
1295
1296#define PCI_MSK_AUD_EXT (1 << 4)
1297#define PCI_MSK_AUD_INT (1 << 3)
1298#define PCI_MSK_VID_C (1 << 2)
1299#define PCI_MSK_VID_B (1 << 1)
1300#define PCI_MSK_VID_A 1
1301
1302#define VID_C_MSK_BAD_PKT (1 << 20)
1303#define VID_C_MSK_OPC_ERR (1 << 16)
1304#define VID_C_MSK_SYNC (1 << 12)
1305#define VID_C_MSK_OF (1 << 8)
1306#define VID_C_MSK_RISCI2 (1 << 4)
1307#define VID_C_MSK_RISCI1 1
1308
03121f05 1309static irqreturn_t cx23885_irq(int irq, void *dev_id)
d19770e5
ST		 1310{
1311 struct cx23885_dev *dev = dev_id;
1312 struct cx23885_tsport *port = &dev->ts2;
1313 u32 pci_status, pci_mask;
1314 u32 ts2_status, ts2_mask;
1315 int count = 0, handled = 0;
1316
1317 pci_status = cx_read(PCI_INT_STAT);
1318 pci_mask = cx_read(PCI_INT_MSK);
1319
1320 ts2_status = cx_read(VID_C_INT_STAT);
1321 ts2_mask = cx_read(VID_C_INT_MSK);
1322
1323 if ( (pci_status == 0) && (ts2_status == 0) )
1324 goto out;
1325
1326 count = cx_read(port->reg_gpcnt);
1327 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n", pci_status, pci_mask );
1328 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
1329
1330 if ( (pci_status & PCI_MSK_RISC_RD) ||
44a6481d
MK		 1331 (pci_status & PCI_MSK_RISC_WR) ||
1332 (pci_status & PCI_MSK_AL_RD) ||
1333 (pci_status & PCI_MSK_AL_WR) ||
1334 (pci_status & PCI_MSK_APB_DMA) ||
1335 (pci_status & PCI_MSK_VID_C) ||
1336 (pci_status & PCI_MSK_VID_B) ||
1337 (pci_status & PCI_MSK_VID_A) ||
1338 (pci_status & PCI_MSK_AUD_INT) ||
1339 (pci_status & PCI_MSK_AUD_EXT) )
d19770e5
ST		 1340 {
1341
1342 if (pci_status & PCI_MSK_RISC_RD)
1343 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1344 if (pci_status & PCI_MSK_RISC_WR)
1345 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1346 if (pci_status & PCI_MSK_AL_RD)
1347 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1348 if (pci_status & PCI_MSK_AL_WR)
1349 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1350 if (pci_status & PCI_MSK_APB_DMA)
1351 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1352 if (pci_status & PCI_MSK_VID_C)
1353 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1354 if (pci_status & PCI_MSK_VID_B)
1355 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1356 if (pci_status & PCI_MSK_VID_A)
1357 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1358 if (pci_status & PCI_MSK_AUD_INT)
1359 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1360 if (pci_status & PCI_MSK_AUD_EXT)
1361 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1362
1363 }
1364
1365 if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
44a6481d
MK		 1366 (ts2_status & VID_C_MSK_BAD_PKT) ||
1367 (ts2_status & VID_C_MSK_SYNC) ||
1368 (ts2_status & VID_C_MSK_OF))
d19770e5
ST		 1369 {
1370 if (ts2_status & VID_C_MSK_OPC_ERR)
1371 dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
1372 if (ts2_status & VID_C_MSK_BAD_PKT)
1373 dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
1374 if (ts2_status & VID_C_MSK_SYNC)
1375 dprintk(7, " (VID_C_MSK_SYNC 0x%08x)\n", VID_C_MSK_SYNC);
1376 if (ts2_status & VID_C_MSK_OF)
1377 dprintk(7, " (VID_C_MSK_OF 0x%08x)\n", VID_C_MSK_OF);
1378
1379 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1380
1381 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
d19770e5 1382 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
d19770e5
ST		 1383
1384 } else if (ts2_status & VID_C_MSK_RISCI1) {
1385
1386 dprintk(7, " (RISCI1 0x%08x)\n", VID_C_MSK_RISCI1);
1387
1388 spin_lock(&port->slock);
1389 count = cx_read(port->reg_gpcnt);
1390 cx23885_wakeup(port, &port->mpegq, count);
1391 spin_unlock(&port->slock);
1392
1393 } else if (ts2_status & VID_C_MSK_RISCI2) {
1394
1395 dprintk(7, " (RISCI2 0x%08x)\n", VID_C_MSK_RISCI2);
1396
1397 spin_lock(&port->slock);
1398 cx23885_restart_queue(port, &port->mpegq);
1399 spin_unlock(&port->slock);
1400
1401 }
1402
1403 cx_write(VID_C_INT_STAT, ts2_status);
1404 cx_write(PCI_INT_STAT, pci_status);
1405 handled = 1;
1406out:
1407 return IRQ_RETVAL(handled);
1408}
1409
1410static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
44a6481d 1411 const struct pci_device_id *pci_id)
d19770e5
ST		 1412{
1413 struct cx23885_dev *dev;
1414 int err;
1415
44a6481d 1416 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
d19770e5
ST		 1417 if (NULL == dev)
1418 return -ENOMEM;
1419
1420 /* pci init */
1421 dev->pci = pci_dev;
1422 if (pci_enable_device(pci_dev)) {
1423 err = -EIO;
1424 goto fail_free;
1425 }
1426
1427 if (cx23885_dev_setup(dev) < 0) {
1428 err = -EINVAL;
1429 goto fail_free;
1430 }
1431
1432 /* print pci info */
1433 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1434 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1435 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1436 "latency: %d, mmio: 0x%llx\n", dev->name,
1437 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1438 dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1439
1440 pci_set_master(pci_dev);
1441 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1442 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1443 err = -EIO;
1444 goto fail_irq;
1445 }
1446
44a6481d
MK		 1447 err = request_irq(pci_dev->irq, cx23885_irq,
1448 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
d19770e5
ST		 1449 if (err < 0) {
1450 printk(KERN_ERR "%s: can't get IRQ %d\n",
1451 dev->name, pci_dev->irq);
1452 goto fail_irq;
1453 }
1454
1455 pci_set_drvdata(pci_dev, dev);
1456 return 0;
1457
1458fail_irq:
1459 cx23885_dev_unregister(dev);
1460fail_free:
1461 kfree(dev);
1462 return err;
1463}
1464
1465static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1466{
1467 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1468
1469 cx23885_shutdown(dev);
1470
1471 pci_disable_device(pci_dev);
1472
1473 /* unregister stuff */
1474 free_irq(pci_dev->irq, dev);
1475 pci_set_drvdata(pci_dev, NULL);
1476
1477 mutex_lock(&devlist);
1478 list_del(&dev->devlist);
1479 mutex_unlock(&devlist);
1480
1481 cx23885_dev_unregister(dev);
1482 kfree(dev);
1483}
1484
1485static struct pci_device_id cx23885_pci_tbl[] = {
1486 {
1487 /* CX23885 */
1488 .vendor = 0x14f1,
1489 .device = 0x8852,
1490 .subvendor = PCI_ANY_ID,
1491 .subdevice = PCI_ANY_ID,
1492 },{
1493 /* CX23887 Rev 2 */
1494 .vendor = 0x14f1,
1495 .device = 0x8880,
1496 .subvendor = PCI_ANY_ID,
1497 .subdevice = PCI_ANY_ID,
1498 },{
1499 /* --- end of list --- */
1500 }
1501};
1502MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1503
1504static struct pci_driver cx23885_pci_driver = {
1505 .name = "cx23885",
1506 .id_table = cx23885_pci_tbl,
1507 .probe = cx23885_initdev,
1508 .remove = __devexit_p(cx23885_finidev),
1509 /* TODO */
1510 .suspend = NULL,
1511 .resume = NULL,
1512};
1513
1514static int cx23885_init(void)
1515{
1516 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
047646bf
ST		 1517 (CX23885_VERSION_CODE >> 16) & 0xff,
1518 (CX23885_VERSION_CODE >> 8) & 0xff,
1519 CX23885_VERSION_CODE & 0xff);
d19770e5
ST		 1520#ifdef SNAPSHOT
1521 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1522 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1523#endif
1524 return pci_register_driver(&cx23885_pci_driver);
1525}
1526
1527static void cx23885_fini(void)
1528{
1529 pci_unregister_driver(&cx23885_pci_driver);
1530}
1531
1532module_init(cx23885_init);
1533module_exit(cx23885_fini);
1534
1535/* ----------------------------------------------------------- */
1536/*
1537 * Local variables:
1538 * c-basic-offset: 8
1539 * End:
1540 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1541 */
Linux 6.x block layer and io_uring tree(s)