projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| e0d3bafd SD |
1 | /* |
| 2 | cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB | |
| 84b5dbf3 | 3 | video capture devices |
| e0d3bafd SD |
4 | |
| 5 | Copyright (C) 2008 <srinivasa.deevi at conexant dot com> | |
| 6 | ||
| 7 | This program is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 2 of the License, or | |
| 10 | (at your option) any later version. | |
| 11 | ||
| 12 | This program is distributed in the hope that it will be useful, | |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | GNU General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with this program; if not, write to the Free Software | |
| 19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 20 | */ | |
| 21 | ||
| e0d3bafd SD |
22 | #ifndef _POLARIS_REG_H_ |
| 23 | #define _POLARIS_REG_H_ | |
| 24 | ||
| 25 | #define BOARD_CFG_STAT 0x0 | |
| 26 | #define TS_MODE_REG 0x4 | |
| 27 | #define TS1_CFG_REG 0x8 | |
| 28 | #define TS1_LENGTH_REG 0xc | |
| 29 | #define TS2_CFG_REG 0x10 | |
| 30 | #define TS2_LENGTH_REG 0x14 | |
| 31 | #define EP_MODE_SET 0x18 | |
| 32 | #define CIR_PWR_PTN1 0x1c | |
| 33 | #define CIR_PWR_PTN2 0x20 | |
| 34 | #define CIR_PWR_PTN3 0x24 | |
| 35 | #define CIR_PWR_MASK0 0x28 | |
| 36 | #define CIR_PWR_MASK1 0x2c | |
| 37 | #define CIR_PWR_MASK2 0x30 | |
| 38 | #define CIR_GAIN 0x34 | |
| 39 | #define CIR_CAR_REG 0x38 | |
| 40 | #define CIR_OT_CFG1 0x40 | |
| 41 | #define CIR_OT_CFG2 0x44 | |
| 64fbf444 | 42 | #define GBULK_BIT_EN 0x68 |
| e0d3bafd SD |
43 | #define PWR_CTL_EN 0x74 |
| 44 | ||
| 45 | /* Polaris Endpoints capture mask for register EP_MODE_SET */ | |
| 6e4f574b SD |
46 | #define ENABLE_EP1 0x01 /* Bit[0]=1 */ |
| 47 | #define ENABLE_EP2 0x02 /* Bit[1]=1 */ | |
| 48 | #define ENABLE_EP3 0x04 /* Bit[2]=1 */ | |
| 49 | #define ENABLE_EP4 0x08 /* Bit[3]=1 */ | |
| 50 | #define ENABLE_EP5 0x10 /* Bit[4]=1 */ | |
| 51 | #define ENABLE_EP6 0x20 /* Bit[5]=1 */ | |
| e0d3bafd SD |
52 | |
| 53 | /* Bit definition for register PWR_CTL_EN */ | |
| 54 | #define PWR_MODE_MASK 0x17f | |
| 6e4f574b SD |
55 | #define PWR_AV_EN 0x08 /* bit3 */ |
| 56 | #define PWR_ISO_EN 0x40 /* bit6 */ | |
| 57 | #define PWR_AV_MODE 0x30 /* bit4,5 */ | |
| 58 | #define PWR_TUNER_EN 0x04 /* bit2 */ | |
| 59 | #define PWR_DEMOD_EN 0x02 /* bit1 */ | |
| 60 | #define I2C_DEMOD_EN 0x01 /* bit0 */ | |
| 61 | #define PWR_RESETOUT_EN 0x100 /* bit8 */ | |
| 62 | ||
| 63 | enum AV_MODE{ | |
| 8ccd4cd0 MCC |
64 | POLARIS_AVMODE_DEFAULT = 0, |
| 65 | POLARIS_AVMODE_DIGITAL = 0x10, | |
| 66 | POLARIS_AVMODE_ANALOGT_TV = 0x20, | |
| 67 | POLARIS_AVMODE_ENXTERNAL_AV = 0x30, | |
| 6e4f574b SD |
68 | |
| 69 | }; | |
| e0d3bafd SD |
70 | |
| 71 | /* Colibri Registers */ | |
| 72 | ||
| 73 | #define SINGLE_ENDED 0x0 | |
| 74 | #define LOW_IF 0x4 | |
| 75 | #define EU_IF 0x9 | |
| 76 | #define US_IF 0xa | |
| 77 | ||
| e0d3bafd SD |
78 | #define SUP_BLK_TUNE1 0x00 |
| 79 | #define SUP_BLK_TUNE2 0x01 | |
| 80 | #define SUP_BLK_TUNE3 0x02 | |
| 81 | #define SUP_BLK_XTAL 0x03 | |
| 82 | #define SUP_BLK_PLL1 0x04 | |
| 83 | #define SUP_BLK_PLL2 0x05 | |
| 84 | #define SUP_BLK_PLL3 0x06 | |
| 85 | #define SUP_BLK_REF 0x07 | |
| 86 | #define SUP_BLK_PWRDN 0x08 | |
| 87 | #define SUP_BLK_TESTPAD 0x09 | |
| 88 | #define ADC_COM_INT5_STAB_REF 0x0a | |
| 89 | #define ADC_COM_QUANT 0x0b | |
| 90 | #define ADC_COM_BIAS1 0x0c | |
| 91 | #define ADC_COM_BIAS2 0x0d | |
| 92 | #define ADC_COM_BIAS3 0x0e | |
| 93 | #define TESTBUS_CTRL 0x12 | |
| 94 | ||
| 6e4f574b SD |
95 | #define FLD_PWRDN_TUNING_BIAS 0x10 |
| 96 | #define FLD_PWRDN_ENABLE_PLL 0x08 | |
| 97 | #define FLD_PWRDN_PD_BANDGAP 0x04 | |
| 98 | #define FLD_PWRDN_PD_BIAS 0x02 | |
| 99 | #define FLD_PWRDN_PD_TUNECK 0x01 | |
| 100 | ||
| 101 | ||
| e0d3bafd SD |
102 | #define ADC_STATUS_CH1 0x20 |
| 103 | #define ADC_STATUS_CH2 0x40 | |
| 104 | #define ADC_STATUS_CH3 0x60 | |
| 105 | ||
| 106 | #define ADC_STATUS2_CH1 0x21 | |
| 107 | #define ADC_STATUS2_CH2 0x41 | |
| 108 | #define ADC_STATUS2_CH3 0x61 | |
| 109 | ||
| 110 | #define ADC_CAL_ATEST_CH1 0x22 | |
| 111 | #define ADC_CAL_ATEST_CH2 0x42 | |
| 112 | #define ADC_CAL_ATEST_CH3 0x62 | |
| 113 | ||
| 114 | #define ADC_PWRDN_CLAMP_CH1 0x23 | |
| 115 | #define ADC_PWRDN_CLAMP_CH2 0x43 | |
| 116 | #define ADC_PWRDN_CLAMP_CH3 0x63 | |
| 117 | ||
| 118 | #define ADC_CTRL_DAC23_CH1 0x24 | |
| 119 | #define ADC_CTRL_DAC23_CH2 0x44 | |
| 120 | #define ADC_CTRL_DAC23_CH3 0x64 | |
| 121 | ||
| 122 | #define ADC_CTRL_DAC1_CH1 0x25 | |
| 123 | #define ADC_CTRL_DAC1_CH2 0x45 | |
| 124 | #define ADC_CTRL_DAC1_CH3 0x65 | |
| 125 | ||
| 126 | #define ADC_DCSERVO_DEM_CH1 0x26 | |
| 127 | #define ADC_DCSERVO_DEM_CH2 0x46 | |
| 128 | #define ADC_DCSERVO_DEM_CH3 0x66 | |
| 129 | ||
| 130 | #define ADC_FB_FRCRST_CH1 0x27 | |
| 131 | #define ADC_FB_FRCRST_CH2 0x47 | |
| 132 | #define ADC_FB_FRCRST_CH3 0x67 | |
| 133 | ||
| 134 | #define ADC_INPUT_CH1 0x28 | |
| 135 | #define ADC_INPUT_CH2 0x48 | |
| 136 | #define ADC_INPUT_CH3 0x68 | |
| 6e4f574b | 137 | #define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ |
| e0d3bafd SD |
138 | |
| 139 | #define ADC_NTF_PRECLMP_EN_CH1 0x29 | |
| 140 | #define ADC_NTF_PRECLMP_EN_CH2 0x49 | |
| 141 | #define ADC_NTF_PRECLMP_EN_CH3 0x69 | |
| 142 | ||
| 143 | #define ADC_QGAIN_RES_TRM_CH1 0x2a | |
| 144 | #define ADC_QGAIN_RES_TRM_CH2 0x4a | |
| 145 | #define ADC_QGAIN_RES_TRM_CH3 0x6a | |
| 146 | ||
| 147 | #define ADC_SOC_PRECLMP_TERM_CH1 0x2b | |
| 148 | #define ADC_SOC_PRECLMP_TERM_CH2 0x4b | |
| 149 | #define ADC_SOC_PRECLMP_TERM_CH3 0x6b | |
| 150 | ||
| 151 | #define TESTBUS_CTRL_CH1 0x32 | |
| 152 | #define TESTBUS_CTRL_CH2 0x52 | |
| 153 | #define TESTBUS_CTRL_CH3 0x72 | |
| 154 | ||
| 155 | /****************************************************************************** | |
| 84b5dbf3 | 156 | * DIF registers * |
| e0d3bafd SD |
157 | ******************************************************************************/ |
| 158 | #define DIRECT_IF_REVB_BASE 0x00300 | |
| 159 | ||
| 160 | /*****************************************************************************/ | |
| 6e4f574b | 161 | #define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) |
| e0d3bafd SD |
162 | /*****************************************************************************/ |
| 163 | #define FLD_DIF_PLL_LOCK 0x80000000 | |
| 164 | /* Reserved [30:29] */ | |
| 165 | #define FLD_DIF_PLL_FREE_RUN 0x10000000 | |
| 6e4f574b | 166 | #define FLD_DIF_PLL_FREQ 0x0fffffff |
| e0d3bafd SD |
167 | |
| 168 | /*****************************************************************************/ | |
| 6e4f574b | 169 | #define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) |
| e0d3bafd | 170 | /*****************************************************************************/ |
| 6e4f574b | 171 | #define FLD_DIF_KD_PD 0xff000000 |
| e0d3bafd | 172 | /* Reserved [23:20] */ |
| 6e4f574b SD |
173 | #define FLD_DIF_KDS_PD 0x000f0000 |
| 174 | #define FLD_DIF_KI_PD 0x0000ff00 | |
| e0d3bafd | 175 | /* Reserved [7:4] */ |
| 6e4f574b | 176 | #define FLD_DIF_KIS_PD 0x0000000f |
| e0d3bafd SD |
177 | |
| 178 | /*****************************************************************************/ | |
| 6e4f574b | 179 | #define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) |
| e0d3bafd | 180 | /*****************************************************************************/ |
| 6e4f574b | 181 | #define FLD_DIF_KD_FD 0xff000000 |
| e0d3bafd | 182 | /* Reserved [23:20] */ |
| 6e4f574b SD |
183 | #define FLD_DIF_KDS_FD 0x000f0000 |
| 184 | #define FLD_DIF_KI_FD 0x0000ff00 | |
| 185 | #define FLD_DIF_SIG_PROP_SZ 0x000000f0 | |
| 186 | #define FLD_DIF_KIS_FD 0x0000000f | |
| e0d3bafd SD |
187 | |
| 188 | /*****************************************************************************/ | |
| 6e4f574b | 189 | #define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c) |
| e0d3bafd | 190 | /*****************************************************************************/ |
| 6e4f574b SD |
191 | #define FLD_DIF_PLL_AGC_REF 0xfff00000 |
| 192 | #define FLD_DIF_PLL_AGC_KI 0x000f0000 | |
| e0d3bafd SD |
193 | /* Reserved [15] */ |
| 194 | #define FLD_DIF_FREQ_LIMIT 0x00007000 | |
| 6e4f574b SD |
195 | #define FLD_DIF_K_FD 0x00000f00 |
| 196 | #define FLD_DIF_DOWNSMPL_FD 0x000000ff | |
| e0d3bafd SD |
197 | |
| 198 | /*****************************************************************************/ | |
| 6e4f574b | 199 | #define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) |
| e0d3bafd SD |
200 | /*****************************************************************************/ |
| 201 | /* Reserved [31:16] */ | |
| 202 | #define FLD_DIF_PLL_AGC_EN 0x00008000 | |
| 203 | /* Reserved [14:12] */ | |
| 6e4f574b | 204 | #define FLD_DIF_PLL_MAN_GAIN 0x00000fff |
| e0d3bafd SD |
205 | |
| 206 | /*****************************************************************************/ | |
| 6e4f574b | 207 | #define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) |
| e0d3bafd | 208 | /*****************************************************************************/ |
| 6e4f574b SD |
209 | #define FLD_DIF_K_AGC_RF 0xf0000000 |
| 210 | #define FLD_DIF_K_AGC_IF 0x0f000000 | |
| 211 | #define FLD_DIF_K_AGC_INT 0x00f00000 | |
| e0d3bafd | 212 | /* Reserved [19:12] */ |
| 6e4f574b | 213 | #define FLD_DIF_IF_REF 0x00000fff |
| e0d3bafd SD |
214 | |
| 215 | /*****************************************************************************/ | |
| 6e4f574b | 216 | #define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) |
| e0d3bafd | 217 | /*****************************************************************************/ |
| 6e4f574b SD |
218 | #define FLD_DIF_IF_MAX 0xff000000 |
| 219 | #define FLD_DIF_IF_MIN 0x00ff0000 | |
| 220 | #define FLD_DIF_IF_AGC 0x0000ffff | |
| e0d3bafd SD |
221 | |
| 222 | /*****************************************************************************/ | |
| 6e4f574b | 223 | #define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c) |
| e0d3bafd | 224 | /*****************************************************************************/ |
| 6e4f574b SD |
225 | #define FLD_DIF_INT_MAX 0xff000000 |
| 226 | #define FLD_DIF_INT_MIN 0x00ff0000 | |
| 227 | #define FLD_DIF_INT_AGC 0x0000ffff | |
| e0d3bafd SD |
228 | |
| 229 | /*****************************************************************************/ | |
| 6e4f574b | 230 | #define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) |
| e0d3bafd | 231 | /*****************************************************************************/ |
| 6e4f574b SD |
232 | #define FLD_DIF_RF_MAX 0xff000000 |
| 233 | #define FLD_DIF_RF_MIN 0x00ff0000 | |
| 234 | #define FLD_DIF_RF_AGC 0x0000ffff | |
| e0d3bafd SD |
235 | |
| 236 | /*****************************************************************************/ | |
| 6e4f574b | 237 | #define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) |
| e0d3bafd | 238 | /*****************************************************************************/ |
| 6e4f574b SD |
239 | #define FLD_DIF_IF_AGC_IN 0xffff0000 |
| 240 | #define FLD_DIF_INT_AGC_IN 0x0000ffff | |
| e0d3bafd SD |
241 | |
| 242 | /*****************************************************************************/ | |
| 6e4f574b | 243 | #define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) |
| e0d3bafd SD |
244 | /*****************************************************************************/ |
| 245 | /* Reserved [31:16] */ | |
| 6e4f574b | 246 | #define FLD_DIF_RF_AGC_IN 0x0000ffff |
| e0d3bafd SD |
247 | |
| 248 | /*****************************************************************************/ | |
| 6e4f574b | 249 | #define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c) |
| e0d3bafd | 250 | /*****************************************************************************/ |
| 6e4f574b | 251 | #define FLD_DIF_AFD 0xc0000000 |
| e0d3bafd | 252 | #define FLD_DIF_K_VID_AGC 0x30000000 |
| 6e4f574b SD |
253 | #define FLD_DIF_LINE_LENGTH 0x0fff0000 |
| 254 | #define FLD_DIF_AGC_GAIN 0x0000ffff | |
| e0d3bafd SD |
255 | |
| 256 | /*****************************************************************************/ | |
| 6e4f574b | 257 | #define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) |
| e0d3bafd SD |
258 | /*****************************************************************************/ |
| 259 | #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 | |
| 260 | /* Reserved [30:30] */ | |
| 6e4f574b | 261 | #define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000 |
| e0d3bafd SD |
262 | /* Reserved [23:17] */ |
| 263 | #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 | |
| 6e4f574b | 264 | #define FLD_DIF_VID_MAN_GAIN 0x0000ffff |
| e0d3bafd SD |
265 | |
| 266 | /*****************************************************************************/ | |
| 6e4f574b | 267 | #define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) |
| e0d3bafd | 268 | /*****************************************************************************/ |
| 6e4f574b SD |
269 | #define FLD_DIF_LPF_FREQ 0xc0000000 |
| 270 | #define FLD_DIF_AV_PHASE_INC 0x3f000000 | |
| 271 | #define FLD_DIF_AUDIO_FREQ 0x00ffffff | |
| e0d3bafd SD |
272 | |
| 273 | /*****************************************************************************/ | |
| 6e4f574b | 274 | #define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) |
| e0d3bafd SD |
275 | /*****************************************************************************/ |
| 276 | /* Reserved [31:24] */ | |
| 6e4f574b SD |
277 | #define FLD_DIF_IIR23_R2 0x00ff0000 |
| 278 | #define FLD_DIF_IIR23_R1 0x0000ff00 | |
| 279 | #define FLD_DIF_IIR1_R1 0x000000ff | |
| e0d3bafd SD |
280 | |
| 281 | /*****************************************************************************/ | |
| 6e4f574b | 282 | #define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c) |
| e0d3bafd SD |
283 | /*****************************************************************************/ |
| 284 | #define FLD_DIF_DIF_BYPASS 0x80000000 | |
| 285 | #define FLD_DIF_FM_NYQ_GAIN 0x40000000 | |
| 286 | #define FLD_DIF_RF_AGC_ENA 0x20000000 | |
| 287 | #define FLD_DIF_INT_AGC_ENA 0x10000000 | |
| 288 | #define FLD_DIF_IF_AGC_ENA 0x08000000 | |
| 289 | #define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000 | |
| 290 | #define FLD_DIF_VIDEO_AGC_ENA 0x02000000 | |
| 291 | #define FLD_DIF_RF_AGC_INV 0x01000000 | |
| 292 | #define FLD_DIF_INT_AGC_INV 0x00800000 | |
| 293 | #define FLD_DIF_IF_AGC_INV 0x00400000 | |
| 294 | #define FLD_DIF_SPEC_INV 0x00200000 | |
| 295 | #define FLD_DIF_AUD_FULL_BW 0x00100000 | |
| 296 | #define FLD_DIF_AUD_SRC_SEL 0x00080000 | |
| 297 | /* Reserved [18] */ | |
| 298 | #define FLD_DIF_IF_FREQ 0x00030000 | |
| 299 | /* Reserved [15:14] */ | |
| 6e4f574b | 300 | #define FLD_DIF_TIP_OFFSET 0x00003f00 |
| e0d3bafd SD |
301 | /* Reserved [7:5] */ |
| 302 | #define FLD_DIF_DITHER_ENA 0x00000010 | |
| 303 | /* Reserved [3:1] */ | |
| 304 | #define FLD_DIF_RF_IF_LOCK 0x00000001 | |
| 305 | ||
| 306 | /*****************************************************************************/ | |
| 6e4f574b | 307 | #define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) |
| e0d3bafd SD |
308 | /*****************************************************************************/ |
| 309 | /* Reserved [31:29] */ | |
| 6e4f574b | 310 | #define FLD_DIF_PHASE_INC 0x1fffffff |
| e0d3bafd SD |
311 | |
| 312 | /*****************************************************************************/ | |
| 6e4f574b | 313 | #define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) |
| e0d3bafd SD |
314 | /*****************************************************************************/ |
| 315 | /* Reserved [31:16] */ | |
| 6e4f574b SD |
316 | #define FLD_DIF_SRC_KI 0x0000ff00 |
| 317 | #define FLD_DIF_SRC_KD 0x000000ff | |
| e0d3bafd SD |
318 | |
| 319 | /*****************************************************************************/ | |
| 6e4f574b | 320 | #define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) |
| e0d3bafd SD |
321 | /*****************************************************************************/ |
| 322 | /* Reserved [31:19] */ | |
| 323 | #define FLD_DIF_BPF_COEFF_0 0x00070000 | |
| 324 | /* Reserved [15:4] */ | |
| 6e4f574b | 325 | #define FLD_DIF_BPF_COEFF_1 0x0000000f |
| e0d3bafd SD |
326 | |
| 327 | /*****************************************************************************/ | |
| 6e4f574b | 328 | #define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) |
| e0d3bafd SD |
329 | /*****************************************************************************/ |
| 330 | /* Reserved [31:22] */ | |
| 6e4f574b | 331 | #define FLD_DIF_BPF_COEFF_2 0x003f0000 |
| e0d3bafd | 332 | /* Reserved [15:7] */ |
| 6e4f574b | 333 | #define FLD_DIF_BPF_COEFF_3 0x0000007f |
| e0d3bafd SD |
334 | |
| 335 | /*****************************************************************************/ | |
| 6e4f574b | 336 | #define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) |
| e0d3bafd SD |
337 | /*****************************************************************************/ |
| 338 | /* Reserved [31:24] */ | |
| 6e4f574b | 339 | #define FLD_DIF_BPF_COEFF_4 0x00ff0000 |
| e0d3bafd | 340 | /* Reserved [15:8] */ |
| 6e4f574b | 341 | #define FLD_DIF_BPF_COEFF_5 0x000000ff |
| e0d3bafd SD |
342 | |
| 343 | /*****************************************************************************/ | |
| 6e4f574b | 344 | #define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) |
| e0d3bafd SD |
345 | /*****************************************************************************/ |
| 346 | /* Reserved [31:25] */ | |
| 6e4f574b | 347 | #define FLD_DIF_BPF_COEFF_6 0x01ff0000 |
| e0d3bafd | 348 | /* Reserved [15:9] */ |
| 6e4f574b | 349 | #define FLD_DIF_BPF_COEFF_7 0x000001ff |
| e0d3bafd SD |
350 | |
| 351 | /*****************************************************************************/ | |
| 6e4f574b | 352 | #define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) |
| e0d3bafd SD |
353 | /*****************************************************************************/ |
| 354 | /* Reserved [31:26] */ | |
| 6e4f574b | 355 | #define FLD_DIF_BPF_COEFF_8 0x03ff0000 |
| e0d3bafd | 356 | /* Reserved [15:10] */ |
| 6e4f574b | 357 | #define FLD_DIF_BPF_COEFF_9 0x000003ff |
| e0d3bafd SD |
358 | |
| 359 | /*****************************************************************************/ | |
| 6e4f574b | 360 | #define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c) |
| e0d3bafd SD |
361 | /*****************************************************************************/ |
| 362 | /* Reserved [31:27] */ | |
| 6e4f574b | 363 | #define FLD_DIF_BPF_COEFF_10 0x07ff0000 |
| e0d3bafd | 364 | /* Reserved [15:11] */ |
| 6e4f574b | 365 | #define FLD_DIF_BPF_COEFF_11 0x000007ff |
| e0d3bafd SD |
366 | |
| 367 | /*****************************************************************************/ | |
| 6e4f574b | 368 | #define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) |
| e0d3bafd SD |
369 | /*****************************************************************************/ |
| 370 | /* Reserved [31:27] */ | |
| 6e4f574b | 371 | #define FLD_DIF_BPF_COEFF_12 0x07ff0000 |
| e0d3bafd | 372 | /* Reserved [15:12] */ |
| 6e4f574b | 373 | #define FLD_DIF_BPF_COEFF_13 0x00000fff |
| e0d3bafd SD |
374 | |
| 375 | /*****************************************************************************/ | |
| 6e4f574b | 376 | #define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) |
| e0d3bafd SD |
377 | /*****************************************************************************/ |
| 378 | /* Reserved [31:28] */ | |
| 6e4f574b | 379 | #define FLD_DIF_BPF_COEFF_14 0x0fff0000 |
| e0d3bafd | 380 | /* Reserved [15:12] */ |
| 6e4f574b | 381 | #define FLD_DIF_BPF_COEFF_15 0x00000fff |
| e0d3bafd SD |
382 | |
| 383 | /*****************************************************************************/ | |
| 6e4f574b | 384 | #define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) |
| e0d3bafd SD |
385 | /*****************************************************************************/ |
| 386 | /* Reserved [31:29] */ | |
| 6e4f574b | 387 | #define FLD_DIF_BPF_COEFF_16 0x1fff0000 |
| e0d3bafd | 388 | /* Reserved [15:13] */ |
| 6e4f574b | 389 | #define FLD_DIF_BPF_COEFF_17 0x00001fff |
| e0d3bafd SD |
390 | |
| 391 | /*****************************************************************************/ | |
| 6e4f574b | 392 | #define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c) |
| e0d3bafd SD |
393 | /*****************************************************************************/ |
| 394 | /* Reserved [31:29] */ | |
| 6e4f574b | 395 | #define FLD_DIF_BPF_COEFF_18 0x1fff0000 |
| e0d3bafd | 396 | /* Reserved [15:13] */ |
| 6e4f574b | 397 | #define FLD_DIF_BPF_COEFF_19 0x00001fff |
| e0d3bafd SD |
398 | |
| 399 | /*****************************************************************************/ | |
| 6e4f574b | 400 | #define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) |
| e0d3bafd SD |
401 | /*****************************************************************************/ |
| 402 | /* Reserved [31:29] */ | |
| 6e4f574b | 403 | #define FLD_DIF_BPF_COEFF_20 0x1fff0000 |
| e0d3bafd | 404 | /* Reserved [15:14] */ |
| 6e4f574b | 405 | #define FLD_DIF_BPF_COEFF_21 0x00003fff |
| e0d3bafd SD |
406 | |
| 407 | /*****************************************************************************/ | |
| 6e4f574b | 408 | #define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) |
| e0d3bafd SD |
409 | /*****************************************************************************/ |
| 410 | /* Reserved [31:30] */ | |
| 6e4f574b | 411 | #define FLD_DIF_BPF_COEFF_22 0x3fff0000 |
| e0d3bafd | 412 | /* Reserved [15:14] */ |
| 6e4f574b | 413 | #define FLD_DIF_BPF_COEFF_23 0x00003fff |
| e0d3bafd SD |
414 | |
| 415 | /*****************************************************************************/ | |
| 6e4f574b | 416 | #define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) |
| e0d3bafd SD |
417 | /*****************************************************************************/ |
| 418 | /* Reserved [31:30] */ | |
| 6e4f574b | 419 | #define FLD_DIF_BPF_COEFF_24 0x3fff0000 |
| e0d3bafd | 420 | /* Reserved [15:14] */ |
| 6e4f574b | 421 | #define FLD_DIF_BPF_COEFF_25 0x00003fff |
| e0d3bafd SD |
422 | |
| 423 | /*****************************************************************************/ | |
| 6e4f574b | 424 | #define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c) |
| e0d3bafd SD |
425 | /*****************************************************************************/ |
| 426 | /* Reserved [31:30] */ | |
| 6e4f574b | 427 | #define FLD_DIF_BPF_COEFF_26 0x3fff0000 |
| e0d3bafd | 428 | /* Reserved [15:14] */ |
| 6e4f574b | 429 | #define FLD_DIF_BPF_COEFF_27 0x00003fff |
| e0d3bafd SD |
430 | |
| 431 | /*****************************************************************************/ | |
| 6e4f574b | 432 | #define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) |
| e0d3bafd SD |
433 | /*****************************************************************************/ |
| 434 | /* Reserved [31:30] */ | |
| 6e4f574b | 435 | #define FLD_DIF_BPF_COEFF_28 0x3fff0000 |
| e0d3bafd | 436 | /* Reserved [15:14] */ |
| 6e4f574b | 437 | #define FLD_DIF_BPF_COEFF_29 0x00003fff |
| e0d3bafd SD |
438 | |
| 439 | /*****************************************************************************/ | |
| 6e4f574b | 440 | #define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) |
| e0d3bafd SD |
441 | /*****************************************************************************/ |
| 442 | /* Reserved [31:30] */ | |
| 6e4f574b | 443 | #define FLD_DIF_BPF_COEFF_30 0x3fff0000 |
| e0d3bafd | 444 | /* Reserved [15:14] */ |
| 6e4f574b | 445 | #define FLD_DIF_BPF_COEFF_31 0x00003fff |
| e0d3bafd SD |
446 | |
| 447 | /*****************************************************************************/ | |
| 6e4f574b | 448 | #define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) |
| e0d3bafd SD |
449 | /*****************************************************************************/ |
| 450 | /* Reserved [31:30] */ | |
| 6e4f574b | 451 | #define FLD_DIF_BPF_COEFF_32 0x3fff0000 |
| e0d3bafd | 452 | /* Reserved [15:14] */ |
| 6e4f574b | 453 | #define FLD_DIF_BPF_COEFF_33 0x00003fff |
| e0d3bafd SD |
454 | |
| 455 | /*****************************************************************************/ | |
| 6e4f574b | 456 | #define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c) |
| e0d3bafd SD |
457 | /*****************************************************************************/ |
| 458 | /* Reserved [31:30] */ | |
| 6e4f574b | 459 | #define FLD_DIF_BPF_COEFF_34 0x3fff0000 |
| e0d3bafd | 460 | /* Reserved [15:14] */ |
| 6e4f574b | 461 | #define FLD_DIF_BPF_COEFF_35 0x00003fff |
| e0d3bafd SD |
462 | |
| 463 | /*****************************************************************************/ | |
| 6e4f574b | 464 | #define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) |
| e0d3bafd SD |
465 | /*****************************************************************************/ |
| 466 | /* Reserved [31:30] */ | |
| 6e4f574b | 467 | #define FLD_DIF_BPF_COEFF_36 0x3fff0000 |
| e0d3bafd SD |
468 | /* Reserved [15:0] */ |
| 469 | ||
| 470 | /*****************************************************************************/ | |
| 6e4f574b | 471 | #define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) |
| e0d3bafd SD |
472 | /*****************************************************************************/ |
| 473 | /* Reserved [31:20] */ | |
| 6e4f574b | 474 | #define FLD_DIF_RPT_VARIANCE 0x000fffff |
| e0d3bafd SD |
475 | |
| 476 | /*****************************************************************************/ | |
| 6e4f574b | 477 | #define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) |
| e0d3bafd SD |
478 | /*****************************************************************************/ |
| 479 | /* Reserved [31:8] */ | |
| 480 | #define FLD_DIF_DIF_SOFT_RST 0x00000080 | |
| 481 | #define FLD_DIF_DIF_REG_RST_MSK 0x00000040 | |
| 482 | #define FLD_DIF_AGC_RST_MSK 0x00000020 | |
| 483 | #define FLD_DIF_CMP_RST_MSK 0x00000010 | |
| 484 | #define FLD_DIF_AVS_RST_MSK 0x00000008 | |
| 485 | #define FLD_DIF_NYQ_RST_MSK 0x00000004 | |
| 486 | #define FLD_DIF_DIF_SRC_RST_MSK 0x00000002 | |
| 487 | #define FLD_DIF_PLL_RST_MSK 0x00000001 | |
| 488 | ||
| 489 | /*****************************************************************************/ | |
| 6e4f574b | 490 | #define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c) |
| e0d3bafd SD |
491 | /*****************************************************************************/ |
| 492 | /* Reserved [31:25] */ | |
| 6e4f574b | 493 | #define FLD_DIF_CTL_IP 0x01ffffff |
| e0d3bafd | 494 | |
| e0d3bafd | 495 | #endif |