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[linux-2.6-block.git] / drivers / media / video / cx231xx / cx231xx-avcore.c
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e0d3bafd 1/*
cde4362f
MCC		 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
e0d3bafd
SD		 4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#include <linux/init.h>
26#include <linux/list.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/bitmap.h>
30#include <linux/usb.h>
31#include <linux/i2c.h>
e0d3bafd
SD		 32#include <linux/mm.h>
33#include <linux/mutex.h>
34
35#include <media/v4l2-common.h>
36#include <media/v4l2-ioctl.h>
37#include <media/v4l2-chip-ident.h>
38
39#include "cx231xx.h"
40
cde4362f 41/******************************************************************************
ecc67d10
SD		 42 -: BLOCK ARRANGEMENT :-
43 I2S block ----------------------|
44 [I2S audio] |
45 |
46 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
47 [video & audio] | [Audio]
48 |
49 |-> Cx25840 --> Video
50 [Video]
51
52*******************************************************************************/
53
54/******************************************************************************
55 * A F E - B L O C K C O N T R O L functions *
56 * [ANALOG FRONT END] *
6e4f574b 57 ******************************************************************************/
ecc67d10
SD		 58static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
59{
60 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
61 saddr, 2, data, 1);
62}
63
64static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
65{
66 int status;
67 u32 temp = 0;
68
69 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
70 saddr, 2, &temp, 1);
71 *data = (u8) temp;
72 return status;
73}
74
75int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
e0d3bafd 76{
84b5dbf3
MCC		 77 int status = 0;
78 u8 temp = 0;
ecc67d10 79 u8 afe_power_status = 0;
84b5dbf3
MCC		 80 int i = 0;
81
82 /* super block initialize */
83 temp = (u8) (ref_count & 0xff);
ecc67d10 84 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
6e4f574b
SD		 85 if (status < 0)
86 return status;
84b5dbf3 87
ecc67d10 88 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
6e4f574b
SD		 89 if (status < 0)
90 return status;
84b5dbf3
MCC		 91
92 temp = (u8) ((ref_count & 0x300) >> 8);
93 temp |= 0x40;
ecc67d10 94 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
6e4f574b
SD		 95 if (status < 0)
96 return status;
97
ecc67d10 98 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
6e4f574b
SD		 99 if (status < 0)
100 return status;
84b5dbf3
MCC		 101
102 /* enable pll */
ecc67d10
SD		 103 while (afe_power_status != 0x18) {
104 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
6e4f574b
SD		 105 if (status < 0) {
106 cx231xx_info(
107 ": Init Super Block failed in send cmd\n");
108 break;
109 }
110
ecc67d10
SD		 111 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
112 afe_power_status &= 0xff;
84b5dbf3 113 if (status < 0) {
b9255176 114 cx231xx_info(
6e4f574b 115 ": Init Super Block failed in receive cmd\n");
84b5dbf3
MCC		 116 break;
117 }
118 i++;
119 if (i == 10) {
b9255176
SD		 120 cx231xx_info(
121 ": Init Super Block force break in loop !!!!\n");
84b5dbf3
MCC		 122 status = -1;
123 break;
124 }
125 }
126
127 if (status < 0)
128 return status;
129
130 /* start tuning filter */
ecc67d10 131 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
6e4f574b
SD		 132 if (status < 0)
133 return status;
134
84b5dbf3
MCC		 135 msleep(5);
136
137 /* exit tuning */
ecc67d10 138 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
84b5dbf3
MCC		 139
140 return status;
e0d3bafd
SD		 141}
142
ecc67d10 143int cx231xx_afe_init_channels(struct cx231xx *dev)
e0d3bafd 144{
84b5dbf3
MCC		 145 int status = 0;
146
147 /* power up all 3 channels, clear pd_buffer */
ecc67d10
SD		 148 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
149 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
150 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
84b5dbf3
MCC		 151
152 /* Enable quantizer calibration */
ecc67d10 153 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
84b5dbf3
MCC		 154
155 /* channel initialize, force modulator (fb) reset */
ecc67d10
SD		 156 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
157 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
158 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
84b5dbf3
MCC		 159
160 /* start quantilizer calibration */
ecc67d10
SD		 161 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
162 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
163 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
84b5dbf3
MCC		 164 msleep(5);
165
166 /* exit modulator (fb) reset */
ecc67d10
SD		 167 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
168 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
169 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
84b5dbf3
MCC		 170
171 /* enable the pre_clamp in each channel for single-ended input */
ecc67d10
SD		 172 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
173 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
174 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
84b5dbf3
MCC		 175
176 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
ecc67d10 177 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
84b5dbf3 178 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
ecc67d10 179 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
84b5dbf3 180 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
ecc67d10 181 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
84b5dbf3
MCC		 182 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
183
184 /* dynamic element matching off */
ecc67d10
SD		 185 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
186 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
187 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
84b5dbf3
MCC		 188
189 return status;
e0d3bafd
SD		 190}
191
ecc67d10 192int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
e0d3bafd 193{
ecc67d10 194 u8 c_value = 0;
84b5dbf3 195 int status = 0;
e0d3bafd 196
ecc67d10 197 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
84b5dbf3 198 c_value &= (~(0x50));
ecc67d10 199 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
e0d3bafd 200
84b5dbf3 201 return status;
e0d3bafd
SD		 202}
203
204/*
6e4f574b
SD		 205 The Analog Front End in Cx231xx has 3 channels. These
206 channels are used to share between different inputs
207 like tuner, s-video and composite inputs.
208
e0d3bafd
SD		 209 channel 1 ----- pin 1 to pin4(in reg is 1-4)
210 channel 2 ----- pin 5 to pin8(in reg is 5-8)
211 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
212*/
ecc67d10 213int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
e0d3bafd 214{
84b5dbf3
MCC		 215 u8 ch1_setting = (u8) input_mux;
216 u8 ch2_setting = (u8) (input_mux >> 8);
217 u8 ch3_setting = (u8) (input_mux >> 16);
218 int status = 0;
ecc67d10 219 u8 value = 0;
84b5dbf3
MCC		 220
221 if (ch1_setting != 0) {
ecc67d10 222 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
84b5dbf3
MCC		 223 value &= (!INPUT_SEL_MASK);
224 value |= (ch1_setting - 1) << 4;
225 value &= 0xff;
ecc67d10 226 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
84b5dbf3
MCC		 227 }
228
229 if (ch2_setting != 0) {
ecc67d10 230 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
84b5dbf3
MCC		 231 value &= (!INPUT_SEL_MASK);
232 value |= (ch2_setting - 1) << 4;
233 value &= 0xff;
ecc67d10 234 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
84b5dbf3
MCC		 235 }
236
cde4362f
MCC		 237 /* For ch3_setting, the value to put in the register is
238 7 less than the input number */
84b5dbf3 239 if (ch3_setting != 0) {
ecc67d10 240 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
84b5dbf3
MCC		 241 value &= (!INPUT_SEL_MASK);
242 value |= (ch3_setting - 1) << 4;
243 value &= 0xff;
ecc67d10 244 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
84b5dbf3
MCC		 245 }
246
247 return status;
e0d3bafd
SD		 248}
249
ecc67d10 250int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
e0d3bafd 251{
84b5dbf3
MCC		 252 int status = 0;
253
6e4f574b
SD		 254 /*
255 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
256 * Currently, only baseband works.
257 */
258
84b5dbf3
MCC		 259 switch (mode) {
260 case AFE_MODE_LOW_IF:
261 /* SetupAFEforLowIF(); */
262 break;
263 case AFE_MODE_BASEBAND:
ecc67d10 264 status = cx231xx_afe_setup_AFE_for_baseband(dev);
84b5dbf3
MCC		 265 break;
266 case AFE_MODE_EU_HI_IF:
267 /* SetupAFEforEuHiIF(); */
268 break;
269 case AFE_MODE_US_HI_IF:
270 /* SetupAFEforUsHiIF(); */
271 break;
272 case AFE_MODE_JAPAN_HI_IF:
273 /* SetupAFEforJapanHiIF(); */
274 break;
275 }
276
ecc67d10 277 if ((mode != dev->afe_mode) &&
b9255176 278 (dev->video_input == CX231XX_VMUX_TELEVISION))
ecc67d10 279 status = cx231xx_afe_adjust_ref_count(dev,
84b5dbf3 280 CX231XX_VMUX_TELEVISION);
84b5dbf3 281
ecc67d10 282 dev->afe_mode = mode;
84b5dbf3
MCC		 283
284 return status;
e0d3bafd
SD		 285}
286
ecc67d10 287int cx231xx_afe_update_power_control(struct cx231xx *dev,
6e4f574b 288 enum AV_MODE avmode)
e0d3bafd 289{
ecc67d10 290 u8 afe_power_status = 0;
84b5dbf3
MCC		 291 int status = 0;
292
293 switch (dev->model) {
294 case CX231XX_BOARD_CNXT_RDE_250:
295 case CX231XX_BOARD_CNXT_RDU_250:
84b5dbf3 296 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
ecc67d10 297 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 298 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 299 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 300 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 301 FLD_PWRDN_ENABLE_PLL);
302 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
303 &afe_power_status);
84b5dbf3
MCC		 304 if (status < 0)
305 break;
306 }
307
ecc67d10
SD		 308 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
309 0x00);
310 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
311 0x00);
312 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
313 0x00);
84b5dbf3 314 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
ecc67d10
SD		 315 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
316 0x70);
317 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
318 0x70);
319 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
320 0x70);
321
322 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
323 &afe_power_status);
324 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
6e4f574b
SD		 325 FLD_PWRDN_PD_BIAS |
326 FLD_PWRDN_PD_TUNECK;
ecc67d10
SD		 327 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
328 afe_power_status);
84b5dbf3 329 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
ecc67d10 330 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 331 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 332 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 333 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 334 FLD_PWRDN_ENABLE_PLL);
335 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
336 &afe_power_status);
84b5dbf3
MCC		 337 if (status < 0)
338 break;
339 }
340
ecc67d10
SD		 341 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
342 0x00);
343 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
344 0x00);
345 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
346 0x00);
84b5dbf3
MCC		 347 } else {
348 cx231xx_info("Invalid AV mode input\n");
349 status = -1;
350 }
351 break;
352 default:
353 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
ecc67d10 354 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 355 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 356 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 357 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 358 FLD_PWRDN_ENABLE_PLL);
359 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
360 &afe_power_status);
84b5dbf3
MCC		 361 if (status < 0)
362 break;
363 }
364
ecc67d10
SD		 365 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
366 0x40);
367 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
368 0x40);
369 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
370 0x00);
84b5dbf3 371 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
ecc67d10
SD		 372 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
373 0x70);
374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
375 0x70);
376 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
377 0x70);
378
379 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
380 &afe_power_status);
381 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
6e4f574b
SD		 382 FLD_PWRDN_PD_BIAS |
383 FLD_PWRDN_PD_TUNECK;
ecc67d10
SD		 384 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
385 afe_power_status);
84b5dbf3 386 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
ecc67d10 387 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 388 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 389 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 390 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 391 FLD_PWRDN_ENABLE_PLL);
392 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
393 &afe_power_status);
84b5dbf3
MCC		 394 if (status < 0)
395 break;
396 }
397
ecc67d10
SD		 398 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
399 0x00);
400 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
401 0x00);
402 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
403 0x40);
84b5dbf3
MCC		 404 } else {
405 cx231xx_info("Invalid AV mode input\n");
406 status = -1;
407 }
408 } /* switch */
409
410 return status;
e0d3bafd
SD		 411}
412
ecc67d10 413int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
e0d3bafd 414{
ecc67d10
SD		 415 u8 input_mode = 0;
416 u8 ntf_mode = 0;
84b5dbf3
MCC		 417 int status = 0;
418
419 dev->video_input = video_input;
420
421 if (video_input == CX231XX_VMUX_TELEVISION) {
ecc67d10
SD		 422 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
423 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
424 &ntf_mode);
84b5dbf3 425 } else {
ecc67d10
SD		 426 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
427 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
428 &ntf_mode);
84b5dbf3 429 }
e0d3bafd 430
84b5dbf3
MCC		 431 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
432
433 switch (input_mode) {
434 case SINGLE_ENDED:
ecc67d10 435 dev->afe_ref_count = 0x23C;
84b5dbf3
MCC		 436 break;
437 case LOW_IF:
ecc67d10 438 dev->afe_ref_count = 0x24C;
84b5dbf3
MCC		 439 break;
440 case EU_IF:
ecc67d10 441 dev->afe_ref_count = 0x258;
84b5dbf3
MCC		 442 break;
443 case US_IF:
ecc67d10 444 dev->afe_ref_count = 0x260;
84b5dbf3
MCC		 445 break;
446 default:
447 break;
448 }
449
ecc67d10 450 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
e0d3bafd 451
84b5dbf3
MCC		 452 return status;
453}
e0d3bafd 454
cde4362f
MCC		 455/******************************************************************************
456 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
6e4f574b 457 ******************************************************************************/
ecc67d10
SD		 458static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
459{
460 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
461 saddr, 2, data, 1);
462}
463
464static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
465{
466 int status;
467 u32 temp = 0;
468
469 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
470 saddr, 2, &temp, 1);
471 *data = (u8) temp;
472 return status;
473}
474
475static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
476{
477 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
478 saddr, 2, data, 4);
479}
480
481static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
482{
483 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
484 saddr, 2, data, 4);
485}
486
e0d3bafd
SD		 487int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
488{
84b5dbf3
MCC		 489 int status = 0;
490
491 switch (INPUT(input)->type) {
492 case CX231XX_VMUX_COMPOSITE1:
493 case CX231XX_VMUX_SVIDEO:
494 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
495 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
cde4362f
MCC		 496 /* External AV */
497 status = cx231xx_set_power_mode(dev,
498 POLARIS_AVMODE_ENXTERNAL_AV);
84b5dbf3 499 if (status < 0) {
b9255176
SD		 500 cx231xx_errdev("%s: set_power_mode : Failed to"
501 " set Power - errCode [%d]!\n",
502 __func__, status);
84b5dbf3
MCC		 503 return status;
504 }
505 }
cde4362f
MCC		 506 status = cx231xx_set_decoder_video_input(dev,
507 INPUT(input)->type,
508 INPUT(input)->vmux);
84b5dbf3
MCC		 509 break;
510 case CX231XX_VMUX_TELEVISION:
511 case CX231XX_VMUX_CABLE:
512 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
513 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
cde4362f
MCC		 514 /* Tuner */
515 status = cx231xx_set_power_mode(dev,
516 POLARIS_AVMODE_ANALOGT_TV);
84b5dbf3 517 if (status < 0) {
b9255176
SD		 518 cx231xx_errdev("%s: set_power_mode:Failed"
519 " to set Power - errCode [%d]!\n",
520 __func__, status);
84b5dbf3
MCC		 521 return status;
522 }
523 }
cde4362f
MCC		 524 status = cx231xx_set_decoder_video_input(dev,
525 CX231XX_VMUX_COMPOSITE1,
526 INPUT(input)->vmux);
84b5dbf3
MCC		 527 break;
528 default:
b9255176 529 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
84b5dbf3
MCC		 530 __func__, INPUT(input)->type);
531 break;
532 }
533
534 /* save the selection */
535 dev->video_input = input;
536
537 return status;
e0d3bafd
SD		 538}
539
b9255176
SD		 540int cx231xx_set_decoder_video_input(struct cx231xx *dev,
541 u8 pin_type, u8 input)
e0d3bafd 542{
84b5dbf3
MCC		 543 int status = 0;
544 u32 value = 0;
545
546 if (pin_type != dev->video_input) {
ecc67d10 547 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
84b5dbf3 548 if (status < 0) {
b9255176 549 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
ecc67d10 550 "AFE input mux - errCode [%d]!\n",
b9255176 551 __func__, status);
84b5dbf3
MCC		 552 return status;
553 }
554 }
e0d3bafd 555
ecc67d10
SD		 556 /* call afe block to set video inputs */
557 status = cx231xx_afe_set_input_mux(dev, input);
84b5dbf3 558 if (status < 0) {
b9255176 559 cx231xx_errdev("%s: set_input_mux :Failed to set"
ecc67d10 560 " AFE input mux - errCode [%d]!\n",
b9255176 561 __func__, status);
84b5dbf3
MCC		 562 return status;
563 }
564
565 switch (pin_type) {
566 case CX231XX_VMUX_COMPOSITE1:
ecc67d10 567 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f
MCC		 568 value |= (0 << 13) | (1 << 4);
569 value &= ~(1 << 5);
570
b9255176
SD		 571 /* set [24:23] [22:15] to 0 */
572 value &= (~(0x1ff8000));
573 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
574 value |= 0x1000000;
ecc67d10 575 status = vid_blk_write_word(dev, AFE_CTRL, value);
cde4362f 576
ecc67d10 577 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
cde4362f 578 value |= (1 << 7);
ecc67d10 579 status = vid_blk_write_word(dev, OUT_CTRL1, value);
cde4362f
MCC		 580
581 /* Set vip 1.1 output mode */
582 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 583 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 584 OUT_CTRL1,
585 FLD_OUT_MODE,
586 OUT_MODE_VIP11);
587
588 /* Tell DIF object to go to baseband mode */
589 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
590 if (status < 0) {
b9255176
SD		 591 cx231xx_errdev("%s: cx231xx_dif set to By pass"
592 " mode- errCode [%d]!\n",
cde4362f
MCC		 593 __func__, status);
594 return status;
595 }
596
597 /* Read the DFE_CTRL1 register */
ecc67d10 598 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
cde4362f
MCC		 599
600 /* enable the VBI_GATE_EN */
601 value |= FLD_VBI_GATE_EN;
602
603 /* Enable the auto-VGA enable */
604 value |= FLD_VGA_AUTO_EN;
605
606 /* Write it back */
ecc67d10 607 status = vid_blk_write_word(dev, DFE_CTRL1, value);
cde4362f
MCC		 608
609 /* Disable auto config of registers */
610 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 611 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 612 MODE_CTRL, FLD_ACFG_DIS,
613 cx231xx_set_field(FLD_ACFG_DIS, 1));
614
615 /* Set CVBS input mode */
616 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 617 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 618 MODE_CTRL, FLD_INPUT_MODE,
619 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
620 break;
621 case CX231XX_VMUX_SVIDEO:
622 /* Disable the use of DIF */
623
ecc67d10 624 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f 625
b9255176
SD		 626 /* set [24:23] [22:15] to 0 */
627 value &= (~(0x1ff8000));
628 /* set FUNC_MODE[24:23] = 2
629 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
630 value |= 0x1000010;
ecc67d10 631 status = vid_blk_write_word(dev, AFE_CTRL, value);
cde4362f
MCC		 632
633 /* Tell DIF object to go to baseband mode */
634 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
635 if (status < 0) {
b9255176
SD		 636 cx231xx_errdev("%s: cx231xx_dif set to By pass"
637 " mode- errCode [%d]!\n",
cde4362f
MCC		 638 __func__, status);
639 return status;
640 }
641
642 /* Read the DFE_CTRL1 register */
ecc67d10 643 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
cde4362f
MCC		 644
645 /* enable the VBI_GATE_EN */
646 value |= FLD_VBI_GATE_EN;
647
648 /* Enable the auto-VGA enable */
649 value |= FLD_VGA_AUTO_EN;
650
651 /* Write it back */
ecc67d10 652 status = vid_blk_write_word(dev, DFE_CTRL1, value);
cde4362f
MCC		 653
654 /* Disable auto config of registers */
655 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 656 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 657 MODE_CTRL, FLD_ACFG_DIS,
658 cx231xx_set_field(FLD_ACFG_DIS, 1));
659
660 /* Set YC input mode */
661 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 662 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 663 MODE_CTRL,
664 FLD_INPUT_MODE,
665 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
666
667 /* Chroma to ADC2 */
ecc67d10 668 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f
MCC		 669 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
670
671 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
672 This sets them to use video
673 rather than audio. Only one of the two will be in use. */
674 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
675
ecc67d10 676 status = vid_blk_write_word(dev, AFE_CTRL, value);
cde4362f 677
ecc67d10 678 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
cde4362f
MCC		 679 break;
680 case CX231XX_VMUX_TELEVISION:
681 case CX231XX_VMUX_CABLE:
682 default:
683 switch (dev->model) {
684 case CX231XX_BOARD_CNXT_RDE_250:
685 case CX231XX_BOARD_CNXT_RDU_250:
686 /* Disable the use of DIF */
687
ecc67d10 688 status = vid_blk_read_word(dev, AFE_CTRL, &value);
84b5dbf3
MCC		 689 value |= (0 << 13) | (1 << 4);
690 value &= ~(1 << 5);
691
b9255176
SD		 692 /* set [24:23] [22:15] to 0 */
693 value &= (~(0x1FF8000));
694 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
695 value |= 0x1000000;
ecc67d10
SD		 696 status = vid_blk_write_word(dev, AFE_CTRL, value);
697
698 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
84b5dbf3 699 value |= (1 << 7);
ecc67d10 700 status = vid_blk_write_word(dev, OUT_CTRL1, value);
84b5dbf3
MCC		 701
702 /* Set vip 1.1 output mode */
cde4362f 703 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 704 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 705 OUT_CTRL1, FLD_OUT_MODE,
706 OUT_MODE_VIP11);
84b5dbf3 707
cde4362f
MCC		 708 /* Tell DIF object to go to baseband mode */
709 status = cx231xx_dif_set_standard(dev,
710 DIF_USE_BASEBAND);
84b5dbf3 711 if (status < 0) {
b9255176
SD		 712 cx231xx_errdev("%s: cx231xx_dif set to By pass"
713 " mode- errCode [%d]!\n",
714 __func__, status);
84b5dbf3
MCC		 715 return status;
716 }
717
718 /* Read the DFE_CTRL1 register */
ecc67d10 719 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
84b5dbf3
MCC		 720
721 /* enable the VBI_GATE_EN */
722 value |= FLD_VBI_GATE_EN;
723
724 /* Enable the auto-VGA enable */
725 value |= FLD_VGA_AUTO_EN;
726
727 /* Write it back */
ecc67d10 728 status = vid_blk_write_word(dev, DFE_CTRL1, value);
84b5dbf3
MCC		 729
730 /* Disable auto config of registers */
cde4362f 731 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 732 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 733 MODE_CTRL, FLD_ACFG_DIS,
734 cx231xx_set_field(FLD_ACFG_DIS, 1));
84b5dbf3
MCC		 735
736 /* Set CVBS input mode */
cde4362f 737 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 738 VID_BLK_I2C_ADDRESS,
cde4362f 739 MODE_CTRL, FLD_INPUT_MODE,
b9255176
SD		 740 cx231xx_set_field(FLD_INPUT_MODE,
741 INPUT_MODE_CVBS_0));
cde4362f
MCC		 742 break;
743 default:
744 /* Enable the DIF for the tuner */
84b5dbf3 745
cde4362f
MCC		 746 /* Reinitialize the DIF */
747 status = cx231xx_dif_set_standard(dev, dev->norm);
84b5dbf3 748 if (status < 0) {
b9255176
SD		 749 cx231xx_errdev("%s: cx231xx_dif set to By pass"
750 " mode- errCode [%d]!\n",
751 __func__, status);
84b5dbf3
MCC		 752 return status;
753 }
754
cde4362f 755 /* Make sure bypass is cleared */
ecc67d10 756 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
cde4362f
MCC		 757
758 /* Clear the bypass bit */
759 value &= ~FLD_DIF_DIF_BYPASS;
760
761 /* Enable the use of the DIF block */
ecc67d10 762 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
cde4362f 763
84b5dbf3 764 /* Read the DFE_CTRL1 register */
ecc67d10 765 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
84b5dbf3 766
cde4362f
MCC		 767 /* Disable the VBI_GATE_EN */
768 value &= ~FLD_VBI_GATE_EN;
84b5dbf3 769
cde4362f
MCC		 770 /* Enable the auto-VGA enable, AGC, and
771 set the skip count to 2 */
772 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
84b5dbf3
MCC		 773
774 /* Write it back */
ecc67d10 775 status = vid_blk_write_word(dev, DFE_CTRL1, value);
84b5dbf3 776
6e4f574b 777 /* Wait until AGC locks up */
cde4362f 778 msleep(1);
84b5dbf3 779
cde4362f
MCC		 780 /* Disable the auto-VGA enable AGC */
781 value &= ~(FLD_VGA_AUTO_EN);
84b5dbf3 782
cde4362f 783 /* Write it back */
ecc67d10 784 status = vid_blk_write_word(dev, DFE_CTRL1, value);
84b5dbf3 785
cde4362f 786 /* Enable Polaris B0 AGC output */
ecc67d10 787 status = vid_blk_read_word(dev, PIN_CTRL, &value);
cde4362f
MCC		 788 value |= (FLD_OEF_AGC_RF) |
789 (FLD_OEF_AGC_IFVGA) |
790 (FLD_OEF_AGC_IF);
ecc67d10 791 status = vid_blk_write_word(dev, PIN_CTRL, value);
cde4362f
MCC		 792
793 /* Set vip 1.1 output mode */
794 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 795 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 796 OUT_CTRL1, FLD_OUT_MODE,
797 OUT_MODE_VIP11);
798
799 /* Disable auto config of registers */
800 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 801 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 802 MODE_CTRL, FLD_ACFG_DIS,
803 cx231xx_set_field(FLD_ACFG_DIS, 1));
804
805 /* Set CVBS input mode */
806 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 807 VID_BLK_I2C_ADDRESS,
cde4362f 808 MODE_CTRL, FLD_INPUT_MODE,
b9255176
SD		 809 cx231xx_set_field(FLD_INPUT_MODE,
810 INPUT_MODE_CVBS_0));
cde4362f 811
b9255176
SD		 812 /* Set some bits in AFE_CTRL so that channel 2 or 3
813 * is ready to receive audio */
cde4362f
MCC		 814 /* Clear clamp for channels 2 and 3 (bit 16-17) */
815 /* Clear droop comp (bit 19-20) */
816 /* Set VGA_SEL (for audio control) (bit 7-8) */
ecc67d10 817 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f
MCC		 818
819 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
820
ecc67d10 821 status = vid_blk_write_word(dev, AFE_CTRL, value);
cde4362f 822 break;
84b5dbf3 823
84b5dbf3
MCC		 824 }
825 break;
826 }
827
828 /* Set raw VBI mode */
cde4362f 829 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 830 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 831 OUT_CTRL1, FLD_VBIHACTRAW_EN,
832 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
84b5dbf3 833
ecc67d10 834 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
84b5dbf3
MCC		 835 if (value & 0x02) {
836 value |= (1 << 19);
ecc67d10 837 status = vid_blk_write_word(dev, OUT_CTRL1, value);
84b5dbf3
MCC		 838 }
839
840 return status;
e0d3bafd
SD		 841}
842
843/*
b9255176
SD		 844 * Handle any video-mode specific overrides that are different
845 * on a per video standards basis after touching the MODE_CTRL
846 * register which resets many values for autodetect
e0d3bafd
SD		 847 */
848int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
849{
84b5dbf3
MCC		 850 int status = 0;
851
852 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
853 (unsigned int)dev->norm);
854
855 /* Change the DFE_CTRL3 bp_percent to fix flagging */
ecc67d10 856 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
84b5dbf3 857
6e4f574b 858 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
84b5dbf3
MCC		 859 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
860
cde4362f
MCC		 861 /* Move the close caption lines out of active video,
862 adjust the active video start point */
863 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 864 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 865 VERT_TIM_CTRL,
866 FLD_VBLANK_CNT, 0x18);
cde4362f 867 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 868 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 869 VERT_TIM_CTRL,
870 FLD_VACTIVE_CNT,
871 0x1E6000);
cde4362f 872 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 873 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 874 VERT_TIM_CTRL,
875 FLD_V656BLANK_CNT,
876 0x1E000000);
877
cde4362f 878 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 879 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 880 HORIZ_TIM_CTRL,
881 FLD_HBLANK_CNT,
882 cx231xx_set_field
883 (FLD_HBLANK_CNT, 0x79));
6e4f574b
SD		 884 } else if (dev->norm & V4L2_STD_SECAM) {
885 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
886 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 887 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 888 VERT_TIM_CTRL,
889 FLD_VBLANK_CNT, 0x24);
890 /* Adjust the active video horizontal start point */
cde4362f 891 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 892 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 893 HORIZ_TIM_CTRL,
894 FLD_HBLANK_CNT,
895 cx231xx_set_field
896 (FLD_HBLANK_CNT, 0x85));
6e4f574b
SD		 897 } else {
898 cx231xx_info("do_mode_ctrl_overrides PAL\n");
899 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 900 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 901 VERT_TIM_CTRL,
902 FLD_VBLANK_CNT, 0x24);
903 /* Adjust the active video horizontal start point */
cde4362f 904 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 905 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 906 HORIZ_TIM_CTRL,
907 FLD_HBLANK_CNT,
908 cx231xx_set_field
909 (FLD_HBLANK_CNT, 0x85));
910 }
911
912 return status;
e0d3bafd
SD		 913}
914
915int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
916{
84b5dbf3
MCC		 917 int status = 0;
918 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
919
920 switch (INPUT(input)->amux) {
921 case CX231XX_AMUX_VIDEO:
922 ainput = AUDIO_INPUT_TUNER_TV;
923 break;
924 case CX231XX_AMUX_LINE_IN:
ecc67d10 925 status = cx231xx_i2s_blk_set_audio_input(dev, input);
84b5dbf3
MCC		 926 ainput = AUDIO_INPUT_LINE;
927 break;
928 default:
929 break;
930 }
931
932 status = cx231xx_set_audio_decoder_input(dev, ainput);
933
934 return status;
e0d3bafd
SD		 935}
936
84b5dbf3
MCC		 937int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
938 enum AUDIO_INPUT audio_input)
e0d3bafd 939{
84b5dbf3
MCC		 940 u32 dwval;
941 int status;
ecc67d10 942 u8 gen_ctrl;
84b5dbf3
MCC		 943 u32 value = 0;
944
945 /* Put it in soft reset */
ecc67d10 946 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
84b5dbf3 947 gen_ctrl |= 1;
ecc67d10 948 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
84b5dbf3
MCC		 949
950 switch (audio_input) {
951 case AUDIO_INPUT_LINE:
84b5dbf3 952 /* setup AUD_IO control from Merlin paralle output */
cde4362f
MCC		 953 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
954 AUD_CHAN_SRC_PARALLEL);
ecc67d10 955 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
84b5dbf3
MCC		 956
957 /* setup input to Merlin, SRC2 connect to AC97
958 bypass upsample-by-2, slave mode, sony mode, left justify
959 adr 091c, dat 01000000 */
ecc67d10 960 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
84b5dbf3 961
ecc67d10
SD		 962 status = vid_blk_write_word(dev, AC97_CTL,
963 (dwval | FLD_AC97_UP2X_BYPASS));
84b5dbf3
MCC		 964
965 /* select the parallel1 and SRC3 */
ecc67d10 966 status = vid_blk_write_word(dev, BAND_OUT_SEL,
cde4362f
MCC		 967 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
968 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
ecc67d10 969 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
84b5dbf3
MCC		 970
971 /* unmute all, AC97 in, independence mode
972 adr 08d0, data 0x00063073 */
ecc67d10 973 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
84b5dbf3
MCC		 974
975 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
ecc67d10
SD		 976 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
977 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
978 (dwval | FLD_PATH1_AVC_THRESHOLD));
84b5dbf3
MCC		 979
980 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
ecc67d10
SD		 981 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
982 status = vid_blk_write_word(dev, PATH1_SC_CTL,
983 (dwval | FLD_PATH1_SC_THRESHOLD));
84b5dbf3
MCC		 984 break;
985
986 case AUDIO_INPUT_TUNER_TV:
987 default:
988
989 /* Setup SRC sources and clocks */
ecc67d10 990 status = vid_blk_write_word(dev, BAND_OUT_SEL,
cde4362f
MCC		 991 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
992 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
993 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
994 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
995 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
996 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
997 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
998 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
999 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1000 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1001 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1002 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
ecc67d10 1003 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
84b5dbf3
MCC		 1004
1005 /* Setup the AUD_IO control */
ecc67d10 1006 status = vid_blk_write_word(dev, AUD_IO_CTRL,
cde4362f
MCC		 1007 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1008 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1009 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1010 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
ecc67d10 1011 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
84b5dbf3 1012
ecc67d10 1013 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
84b5dbf3
MCC		 1014
1015 /* setAudioStandard(_audio_standard); */
1016
ecc67d10 1017 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
84b5dbf3
MCC		 1018 switch (dev->model) {
1019 case CX231XX_BOARD_CNXT_RDE_250:
1020 case CX231XX_BOARD_CNXT_RDU_250:
cde4362f 1021 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 1022 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 1023 CHIP_CTRL,
1024 FLD_SIF_EN,
1025 cx231xx_set_field(FLD_SIF_EN, 1));
84b5dbf3
MCC		 1026 break;
1027 default:
1028 break;
1029 }
1030 break;
1031
1032 case AUDIO_INPUT_TUNER_FM:
1033 /* use SIF for FM radio
1034 setupFM();
1035 setAudioStandard(_audio_standard);
1036 */
1037 break;
1038
1039 case AUDIO_INPUT_MUTE:
ecc67d10 1040 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
84b5dbf3
MCC		 1041 break;
1042 }
e0d3bafd 1043
84b5dbf3 1044 /* Take it out of soft reset */
ecc67d10 1045 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
84b5dbf3 1046 gen_ctrl &= ~1;
ecc67d10 1047 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
e0d3bafd 1048
84b5dbf3
MCC		 1049 return status;
1050}
e0d3bafd
SD		 1051
1052/* Set resolution of the video */
1053int cx231xx_resolution_set(struct cx231xx *dev)
1054{
84b5dbf3 1055 /* set horzontal scale */
1ca27379
TP		 1056 int status = vid_blk_write_word(dev, HSCALE_CTRL, dev->hscale);
1057 if (status)
1058 return status;
e0d3bafd 1059
84b5dbf3 1060 /* set vertical scale */
1ca27379 1061 return vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale);
e0d3bafd
SD		 1062}
1063
cde4362f
MCC		 1064/******************************************************************************
1065 * C H I P Specific C O N T R O L functions *
1066 ******************************************************************************/
e0d3bafd
SD		 1067int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1068{
84b5dbf3
MCC		 1069 u32 value;
1070 int status = 0;
e0d3bafd 1071
ecc67d10 1072 status = vid_blk_read_word(dev, PIN_CTRL, &value);
84b5dbf3 1073 value |= (~dev->board.ctl_pin_status_mask);
ecc67d10 1074 status = vid_blk_write_word(dev, PIN_CTRL, value);
e0d3bafd 1075
84b5dbf3 1076 return status;
e0d3bafd
SD		 1077}
1078
84b5dbf3
MCC		 1079int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1080 u8 analog_or_digital)
e0d3bafd 1081{
84b5dbf3 1082 int status = 0;
e0d3bafd 1083
84b5dbf3 1084 /* first set the direction to output */
cde4362f
MCC		 1085 status = cx231xx_set_gpio_direction(dev,
1086 dev->board.
1087 agc_analog_digital_select_gpio, 1);
e0d3bafd 1088
84b5dbf3 1089 /* 0 - demod ; 1 - Analog mode */
cde4362f 1090 status = cx231xx_set_gpio_value(dev,
84b5dbf3
MCC		 1091 dev->board.agc_analog_digital_select_gpio,
1092 analog_or_digital);
e0d3bafd 1093
84b5dbf3 1094 return status;
e0d3bafd
SD		 1095}
1096
1097int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1098{
84b5dbf3
MCC		 1099 u8 value[4] = { 0, 0, 0, 0 };
1100 int status = 0;
e0d3bafd 1101
84b5dbf3 1102 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
e0d3bafd 1103
cde4362f
MCC		 1104 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1105 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1106 if (status < 0)
1107 return status;
e0d3bafd 1108
84b5dbf3
MCC		 1109 if (I2CIndex == I2C_1) {
1110 if (value[0] & I2C_DEMOD_EN) {
1111 value[0] &= ~I2C_DEMOD_EN;
cde4362f 1112 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
84b5dbf3
MCC		 1113 PWR_CTL_EN, value, 4);
1114 }
1115 } else {
1116 if (!(value[0] & I2C_DEMOD_EN)) {
1117 value[0] |= I2C_DEMOD_EN;
cde4362f 1118 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
84b5dbf3
MCC		 1119 PWR_CTL_EN, value, 4);
1120 }
1121 }
e0d3bafd 1122
84b5dbf3 1123 return status;
e0d3bafd
SD		 1124
1125}
1126
cde4362f
MCC		 1127/******************************************************************************
1128 * D I F - B L O C K C O N T R O L functions *
1129 ******************************************************************************/
e0d3bafd 1130int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
84b5dbf3 1131 u32 function_mode, u32 standard)
e0d3bafd 1132{
84b5dbf3
MCC		 1133 int status = 0;
1134
1135 if (mode == V4L2_TUNER_RADIO) {
1136 /* C2HH */
b9255176
SD		 1137 /* lo if big signal */
1138 status = cx231xx_reg_mask_write(dev,
ecc67d10 1139 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1140 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1141 /* FUNC_MODE = DIF */
1142 status = cx231xx_reg_mask_write(dev,
ecc67d10 1143 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1144 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1145 /* IF_MODE */
1146 status = cx231xx_reg_mask_write(dev,
ecc67d10 1147 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1148 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1149 /* no inv */
1150 status = cx231xx_reg_mask_write(dev,
ecc67d10 1151 VID_BLK_I2C_ADDRESS, 32,
b9255176 1152 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
6e4f574b
SD		 1153 } else if (standard != DIF_USE_BASEBAND) {
1154 if (standard & V4L2_STD_MN) {
b9255176 1155 /* lo if big signal */
cde4362f 1156 status = cx231xx_reg_mask_write(dev,
ecc67d10 1157 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1158 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1159 /* FUNC_MODE = DIF */
cde4362f 1160 status = cx231xx_reg_mask_write(dev,
ecc67d10 1161 VID_BLK_I2C_ADDRESS, 32,
cde4362f 1162 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
b9255176
SD		 1163 function_mode);
1164 /* IF_MODE */
cde4362f 1165 status = cx231xx_reg_mask_write(dev,
ecc67d10 1166 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1167 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1168 /* no inv */
cde4362f 1169 status = cx231xx_reg_mask_write(dev,
ecc67d10 1170 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1171 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1172 /* 0x124, AUD_CHAN1_SRC = 0x3 */
cde4362f 1173 status = cx231xx_reg_mask_write(dev,
ecc67d10 1174 VID_BLK_I2C_ADDRESS, 32,
b9255176 1175 AUD_IO_CTRL, 0, 31, 0x00000003);
6e4f574b
SD		 1176 } else if ((standard == V4L2_STD_PAL_I) |
1177 (standard & V4L2_STD_SECAM)) {
84b5dbf3 1178 /* C2HH setup */
b9255176 1179 /* lo if big signal */
cde4362f 1180 status = cx231xx_reg_mask_write(dev,
ecc67d10 1181 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1182 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1183 /* FUNC_MODE = DIF */
cde4362f 1184 status = cx231xx_reg_mask_write(dev,
ecc67d10 1185 VID_BLK_I2C_ADDRESS, 32,
cde4362f 1186 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
b9255176
SD		 1187 function_mode);
1188 /* IF_MODE */
cde4362f 1189 status = cx231xx_reg_mask_write(dev,
ecc67d10 1190 VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1191 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
b9255176 1192 /* no inv */
cde4362f 1193 status = cx231xx_reg_mask_write(dev,
ecc67d10 1194 VID_BLK_I2C_ADDRESS, 32,
b9255176 1195 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
6e4f574b
SD		 1196 } else {
1197 /* default PAL BG */
84b5dbf3 1198 /* C2HH setup */
b9255176 1199 /* lo if big signal */
cde4362f 1200 status = cx231xx_reg_mask_write(dev,
ecc67d10 1201 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1202 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1203 /* FUNC_MODE = DIF */
cde4362f 1204 status = cx231xx_reg_mask_write(dev,
ecc67d10 1205 VID_BLK_I2C_ADDRESS, 32,
cde4362f 1206 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
b9255176
SD		 1207 function_mode);
1208 /* IF_MODE */
cde4362f 1209 status = cx231xx_reg_mask_write(dev,
ecc67d10 1210 VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1211 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
b9255176 1212 /* no inv */
cde4362f 1213 status = cx231xx_reg_mask_write(dev,
ecc67d10 1214 VID_BLK_I2C_ADDRESS, 32,
b9255176 1215 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
84b5dbf3
MCC		 1216 }
1217 }
1218
1219 return status;
e0d3bafd
SD		 1220}
1221
1222int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1223{
84b5dbf3
MCC		 1224 int status = 0;
1225 u32 dif_misc_ctrl_value = 0;
1226 u32 func_mode = 0;
1227
1228 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1229
ecc67d10 1230 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
84b5dbf3
MCC		 1231 if (standard != DIF_USE_BASEBAND)
1232 dev->norm = standard;
1233
1234 switch (dev->model) {
1235 case CX231XX_BOARD_CNXT_RDE_250:
1236 case CX231XX_BOARD_CNXT_RDU_250:
1237 func_mode = 0x03;
1238 break;
1239 default:
1240 func_mode = 0x01;
1241 }
1242
cde4362f 1243 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
84b5dbf3
MCC		 1244 func_mode, standard);
1245
1246 if (standard == DIF_USE_BASEBAND) { /* base band */
cde4362f
MCC		 1247 /* There is a different SRC_PHASE_INC value
1248 for baseband vs. DIF */
ecc67d10
SD		 1249 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1250 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1251 &dif_misc_ctrl_value);
84b5dbf3 1252 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
ecc67d10
SD		 1253 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1254 dif_misc_ctrl_value);
84b5dbf3 1255 } else if (standard & V4L2_STD_PAL_D) {
ecc67d10 1256 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1257 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1258 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1259 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1260 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1261 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1262 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1263 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1264 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1265 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
ecc67d10 1266 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1267 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
ecc67d10 1268 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1269 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
ecc67d10 1270 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1271 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
ecc67d10 1272 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1273 DIF_AGC_IF_INT_CURRENT, 0, 31,
1274 0x26001700);
ecc67d10 1275 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1276 DIF_AGC_RF_CURRENT, 0, 31,
1277 0x00002660);
ecc67d10 1278 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1279 DIF_VIDEO_AGC_CTRL, 0, 31,
1280 0x72500800);
ecc67d10 1281 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1282 DIF_VID_AUD_OVERRIDE, 0, 31,
1283 0x27000100);
ecc67d10 1284 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1285 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
ecc67d10 1286 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1287 DIF_COMP_FLT_CTRL, 0, 31,
1288 0x00000000);
ecc67d10 1289 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1290 DIF_SRC_PHASE_INC, 0, 31,
1291 0x1befbf06);
ecc67d10 1292 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1293 DIF_SRC_GAIN_CONTROL, 0, 31,
1294 0x000035e8);
ecc67d10 1295 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1296 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1297 /* Save the Spec Inversion value */
1298 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1299 dif_misc_ctrl_value |= 0x3a023F11;
84b5dbf3 1300 } else if (standard & V4L2_STD_PAL_I) {
ecc67d10 1301 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1302 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1303 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1304 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1305 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1306 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1307 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1308 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1309 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1310 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
ecc67d10 1311 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1312 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
ecc67d10 1313 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1314 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
ecc67d10 1315 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1316 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
ecc67d10 1317 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1318 DIF_AGC_IF_INT_CURRENT, 0, 31,
1319 0x26001700);
ecc67d10 1320 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1321 DIF_AGC_RF_CURRENT, 0, 31,
1322 0x00002660);
ecc67d10 1323 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1324 DIF_VIDEO_AGC_CTRL, 0, 31,
1325 0x72500800);
ecc67d10 1326 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1327 DIF_VID_AUD_OVERRIDE, 0, 31,
1328 0x27000100);
ecc67d10 1329 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1330 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
ecc67d10 1331 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1332 DIF_COMP_FLT_CTRL, 0, 31,
1333 0x00000000);
ecc67d10 1334 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1335 DIF_SRC_PHASE_INC, 0, 31,
1336 0x1befbf06);
ecc67d10 1337 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1338 DIF_SRC_GAIN_CONTROL, 0, 31,
1339 0x000035e8);
ecc67d10 1340 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1341 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1342 /* Save the Spec Inversion value */
1343 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1344 dif_misc_ctrl_value |= 0x3a033F11;
84b5dbf3 1345 } else if (standard & V4L2_STD_PAL_M) {
84b5dbf3 1346 /* improved Low Frequency Phase Noise */
ecc67d10
SD		 1347 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1348 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1349 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1350 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1351 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1352 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1353 0x26001700);
1354 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1355 0x00002660);
1356 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1357 0x72500800);
1358 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1359 0x27000100);
1360 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1361 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1362 0x009f50c1);
1363 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1364 0x1befbf06);
1365 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1366 0x000035e8);
1367 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1368 0x00000000);
84b5dbf3
MCC		 1369 /* Save the Spec Inversion value */
1370 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1371 dif_misc_ctrl_value |= 0x3A0A3F10;
84b5dbf3 1372 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
84b5dbf3 1373 /* improved Low Frequency Phase Noise */
ecc67d10
SD		 1374 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1375 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1376 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1377 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1378 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1379 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1380 0x26001700);
1381 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1382 0x00002660);
1383 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1384 0x72500800);
1385 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1386 0x27000100);
1387 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1388 0x012c405d);
1389 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1390 0x009f50c1);
1391 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1392 0x1befbf06);
1393 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1394 0x000035e8);
1395 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1396 0x00000000);
84b5dbf3
MCC		 1397 /* Save the Spec Inversion value */
1398 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1399 dif_misc_ctrl_value = 0x3A093F10;
84b5dbf3 1400 } else if (standard &
6e4f574b
SD		 1401 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1402 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
84b5dbf3 1403
ecc67d10 1404 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1405 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1406 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1407 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1408 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1409 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1410 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1411 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1412 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1413 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
ecc67d10 1414 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1415 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
ecc67d10 1416 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1417 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
ecc67d10 1418 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1419 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
ecc67d10 1420 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1421 DIF_AGC_IF_INT_CURRENT, 0, 31,
1422 0x26001700);
ecc67d10 1423 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1424 DIF_AGC_RF_CURRENT, 0, 31,
1425 0x00002660);
ecc67d10 1426 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1427 DIF_VID_AUD_OVERRIDE, 0, 31,
1428 0x27000100);
ecc67d10 1429 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1430 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
ecc67d10 1431 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1432 DIF_COMP_FLT_CTRL, 0, 31,
1433 0x00000000);
ecc67d10 1434 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1435 DIF_SRC_PHASE_INC, 0, 31,
1436 0x1befbf06);
ecc67d10 1437 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1438 DIF_SRC_GAIN_CONTROL, 0, 31,
1439 0x000035e8);
ecc67d10 1440 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1441 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
ecc67d10 1442 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1443 DIF_VIDEO_AGC_CTRL, 0, 31,
1444 0xf4000000);
1445
1446 /* Save the Spec Inversion value */
1447 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1448 dif_misc_ctrl_value |= 0x3a023F11;
84b5dbf3 1449 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
84b5dbf3 1450 /* Is it SECAM_L1? */
ecc67d10 1451 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1452 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1453 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1454 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1455 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1456 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1457 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1458 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1459 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1460 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
ecc67d10 1461 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1462 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
ecc67d10 1463 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1464 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
ecc67d10 1465 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1466 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
ecc67d10 1467 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1468 DIF_AGC_IF_INT_CURRENT, 0, 31,
1469 0x26001700);
ecc67d10 1470 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1471 DIF_AGC_RF_CURRENT, 0, 31,
1472 0x00002660);
ecc67d10 1473 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1474 DIF_VID_AUD_OVERRIDE, 0, 31,
1475 0x27000100);
ecc67d10 1476 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1477 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
ecc67d10 1478 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1479 DIF_COMP_FLT_CTRL, 0, 31,
1480 0x00000000);
ecc67d10 1481 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1482 DIF_SRC_PHASE_INC, 0, 31,
1483 0x1befbf06);
ecc67d10 1484 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1485 DIF_SRC_GAIN_CONTROL, 0, 31,
1486 0x000035e8);
ecc67d10 1487 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1488 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
ecc67d10 1489 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1490 DIF_VIDEO_AGC_CTRL, 0, 31,
1491 0xf2560000);
1492
1493 /* Save the Spec Inversion value */
1494 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1495 dif_misc_ctrl_value |= 0x3a023F11;
1496
6e4f574b 1497 } else if (standard & V4L2_STD_NTSC_M) {
cde4362f
MCC		 1498 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1499 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
84b5dbf3 1500
cde4362f
MCC		 1501 /* For NTSC the centre frequency of video coming out of
1502 sidewinder is around 7.1MHz or 3.6MHz depending on the
1503 spectral inversion. so for a non spectrally inverted channel
1504 the pll freq word is 0x03420c49
84b5dbf3
MCC		 1505 */
1506
ecc67d10
SD		 1507 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
1508 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
1509 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
1510 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1511 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
1512 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1513 0x26001700);
1514 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1515 0x00002660);
1516 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1517 0x04000800);
1518 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1519 0x27000100);
1520 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
1521
1522 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1523 0x009f50c1);
1524 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1525 0x1befbf06);
1526 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1527 0x000035e8);
1528
1529 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
1530 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
1531 0xC2262600);
1532 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
84b5dbf3
MCC		 1533
1534 /* Save the Spec Inversion value */
1535 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1536 dif_misc_ctrl_value |= 0x3a003F10;
6e4f574b
SD		 1537 } else {
1538 /* default PAL BG */
ecc67d10 1539 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1540 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1541 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1542 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1543 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1544 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1545 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1546 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1547 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1548 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
ecc67d10 1549 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1550 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
ecc67d10 1551 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1552 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
ecc67d10 1553 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1554 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
ecc67d10 1555 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1556 DIF_AGC_IF_INT_CURRENT, 0, 31,
1557 0x26001700);
ecc67d10 1558 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1559 DIF_AGC_RF_CURRENT, 0, 31,
1560 0x00002660);
ecc67d10 1561 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1562 DIF_VIDEO_AGC_CTRL, 0, 31,
1563 0x72500800);
ecc67d10 1564 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1565 DIF_VID_AUD_OVERRIDE, 0, 31,
1566 0x27000100);
ecc67d10 1567 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1568 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
ecc67d10 1569 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1570 DIF_COMP_FLT_CTRL, 0, 31,
1571 0x00A653A8);
ecc67d10 1572 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1573 DIF_SRC_PHASE_INC, 0, 31,
1574 0x1befbf06);
ecc67d10 1575 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1576 DIF_SRC_GAIN_CONTROL, 0, 31,
1577 0x000035e8);
ecc67d10 1578 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 1579 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1580 /* Save the Spec Inversion value */
1581 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1582 dif_misc_ctrl_value |= 0x3a013F11;
84b5dbf3
MCC		 1583 }
1584
1585 /* The AGC values should be the same for all standards,
1586 AUD_SRC_SEL[19] should always be disabled */
1587 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
1588
cde4362f
MCC		 1589 /* It is still possible to get Set Standard calls even when we
1590 are in FM mode.
84b5dbf3
MCC		 1591 This is done to override the value for FM. */
1592 if (dev->active_mode == V4L2_TUNER_RADIO)
1593 dif_misc_ctrl_value = 0x7a080000;
1594
1595 /* Write the calculated value for misc ontrol register */
ecc67d10 1596 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
84b5dbf3
MCC		 1597
1598 return status;
e0d3bafd
SD		 1599}
1600
1601int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1602{
1603 int status = 0;
1604 u32 dwval;
1605
1606 /* Set the RF and IF k_agc values to 3 */
ecc67d10 1607 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
e0d3bafd
SD		 1608 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1609 dwval |= 0x33000000;
1610
ecc67d10 1611 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
e0d3bafd 1612
84b5dbf3 1613 return status;
e0d3bafd
SD		 1614}
1615
1616int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1617{
84b5dbf3 1618 int status = 0;
e0d3bafd
SD		 1619 u32 dwval;
1620
6e4f574b
SD		 1621 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1622 * SECAM L/B/D standards */
ecc67d10 1623 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
84b5dbf3 1624 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
e0d3bafd 1625
cde4362f
MCC		 1626 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
1627 V4L2_STD_SECAM_D))
84b5dbf3 1628 dwval |= 0x88000000;
cde4362f 1629 else
84b5dbf3 1630 dwval |= 0x44000000;
e0d3bafd 1631
ecc67d10 1632 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
e0d3bafd 1633
84b5dbf3 1634 return status;
e0d3bafd
SD		 1635}
1636
cde4362f 1637/******************************************************************************
ecc67d10 1638 * I 2 S - B L O C K C O N T R O L functions *
cde4362f 1639 ******************************************************************************/
ecc67d10 1640int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
e0d3bafd 1641{
84b5dbf3
MCC		 1642 int status = 0;
1643 u32 value;
1644
ecc67d10 1645 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
cde4362f 1646 CH_PWR_CTRL1, 1, &value, 1);
84b5dbf3
MCC		 1647 /* enables clock to delta-sigma and decimation filter */
1648 value |= 0x80;
ecc67d10 1649 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 1650 CH_PWR_CTRL1, 1, value, 1);
1651 /* power up all channel */
ecc67d10 1652 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 1653 CH_PWR_CTRL2, 1, 0x00, 1);
1654
1655 return status;
e0d3bafd
SD		 1656}
1657
ecc67d10 1658int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
6e4f574b 1659 enum AV_MODE avmode)
e0d3bafd 1660{
84b5dbf3
MCC		 1661 int status = 0;
1662 u32 value = 0;
1663
1664 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
ecc67d10 1665 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 1666 CH_PWR_CTRL2, 1, &value, 1);
1667 value |= 0xfe;
ecc67d10 1668 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 1669 CH_PWR_CTRL2, 1, value, 1);
1670 } else {
ecc67d10 1671 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 1672 CH_PWR_CTRL2, 1, 0x00, 1);
1673 }
1674
1675 return status;
e0d3bafd
SD		 1676}
1677
ecc67d10
SD		 1678/* set i2s_blk for audio input types */
1679int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
e0d3bafd 1680{
84b5dbf3 1681 int status = 0;
e0d3bafd 1682
84b5dbf3
MCC		 1683 switch (audio_input) {
1684 case CX231XX_AMUX_LINE_IN:
ecc67d10 1685 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3 1686 CH_PWR_CTRL2, 1, 0x00, 1);
ecc67d10 1687 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 1688 CH_PWR_CTRL1, 1, 0x80, 1);
1689 break;
1690 case CX231XX_AMUX_VIDEO:
1691 default:
1692 break;
1693 }
e0d3bafd 1694
84b5dbf3 1695 dev->ctl_ainput = audio_input;
e0d3bafd 1696
84b5dbf3 1697 return status;
e0d3bafd
SD		 1698}
1699
cde4362f
MCC		 1700/******************************************************************************
1701 * P O W E R C O N T R O L functions *
1702 ******************************************************************************/
6e4f574b 1703int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
e0d3bafd 1704{
84b5dbf3
MCC		 1705 u8 value[4] = { 0, 0, 0, 0 };
1706 u32 tmp = 0;
1707 int status = 0;
1708
1709 if (dev->power_mode != mode)
1710 dev->power_mode = mode;
1711 else {
1712 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
1713 mode);
1714 return 0;
1715 }
1716
1717 cx231xx_info(" setPowerMode::mode = %d\n", mode);
1718
cde4362f
MCC		 1719 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1720 4);
84b5dbf3
MCC		 1721 if (status < 0)
1722 return status;
1723
1724 tmp = *((u32 *) value);
1725
1726 switch (mode) {
1727 case POLARIS_AVMODE_ENXTERNAL_AV:
1728
1729 tmp &= (~PWR_MODE_MASK);
1730
1731 tmp |= PWR_AV_EN;
1732 value[0] = (u8) tmp;
1733 value[1] = (u8) (tmp >> 8);
1734 value[2] = (u8) (tmp >> 16);
1735 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1736 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1737 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1738 msleep(PWR_SLEEP_INTERVAL);
1739
1740 tmp |= PWR_ISO_EN;
1741 value[0] = (u8) tmp;
1742 value[1] = (u8) (tmp >> 8);
1743 value[2] = (u8) (tmp >> 16);
1744 value[3] = (u8) (tmp >> 24);
1745 status =
1746 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1747 value, 4);
1748 msleep(PWR_SLEEP_INTERVAL);
1749
1750 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
1751 value[0] = (u8) tmp;
1752 value[1] = (u8) (tmp >> 8);
1753 value[2] = (u8) (tmp >> 16);
1754 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1755 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1756 PWR_CTL_EN, value, 4);
84b5dbf3 1757
b9255176
SD		 1758 /* reset state of xceive tuner */
1759 dev->xc_fw_load_done = 0;
84b5dbf3
MCC		 1760 break;
1761
1762 case POLARIS_AVMODE_ANALOGT_TV:
1763
1764 tmp &= (~PWR_DEMOD_EN);
1765 tmp |= (I2C_DEMOD_EN);
1766 value[0] = (u8) tmp;
1767 value[1] = (u8) (tmp >> 8);
1768 value[2] = (u8) (tmp >> 16);
1769 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1770 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1771 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1772 msleep(PWR_SLEEP_INTERVAL);
1773
1774 if (!(tmp & PWR_TUNER_EN)) {
1775 tmp |= (PWR_TUNER_EN);
1776 value[0] = (u8) tmp;
1777 value[1] = (u8) (tmp >> 8);
1778 value[2] = (u8) (tmp >> 16);
1779 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1780 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1781 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1782 msleep(PWR_SLEEP_INTERVAL);
1783 }
1784
1785 if (!(tmp & PWR_AV_EN)) {
1786 tmp |= PWR_AV_EN;
1787 value[0] = (u8) tmp;
1788 value[1] = (u8) (tmp >> 8);
1789 value[2] = (u8) (tmp >> 16);
1790 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1791 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1792 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1793 msleep(PWR_SLEEP_INTERVAL);
1794 }
1795 if (!(tmp & PWR_ISO_EN)) {
1796 tmp |= PWR_ISO_EN;
1797 value[0] = (u8) tmp;
1798 value[1] = (u8) (tmp >> 8);
1799 value[2] = (u8) (tmp >> 16);
1800 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1801 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1802 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1803 msleep(PWR_SLEEP_INTERVAL);
1804 }
1805
1806 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
1807 tmp |= POLARIS_AVMODE_ANALOGT_TV;
1808 value[0] = (u8) tmp;
1809 value[1] = (u8) (tmp >> 8);
1810 value[2] = (u8) (tmp >> 16);
1811 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1812 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1813 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1814 msleep(PWR_SLEEP_INTERVAL);
1815 }
1816
1817 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1818 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
84b5dbf3
MCC		 1819 /* tuner path to channel 1 from port 3 */
1820 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1821
1822 if (dev->cx231xx_reset_analog_tuner)
1823 dev->cx231xx_reset_analog_tuner(dev);
1824 }
1825 break;
1826
1827 case POLARIS_AVMODE_DIGITAL:
84b5dbf3
MCC		 1828 if (!(tmp & PWR_TUNER_EN)) {
1829 tmp |= (PWR_TUNER_EN);
1830 value[0] = (u8) tmp;
1831 value[1] = (u8) (tmp >> 8);
1832 value[2] = (u8) (tmp >> 16);
1833 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1834 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1835 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1836 msleep(PWR_SLEEP_INTERVAL);
1837 }
1838 if (!(tmp & PWR_AV_EN)) {
1839 tmp |= PWR_AV_EN;
1840 value[0] = (u8) tmp;
1841 value[1] = (u8) (tmp >> 8);
1842 value[2] = (u8) (tmp >> 16);
1843 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1844 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1845 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1846 msleep(PWR_SLEEP_INTERVAL);
1847 }
1848 if (!(tmp & PWR_ISO_EN)) {
1849 tmp |= PWR_ISO_EN;
1850 value[0] = (u8) tmp;
1851 value[1] = (u8) (tmp >> 8);
1852 value[2] = (u8) (tmp >> 16);
1853 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1854 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1855 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1856 msleep(PWR_SLEEP_INTERVAL);
1857 }
1858
1859 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
1860 value[0] = (u8) tmp;
1861 value[1] = (u8) (tmp >> 8);
1862 value[2] = (u8) (tmp >> 16);
1863 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1864 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1865 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1866 msleep(PWR_SLEEP_INTERVAL);
1867
1868 if (!(tmp & PWR_DEMOD_EN)) {
1869 tmp |= PWR_DEMOD_EN;
1870 value[0] = (u8) tmp;
1871 value[1] = (u8) (tmp >> 8);
1872 value[2] = (u8) (tmp >> 16);
1873 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1874 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1875 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1876 msleep(PWR_SLEEP_INTERVAL);
1877 }
1878
1879 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1880 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
84b5dbf3
MCC		 1881 /* tuner path to channel 1 from port 3 */
1882 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1883
1884 if (dev->cx231xx_reset_analog_tuner)
1885 dev->cx231xx_reset_analog_tuner(dev);
1886 }
1887 break;
1888
1889 default:
1890 break;
1891 }
1892
1893 msleep(PWR_SLEEP_INTERVAL);
1894
cde4362f
MCC		 1895 /* For power saving, only enable Pwr_resetout_n
1896 when digital TV is selected. */
84b5dbf3
MCC		 1897 if (mode == POLARIS_AVMODE_DIGITAL) {
1898 tmp |= PWR_RESETOUT_EN;
1899 value[0] = (u8) tmp;
1900 value[1] = (u8) (tmp >> 8);
1901 value[2] = (u8) (tmp >> 16);
1902 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1903 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1904 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1905 msleep(PWR_SLEEP_INTERVAL);
1906 }
1907
ecc67d10
SD		 1908 /* update power control for afe */
1909 status = cx231xx_afe_update_power_control(dev, mode);
84b5dbf3 1910
ecc67d10
SD		 1911 /* update power control for i2s_blk */
1912 status = cx231xx_i2s_blk_update_power_control(dev, mode);
84b5dbf3 1913
cde4362f
MCC		 1914 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1915 4);
b9255176
SD		 1916 cx231xx_info(" The data of PWR_CTL_EN register 0x74"
1917 "=0x%0x,0x%0x,0x%0x,0x%0x\n",
cde4362f 1918 value[0], value[1], value[2], value[3]);
84b5dbf3
MCC		 1919
1920 return status;
e0d3bafd
SD		 1921}
1922
1923int cx231xx_power_suspend(struct cx231xx *dev)
1924{
84b5dbf3
MCC		 1925 u8 value[4] = { 0, 0, 0, 0 };
1926 u32 tmp = 0;
1927 int status = 0;
e0d3bafd 1928
cde4362f
MCC		 1929 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1930 value, 4);
84b5dbf3
MCC		 1931 if (status > 0)
1932 return status;
e0d3bafd 1933
84b5dbf3
MCC		 1934 tmp = *((u32 *) value);
1935 tmp &= (~PWR_MODE_MASK);
e0d3bafd 1936
84b5dbf3
MCC		 1937 value[0] = (u8) tmp;
1938 value[1] = (u8) (tmp >> 8);
1939 value[2] = (u8) (tmp >> 16);
1940 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 1941 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1942 value, 4);
e0d3bafd 1943
84b5dbf3 1944 return status;
e0d3bafd
SD		 1945}
1946
cde4362f
MCC		 1947/******************************************************************************
1948 * S T R E A M C O N T R O L functions *
1949 ******************************************************************************/
e0d3bafd
SD		 1950int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
1951{
84b5dbf3
MCC		 1952 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1953 u32 tmp = 0;
1954 int status = 0;
e0d3bafd 1955
84b5dbf3 1956 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
cde4362f
MCC		 1957 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1958 value, 4);
84b5dbf3
MCC		 1959 if (status < 0)
1960 return status;
e0d3bafd 1961
84b5dbf3
MCC		 1962 tmp = *((u32 *) value);
1963 tmp |= ep_mask;
1964 value[0] = (u8) tmp;
1965 value[1] = (u8) (tmp >> 8);
1966 value[2] = (u8) (tmp >> 16);
1967 value[3] = (u8) (tmp >> 24);
e0d3bafd 1968
cde4362f
MCC		 1969 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1970 value, 4);
e0d3bafd 1971
84b5dbf3 1972 return status;
e0d3bafd
SD		 1973}
1974
1975int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
1976{
84b5dbf3
MCC		 1977 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1978 u32 tmp = 0;
1979 int status = 0;
e0d3bafd 1980
84b5dbf3
MCC		 1981 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
1982 status =
1983 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
1984 if (status < 0)
1985 return status;
e0d3bafd 1986
84b5dbf3
MCC		 1987 tmp = *((u32 *) value);
1988 tmp &= (~ep_mask);
1989 value[0] = (u8) tmp;
1990 value[1] = (u8) (tmp >> 8);
1991 value[2] = (u8) (tmp >> 16);
1992 value[3] = (u8) (tmp >> 24);
e0d3bafd 1993
cde4362f
MCC		 1994 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1995 value, 4);
e0d3bafd 1996
84b5dbf3 1997 return status;
e0d3bafd
SD		 1998}
1999
2000int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2001{
84b5dbf3 2002 int status = 0;
e0d3bafd 2003
84b5dbf3
MCC		 2004 if (dev->udev->speed == USB_SPEED_HIGH) {
2005 switch (media_type) {
6e4f574b 2006 case 81: /* audio */
84b5dbf3
MCC		 2007 cx231xx_info("%s: Audio enter HANC\n", __func__);
2008 status =
2009 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2010 break;
2011
2012 case 2: /* vbi */
2013 cx231xx_info("%s: set vanc registers\n", __func__);
2014 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2015 break;
2016
2017 case 3: /* sliced cc */
2018 cx231xx_info("%s: set hanc registers\n", __func__);
2019 status =
2020 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2021 break;
2022
2023 case 0: /* video */
2024 cx231xx_info("%s: set video registers\n", __func__);
2025 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2026 break;
2027
2028 case 4: /* ts1 */
2029 cx231xx_info("%s: set ts1 registers\n", __func__);
2030 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2031 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2032 break;
2033 case 6: /* ts1 parallel mode */
2034 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2035 __func__);
2036 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2037 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2038 break;
2039 }
2040 } else {
2041 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2042 }
e0d3bafd 2043
84b5dbf3
MCC		 2044 return status;
2045}
e0d3bafd
SD		 2046
2047int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2048{
aad40d3d 2049 int rc = -1;
84b5dbf3 2050 u32 ep_mask = -1;
b9255176 2051 struct pcb_config *pcb_config;
84b5dbf3
MCC		 2052
2053 /* get EP for media type */
b9255176 2054 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
84b5dbf3
MCC		 2055
2056 if (pcb_config->config_num == 1) {
2057 switch (media_type) {
2058 case 0: /* Video */
2059 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2060 break;
2061 case 1: /* Audio */
2062 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2063 break;
2064 case 2: /* Vbi */
2065 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2066 break;
2067 case 3: /* Sliced_cc */
2068 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2069 break;
2070 case 4: /* ts1 */
2071 case 6: /* ts1 parallel mode */
2072 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2073 break;
2074 case 5: /* ts2 */
2075 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2076 break;
2077 }
2078
2079 } else if (pcb_config->config_num > 1) {
2080 switch (media_type) {
2081 case 0: /* Video */
2082 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2083 break;
2084 case 1: /* Audio */
2085 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2086 break;
2087 case 2: /* Vbi */
2088 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2089 break;
2090 case 3: /* Sliced_cc */
2091 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2092 break;
2093 case 4: /* ts1 */
2094 case 6: /* ts1 parallel mode */
2095 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2096 break;
2097 case 5: /* ts2 */
2098 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2099 break;
2100 }
2101
2102 }
2103
2104 if (start) {
2105 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2106
cde4362f 2107 if (rc < 0)
84b5dbf3 2108 return rc;
84b5dbf3
MCC		 2109
2110 /* enable video capture */
2111 if (ep_mask > 0)
2112 rc = cx231xx_start_stream(dev, ep_mask);
2113 } else {
2114 /* disable video capture */
2115 if (ep_mask > 0)
2116 rc = cx231xx_stop_stream(dev, ep_mask);
2117 }
2118
b9255176
SD		 2119 if (dev->mode == CX231XX_ANALOG_MODE)
2120 ;/* do any in Analog mode */
2121 else
2122 ;/* do any in digital mode */
e0d3bafd
SD		 2123
2124 return rc;
2125}
84b5dbf3 2126EXPORT_SYMBOL_GPL(cx231xx_capture_start);
e0d3bafd 2127
cde4362f
MCC		 2128/*****************************************************************************
2129* G P I O B I T control functions *
2130******************************************************************************/
84b5dbf3 2131int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
e0d3bafd 2132{
84b5dbf3 2133 int status = 0;
e0d3bafd 2134
84b5dbf3 2135 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
e0d3bafd 2136
84b5dbf3 2137 return status;
e0d3bafd
SD		 2138}
2139
84b5dbf3 2140int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
e0d3bafd 2141{
84b5dbf3 2142 int status = 0;
e0d3bafd 2143
84b5dbf3 2144 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
e0d3bafd 2145
84b5dbf3 2146 return status;
e0d3bafd
SD		 2147}
2148
2149/*
2150* cx231xx_set_gpio_direction
2151* Sets the direction of the GPIO pin to input or output
2152*
2153* Parameters :
2154* pin_number : The GPIO Pin number to program the direction for
2155* from 0 to 31
2156* pin_value : The Direction of the GPIO Pin under reference.
2157* 0 = Input direction
2158* 1 = Output direction
2159*/
2160int cx231xx_set_gpio_direction(struct cx231xx *dev,
84b5dbf3 2161 int pin_number, int pin_value)
e0d3bafd
SD		 2162{
2163 int status = 0;
84b5dbf3 2164 u32 value = 0;
e0d3bafd 2165
84b5dbf3 2166 /* Check for valid pin_number - if 32 , bail out */
cde4362f 2167 if (pin_number >= 32)
84b5dbf3 2168 return -EINVAL;
e0d3bafd 2169
cde4362f
MCC		 2170 /* input */
2171 if (pin_value == 0)
84b5dbf3 2172 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
cde4362f 2173 else
84b5dbf3 2174 value = dev->gpio_dir | (1 << pin_number);
e0d3bafd 2175
cde4362f 2176 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
e0d3bafd 2177
84b5dbf3 2178 /* cache the value for future */
e0d3bafd
SD		 2179 dev->gpio_dir = value;
2180
84b5dbf3 2181 return status;
e0d3bafd
SD		 2182}
2183
e0d3bafd 2184/*
6e4f574b 2185* cx231xx_set_gpio_value
e0d3bafd
SD		 2186* Sets the value of the GPIO pin to Logic high or low. The Pin under
2187* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2188*
2189* Parameters :
2190* pin_number : The GPIO Pin number to program the direction for
2191* pin_value : The value of the GPIO Pin under reference.
2192* 0 = set it to 0
2193* 1 = set it to 1
2194*/
84b5dbf3 2195int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
e0d3bafd 2196{
84b5dbf3
MCC		 2197 int status = 0;
2198 u32 value = 0;
2199
2200 /* Check for valid pin_number - if 0xFF , bail out */
2201 if (pin_number >= 32)
2202 return -EINVAL;
2203
2204 /* first do a sanity check - if the Pin is not output, make it output */
2205 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2206 /* It was in input mode */
2207 value = dev->gpio_dir | (1 << pin_number);
2208 dev->gpio_dir = value;
cde4362f
MCC		 2209 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2210 (u8 *) &dev->gpio_val);
e0d3bafd 2211 value = 0;
84b5dbf3 2212 }
e0d3bafd 2213
cde4362f 2214 if (pin_value == 0)
84b5dbf3 2215 value = dev->gpio_val & (~(1 << pin_number));
cde4362f 2216 else
84b5dbf3 2217 value = dev->gpio_val | (1 << pin_number);
e0d3bafd 2218
84b5dbf3
MCC		 2219 /* store the value */
2220 dev->gpio_val = value;
e0d3bafd 2221
84b5dbf3 2222 /* toggle bit0 of GP_IO */
cde4362f 2223 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd 2224
84b5dbf3 2225 return status;
e0d3bafd
SD		 2226}
2227
cde4362f
MCC		 2228/*****************************************************************************
2229* G P I O I2C related functions *
2230******************************************************************************/
e0d3bafd
SD		 2231int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2232{
2233 int status = 0;
2234
2235 /* set SCL to output 1 ; set SDA to output 1 */
84b5dbf3
MCC		 2236 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2237 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2238 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2239 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2240
cde4362f
MCC		 2241 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2242 if (status < 0)
e0d3bafd 2243 return -EINVAL;
e0d3bafd
SD		 2244
2245 /* set SCL to output 1; set SDA to output 0 */
84b5dbf3
MCC		 2246 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2247 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2248
cde4362f
MCC		 2249 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2250 if (status < 0)
e0d3bafd 2251 return -EINVAL;
e0d3bafd 2252
84b5dbf3
MCC		 2253 /* set SCL to output 0; set SDA to output 0 */
2254 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2255 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2256
cde4362f
MCC		 2257 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2258 if (status < 0)
e0d3bafd 2259 return -EINVAL;
e0d3bafd
SD		 2260
2261 return status;
2262}
2263
e0d3bafd
SD		 2264int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2265{
84b5dbf3 2266 int status = 0;
e0d3bafd 2267
84b5dbf3
MCC		 2268 /* set SCL to output 0; set SDA to output 0 */
2269 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2270 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
e0d3bafd 2271
84b5dbf3
MCC		 2272 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2273 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2274
cde4362f
MCC		 2275 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2276 if (status < 0)
e0d3bafd 2277 return -EINVAL;
e0d3bafd 2278
84b5dbf3
MCC		 2279 /* set SCL to output 1; set SDA to output 0 */
2280 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2281 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2282
cde4362f
MCC		 2283 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2284 if (status < 0)
e0d3bafd 2285 return -EINVAL;
e0d3bafd
SD		 2286
2287 /* set SCL to input ,release SCL cable control
2288 set SDA to input ,release SDA cable control */
84b5dbf3
MCC		 2289 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2290 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2291
84b5dbf3 2292 status =
cde4362f
MCC		 2293 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2294 if (status < 0)
e0d3bafd 2295 return -EINVAL;
cde4362f 2296
e0d3bafd
SD		 2297 return status;
2298}
2299
e0d3bafd
SD		 2300int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2301{
84b5dbf3
MCC		 2302 int status = 0;
2303 u8 i;
e0d3bafd
SD		 2304
2305 /* set SCL to output ; set SDA to output */
84b5dbf3
MCC		 2306 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2307 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2308
2309 for (i = 0; i < 8; i++) {
2310 if (((data << i) & 0x80) == 0) {
2311 /* set SCL to output 0; set SDA to output 0 */
2312 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2313 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
cde4362f
MCC		 2314 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2315 (u8 *)&dev->gpio_val);
84b5dbf3
MCC		 2316
2317 /* set SCL to output 1; set SDA to output 0 */
2318 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f
MCC		 2319 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2320 (u8 *)&dev->gpio_val);
84b5dbf3
MCC		 2321
2322 /* set SCL to output 0; set SDA to output 0 */
2323 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f
MCC		 2324 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2325 (u8 *)&dev->gpio_val);
e0d3bafd 2326 } else {
84b5dbf3
MCC		 2327 /* set SCL to output 0; set SDA to output 1 */
2328 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2329 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
cde4362f
MCC		 2330 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2331 (u8 *)&dev->gpio_val);
84b5dbf3
MCC		 2332
2333 /* set SCL to output 1; set SDA to output 1 */
2334 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f
MCC		 2335 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2336 (u8 *)&dev->gpio_val);
84b5dbf3
MCC		 2337
2338 /* set SCL to output 0; set SDA to output 1 */
2339 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f
MCC		 2340 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2341 (u8 *)&dev->gpio_val);
84b5dbf3 2342 }
e0d3bafd
SD		 2343 }
2344 return status;
2345}
2346
84b5dbf3 2347int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
e0d3bafd
SD		 2348{
2349 u8 value = 0;
84b5dbf3
MCC		 2350 int status = 0;
2351 u32 gpio_logic_value = 0;
2352 u8 i;
e0d3bafd
SD		 2353
2354 /* read byte */
84b5dbf3 2355 for (i = 0; i < 8; i++) { /* send write I2c addr */
e0d3bafd
SD		 2356
2357 /* set SCL to output 0; set SDA to input */
84b5dbf3 2358 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f
MCC		 2359 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2360 (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2361
2362 /* set SCL to output 1; set SDA to input */
84b5dbf3 2363 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f
MCC		 2364 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2365 (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2366
2367 /* get SDA data bit */
2368 gpio_logic_value = dev->gpio_val;
cde4362f
MCC		 2369 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2370 (u8 *)&dev->gpio_val);
2371 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
84b5dbf3 2372 value |= (1 << (8 - i - 1));
e0d3bafd
SD		 2373
2374 dev->gpio_val = gpio_logic_value;
2375 }
2376
2377 /* set SCL to output 0,finish the read latest SCL signal.
cde4362f
MCC		 2378 !!!set SDA to input, never to modify SDA direction at
2379 the same times */
84b5dbf3 2380 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2381 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd 2382
84b5dbf3
MCC		 2383 /* store the value */
2384 *buf = value & 0xff;
e0d3bafd
SD		 2385
2386 return status;
2387}
2388
2389int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2390{
84b5dbf3 2391 int status = 0;
e0d3bafd 2392 u32 gpio_logic_value = 0;
84b5dbf3
MCC		 2393 int nCnt = 10;
2394 int nInit = nCnt;
e0d3bafd 2395
cde4362f
MCC		 2396 /* clock stretch; set SCL to input; set SDA to input;
2397 get SCL value till SCL = 1 */
84b5dbf3
MCC		 2398 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2399 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
e0d3bafd
SD		 2400
2401 gpio_logic_value = dev->gpio_val;
cde4362f 2402 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd 2403
84b5dbf3 2404 do {
e0d3bafd 2405 msleep(2);
cde4362f
MCC		 2406 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2407 (u8 *)&dev->gpio_val);
84b5dbf3 2408 nCnt--;
b9255176
SD		 2409 } while (((dev->gpio_val &
2410 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2411 (nCnt > 0));
84b5dbf3 2412
cde4362f 2413 if (nCnt == 0)
b9255176 2414 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
cde4362f 2415 nInit * 10);
e0d3bafd 2416
af901ca1
AGR		 2417 /*
2418 * readAck
2419 * through clock stretch, slave has given a SCL signal,
2420 * so the SDA data can be directly read.
2421 */
cde4362f 2422 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd 2423
84b5dbf3 2424 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
e0d3bafd 2425 dev->gpio_val = gpio_logic_value;
84b5dbf3 2426 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd
SD		 2427 status = 0;
2428 } else {
2429 dev->gpio_val = gpio_logic_value;
84b5dbf3 2430 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
e0d3bafd
SD		 2431 }
2432
cde4362f
MCC		 2433 /* read SDA end, set the SCL to output 0, after this operation,
2434 SDA direction can be changed. */
e0d3bafd 2435 dev->gpio_val = gpio_logic_value;
84b5dbf3
MCC		 2436 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2437 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2438 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2439
2440 return status;
2441}
2442
e0d3bafd
SD		 2443int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2444{
84b5dbf3 2445 int status = 0;
e0d3bafd
SD		 2446
2447 /* set SDA to ouput */
84b5dbf3 2448 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
cde4362f 2449 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2450
2451 /* set SCL = 0 (output); set SDA = 0 (output) */
84b5dbf3
MCC		 2452 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2453 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2454 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2455
2456 /* set SCL = 1 (output); set SDA = 0 (output) */
84b5dbf3 2457 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f 2458 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2459
2460 /* set SCL = 0 (output); set SDA = 0 (output) */
84b5dbf3 2461 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2462 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2463
2464 /* set SDA to input,and then the slave will read data from SDA. */
84b5dbf3 2465 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
cde4362f 2466 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2467
2468 return status;
2469}
2470
2471int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2472{
84b5dbf3 2473 int status = 0;
e0d3bafd
SD		 2474
2475 /* set scl to output ; set sda to input */
84b5dbf3
MCC		 2476 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2477 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
cde4362f 2478 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2479
2480 /* set scl to output 0; set sda to input */
84b5dbf3 2481 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2482 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2483
2484 /* set scl to output 1; set sda to input */
84b5dbf3 2485 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f 2486 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
e0d3bafd
SD		 2487
2488 return status;
2489}
2490
cde4362f
MCC		 2491/*****************************************************************************
2492* G P I O I2C related functions *
2493******************************************************************************/
e0d3bafd
SD		 2494/* cx231xx_gpio_i2c_read
2495 * Function to read data from gpio based I2C interface
2496 */
84b5dbf3 2497int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
e0d3bafd 2498{
84b5dbf3
MCC		 2499 int status = 0;
2500 int i = 0;
e0d3bafd 2501
84b5dbf3 2502 /* get the lock */
e0d3bafd
SD		 2503 mutex_lock(&dev->gpio_i2c_lock);
2504
2505 /* start */
2506 status = cx231xx_gpio_i2c_start(dev);
2507
2508 /* write dev_addr */
84b5dbf3 2509 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
e0d3bafd
SD		 2510
2511 /* readAck */
2512 status = cx231xx_gpio_i2c_read_ack(dev);
2513
84b5dbf3
MCC		 2514 /* read data */
2515 for (i = 0; i < len; i++) {
2516 /* read data */
2517 buf[i] = 0;
2518 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
e0d3bafd 2519
84b5dbf3
MCC		 2520 if ((i + 1) != len) {
2521 /* only do write ack if we more length */
2522 status = cx231xx_gpio_i2c_write_ack(dev);
2523 }
2524 }
e0d3bafd
SD		 2525
2526 /* write NAK - inform reads are complete */
2527 status = cx231xx_gpio_i2c_write_nak(dev);
2528
2529 /* write end */
2530 status = cx231xx_gpio_i2c_end(dev);
2531
2532 /* release the lock */
2533 mutex_unlock(&dev->gpio_i2c_lock);
2534
2535 return status;
2536}
2537
e0d3bafd
SD		 2538/* cx231xx_gpio_i2c_write
2539 * Function to write data to gpio based I2C interface
2540 */
84b5dbf3 2541int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
e0d3bafd 2542{
84b5dbf3
MCC		 2543 int status = 0;
2544 int i = 0;
e0d3bafd
SD		 2545
2546 /* get the lock */
2547 mutex_lock(&dev->gpio_i2c_lock);
2548
2549 /* start */
2550 status = cx231xx_gpio_i2c_start(dev);
2551
2552 /* write dev_addr */
2553 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2554
2555 /* read Ack */
84b5dbf3 2556 status = cx231xx_gpio_i2c_read_ack(dev);
e0d3bafd 2557
84b5dbf3 2558 for (i = 0; i < len; i++) {
e0d3bafd 2559 /* Write data */
84b5dbf3 2560 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
e0d3bafd 2561
84b5dbf3
MCC		 2562 /* read Ack */
2563 status = cx231xx_gpio_i2c_read_ack(dev);
2564 }
e0d3bafd 2565
84b5dbf3 2566 /* write End */
e0d3bafd
SD		 2567 status = cx231xx_gpio_i2c_end(dev);
2568
2569 /* release the lock */
2570 mutex_unlock(&dev->gpio_i2c_lock);
2571
2572 return 0;
2573}
Linux 6.x block layer and io_uring tree(s)