Commit | Line | Data |
---|---|---|
1c1e45d1 HV |
1 | /* |
2 | * cx18 ADEC audio functions | |
3 | * | |
4 | * Derived from cx25840-core.c | |
5 | * | |
6 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
1ed9dcc8 | 7 | * Copyright (C) 2008 Andy Walls <awalls@radix.net> |
1c1e45d1 HV |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
22 | * 02110-1301, USA. | |
23 | */ | |
24 | ||
1a267046 | 25 | #include <media/v4l2-chip-ident.h> |
1c1e45d1 | 26 | #include "cx18-driver.h" |
b1526421 | 27 | #include "cx18-io.h" |
1a267046 | 28 | #include "cx18-cards.h" |
1c1e45d1 HV |
29 | |
30 | int cx18_av_write(struct cx18 *cx, u16 addr, u8 value) | |
31 | { | |
b1526421 | 32 | u32 reg = 0xc40000 + (addr & ~3); |
1c1e45d1 HV |
33 | u32 mask = 0xff; |
34 | int shift = (addr & 3) * 8; | |
b1526421 | 35 | u32 x = cx18_read_reg(cx, reg); |
1c1e45d1 HV |
36 | |
37 | x = (x & ~(mask << shift)) | ((u32)value << shift); | |
b1526421 | 38 | cx18_write_reg(cx, x, reg); |
1c1e45d1 HV |
39 | return 0; |
40 | } | |
41 | ||
ced07371 AW |
42 | int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask) |
43 | { | |
44 | u32 reg = 0xc40000 + (addr & ~3); | |
45 | int shift = (addr & 3) * 8; | |
46 | u32 x = cx18_read_reg(cx, reg); | |
47 | ||
48 | x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); | |
49 | cx18_write_reg_expect(cx, x, reg, | |
50 | ((u32)eval << shift), ((u32)mask << shift)); | |
51 | return 0; | |
52 | } | |
53 | ||
1c1e45d1 HV |
54 | int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value) |
55 | { | |
b1526421 | 56 | cx18_write_reg(cx, value, 0xc40000 + addr); |
1c1e45d1 HV |
57 | return 0; |
58 | } | |
59 | ||
ced07371 AW |
60 | int |
61 | cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask) | |
62 | { | |
63 | cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); | |
64 | return 0; | |
65 | } | |
66 | ||
d267d851 AW |
67 | int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value) |
68 | { | |
69 | cx18_write_reg_noretry(cx, value, 0xc40000 + addr); | |
70 | return 0; | |
71 | } | |
72 | ||
1c1e45d1 HV |
73 | u8 cx18_av_read(struct cx18 *cx, u16 addr) |
74 | { | |
b1526421 | 75 | u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3)); |
1c1e45d1 HV |
76 | int shift = (addr & 3) * 8; |
77 | ||
78 | return (x >> shift) & 0xff; | |
79 | } | |
80 | ||
81 | u32 cx18_av_read4(struct cx18 *cx, u16 addr) | |
82 | { | |
b1526421 | 83 | return cx18_read_reg(cx, 0xc40000 + addr); |
1c1e45d1 HV |
84 | } |
85 | ||
86 | int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask, | |
87 | u8 or_value) | |
88 | { | |
89 | return cx18_av_write(cx, addr, | |
90 | (cx18_av_read(cx, addr) & and_mask) | | |
91 | or_value); | |
92 | } | |
93 | ||
94 | int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask, | |
95 | u32 or_value) | |
96 | { | |
97 | return cx18_av_write4(cx, addr, | |
98 | (cx18_av_read4(cx, addr) & and_mask) | | |
99 | or_value); | |
100 | } | |
101 | ||
1c1e45d1 HV |
102 | static void cx18_av_initialize(struct cx18 *cx) |
103 | { | |
ca130eef | 104 | struct cx18_av_state *state = &cx->av_state; |
1c1e45d1 HV |
105 | u32 v; |
106 | ||
107 | cx18_av_loadfw(cx); | |
108 | /* Stop 8051 code execution */ | |
ced07371 AW |
109 | cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000, |
110 | 0x03000000, 0x13000000); | |
1c1e45d1 HV |
111 | |
112 | /* initallize the PLL by toggling sleep bit */ | |
113 | v = cx18_av_read4(cx, CXADEC_HOST_REG1); | |
ced07371 AW |
114 | /* enable sleep mode - register appears to be read only... */ |
115 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe); | |
1c1e45d1 | 116 | /* disable sleep mode */ |
ced07371 AW |
117 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe, |
118 | v & 0xfffe, 0xffff); | |
1c1e45d1 HV |
119 | |
120 | /* initialize DLLs */ | |
121 | v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF; | |
122 | /* disable FLD */ | |
123 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v); | |
124 | /* enable FLD */ | |
125 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100); | |
126 | ||
127 | v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF; | |
128 | /* disable FLD */ | |
129 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v); | |
130 | /* enable FLD */ | |
131 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100); | |
132 | ||
133 | /* set analog bias currents. Set Vreg to 1.20V. */ | |
134 | cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802); | |
135 | ||
136 | v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1; | |
137 | /* enable TUNE_FIL_RST */ | |
ced07371 | 138 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F); |
1c1e45d1 | 139 | /* disable TUNE_FIL_RST */ |
ced07371 AW |
140 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, |
141 | v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F); | |
1c1e45d1 HV |
142 | |
143 | /* enable 656 output */ | |
144 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00); | |
145 | ||
146 | /* video output drive strength */ | |
147 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2); | |
148 | ||
149 | /* reset video */ | |
150 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000); | |
151 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0); | |
152 | ||
153 | /* set video to auto-detect */ | |
154 | /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */ | |
155 | /* set the comb notch = 1 */ | |
156 | cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800); | |
157 | ||
158 | /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */ | |
159 | /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */ | |
160 | cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000); | |
161 | ||
162 | /* Set VGA_TRACK_RANGE to 0x20 */ | |
163 | cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000); | |
164 | ||
302df970 AW |
165 | /* |
166 | * Initial VBI setup | |
167 | * VIP-1.1, 10 bit mode, enable Raw, disable sliced, | |
812b1f9d AW |
168 | * don't clamp raw samples when codes are in use, 1 byte user D-words, |
169 | * IDID0 has line #, RP code V bit transition on VBLANK, data during | |
302df970 AW |
170 | * blanking intervals |
171 | */ | |
812b1f9d | 172 | cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e); |
1c1e45d1 HV |
173 | |
174 | /* Set the video input. | |
175 | The setting in MODE_CTRL gets lost when we do the above setup */ | |
176 | /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */ | |
177 | /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */ | |
178 | ||
179 | v = cx18_av_read4(cx, CXADEC_AFE_CTRL); | |
180 | v &= 0xFFFBFFFF; /* turn OFF bit 18 for droop_comp_ch1 */ | |
181 | v &= 0xFFFF7FFF; /* turn OFF bit 9 for clamp_sel_ch1 */ | |
182 | v &= 0xFFFFFFFE; /* turn OFF bit 0 for 12db_ch1 */ | |
183 | /* v |= 0x00000001;*/ /* turn ON bit 0 for 12db_ch1 */ | |
184 | cx18_av_write4(cx, CXADEC_AFE_CTRL, v); | |
185 | ||
186 | /* if(dwEnable && dw3DCombAvailable) { */ | |
187 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */ | |
188 | /* } else { */ | |
189 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */ | |
190 | /* } */ | |
191 | cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F); | |
ca130eef HV |
192 | state->default_volume = 228 - cx18_av_read(cx, 0x8d4); |
193 | state->default_volume = ((state->default_volume / 2) + 23) << 9; | |
1c1e45d1 HV |
194 | } |
195 | ||
1a267046 AW |
196 | static int cx18_av_reset(struct v4l2_subdev *sd, u32 val) |
197 | { | |
198 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
199 | ||
200 | cx18_av_initialize(cx); | |
201 | return 0; | |
202 | } | |
203 | ||
fa3e7036 | 204 | static int cx18_av_init(struct v4l2_subdev *sd, u32 val) |
1a267046 AW |
205 | { |
206 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
207 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
208 | ||
fa3e7036 AW |
209 | switch (val) { |
210 | case CX18_AV_INIT_PLLS: | |
211 | /* | |
212 | * The crystal freq used in calculations in this driver will be | |
213 | * 28.636360 MHz. | |
214 | * Aim to run the PLLs' VCOs near 400 MHz to minimze errors. | |
215 | */ | |
216 | ||
217 | /* | |
218 | * VDCLK Integer = 0x0f, Post Divider = 0x04 | |
219 | * AIMCLK Integer = 0x0e, Post Divider = 0x16 | |
220 | */ | |
221 | cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f); | |
222 | ||
223 | /* VDCLK Fraction = 0x2be2fe */ | |
224 | /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */ | |
225 | cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe); | |
226 | ||
227 | /* AIMCLK Fraction = 0x05227ad */ | |
228 | /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/ | |
229 | cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad); | |
230 | ||
231 | /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */ | |
232 | cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56); | |
233 | break; | |
234 | ||
235 | case CX18_AV_INIT_NORMAL: | |
236 | default: | |
237 | if (!state->is_initialized) { | |
238 | /* initialize on first use */ | |
239 | state->is_initialized = 1; | |
240 | cx18_av_initialize(cx); | |
241 | } | |
242 | break; | |
1a267046 AW |
243 | } |
244 | return 0; | |
245 | } | |
1c1e45d1 | 246 | |
03b52c36 HV |
247 | void cx18_av_std_setup(struct cx18 *cx) |
248 | { | |
249 | struct cx18_av_state *state = &cx->av_state; | |
250 | v4l2_std_id std = state->std; | |
251 | int hblank, hactive, burst, vblank, vactive, sc; | |
252 | int vblank656, src_decimation; | |
253 | int luma_lpf, uv_lpf, comb; | |
254 | u32 pll_int, pll_frac, pll_post; | |
255 | ||
256 | /* datasheet startup, step 8d */ | |
257 | if (std & ~V4L2_STD_NTSC) | |
258 | cx18_av_write(cx, 0x49f, 0x11); | |
259 | else | |
260 | cx18_av_write(cx, 0x49f, 0x14); | |
261 | ||
262 | if (std & V4L2_STD_625_50) { | |
812b1f9d | 263 | /* FIXME - revisit these for Sliced VBI */ |
03b52c36 HV |
264 | hblank = 132; |
265 | hactive = 720; | |
266 | burst = 93; | |
267 | vblank = 36; | |
268 | vactive = 580; | |
269 | vblank656 = 40; | |
270 | src_decimation = 0x21f; | |
271 | ||
272 | luma_lpf = 2; | |
273 | if (std & V4L2_STD_PAL) { | |
274 | uv_lpf = 1; | |
275 | comb = 0x20; | |
276 | sc = 688739; | |
277 | } else if (std == V4L2_STD_PAL_Nc) { | |
278 | uv_lpf = 1; | |
279 | comb = 0x20; | |
280 | sc = 556453; | |
281 | } else { /* SECAM */ | |
282 | uv_lpf = 0; | |
283 | comb = 0; | |
284 | sc = 672351; | |
285 | } | |
286 | } else { | |
812b1f9d AW |
287 | /* |
288 | * The following relationships of half line counts should hold: | |
289 | * 525 = vsync + vactive + vblank656 | |
290 | * 12 = vblank656 - vblank | |
291 | * | |
292 | * vsync: always 6 half-lines of vsync pulses | |
293 | * vactive: half lines of active video | |
294 | * vblank656: half lines, after line 3, of blanked video | |
295 | * vblank: half lines, after line 9, of blanked video | |
296 | * | |
297 | * vblank656 starts counting from the falling edge of the first | |
298 | * vsync pulse (start of line 4) | |
299 | * vblank starts counting from the after the 6 vsync pulses and | |
300 | * 6 equalization pulses (start of line 10) | |
301 | * | |
302 | * For 525 line systems the driver will extract VBI information | |
303 | * from lines 10 through 21. To avoid the EAV RP code from | |
304 | * toggling at the start of hblank at line 22, where sliced VBI | |
305 | * data from line 21 is stuffed, also treat line 22 as blanked. | |
306 | */ | |
307 | vblank656 = 38; /* lines 4 through 22 */ | |
308 | vblank = 26; /* lines 10 through 22 */ | |
309 | vactive = 481; /* lines 23 through 262.5 */ | |
310 | ||
03b52c36 HV |
311 | hactive = 720; |
312 | hblank = 122; | |
03b52c36 HV |
313 | luma_lpf = 1; |
314 | uv_lpf = 1; | |
03b52c36 HV |
315 | |
316 | src_decimation = 0x21f; | |
317 | if (std == V4L2_STD_PAL_60) { | |
318 | burst = 0x5b; | |
319 | luma_lpf = 2; | |
320 | comb = 0x20; | |
321 | sc = 688739; | |
322 | } else if (std == V4L2_STD_PAL_M) { | |
323 | burst = 0x61; | |
324 | comb = 0x20; | |
325 | sc = 555452; | |
326 | } else { | |
327 | burst = 0x5b; | |
328 | comb = 0x66; | |
329 | sc = 556063; | |
330 | } | |
331 | } | |
332 | ||
333 | /* DEBUG: Displays configured PLL frequency */ | |
334 | pll_int = cx18_av_read(cx, 0x108); | |
335 | pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff; | |
336 | pll_post = cx18_av_read(cx, 0x109); | |
337 | CX18_DEBUG_INFO("PLL regs = int: %u, frac: %u, post: %u\n", | |
338 | pll_int, pll_frac, pll_post); | |
339 | ||
340 | if (pll_post) { | |
f4167342 | 341 | int fin, fsc, pll; |
03b52c36 | 342 | |
55d81aa5 | 343 | pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25; |
03b52c36 HV |
344 | pll /= pll_post; |
345 | CX18_DEBUG_INFO("PLL = %d.%06d MHz\n", | |
346 | pll / 1000000, pll % 1000000); | |
347 | CX18_DEBUG_INFO("PLL/8 = %d.%06d MHz\n", | |
348 | pll / 8000000, (pll / 8) % 1000000); | |
349 | ||
350 | fin = ((u64)src_decimation * pll) >> 12; | |
351 | CX18_DEBUG_INFO("ADC Sampling freq = %d.%06d MHz\n", | |
352 | fin / 1000000, fin % 1000000); | |
353 | ||
354 | fsc = (((u64)sc) * pll) >> 24L; | |
355 | CX18_DEBUG_INFO("Chroma sub-carrier freq = %d.%06d MHz\n", | |
356 | fsc / 1000000, fsc % 1000000); | |
357 | ||
358 | CX18_DEBUG_INFO("hblank %i, hactive %i, " | |
359 | "vblank %i , vactive %i, vblank656 %i, src_dec %i," | |
360 | "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x," | |
361 | " sc 0x%06x\n", | |
362 | hblank, hactive, vblank, vactive, vblank656, | |
363 | src_decimation, burst, luma_lpf, uv_lpf, comb, sc); | |
364 | } | |
365 | ||
366 | /* Sets horizontal blanking delay and active lines */ | |
367 | cx18_av_write(cx, 0x470, hblank); | |
368 | cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) | | |
369 | (hactive << 4))); | |
370 | cx18_av_write(cx, 0x472, hactive >> 4); | |
371 | ||
372 | /* Sets burst gate delay */ | |
373 | cx18_av_write(cx, 0x473, burst); | |
374 | ||
375 | /* Sets vertical blanking delay and active duration */ | |
376 | cx18_av_write(cx, 0x474, vblank); | |
377 | cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) | | |
378 | (vactive << 4))); | |
379 | cx18_av_write(cx, 0x476, vactive >> 4); | |
380 | cx18_av_write(cx, 0x477, vblank656); | |
381 | ||
382 | /* Sets src decimation rate */ | |
383 | cx18_av_write(cx, 0x478, 0xff & src_decimation); | |
384 | cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8)); | |
385 | ||
386 | /* Sets Luma and UV Low pass filters */ | |
387 | cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30)); | |
388 | ||
389 | /* Enables comb filters */ | |
390 | cx18_av_write(cx, 0x47b, comb); | |
391 | ||
392 | /* Sets SC Step*/ | |
393 | cx18_av_write(cx, 0x47c, sc); | |
394 | cx18_av_write(cx, 0x47d, 0xff & sc >> 8); | |
395 | cx18_av_write(cx, 0x47e, 0xff & sc >> 16); | |
396 | ||
03b52c36 | 397 | if (std & V4L2_STD_625_50) { |
812b1f9d AW |
398 | state->slicer_line_delay = 1; |
399 | state->slicer_line_offset = (6 + state->slicer_line_delay - 2); | |
03b52c36 | 400 | } else { |
812b1f9d AW |
401 | state->slicer_line_delay = 0; |
402 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
03b52c36 | 403 | } |
812b1f9d | 404 | cx18_av_write(cx, 0x47f, state->slicer_line_delay); |
03b52c36 HV |
405 | } |
406 | ||
1a267046 AW |
407 | static int cx18_av_decode_vbi_line(struct v4l2_subdev *sd, |
408 | struct v4l2_decode_vbi_line *vbi_line) | |
409 | { | |
410 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
411 | return cx18_av_vbi(cx, VIDIOC_INT_DECODE_VBI_LINE, vbi_line); | |
412 | } | |
413 | ||
414 | static int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq) | |
415 | { | |
416 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
417 | return cx18_av_audio(cx, VIDIOC_INT_AUDIO_CLOCK_FREQ, &freq); | |
418 | } | |
03b52c36 | 419 | |
1c1e45d1 HV |
420 | static void input_change(struct cx18 *cx) |
421 | { | |
422 | struct cx18_av_state *state = &cx->av_state; | |
423 | v4l2_std_id std = state->std; | |
ced07371 | 424 | u8 v; |
1c1e45d1 HV |
425 | |
426 | /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */ | |
c1738904 HV |
427 | cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11); |
428 | cx18_av_and_or(cx, 0x401, ~0x60, 0); | |
429 | cx18_av_and_or(cx, 0x401, ~0x60, 0x60); | |
1c1e45d1 HV |
430 | |
431 | if (std & V4L2_STD_525_60) { | |
432 | if (std == V4L2_STD_NTSC_M_JP) { | |
433 | /* Japan uses EIAJ audio standard */ | |
ced07371 AW |
434 | cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff); |
435 | cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f); | |
1c1e45d1 HV |
436 | } else if (std == V4L2_STD_NTSC_M_KR) { |
437 | /* South Korea uses A2 audio standard */ | |
ced07371 AW |
438 | cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff); |
439 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
440 | } else { |
441 | /* Others use the BTSC audio standard */ | |
ced07371 AW |
442 | cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff); |
443 | cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f); | |
1c1e45d1 | 444 | } |
1c1e45d1 HV |
445 | } else if (std & V4L2_STD_PAL) { |
446 | /* Follow tuner change procedure for PAL */ | |
ced07371 AW |
447 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
448 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
449 | } else if (std & V4L2_STD_SECAM) { |
450 | /* Select autodetect for SECAM */ | |
ced07371 AW |
451 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
452 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
453 | } |
454 | ||
ced07371 AW |
455 | v = cx18_av_read(cx, 0x803); |
456 | if (v & 0x10) { | |
1c1e45d1 | 457 | /* restart audio decoder microcontroller */ |
ced07371 AW |
458 | v &= ~0x10; |
459 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
460 | v |= 0x10; | |
461 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
1c1e45d1 HV |
462 | } |
463 | } | |
464 | ||
1a267046 AW |
465 | static int cx18_av_s_frequency(struct v4l2_subdev *sd, |
466 | struct v4l2_frequency *freq) | |
467 | { | |
468 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
469 | input_change(cx); | |
470 | return 0; | |
471 | } | |
472 | ||
1c1e45d1 HV |
473 | static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, |
474 | enum cx18_av_audio_input aud_input) | |
475 | { | |
476 | struct cx18_av_state *state = &cx->av_state; | |
477 | u8 is_composite = (vid_input >= CX18_AV_COMPOSITE1 && | |
478 | vid_input <= CX18_AV_COMPOSITE8); | |
479 | u8 reg; | |
ced07371 | 480 | u8 v; |
1c1e45d1 HV |
481 | |
482 | CX18_DEBUG_INFO("decoder set video input %d, audio input %d\n", | |
483 | vid_input, aud_input); | |
484 | ||
485 | if (is_composite) { | |
486 | reg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1); | |
487 | } else { | |
488 | int luma = vid_input & 0xf0; | |
489 | int chroma = vid_input & 0xf00; | |
490 | ||
491 | if ((vid_input & ~0xff0) || | |
492 | luma < CX18_AV_SVIDEO_LUMA1 || | |
45270a15 | 493 | luma > CX18_AV_SVIDEO_LUMA8 || |
1c1e45d1 HV |
494 | chroma < CX18_AV_SVIDEO_CHROMA4 || |
495 | chroma > CX18_AV_SVIDEO_CHROMA8) { | |
496 | CX18_ERR("0x%04x is not a valid video input!\n", | |
497 | vid_input); | |
498 | return -EINVAL; | |
499 | } | |
500 | reg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4); | |
501 | if (chroma >= CX18_AV_SVIDEO_CHROMA7) { | |
502 | reg &= 0x3f; | |
503 | reg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2; | |
504 | } else { | |
505 | reg &= 0xcf; | |
506 | reg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4; | |
507 | } | |
508 | } | |
509 | ||
510 | switch (aud_input) { | |
81cb727d HV |
511 | case CX18_AV_AUDIO_SERIAL1: |
512 | case CX18_AV_AUDIO_SERIAL2: | |
1c1e45d1 HV |
513 | /* do nothing, use serial audio input */ |
514 | break; | |
515 | case CX18_AV_AUDIO4: reg &= ~0x30; break; | |
516 | case CX18_AV_AUDIO5: reg &= ~0x30; reg |= 0x10; break; | |
517 | case CX18_AV_AUDIO6: reg &= ~0x30; reg |= 0x20; break; | |
518 | case CX18_AV_AUDIO7: reg &= ~0xc0; break; | |
519 | case CX18_AV_AUDIO8: reg &= ~0xc0; reg |= 0x40; break; | |
520 | ||
521 | default: | |
522 | CX18_ERR("0x%04x is not a valid audio input!\n", aud_input); | |
523 | return -EINVAL; | |
524 | } | |
525 | ||
ced07371 | 526 | cx18_av_write_expect(cx, 0x103, reg, reg, 0xf7); |
1c1e45d1 | 527 | /* Set INPUT_MODE to Composite (0) or S-Video (1) */ |
c1738904 | 528 | cx18_av_and_or(cx, 0x401, ~0x6, is_composite ? 0 : 0x02); |
ced07371 | 529 | |
1c1e45d1 | 530 | /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */ |
ced07371 AW |
531 | v = cx18_av_read(cx, 0x102); |
532 | if (reg & 0x80) | |
533 | v &= ~0x2; | |
534 | else | |
535 | v |= 0x2; | |
1c1e45d1 HV |
536 | /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */ |
537 | if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30) | |
ced07371 | 538 | v |= 0x4; |
1c1e45d1 | 539 | else |
ced07371 AW |
540 | v &= ~0x4; |
541 | cx18_av_write_expect(cx, 0x102, v, v, 0x17); | |
542 | ||
1c1e45d1 HV |
543 | /*cx18_av_and_or4(cx, 0x104, ~0x001b4180, 0x00004180);*/ |
544 | ||
545 | state->vid_input = vid_input; | |
546 | state->aud_input = aud_input; | |
547 | cx18_av_audio_set_path(cx); | |
548 | input_change(cx); | |
549 | return 0; | |
550 | } | |
551 | ||
1a267046 AW |
552 | static int cx18_av_s_video_routing(struct v4l2_subdev *sd, |
553 | const struct v4l2_routing *route) | |
554 | { | |
555 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
556 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
557 | return set_input(cx, route->input, state->aud_input); | |
558 | } | |
1c1e45d1 | 559 | |
1a267046 AW |
560 | static int cx18_av_s_audio_routing(struct v4l2_subdev *sd, |
561 | const struct v4l2_routing *route) | |
1c1e45d1 | 562 | { |
1a267046 AW |
563 | struct cx18_av_state *state = to_cx18_av_state(sd); |
564 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
565 | return set_input(cx, state->vid_input, route->input); | |
566 | } | |
567 | ||
568 | static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) | |
569 | { | |
570 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
571 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
572 | u8 vpres; | |
573 | u8 mode; | |
574 | int val = 0; | |
575 | ||
576 | if (state->radio) | |
577 | return 0; | |
578 | ||
579 | vpres = cx18_av_read(cx, 0x40e) & 0x20; | |
580 | vt->signal = vpres ? 0xffff : 0x0; | |
581 | ||
582 | vt->capability |= | |
583 | V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 | | |
584 | V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP; | |
585 | ||
586 | mode = cx18_av_read(cx, 0x804); | |
587 | ||
588 | /* get rxsubchans and audmode */ | |
589 | if ((mode & 0xf) == 1) | |
590 | val |= V4L2_TUNER_SUB_STEREO; | |
591 | else | |
592 | val |= V4L2_TUNER_SUB_MONO; | |
593 | ||
594 | if (mode == 2 || mode == 4) | |
595 | val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; | |
596 | ||
597 | if (mode & 0x10) | |
598 | val |= V4L2_TUNER_SUB_SAP; | |
599 | ||
600 | vt->rxsubchans = val; | |
601 | vt->audmode = state->audmode; | |
602 | return 0; | |
603 | } | |
604 | ||
605 | static int cx18_av_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) | |
606 | { | |
607 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
608 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
609 | u8 v; | |
610 | ||
611 | if (state->radio) | |
612 | return 0; | |
613 | ||
614 | v = cx18_av_read(cx, 0x809); | |
615 | v &= ~0xf; | |
616 | ||
617 | switch (vt->audmode) { | |
618 | case V4L2_TUNER_MODE_MONO: | |
619 | /* mono -> mono | |
620 | stereo -> mono | |
621 | bilingual -> lang1 */ | |
622 | break; | |
623 | case V4L2_TUNER_MODE_STEREO: | |
624 | case V4L2_TUNER_MODE_LANG1: | |
625 | /* mono -> mono | |
626 | stereo -> stereo | |
627 | bilingual -> lang1 */ | |
628 | v |= 0x4; | |
629 | break; | |
630 | case V4L2_TUNER_MODE_LANG1_LANG2: | |
631 | /* mono -> mono | |
632 | stereo -> stereo | |
633 | bilingual -> lang1/lang2 */ | |
634 | v |= 0x7; | |
635 | break; | |
636 | case V4L2_TUNER_MODE_LANG2: | |
637 | /* mono -> mono | |
638 | stereo -> stereo | |
639 | bilingual -> lang2 */ | |
640 | v |= 0x1; | |
641 | break; | |
642 | default: | |
643 | return -EINVAL; | |
644 | } | |
645 | cx18_av_write_expect(cx, 0x809, v, v, 0xff); | |
646 | state->audmode = vt->audmode; | |
647 | return 0; | |
648 | } | |
649 | ||
650 | static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) | |
651 | { | |
652 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
653 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
654 | ||
1c1e45d1 HV |
655 | u8 fmt = 0; /* zero is autodetect */ |
656 | u8 pal_m = 0; | |
657 | ||
1a267046 AW |
658 | if (state->radio == 0 && state->std == norm) |
659 | return 0; | |
660 | ||
661 | state->radio = 0; | |
662 | state->std = norm; | |
663 | ||
1c1e45d1 HV |
664 | /* First tests should be against specific std */ |
665 | if (state->std == V4L2_STD_NTSC_M_JP) { | |
666 | fmt = 0x2; | |
667 | } else if (state->std == V4L2_STD_NTSC_443) { | |
668 | fmt = 0x3; | |
669 | } else if (state->std == V4L2_STD_PAL_M) { | |
670 | pal_m = 1; | |
671 | fmt = 0x5; | |
672 | } else if (state->std == V4L2_STD_PAL_N) { | |
673 | fmt = 0x6; | |
674 | } else if (state->std == V4L2_STD_PAL_Nc) { | |
675 | fmt = 0x7; | |
676 | } else if (state->std == V4L2_STD_PAL_60) { | |
677 | fmt = 0x8; | |
678 | } else { | |
679 | /* Then, test against generic ones */ | |
680 | if (state->std & V4L2_STD_NTSC) | |
681 | fmt = 0x1; | |
682 | else if (state->std & V4L2_STD_PAL) | |
683 | fmt = 0x4; | |
684 | else if (state->std & V4L2_STD_SECAM) | |
685 | fmt = 0xc; | |
686 | } | |
687 | ||
688 | CX18_DEBUG_INFO("changing video std to fmt %i\n", fmt); | |
689 | ||
690 | /* Follow step 9 of section 3.16 in the cx18_av datasheet. | |
691 | Without this PAL may display a vertical ghosting effect. | |
692 | This happens for example with the Yuan MPC622. */ | |
693 | if (fmt >= 4 && fmt < 8) { | |
694 | /* Set format to NTSC-M */ | |
c1738904 | 695 | cx18_av_and_or(cx, 0x400, ~0xf, 1); |
1c1e45d1 HV |
696 | /* Turn off LCOMB */ |
697 | cx18_av_and_or(cx, 0x47b, ~6, 0); | |
698 | } | |
c1738904 HV |
699 | cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20); |
700 | cx18_av_and_or(cx, 0x403, ~0x3, pal_m); | |
03b52c36 | 701 | cx18_av_std_setup(cx); |
1c1e45d1 HV |
702 | input_change(cx); |
703 | return 0; | |
704 | } | |
705 | ||
1a267046 AW |
706 | static int cx18_av_s_radio(struct v4l2_subdev *sd) |
707 | { | |
708 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
709 | state->radio = 1; | |
710 | return 0; | |
711 | } | |
1c1e45d1 | 712 | |
1a267046 | 713 | static int cx18_av_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
1c1e45d1 | 714 | { |
1a267046 AW |
715 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
716 | ||
1c1e45d1 HV |
717 | switch (ctrl->id) { |
718 | case V4L2_CID_BRIGHTNESS: | |
719 | if (ctrl->value < 0 || ctrl->value > 255) { | |
720 | CX18_ERR("invalid brightness setting %d\n", | |
721 | ctrl->value); | |
722 | return -ERANGE; | |
723 | } | |
724 | ||
725 | cx18_av_write(cx, 0x414, ctrl->value - 128); | |
726 | break; | |
727 | ||
728 | case V4L2_CID_CONTRAST: | |
729 | if (ctrl->value < 0 || ctrl->value > 127) { | |
730 | CX18_ERR("invalid contrast setting %d\n", | |
731 | ctrl->value); | |
732 | return -ERANGE; | |
733 | } | |
734 | ||
735 | cx18_av_write(cx, 0x415, ctrl->value << 1); | |
736 | break; | |
737 | ||
738 | case V4L2_CID_SATURATION: | |
739 | if (ctrl->value < 0 || ctrl->value > 127) { | |
740 | CX18_ERR("invalid saturation setting %d\n", | |
741 | ctrl->value); | |
742 | return -ERANGE; | |
743 | } | |
744 | ||
745 | cx18_av_write(cx, 0x420, ctrl->value << 1); | |
746 | cx18_av_write(cx, 0x421, ctrl->value << 1); | |
747 | break; | |
748 | ||
749 | case V4L2_CID_HUE: | |
de6476f5 | 750 | if (ctrl->value < -128 || ctrl->value > 127) { |
1c1e45d1 HV |
751 | CX18_ERR("invalid hue setting %d\n", ctrl->value); |
752 | return -ERANGE; | |
753 | } | |
754 | ||
755 | cx18_av_write(cx, 0x422, ctrl->value); | |
756 | break; | |
757 | ||
758 | case V4L2_CID_AUDIO_VOLUME: | |
759 | case V4L2_CID_AUDIO_BASS: | |
760 | case V4L2_CID_AUDIO_TREBLE: | |
761 | case V4L2_CID_AUDIO_BALANCE: | |
762 | case V4L2_CID_AUDIO_MUTE: | |
763 | return cx18_av_audio(cx, VIDIOC_S_CTRL, ctrl); | |
764 | ||
765 | default: | |
766 | return -EINVAL; | |
767 | } | |
1c1e45d1 HV |
768 | return 0; |
769 | } | |
770 | ||
1a267046 | 771 | static int cx18_av_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
1c1e45d1 | 772 | { |
1a267046 AW |
773 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
774 | ||
1c1e45d1 HV |
775 | switch (ctrl->id) { |
776 | case V4L2_CID_BRIGHTNESS: | |
777 | ctrl->value = (s8)cx18_av_read(cx, 0x414) + 128; | |
778 | break; | |
779 | case V4L2_CID_CONTRAST: | |
780 | ctrl->value = cx18_av_read(cx, 0x415) >> 1; | |
781 | break; | |
782 | case V4L2_CID_SATURATION: | |
783 | ctrl->value = cx18_av_read(cx, 0x420) >> 1; | |
784 | break; | |
785 | case V4L2_CID_HUE: | |
786 | ctrl->value = (s8)cx18_av_read(cx, 0x422); | |
787 | break; | |
788 | case V4L2_CID_AUDIO_VOLUME: | |
789 | case V4L2_CID_AUDIO_BASS: | |
790 | case V4L2_CID_AUDIO_TREBLE: | |
791 | case V4L2_CID_AUDIO_BALANCE: | |
792 | case V4L2_CID_AUDIO_MUTE: | |
793 | return cx18_av_audio(cx, VIDIOC_G_CTRL, ctrl); | |
794 | default: | |
795 | return -EINVAL; | |
796 | } | |
1c1e45d1 HV |
797 | return 0; |
798 | } | |
799 | ||
1a267046 AW |
800 | static int cx18_av_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc) |
801 | { | |
802 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
803 | ||
804 | switch (qc->id) { | |
805 | case V4L2_CID_BRIGHTNESS: | |
806 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
807 | case V4L2_CID_CONTRAST: | |
808 | case V4L2_CID_SATURATION: | |
809 | return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64); | |
810 | case V4L2_CID_HUE: | |
811 | return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0); | |
812 | default: | |
813 | break; | |
814 | } | |
815 | ||
816 | switch (qc->id) { | |
817 | case V4L2_CID_AUDIO_VOLUME: | |
818 | return v4l2_ctrl_query_fill(qc, 0, 65535, | |
819 | 65535 / 100, state->default_volume); | |
820 | case V4L2_CID_AUDIO_MUTE: | |
821 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
822 | case V4L2_CID_AUDIO_BALANCE: | |
823 | case V4L2_CID_AUDIO_BASS: | |
824 | case V4L2_CID_AUDIO_TREBLE: | |
825 | return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768); | |
826 | default: | |
827 | return -EINVAL; | |
828 | } | |
829 | return -EINVAL; | |
830 | } | |
1c1e45d1 | 831 | |
1a267046 | 832 | static int cx18_av_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
1c1e45d1 | 833 | { |
1a267046 AW |
834 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
835 | ||
1c1e45d1 HV |
836 | switch (fmt->type) { |
837 | case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: | |
838 | return cx18_av_vbi(cx, VIDIOC_G_FMT, fmt); | |
839 | default: | |
840 | return -EINVAL; | |
841 | } | |
1c1e45d1 HV |
842 | return 0; |
843 | } | |
844 | ||
1a267046 | 845 | static int cx18_av_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
1c1e45d1 | 846 | { |
1a267046 AW |
847 | struct cx18_av_state *state = to_cx18_av_state(sd); |
848 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
849 | ||
1c1e45d1 HV |
850 | struct v4l2_pix_format *pix; |
851 | int HSC, VSC, Vsrc, Hsrc, filter, Vlines; | |
852 | int is_50Hz = !(state->std & V4L2_STD_525_60); | |
853 | ||
854 | switch (fmt->type) { | |
855 | case V4L2_BUF_TYPE_VIDEO_CAPTURE: | |
856 | pix = &(fmt->fmt.pix); | |
857 | ||
858 | Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4; | |
859 | Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4; | |
860 | ||
861 | Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4; | |
862 | Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4; | |
863 | ||
864 | Vlines = pix->height + (is_50Hz ? 4 : 7); | |
865 | ||
866 | if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) || | |
867 | (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) { | |
868 | CX18_ERR("%dx%d is not a valid size!\n", | |
869 | pix->width, pix->height); | |
870 | return -ERANGE; | |
871 | } | |
872 | ||
873 | HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20); | |
874 | VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9)); | |
875 | VSC &= 0x1fff; | |
876 | ||
877 | if (pix->width >= 385) | |
878 | filter = 0; | |
879 | else if (pix->width > 192) | |
880 | filter = 1; | |
881 | else if (pix->width > 96) | |
882 | filter = 2; | |
883 | else | |
884 | filter = 3; | |
885 | ||
886 | CX18_DEBUG_INFO("decoder set size %dx%d -> scale %ux%u\n", | |
887 | pix->width, pix->height, HSC, VSC); | |
888 | ||
889 | /* HSCALE=HSC */ | |
890 | cx18_av_write(cx, 0x418, HSC & 0xff); | |
891 | cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff); | |
892 | cx18_av_write(cx, 0x41a, HSC >> 16); | |
893 | /* VSCALE=VSC */ | |
894 | cx18_av_write(cx, 0x41c, VSC & 0xff); | |
895 | cx18_av_write(cx, 0x41d, VSC >> 8); | |
896 | /* VS_INTRLACE=1 VFILT=filter */ | |
897 | cx18_av_write(cx, 0x41e, 0x8 | filter); | |
898 | break; | |
899 | ||
900 | case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: | |
901 | return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt); | |
902 | ||
903 | case V4L2_BUF_TYPE_VBI_CAPTURE: | |
904 | return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt); | |
905 | ||
906 | default: | |
907 | return -EINVAL; | |
908 | } | |
1c1e45d1 HV |
909 | return 0; |
910 | } | |
911 | ||
1a267046 | 912 | static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable) |
e474200d | 913 | { |
1a267046 | 914 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
1c1e45d1 | 915 | |
1a267046 AW |
916 | CX18_DEBUG_INFO("%s output\n", enable ? "enable" : "disable"); |
917 | if (enable) { | |
1c1e45d1 HV |
918 | cx18_av_write(cx, 0x115, 0x8c); |
919 | cx18_av_write(cx, 0x116, 0x07); | |
1a267046 | 920 | } else { |
1c1e45d1 HV |
921 | cx18_av_write(cx, 0x115, 0x00); |
922 | cx18_av_write(cx, 0x116, 0x00); | |
1c1e45d1 | 923 | } |
1c1e45d1 HV |
924 | return 0; |
925 | } | |
926 | ||
1c1e45d1 HV |
927 | static void log_video_status(struct cx18 *cx) |
928 | { | |
929 | static const char *const fmt_strs[] = { | |
930 | "0x0", | |
931 | "NTSC-M", "NTSC-J", "NTSC-4.43", | |
932 | "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60", | |
933 | "0x9", "0xA", "0xB", | |
934 | "SECAM", | |
935 | "0xD", "0xE", "0xF" | |
936 | }; | |
937 | ||
938 | struct cx18_av_state *state = &cx->av_state; | |
939 | u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf; | |
940 | u8 gen_stat1 = cx18_av_read(cx, 0x40d); | |
941 | u8 gen_stat2 = cx18_av_read(cx, 0x40e); | |
942 | int vid_input = state->vid_input; | |
943 | ||
944 | CX18_INFO("Video signal: %spresent\n", | |
945 | (gen_stat2 & 0x20) ? "" : "not "); | |
946 | CX18_INFO("Detected format: %s\n", | |
947 | fmt_strs[gen_stat1 & 0xf]); | |
948 | ||
949 | CX18_INFO("Specified standard: %s\n", | |
950 | vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection"); | |
951 | ||
952 | if (vid_input >= CX18_AV_COMPOSITE1 && | |
953 | vid_input <= CX18_AV_COMPOSITE8) { | |
954 | CX18_INFO("Specified video input: Composite %d\n", | |
955 | vid_input - CX18_AV_COMPOSITE1 + 1); | |
956 | } else { | |
957 | CX18_INFO("Specified video input: S-Video (Luma In%d, Chroma In%d)\n", | |
958 | (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8); | |
959 | } | |
960 | ||
961 | CX18_INFO("Specified audioclock freq: %d Hz\n", state->audclk_freq); | |
962 | } | |
963 | ||
1c1e45d1 HV |
964 | static void log_audio_status(struct cx18 *cx) |
965 | { | |
966 | struct cx18_av_state *state = &cx->av_state; | |
967 | u8 download_ctl = cx18_av_read(cx, 0x803); | |
63b8c709 HV |
968 | u8 mod_det_stat0 = cx18_av_read(cx, 0x804); |
969 | u8 mod_det_stat1 = cx18_av_read(cx, 0x805); | |
1c1e45d1 HV |
970 | u8 audio_config = cx18_av_read(cx, 0x808); |
971 | u8 pref_mode = cx18_av_read(cx, 0x809); | |
972 | u8 afc0 = cx18_av_read(cx, 0x80b); | |
973 | u8 mute_ctl = cx18_av_read(cx, 0x8d3); | |
974 | int aud_input = state->aud_input; | |
975 | char *p; | |
976 | ||
977 | switch (mod_det_stat0) { | |
978 | case 0x00: p = "mono"; break; | |
979 | case 0x01: p = "stereo"; break; | |
980 | case 0x02: p = "dual"; break; | |
981 | case 0x04: p = "tri"; break; | |
982 | case 0x10: p = "mono with SAP"; break; | |
983 | case 0x11: p = "stereo with SAP"; break; | |
984 | case 0x12: p = "dual with SAP"; break; | |
985 | case 0x14: p = "tri with SAP"; break; | |
986 | case 0xfe: p = "forced mode"; break; | |
63b8c709 | 987 | default: p = "not defined"; break; |
1c1e45d1 HV |
988 | } |
989 | CX18_INFO("Detected audio mode: %s\n", p); | |
990 | ||
991 | switch (mod_det_stat1) { | |
63b8c709 | 992 | case 0x00: p = "not defined"; break; |
1c1e45d1 HV |
993 | case 0x01: p = "EIAJ"; break; |
994 | case 0x02: p = "A2-M"; break; | |
995 | case 0x03: p = "A2-BG"; break; | |
996 | case 0x04: p = "A2-DK1"; break; | |
997 | case 0x05: p = "A2-DK2"; break; | |
998 | case 0x06: p = "A2-DK3"; break; | |
999 | case 0x07: p = "A1 (6.0 MHz FM Mono)"; break; | |
1000 | case 0x08: p = "AM-L"; break; | |
1001 | case 0x09: p = "NICAM-BG"; break; | |
1002 | case 0x0a: p = "NICAM-DK"; break; | |
1003 | case 0x0b: p = "NICAM-I"; break; | |
1004 | case 0x0c: p = "NICAM-L"; break; | |
1005 | case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break; | |
63b8c709 HV |
1006 | case 0x0e: p = "IF FM Radio"; break; |
1007 | case 0x0f: p = "BTSC"; break; | |
1008 | case 0x10: p = "detected chrominance"; break; | |
1009 | case 0xfd: p = "unknown audio standard"; break; | |
1010 | case 0xfe: p = "forced audio standard"; break; | |
1c1e45d1 | 1011 | case 0xff: p = "no detected audio standard"; break; |
63b8c709 | 1012 | default: p = "not defined"; break; |
1c1e45d1 HV |
1013 | } |
1014 | CX18_INFO("Detected audio standard: %s\n", p); | |
1015 | CX18_INFO("Audio muted: %s\n", | |
1016 | (mute_ctl & 0x2) ? "yes" : "no"); | |
1017 | CX18_INFO("Audio microcontroller: %s\n", | |
1018 | (download_ctl & 0x10) ? "running" : "stopped"); | |
1019 | ||
1020 | switch (audio_config >> 4) { | |
63b8c709 HV |
1021 | case 0x00: p = "undefined"; break; |
1022 | case 0x01: p = "BTSC"; break; | |
1023 | case 0x02: p = "EIAJ"; break; | |
1024 | case 0x03: p = "A2-M"; break; | |
1025 | case 0x04: p = "A2-BG"; break; | |
1026 | case 0x05: p = "A2-DK1"; break; | |
1027 | case 0x06: p = "A2-DK2"; break; | |
1028 | case 0x07: p = "A2-DK3"; break; | |
1029 | case 0x08: p = "A1 (6.0 MHz FM Mono)"; break; | |
1030 | case 0x09: p = "AM-L"; break; | |
1031 | case 0x0a: p = "NICAM-BG"; break; | |
1032 | case 0x0b: p = "NICAM-DK"; break; | |
1033 | case 0x0c: p = "NICAM-I"; break; | |
1034 | case 0x0d: p = "NICAM-L"; break; | |
1035 | case 0x0e: p = "FM radio"; break; | |
1c1e45d1 | 1036 | case 0x0f: p = "automatic detection"; break; |
63b8c709 | 1037 | default: p = "undefined"; break; |
1c1e45d1 HV |
1038 | } |
1039 | CX18_INFO("Configured audio standard: %s\n", p); | |
1040 | ||
1041 | if ((audio_config >> 4) < 0xF) { | |
1042 | switch (audio_config & 0xF) { | |
1043 | case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break; | |
1044 | case 0x01: p = "MONO2 (LANGUAGE B)"; break; | |
1045 | case 0x02: p = "MONO3 (STEREO forced MONO)"; break; | |
1046 | case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break; | |
1047 | case 0x04: p = "STEREO"; break; | |
63b8c709 HV |
1048 | case 0x05: p = "DUAL1 (AC)"; break; |
1049 | case 0x06: p = "DUAL2 (BC)"; break; | |
1050 | case 0x07: p = "DUAL3 (AB)"; break; | |
1c1e45d1 HV |
1051 | default: p = "undefined"; |
1052 | } | |
1053 | CX18_INFO("Configured audio mode: %s\n", p); | |
1054 | } else { | |
1055 | switch (audio_config & 0xF) { | |
1056 | case 0x00: p = "BG"; break; | |
1057 | case 0x01: p = "DK1"; break; | |
1058 | case 0x02: p = "DK2"; break; | |
1059 | case 0x03: p = "DK3"; break; | |
1060 | case 0x04: p = "I"; break; | |
1061 | case 0x05: p = "L"; break; | |
1062 | case 0x06: p = "BTSC"; break; | |
1063 | case 0x07: p = "EIAJ"; break; | |
1064 | case 0x08: p = "A2-M"; break; | |
63b8c709 HV |
1065 | case 0x09: p = "FM Radio (4.5 MHz)"; break; |
1066 | case 0x0a: p = "FM Radio (5.5 MHz)"; break; | |
1067 | case 0x0b: p = "S-Video"; break; | |
1c1e45d1 | 1068 | case 0x0f: p = "automatic standard and mode detection"; break; |
63b8c709 | 1069 | default: p = "undefined"; break; |
1c1e45d1 HV |
1070 | } |
1071 | CX18_INFO("Configured audio system: %s\n", p); | |
1072 | } | |
1073 | ||
1074 | if (aud_input) | |
1075 | CX18_INFO("Specified audio input: Tuner (In%d)\n", | |
1076 | aud_input); | |
1077 | else | |
1078 | CX18_INFO("Specified audio input: External\n"); | |
1079 | ||
1080 | switch (pref_mode & 0xf) { | |
1081 | case 0: p = "mono/language A"; break; | |
1082 | case 1: p = "language B"; break; | |
1083 | case 2: p = "language C"; break; | |
1084 | case 3: p = "analog fallback"; break; | |
1085 | case 4: p = "stereo"; break; | |
1086 | case 5: p = "language AC"; break; | |
1087 | case 6: p = "language BC"; break; | |
1088 | case 7: p = "language AB"; break; | |
63b8c709 | 1089 | default: p = "undefined"; break; |
1c1e45d1 HV |
1090 | } |
1091 | CX18_INFO("Preferred audio mode: %s\n", p); | |
1092 | ||
1093 | if ((audio_config & 0xf) == 0xf) { | |
63b8c709 | 1094 | switch ((afc0 >> 3) & 0x1) { |
1c1e45d1 HV |
1095 | case 0: p = "system DK"; break; |
1096 | case 1: p = "system L"; break; | |
1097 | } | |
1098 | CX18_INFO("Selected 65 MHz format: %s\n", p); | |
1099 | ||
63b8c709 HV |
1100 | switch (afc0 & 0x7) { |
1101 | case 0: p = "Chroma"; break; | |
1102 | case 1: p = "BTSC"; break; | |
1103 | case 2: p = "EIAJ"; break; | |
1104 | case 3: p = "A2-M"; break; | |
1105 | case 4: p = "autodetect"; break; | |
1106 | default: p = "undefined"; break; | |
1c1e45d1 HV |
1107 | } |
1108 | CX18_INFO("Selected 45 MHz format: %s\n", p); | |
1109 | } | |
1110 | } | |
1a267046 AW |
1111 | |
1112 | static int cx18_av_log_status(struct v4l2_subdev *sd) | |
1113 | { | |
1114 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1115 | log_video_status(cx); | |
1116 | log_audio_status(cx); | |
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | static inline int cx18_av_dbg_match(const struct v4l2_dbg_match *match) | |
1121 | { | |
1122 | return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 1; | |
1123 | } | |
1124 | ||
1125 | static int cx18_av_g_chip_ident(struct v4l2_subdev *sd, | |
1126 | struct v4l2_dbg_chip_ident *chip) | |
1127 | { | |
fa3e7036 AW |
1128 | struct cx18_av_state *state = to_cx18_av_state(sd); |
1129 | ||
1a267046 | 1130 | if (cx18_av_dbg_match(&chip->match)) { |
fa3e7036 AW |
1131 | chip->ident = state->id; |
1132 | chip->revision = state->rev; | |
1a267046 AW |
1133 | } |
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1138 | static int cx18_av_g_register(struct v4l2_subdev *sd, | |
1139 | struct v4l2_dbg_register *reg) | |
1140 | { | |
1141 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1142 | ||
1143 | if (!cx18_av_dbg_match(®->match)) | |
1144 | return -EINVAL; | |
1145 | if ((reg->reg & 0x3) != 0) | |
1146 | return -EINVAL; | |
1147 | if (!capable(CAP_SYS_ADMIN)) | |
1148 | return -EPERM; | |
1149 | reg->size = 4; | |
1150 | reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc); | |
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | static int cx18_av_s_register(struct v4l2_subdev *sd, | |
1155 | struct v4l2_dbg_register *reg) | |
1156 | { | |
1157 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1158 | ||
1159 | if (!cx18_av_dbg_match(®->match)) | |
1160 | return -EINVAL; | |
1161 | if ((reg->reg & 0x3) != 0) | |
1162 | return -EINVAL; | |
1163 | if (!capable(CAP_SYS_ADMIN)) | |
1164 | return -EPERM; | |
1165 | cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val); | |
1166 | return 0; | |
1167 | } | |
1168 | #endif | |
1169 | ||
1170 | static const struct v4l2_subdev_core_ops cx18_av_general_ops = { | |
1171 | .g_chip_ident = cx18_av_g_chip_ident, | |
1172 | .log_status = cx18_av_log_status, | |
fa3e7036 | 1173 | .init = cx18_av_init, |
1a267046 AW |
1174 | .reset = cx18_av_reset, |
1175 | .queryctrl = cx18_av_queryctrl, | |
1176 | .g_ctrl = cx18_av_g_ctrl, | |
1177 | .s_ctrl = cx18_av_s_ctrl, | |
1178 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1179 | .g_register = cx18_av_g_register, | |
1180 | .s_register = cx18_av_s_register, | |
1181 | #endif | |
1182 | }; | |
1183 | ||
1184 | static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = { | |
1185 | .s_radio = cx18_av_s_radio, | |
1186 | .s_frequency = cx18_av_s_frequency, | |
1187 | .g_tuner = cx18_av_g_tuner, | |
1188 | .s_tuner = cx18_av_s_tuner, | |
1189 | .s_std = cx18_av_s_std, | |
1190 | }; | |
1191 | ||
1192 | static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = { | |
1193 | .s_clock_freq = cx18_av_s_clock_freq, | |
1194 | .s_routing = cx18_av_s_audio_routing, | |
1195 | }; | |
1196 | ||
1197 | static const struct v4l2_subdev_video_ops cx18_av_video_ops = { | |
1198 | .s_routing = cx18_av_s_video_routing, | |
1199 | .decode_vbi_line = cx18_av_decode_vbi_line, | |
1200 | .s_stream = cx18_av_s_stream, | |
1201 | .g_fmt = cx18_av_g_fmt, | |
1202 | .s_fmt = cx18_av_s_fmt, | |
1203 | }; | |
1204 | ||
1205 | static const struct v4l2_subdev_ops cx18_av_ops = { | |
1206 | .core = &cx18_av_general_ops, | |
1207 | .tuner = &cx18_av_tuner_ops, | |
1208 | .audio = &cx18_av_audio_ops, | |
1209 | .video = &cx18_av_video_ops, | |
1210 | }; | |
1211 | ||
ff2a2001 | 1212 | int cx18_av_probe(struct cx18 *cx) |
1a267046 | 1213 | { |
fa3e7036 | 1214 | struct cx18_av_state *state = &cx->av_state; |
ff2a2001 | 1215 | struct v4l2_subdev *sd; |
fa3e7036 AW |
1216 | |
1217 | state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff; | |
1218 | state->id = ((state->rev >> 4) == CXADEC_CHIP_TYPE_MAKO) | |
1219 | ? V4L2_IDENT_CX23418_843 : V4L2_IDENT_UNKNOWN; | |
1220 | ||
1221 | state->vid_input = CX18_AV_COMPOSITE7; | |
1222 | state->aud_input = CX18_AV_AUDIO8; | |
1223 | state->audclk_freq = 48000; | |
1224 | state->audmode = V4L2_TUNER_MODE_LANG1; | |
1225 | state->slicer_line_delay = 0; | |
1226 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
1227 | ||
ff2a2001 AW |
1228 | sd = &state->sd; |
1229 | v4l2_subdev_init(sd, &cx18_av_ops); | |
1230 | v4l2_set_subdevdata(sd, cx); | |
1231 | snprintf(sd->name, sizeof(sd->name), | |
fa3e7036 | 1232 | "%s internal A/V decoder", cx->v4l2_dev.name); |
ff2a2001 AW |
1233 | sd->grp_id = CX18_HW_418_AV; |
1234 | return v4l2_device_register_subdev(&cx->v4l2_dev, sd); | |
1a267046 AW |
1235 | } |
1236 | ||
fa3e7036 | 1237 | void cx18_av_exit(struct cx18 *cx, struct v4l2_subdev *sd) |
1a267046 AW |
1238 | { |
1239 | v4l2_device_unregister_subdev(&cx->av_state.sd); | |
1240 | } |