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V4L/DVB (10853): cx18: Fix s-parse warnings and a logic error about extracting the...
[linux-block.git] / drivers / media / video / cx18 / cx18-av-core.c
CommitLineData
1c1e45d1
HV		 1/*
2 * cx18 ADEC audio functions
3 *
4 * Derived from cx25840-core.c
5 *
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
1ed9dcc8 7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
1c1e45d1
HV		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 * 02110-1301, USA.
23 */
24
1a267046 25#include <media/v4l2-chip-ident.h>
1c1e45d1 26#include "cx18-driver.h"
b1526421 27#include "cx18-io.h"
1a267046 28#include "cx18-cards.h"
1c1e45d1
HV		 29
30int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
31{
b1526421 32 u32 reg = 0xc40000 + (addr & ~3);
1c1e45d1
HV		 33 u32 mask = 0xff;
34 int shift = (addr & 3) * 8;
b1526421 35 u32 x = cx18_read_reg(cx, reg);
1c1e45d1
HV		 36
37 x = (x & ~(mask << shift)) | ((u32)value << shift);
b1526421 38 cx18_write_reg(cx, x, reg);
1c1e45d1
HV		 39 return 0;
40}
41
ced07371
AW		 42int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
43{
44 u32 reg = 0xc40000 + (addr & ~3);
45 int shift = (addr & 3) * 8;
46 u32 x = cx18_read_reg(cx, reg);
47
48 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
49 cx18_write_reg_expect(cx, x, reg,
50 ((u32)eval << shift), ((u32)mask << shift));
51 return 0;
52}
53
1c1e45d1
HV		 54int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
55{
b1526421 56 cx18_write_reg(cx, value, 0xc40000 + addr);
1c1e45d1
HV		 57 return 0;
58}
59
ced07371
AW		 60int
61cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
62{
63 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
64 return 0;
65}
66
d267d851
AW		 67int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
68{
69 cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
70 return 0;
71}
72
1c1e45d1
HV		 73u8 cx18_av_read(struct cx18 *cx, u16 addr)
74{
b1526421 75 u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
1c1e45d1
HV		 76 int shift = (addr & 3) * 8;
77
78 return (x >> shift) & 0xff;
79}
80
81u32 cx18_av_read4(struct cx18 *cx, u16 addr)
82{
b1526421 83 return cx18_read_reg(cx, 0xc40000 + addr);
1c1e45d1
HV		 84}
85
86int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
87 u8 or_value)
88{
89 return cx18_av_write(cx, addr,
90 (cx18_av_read(cx, addr) & and_mask) |
91 or_value);
92}
93
94int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
95 u32 or_value)
96{
97 return cx18_av_write4(cx, addr,
98 (cx18_av_read4(cx, addr) & and_mask) |
99 or_value);
100}
101
1c1e45d1
HV		 102static void cx18_av_initialize(struct cx18 *cx)
103{
ca130eef 104 struct cx18_av_state *state = &cx->av_state;
1c1e45d1
HV		 105 u32 v;
106
107 cx18_av_loadfw(cx);
108 /* Stop 8051 code execution */
ced07371
AW		 109 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
110 0x03000000, 0x13000000);
1c1e45d1
HV		 111
112 /* initallize the PLL by toggling sleep bit */
113 v = cx18_av_read4(cx, CXADEC_HOST_REG1);
ced07371
AW		 114 /* enable sleep mode - register appears to be read only... */
115 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
1c1e45d1 116 /* disable sleep mode */
ced07371
AW		 117 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
118 v & 0xfffe, 0xffff);
1c1e45d1
HV		 119
120 /* initialize DLLs */
121 v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
122 /* disable FLD */
123 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
124 /* enable FLD */
125 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
126
127 v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
128 /* disable FLD */
129 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
130 /* enable FLD */
131 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
132
133 /* set analog bias currents. Set Vreg to 1.20V. */
134 cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
135
136 v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
137 /* enable TUNE_FIL_RST */
ced07371 138 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
1c1e45d1 139 /* disable TUNE_FIL_RST */
ced07371
AW		 140 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
141 v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
1c1e45d1
HV		 142
143 /* enable 656 output */
144 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
145
146 /* video output drive strength */
147 cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
148
149 /* reset video */
150 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
151 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
152
153 /* set video to auto-detect */
154 /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */
155 /* set the comb notch = 1 */
156 cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
157
158 /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
159 /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
160 cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
161
162 /* Set VGA_TRACK_RANGE to 0x20 */
163 cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
164
302df970
AW		 165 /*
166 * Initial VBI setup
167 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
812b1f9d
AW		 168 * don't clamp raw samples when codes are in use, 1 byte user D-words,
169 * IDID0 has line #, RP code V bit transition on VBLANK, data during
302df970
AW		 170 * blanking intervals
171 */
812b1f9d 172 cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
1c1e45d1
HV		 173
174 /* Set the video input.
175 The setting in MODE_CTRL gets lost when we do the above setup */
176 /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
177 /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
178
179 v = cx18_av_read4(cx, CXADEC_AFE_CTRL);
180 v &= 0xFFFBFFFF; /* turn OFF bit 18 for droop_comp_ch1 */
181 v &= 0xFFFF7FFF; /* turn OFF bit 9 for clamp_sel_ch1 */
182 v &= 0xFFFFFFFE; /* turn OFF bit 0 for 12db_ch1 */
183 /* v |= 0x00000001;*/ /* turn ON bit 0 for 12db_ch1 */
184 cx18_av_write4(cx, CXADEC_AFE_CTRL, v);
185
186/* if(dwEnable && dw3DCombAvailable) { */
187/* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
188/* } else { */
189/* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
190/* } */
191 cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
ca130eef
HV		 192 state->default_volume = 228 - cx18_av_read(cx, 0x8d4);
193 state->default_volume = ((state->default_volume / 2) + 23) << 9;
1c1e45d1
HV		 194}
195
1a267046
AW		 196static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
197{
198 struct cx18 *cx = v4l2_get_subdevdata(sd);
199
200 cx18_av_initialize(cx);
201 return 0;
202}
203
fa3e7036 204static int cx18_av_init(struct v4l2_subdev *sd, u32 val)
1a267046
AW		 205{
206 struct cx18_av_state *state = to_cx18_av_state(sd);
207 struct cx18 *cx = v4l2_get_subdevdata(sd);
208
fa3e7036
AW		 209 switch (val) {
210 case CX18_AV_INIT_PLLS:
211 /*
212 * The crystal freq used in calculations in this driver will be
213 * 28.636360 MHz.
214 * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
215 */
216
217 /*
218 * VDCLK Integer = 0x0f, Post Divider = 0x04
219 * AIMCLK Integer = 0x0e, Post Divider = 0x16
220 */
221 cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
222
223 /* VDCLK Fraction = 0x2be2fe */
224 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
225 cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
226
227 /* AIMCLK Fraction = 0x05227ad */
228 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
229 cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
230
231 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
232 cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
233 break;
234
235 case CX18_AV_INIT_NORMAL:
236 default:
237 if (!state->is_initialized) {
238 /* initialize on first use */
239 state->is_initialized = 1;
240 cx18_av_initialize(cx);
241 }
242 break;
1a267046
AW		 243 }
244 return 0;
245}
1c1e45d1 246
03b52c36
HV		 247void cx18_av_std_setup(struct cx18 *cx)
248{
249 struct cx18_av_state *state = &cx->av_state;
6246d4e1 250 struct v4l2_subdev *sd = &state->sd;
03b52c36
HV		 251 v4l2_std_id std = state->std;
252 int hblank, hactive, burst, vblank, vactive, sc;
253 int vblank656, src_decimation;
254 int luma_lpf, uv_lpf, comb;
255 u32 pll_int, pll_frac, pll_post;
256
257 /* datasheet startup, step 8d */
258 if (std & ~V4L2_STD_NTSC)
259 cx18_av_write(cx, 0x49f, 0x11);
260 else
261 cx18_av_write(cx, 0x49f, 0x14);
262
263 if (std & V4L2_STD_625_50) {
812b1f9d 264 /* FIXME - revisit these for Sliced VBI */
03b52c36
HV		 265 hblank = 132;
266 hactive = 720;
267 burst = 93;
268 vblank = 36;
269 vactive = 580;
270 vblank656 = 40;
271 src_decimation = 0x21f;
272
273 luma_lpf = 2;
274 if (std & V4L2_STD_PAL) {
275 uv_lpf = 1;
276 comb = 0x20;
277 sc = 688739;
278 } else if (std == V4L2_STD_PAL_Nc) {
279 uv_lpf = 1;
280 comb = 0x20;
281 sc = 556453;
282 } else { /* SECAM */
283 uv_lpf = 0;
284 comb = 0;
285 sc = 672351;
286 }
287 } else {
812b1f9d
AW		 288 /*
289 * The following relationships of half line counts should hold:
290 * 525 = vsync + vactive + vblank656
291 * 12 = vblank656 - vblank
292 *
293 * vsync: always 6 half-lines of vsync pulses
294 * vactive: half lines of active video
295 * vblank656: half lines, after line 3, of blanked video
296 * vblank: half lines, after line 9, of blanked video
297 *
298 * vblank656 starts counting from the falling edge of the first
299 * vsync pulse (start of line 4)
300 * vblank starts counting from the after the 6 vsync pulses and
301 * 6 equalization pulses (start of line 10)
302 *
303 * For 525 line systems the driver will extract VBI information
304 * from lines 10 through 21. To avoid the EAV RP code from
305 * toggling at the start of hblank at line 22, where sliced VBI
306 * data from line 21 is stuffed, also treat line 22 as blanked.
307 */
308 vblank656 = 38; /* lines 4 through 22 */
309 vblank = 26; /* lines 10 through 22 */
310 vactive = 481; /* lines 23 through 262.5 */
311
03b52c36
HV		 312 hactive = 720;
313 hblank = 122;
03b52c36
HV		 314 luma_lpf = 1;
315 uv_lpf = 1;
03b52c36
HV		 316
317 src_decimation = 0x21f;
318 if (std == V4L2_STD_PAL_60) {
319 burst = 0x5b;
320 luma_lpf = 2;
321 comb = 0x20;
322 sc = 688739;
323 } else if (std == V4L2_STD_PAL_M) {
324 burst = 0x61;
325 comb = 0x20;
326 sc = 555452;
327 } else {
328 burst = 0x5b;
329 comb = 0x66;
330 sc = 556063;
331 }
332 }
333
334 /* DEBUG: Displays configured PLL frequency */
335 pll_int = cx18_av_read(cx, 0x108);
336 pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
337 pll_post = cx18_av_read(cx, 0x109);
6246d4e1
AW		 338 CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n",
339 pll_int, pll_frac, pll_post);
03b52c36
HV		 340
341 if (pll_post) {
f4167342 342 int fin, fsc, pll;
03b52c36 343
55d81aa5 344 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
03b52c36 345 pll /= pll_post;
6246d4e1
AW		 346 CX18_DEBUG_INFO_DEV(sd, "PLL = %d.%06d MHz\n",
347 pll / 1000000, pll % 1000000);
348 CX18_DEBUG_INFO_DEV(sd, "PLL/8 = %d.%06d MHz\n",
349 pll / 8000000, (pll / 8) % 1000000);
03b52c36
HV		 350
351 fin = ((u64)src_decimation * pll) >> 12;
6246d4e1
AW		 352 CX18_DEBUG_INFO_DEV(sd, "ADC Sampling freq = %d.%06d MHz\n",
353 fin / 1000000, fin % 1000000);
03b52c36
HV		 354
355 fsc = (((u64)sc) * pll) >> 24L;
6246d4e1
AW		 356 CX18_DEBUG_INFO_DEV(sd,
357 "Chroma sub-carrier freq = %d.%06d MHz\n",
358 fsc / 1000000, fsc % 1000000);
359
360 CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, "
361 "vactive %i, vblank656 %i, src_dec %i, "
362 "burst 0x%02x, luma_lpf %i, uv_lpf %i, "
363 "comb 0x%02x, sc 0x%06x\n",
364 hblank, hactive, vblank, vactive, vblank656,
365 src_decimation, burst, luma_lpf, uv_lpf,
366 comb, sc);
03b52c36
HV		 367 }
368
369 /* Sets horizontal blanking delay and active lines */
370 cx18_av_write(cx, 0x470, hblank);
371 cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) |
372 (hactive << 4)));
373 cx18_av_write(cx, 0x472, hactive >> 4);
374
375 /* Sets burst gate delay */
376 cx18_av_write(cx, 0x473, burst);
377
378 /* Sets vertical blanking delay and active duration */
379 cx18_av_write(cx, 0x474, vblank);
380 cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) |
381 (vactive << 4)));
382 cx18_av_write(cx, 0x476, vactive >> 4);
383 cx18_av_write(cx, 0x477, vblank656);
384
385 /* Sets src decimation rate */
386 cx18_av_write(cx, 0x478, 0xff & src_decimation);
387 cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8));
388
389 /* Sets Luma and UV Low pass filters */
390 cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
391
392 /* Enables comb filters */
393 cx18_av_write(cx, 0x47b, comb);
394
395 /* Sets SC Step*/
396 cx18_av_write(cx, 0x47c, sc);
397 cx18_av_write(cx, 0x47d, 0xff & sc >> 8);
398 cx18_av_write(cx, 0x47e, 0xff & sc >> 16);
399
03b52c36 400 if (std & V4L2_STD_625_50) {
812b1f9d
AW		 401 state->slicer_line_delay = 1;
402 state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
03b52c36 403 } else {
812b1f9d
AW		 404 state->slicer_line_delay = 0;
405 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
03b52c36 406 }
812b1f9d 407 cx18_av_write(cx, 0x47f, state->slicer_line_delay);
03b52c36
HV		 408}
409
1a267046
AW		 410static int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
411 struct v4l2_decode_vbi_line *vbi_line)
412{
413 struct cx18 *cx = v4l2_get_subdevdata(sd);
414 return cx18_av_vbi(cx, VIDIOC_INT_DECODE_VBI_LINE, vbi_line);
415}
416
417static int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
418{
419 struct cx18 *cx = v4l2_get_subdevdata(sd);
420 return cx18_av_audio(cx, VIDIOC_INT_AUDIO_CLOCK_FREQ, &freq);
421}
03b52c36 422
1c1e45d1
HV		 423static void input_change(struct cx18 *cx)
424{
425 struct cx18_av_state *state = &cx->av_state;
426 v4l2_std_id std = state->std;
ced07371 427 u8 v;
1c1e45d1
HV		 428
429 /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
c1738904
HV		 430 cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
431 cx18_av_and_or(cx, 0x401, ~0x60, 0);
432 cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
1c1e45d1
HV		 433
434 if (std & V4L2_STD_525_60) {
435 if (std == V4L2_STD_NTSC_M_JP) {
436 /* Japan uses EIAJ audio standard */
ced07371
AW		 437 cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
438 cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
1c1e45d1
HV		 439 } else if (std == V4L2_STD_NTSC_M_KR) {
440 /* South Korea uses A2 audio standard */
ced07371
AW		 441 cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
442 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
1c1e45d1
HV		 443 } else {
444 /* Others use the BTSC audio standard */
ced07371
AW		 445 cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
446 cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
1c1e45d1 447 }
1c1e45d1
HV		 448 } else if (std & V4L2_STD_PAL) {
449 /* Follow tuner change procedure for PAL */
ced07371
AW		 450 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
451 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
1c1e45d1
HV		 452 } else if (std & V4L2_STD_SECAM) {
453 /* Select autodetect for SECAM */
ced07371
AW		 454 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
455 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
1c1e45d1
HV		 456 }
457
ced07371
AW		 458 v = cx18_av_read(cx, 0x803);
459 if (v & 0x10) {
1c1e45d1 460 /* restart audio decoder microcontroller */
ced07371
AW		 461 v &= ~0x10;
462 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
463 v |= 0x10;
464 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
1c1e45d1
HV		 465 }
466}
467
1a267046
AW		 468static int cx18_av_s_frequency(struct v4l2_subdev *sd,
469 struct v4l2_frequency *freq)
470{
471 struct cx18 *cx = v4l2_get_subdevdata(sd);
472 input_change(cx);
473 return 0;
474}
475
1c1e45d1
HV		 476static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
477 enum cx18_av_audio_input aud_input)
478{
479 struct cx18_av_state *state = &cx->av_state;
6246d4e1 480 struct v4l2_subdev *sd = &state->sd;
1c1e45d1
HV		 481 u8 is_composite = (vid_input >= CX18_AV_COMPOSITE1 &&
482 vid_input <= CX18_AV_COMPOSITE8);
483 u8 reg;
ced07371 484 u8 v;
1c1e45d1 485
6246d4e1
AW		 486 CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n",
487 vid_input, aud_input);
1c1e45d1
HV		 488
489 if (is_composite) {
490 reg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
491 } else {
492 int luma = vid_input & 0xf0;
493 int chroma = vid_input & 0xf00;
494
495 if ((vid_input & ~0xff0) ||
496 luma < CX18_AV_SVIDEO_LUMA1 ||
45270a15 497 luma > CX18_AV_SVIDEO_LUMA8 ||
1c1e45d1
HV		 498 chroma < CX18_AV_SVIDEO_CHROMA4 ||
499 chroma > CX18_AV_SVIDEO_CHROMA8) {
6246d4e1
AW		 500 CX18_ERR_DEV(sd, "0x%04x is not a valid video input!\n",
501 vid_input);
1c1e45d1
HV		 502 return -EINVAL;
503 }
504 reg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
505 if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
506 reg &= 0x3f;
507 reg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
508 } else {
509 reg &= 0xcf;
510 reg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
511 }
512 }
513
514 switch (aud_input) {
81cb727d
HV		 515 case CX18_AV_AUDIO_SERIAL1:
516 case CX18_AV_AUDIO_SERIAL2:
1c1e45d1
HV		 517 /* do nothing, use serial audio input */
518 break;
519 case CX18_AV_AUDIO4: reg &= ~0x30; break;
520 case CX18_AV_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
521 case CX18_AV_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
522 case CX18_AV_AUDIO7: reg &= ~0xc0; break;
523 case CX18_AV_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
524
525 default:
6246d4e1
AW		 526 CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n",
527 aud_input);
1c1e45d1
HV		 528 return -EINVAL;
529 }
530
ced07371 531 cx18_av_write_expect(cx, 0x103, reg, reg, 0xf7);
1c1e45d1 532 /* Set INPUT_MODE to Composite (0) or S-Video (1) */
c1738904 533 cx18_av_and_or(cx, 0x401, ~0x6, is_composite ? 0 : 0x02);
ced07371 534
1c1e45d1 535 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
ced07371
AW		 536 v = cx18_av_read(cx, 0x102);
537 if (reg & 0x80)
538 v &= ~0x2;
539 else
540 v |= 0x2;
1c1e45d1
HV		 541 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
542 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
ced07371 543 v |= 0x4;
1c1e45d1 544 else
ced07371
AW		 545 v &= ~0x4;
546 cx18_av_write_expect(cx, 0x102, v, v, 0x17);
547
1c1e45d1
HV		 548 /*cx18_av_and_or4(cx, 0x104, ~0x001b4180, 0x00004180);*/
549
550 state->vid_input = vid_input;
551 state->aud_input = aud_input;
552 cx18_av_audio_set_path(cx);
553 input_change(cx);
554 return 0;
555}
556
1a267046
AW		 557static int cx18_av_s_video_routing(struct v4l2_subdev *sd,
558 const struct v4l2_routing *route)
559{
560 struct cx18_av_state *state = to_cx18_av_state(sd);
561 struct cx18 *cx = v4l2_get_subdevdata(sd);
562 return set_input(cx, route->input, state->aud_input);
563}
1c1e45d1 564
1a267046
AW		 565static int cx18_av_s_audio_routing(struct v4l2_subdev *sd,
566 const struct v4l2_routing *route)
1c1e45d1 567{
1a267046
AW		 568 struct cx18_av_state *state = to_cx18_av_state(sd);
569 struct cx18 *cx = v4l2_get_subdevdata(sd);
570 return set_input(cx, state->vid_input, route->input);
571}
572
573static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
574{
575 struct cx18_av_state *state = to_cx18_av_state(sd);
576 struct cx18 *cx = v4l2_get_subdevdata(sd);
577 u8 vpres;
578 u8 mode;
579 int val = 0;
580
581 if (state->radio)
582 return 0;
583
584 vpres = cx18_av_read(cx, 0x40e) & 0x20;
585 vt->signal = vpres ? 0xffff : 0x0;
586
587 vt->capability |=
588 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
589 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
590
591 mode = cx18_av_read(cx, 0x804);
592
593 /* get rxsubchans and audmode */
594 if ((mode & 0xf) == 1)
595 val |= V4L2_TUNER_SUB_STEREO;
596 else
597 val |= V4L2_TUNER_SUB_MONO;
598
599 if (mode == 2 || mode == 4)
600 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
601
602 if (mode & 0x10)
603 val |= V4L2_TUNER_SUB_SAP;
604
605 vt->rxsubchans = val;
606 vt->audmode = state->audmode;
607 return 0;
608}
609
610static int cx18_av_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
611{
612 struct cx18_av_state *state = to_cx18_av_state(sd);
613 struct cx18 *cx = v4l2_get_subdevdata(sd);
614 u8 v;
615
616 if (state->radio)
617 return 0;
618
619 v = cx18_av_read(cx, 0x809);
620 v &= ~0xf;
621
622 switch (vt->audmode) {
623 case V4L2_TUNER_MODE_MONO:
624 /* mono -> mono
625 stereo -> mono
626 bilingual -> lang1 */
627 break;
628 case V4L2_TUNER_MODE_STEREO:
629 case V4L2_TUNER_MODE_LANG1:
630 /* mono -> mono
631 stereo -> stereo
632 bilingual -> lang1 */
633 v |= 0x4;
634 break;
635 case V4L2_TUNER_MODE_LANG1_LANG2:
636 /* mono -> mono
637 stereo -> stereo
638 bilingual -> lang1/lang2 */
639 v |= 0x7;
640 break;
641 case V4L2_TUNER_MODE_LANG2:
642 /* mono -> mono
643 stereo -> stereo
644 bilingual -> lang2 */
645 v |= 0x1;
646 break;
647 default:
648 return -EINVAL;
649 }
650 cx18_av_write_expect(cx, 0x809, v, v, 0xff);
651 state->audmode = vt->audmode;
652 return 0;
653}
654
655static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
656{
657 struct cx18_av_state *state = to_cx18_av_state(sd);
658 struct cx18 *cx = v4l2_get_subdevdata(sd);
659
1c1e45d1
HV		 660 u8 fmt = 0; /* zero is autodetect */
661 u8 pal_m = 0;
662
1a267046
AW		 663 if (state->radio == 0 && state->std == norm)
664 return 0;
665
666 state->radio = 0;
667 state->std = norm;
668
1c1e45d1
HV		 669 /* First tests should be against specific std */
670 if (state->std == V4L2_STD_NTSC_M_JP) {
671 fmt = 0x2;
672 } else if (state->std == V4L2_STD_NTSC_443) {
673 fmt = 0x3;
674 } else if (state->std == V4L2_STD_PAL_M) {
675 pal_m = 1;
676 fmt = 0x5;
677 } else if (state->std == V4L2_STD_PAL_N) {
678 fmt = 0x6;
679 } else if (state->std == V4L2_STD_PAL_Nc) {
680 fmt = 0x7;
681 } else if (state->std == V4L2_STD_PAL_60) {
682 fmt = 0x8;
683 } else {
684 /* Then, test against generic ones */
685 if (state->std & V4L2_STD_NTSC)
686 fmt = 0x1;
687 else if (state->std & V4L2_STD_PAL)
688 fmt = 0x4;
689 else if (state->std & V4L2_STD_SECAM)
690 fmt = 0xc;
691 }
692
6246d4e1 693 CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt);
1c1e45d1
HV		 694
695 /* Follow step 9 of section 3.16 in the cx18_av datasheet.
696 Without this PAL may display a vertical ghosting effect.
697 This happens for example with the Yuan MPC622. */
698 if (fmt >= 4 && fmt < 8) {
699 /* Set format to NTSC-M */
c1738904 700 cx18_av_and_or(cx, 0x400, ~0xf, 1);
1c1e45d1
HV		 701 /* Turn off LCOMB */
702 cx18_av_and_or(cx, 0x47b, ~6, 0);
703 }
c1738904
HV		 704 cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
705 cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
03b52c36 706 cx18_av_std_setup(cx);
1c1e45d1
HV		 707 input_change(cx);
708 return 0;
709}
710
1a267046
AW		 711static int cx18_av_s_radio(struct v4l2_subdev *sd)
712{
713 struct cx18_av_state *state = to_cx18_av_state(sd);
714 state->radio = 1;
715 return 0;
716}
1c1e45d1 717
1a267046 718static int cx18_av_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1c1e45d1 719{
1a267046
AW		 720 struct cx18 *cx = v4l2_get_subdevdata(sd);
721
1c1e45d1
HV		 722 switch (ctrl->id) {
723 case V4L2_CID_BRIGHTNESS:
724 if (ctrl->value < 0 || ctrl->value > 255) {
6246d4e1
AW		 725 CX18_ERR_DEV(sd, "invalid brightness setting %d\n",
726 ctrl->value);
1c1e45d1
HV		 727 return -ERANGE;
728 }
729
730 cx18_av_write(cx, 0x414, ctrl->value - 128);
731 break;
732
733 case V4L2_CID_CONTRAST:
734 if (ctrl->value < 0 || ctrl->value > 127) {
6246d4e1
AW		 735 CX18_ERR_DEV(sd, "invalid contrast setting %d\n",
736 ctrl->value);
1c1e45d1
HV		 737 return -ERANGE;
738 }
739
740 cx18_av_write(cx, 0x415, ctrl->value << 1);
741 break;
742
743 case V4L2_CID_SATURATION:
744 if (ctrl->value < 0 || ctrl->value > 127) {
6246d4e1
AW		 745 CX18_ERR_DEV(sd, "invalid saturation setting %d\n",
746 ctrl->value);
1c1e45d1
HV		 747 return -ERANGE;
748 }
749
750 cx18_av_write(cx, 0x420, ctrl->value << 1);
751 cx18_av_write(cx, 0x421, ctrl->value << 1);
752 break;
753
754 case V4L2_CID_HUE:
de6476f5 755 if (ctrl->value < -128 || ctrl->value > 127) {
6246d4e1
AW		 756 CX18_ERR_DEV(sd, "invalid hue setting %d\n",
757 ctrl->value);
1c1e45d1
HV		 758 return -ERANGE;
759 }
760
761 cx18_av_write(cx, 0x422, ctrl->value);
762 break;
763
764 case V4L2_CID_AUDIO_VOLUME:
765 case V4L2_CID_AUDIO_BASS:
766 case V4L2_CID_AUDIO_TREBLE:
767 case V4L2_CID_AUDIO_BALANCE:
768 case V4L2_CID_AUDIO_MUTE:
769 return cx18_av_audio(cx, VIDIOC_S_CTRL, ctrl);
770
771 default:
772 return -EINVAL;
773 }
1c1e45d1
HV		 774 return 0;
775}
776
1a267046 777static int cx18_av_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1c1e45d1 778{
1a267046
AW		 779 struct cx18 *cx = v4l2_get_subdevdata(sd);
780
1c1e45d1
HV		 781 switch (ctrl->id) {
782 case V4L2_CID_BRIGHTNESS:
783 ctrl->value = (s8)cx18_av_read(cx, 0x414) + 128;
784 break;
785 case V4L2_CID_CONTRAST:
786 ctrl->value = cx18_av_read(cx, 0x415) >> 1;
787 break;
788 case V4L2_CID_SATURATION:
789 ctrl->value = cx18_av_read(cx, 0x420) >> 1;
790 break;
791 case V4L2_CID_HUE:
792 ctrl->value = (s8)cx18_av_read(cx, 0x422);
793 break;
794 case V4L2_CID_AUDIO_VOLUME:
795 case V4L2_CID_AUDIO_BASS:
796 case V4L2_CID_AUDIO_TREBLE:
797 case V4L2_CID_AUDIO_BALANCE:
798 case V4L2_CID_AUDIO_MUTE:
799 return cx18_av_audio(cx, VIDIOC_G_CTRL, ctrl);
800 default:
801 return -EINVAL;
802 }
1c1e45d1
HV		 803 return 0;
804}
805
1a267046
AW		 806static int cx18_av_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
807{
808 struct cx18_av_state *state = to_cx18_av_state(sd);
809
810 switch (qc->id) {
811 case V4L2_CID_BRIGHTNESS:
812 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
813 case V4L2_CID_CONTRAST:
814 case V4L2_CID_SATURATION:
815 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
816 case V4L2_CID_HUE:
817 return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0);
818 default:
819 break;
820 }
821
822 switch (qc->id) {
823 case V4L2_CID_AUDIO_VOLUME:
824 return v4l2_ctrl_query_fill(qc, 0, 65535,
825 65535 / 100, state->default_volume);
826 case V4L2_CID_AUDIO_MUTE:
827 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
828 case V4L2_CID_AUDIO_BALANCE:
829 case V4L2_CID_AUDIO_BASS:
830 case V4L2_CID_AUDIO_TREBLE:
831 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
832 default:
833 return -EINVAL;
834 }
835 return -EINVAL;
836}
1c1e45d1 837
1a267046 838static int cx18_av_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
1c1e45d1 839{
1a267046
AW		 840 struct cx18 *cx = v4l2_get_subdevdata(sd);
841
1c1e45d1
HV		 842 switch (fmt->type) {
843 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
844 return cx18_av_vbi(cx, VIDIOC_G_FMT, fmt);
845 default:
846 return -EINVAL;
847 }
1c1e45d1
HV		 848 return 0;
849}
850
1a267046 851static int cx18_av_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
1c1e45d1 852{
1a267046
AW		 853 struct cx18_av_state *state = to_cx18_av_state(sd);
854 struct cx18 *cx = v4l2_get_subdevdata(sd);
855
1c1e45d1
HV		 856 struct v4l2_pix_format *pix;
857 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
858 int is_50Hz = !(state->std & V4L2_STD_525_60);
859
860 switch (fmt->type) {
861 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
862 pix = &(fmt->fmt.pix);
863
864 Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
865 Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
866
867 Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
868 Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
869
72401b7a
AW		 870 /*
871 * This adjustment reflects the excess of vactive, set in
872 * cx18_av_std_setup(), above standard values:
873 *
874 * 480 + 1 for 60 Hz systems
875 * 576 + 4 for 50 Hz systems
876 */
877 Vlines = pix->height + (is_50Hz ? 4 : 1);
1c1e45d1 878
72401b7a
AW		 879 /*
880 * Invalid height and width scaling requests are:
881 * 1. width less than 1/16 of the source width
882 * 2. width greater than the source width
883 * 3. height less than 1/8 of the source height
884 * 4. height greater than the source height
885 */
1c1e45d1
HV		 886 if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) ||
887 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
6246d4e1
AW		 888 CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n",
889 pix->width, pix->height);
1c1e45d1
HV		 890 return -ERANGE;
891 }
892
893 HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20);
894 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
895 VSC &= 0x1fff;
896
897 if (pix->width >= 385)
898 filter = 0;
899 else if (pix->width > 192)
900 filter = 1;
901 else if (pix->width > 96)
902 filter = 2;
903 else
904 filter = 3;
905
6246d4e1
AW		 906 CX18_DEBUG_INFO_DEV(sd,
907 "decoder set size %dx%d -> scale %ux%u\n",
908 pix->width, pix->height, HSC, VSC);
1c1e45d1
HV		 909
910 /* HSCALE=HSC */
911 cx18_av_write(cx, 0x418, HSC & 0xff);
912 cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
913 cx18_av_write(cx, 0x41a, HSC >> 16);
914 /* VSCALE=VSC */
915 cx18_av_write(cx, 0x41c, VSC & 0xff);
916 cx18_av_write(cx, 0x41d, VSC >> 8);
917 /* VS_INTRLACE=1 VFILT=filter */
918 cx18_av_write(cx, 0x41e, 0x8 | filter);
919 break;
920
921 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
922 return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt);
923
924 case V4L2_BUF_TYPE_VBI_CAPTURE:
925 return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt);
926
927 default:
928 return -EINVAL;
929 }
1c1e45d1
HV		 930 return 0;
931}
932
1a267046 933static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable)
e474200d 934{
1a267046 935 struct cx18 *cx = v4l2_get_subdevdata(sd);
1c1e45d1 936
6246d4e1 937 CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable");
1a267046 938 if (enable) {
1c1e45d1
HV		 939 cx18_av_write(cx, 0x115, 0x8c);
940 cx18_av_write(cx, 0x116, 0x07);
1a267046 941 } else {
1c1e45d1
HV		 942 cx18_av_write(cx, 0x115, 0x00);
943 cx18_av_write(cx, 0x116, 0x00);
1c1e45d1 944 }
1c1e45d1
HV		 945 return 0;
946}
947
1c1e45d1
HV		 948static void log_video_status(struct cx18 *cx)
949{
950 static const char *const fmt_strs[] = {
951 "0x0",
952 "NTSC-M", "NTSC-J", "NTSC-4.43",
953 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
954 "0x9", "0xA", "0xB",
955 "SECAM",
956 "0xD", "0xE", "0xF"
957 };
958
959 struct cx18_av_state *state = &cx->av_state;
6246d4e1 960 struct v4l2_subdev *sd = &state->sd;
1c1e45d1
HV		 961 u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
962 u8 gen_stat1 = cx18_av_read(cx, 0x40d);
963 u8 gen_stat2 = cx18_av_read(cx, 0x40e);
964 int vid_input = state->vid_input;
965
6246d4e1
AW		 966 CX18_INFO_DEV(sd, "Video signal: %spresent\n",
967 (gen_stat2 & 0x20) ? "" : "not ");
968 CX18_INFO_DEV(sd, "Detected format: %s\n",
969 fmt_strs[gen_stat1 & 0xf]);
1c1e45d1 970
6246d4e1
AW		 971 CX18_INFO_DEV(sd, "Specified standard: %s\n",
972 vidfmt_sel ? fmt_strs[vidfmt_sel]
973 : "automatic detection");
1c1e45d1
HV		 974
975 if (vid_input >= CX18_AV_COMPOSITE1 &&
976 vid_input <= CX18_AV_COMPOSITE8) {
6246d4e1
AW		 977 CX18_INFO_DEV(sd, "Specified video input: Composite %d\n",
978 vid_input - CX18_AV_COMPOSITE1 + 1);
1c1e45d1 979 } else {
6246d4e1
AW		 980 CX18_INFO_DEV(sd, "Specified video input: "
981 "S-Video (Luma In%d, Chroma In%d)\n",
982 (vid_input & 0xf0) >> 4,
983 (vid_input & 0xf00) >> 8);
1c1e45d1
HV		 984 }
985
6246d4e1
AW		 986 CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n",
987 state->audclk_freq);
1c1e45d1
HV		 988}
989
1c1e45d1
HV		 990static void log_audio_status(struct cx18 *cx)
991{
992 struct cx18_av_state *state = &cx->av_state;
6246d4e1 993 struct v4l2_subdev *sd = &state->sd;
1c1e45d1 994 u8 download_ctl = cx18_av_read(cx, 0x803);
63b8c709
HV		 995 u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
996 u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
1c1e45d1
HV		 997 u8 audio_config = cx18_av_read(cx, 0x808);
998 u8 pref_mode = cx18_av_read(cx, 0x809);
999 u8 afc0 = cx18_av_read(cx, 0x80b);
1000 u8 mute_ctl = cx18_av_read(cx, 0x8d3);
1001 int aud_input = state->aud_input;
1002 char *p;
1003
1004 switch (mod_det_stat0) {
1005 case 0x00: p = "mono"; break;
1006 case 0x01: p = "stereo"; break;
1007 case 0x02: p = "dual"; break;
1008 case 0x04: p = "tri"; break;
1009 case 0x10: p = "mono with SAP"; break;
1010 case 0x11: p = "stereo with SAP"; break;
1011 case 0x12: p = "dual with SAP"; break;
1012 case 0x14: p = "tri with SAP"; break;
1013 case 0xfe: p = "forced mode"; break;
63b8c709 1014 default: p = "not defined"; break;
1c1e45d1 1015 }
6246d4e1 1016 CX18_INFO_DEV(sd, "Detected audio mode: %s\n", p);
1c1e45d1
HV		 1017
1018 switch (mod_det_stat1) {
63b8c709 1019 case 0x00: p = "not defined"; break;
1c1e45d1
HV		 1020 case 0x01: p = "EIAJ"; break;
1021 case 0x02: p = "A2-M"; break;
1022 case 0x03: p = "A2-BG"; break;
1023 case 0x04: p = "A2-DK1"; break;
1024 case 0x05: p = "A2-DK2"; break;
1025 case 0x06: p = "A2-DK3"; break;
1026 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1027 case 0x08: p = "AM-L"; break;
1028 case 0x09: p = "NICAM-BG"; break;
1029 case 0x0a: p = "NICAM-DK"; break;
1030 case 0x0b: p = "NICAM-I"; break;
1031 case 0x0c: p = "NICAM-L"; break;
1032 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
63b8c709
HV		 1033 case 0x0e: p = "IF FM Radio"; break;
1034 case 0x0f: p = "BTSC"; break;
1035 case 0x10: p = "detected chrominance"; break;
1036 case 0xfd: p = "unknown audio standard"; break;
1037 case 0xfe: p = "forced audio standard"; break;
1c1e45d1 1038 case 0xff: p = "no detected audio standard"; break;
63b8c709 1039 default: p = "not defined"; break;
1c1e45d1 1040 }
6246d4e1
AW		 1041 CX18_INFO_DEV(sd, "Detected audio standard: %s\n", p);
1042 CX18_INFO_DEV(sd, "Audio muted: %s\n",
1043 (mute_ctl & 0x2) ? "yes" : "no");
1044 CX18_INFO_DEV(sd, "Audio microcontroller: %s\n",
1045 (download_ctl & 0x10) ? "running" : "stopped");
1c1e45d1
HV		 1046
1047 switch (audio_config >> 4) {
63b8c709
HV		 1048 case 0x00: p = "undefined"; break;
1049 case 0x01: p = "BTSC"; break;
1050 case 0x02: p = "EIAJ"; break;
1051 case 0x03: p = "A2-M"; break;
1052 case 0x04: p = "A2-BG"; break;
1053 case 0x05: p = "A2-DK1"; break;
1054 case 0x06: p = "A2-DK2"; break;
1055 case 0x07: p = "A2-DK3"; break;
1056 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1057 case 0x09: p = "AM-L"; break;
1058 case 0x0a: p = "NICAM-BG"; break;
1059 case 0x0b: p = "NICAM-DK"; break;
1060 case 0x0c: p = "NICAM-I"; break;
1061 case 0x0d: p = "NICAM-L"; break;
1062 case 0x0e: p = "FM radio"; break;
1c1e45d1 1063 case 0x0f: p = "automatic detection"; break;
63b8c709 1064 default: p = "undefined"; break;
1c1e45d1 1065 }
6246d4e1 1066 CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p);
1c1e45d1
HV		 1067
1068 if ((audio_config >> 4) < 0xF) {
1069 switch (audio_config & 0xF) {
1070 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1071 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1072 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1073 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1074 case 0x04: p = "STEREO"; break;
63b8c709
HV		 1075 case 0x05: p = "DUAL1 (AC)"; break;
1076 case 0x06: p = "DUAL2 (BC)"; break;
1077 case 0x07: p = "DUAL3 (AB)"; break;
1c1e45d1
HV		 1078 default: p = "undefined";
1079 }
6246d4e1 1080 CX18_INFO_DEV(sd, "Configured audio mode: %s\n", p);
1c1e45d1
HV		 1081 } else {
1082 switch (audio_config & 0xF) {
1083 case 0x00: p = "BG"; break;
1084 case 0x01: p = "DK1"; break;
1085 case 0x02: p = "DK2"; break;
1086 case 0x03: p = "DK3"; break;
1087 case 0x04: p = "I"; break;
1088 case 0x05: p = "L"; break;
1089 case 0x06: p = "BTSC"; break;
1090 case 0x07: p = "EIAJ"; break;
1091 case 0x08: p = "A2-M"; break;
63b8c709
HV		 1092 case 0x09: p = "FM Radio (4.5 MHz)"; break;
1093 case 0x0a: p = "FM Radio (5.5 MHz)"; break;
1094 case 0x0b: p = "S-Video"; break;
1c1e45d1 1095 case 0x0f: p = "automatic standard and mode detection"; break;
63b8c709 1096 default: p = "undefined"; break;
1c1e45d1 1097 }
6246d4e1 1098 CX18_INFO_DEV(sd, "Configured audio system: %s\n", p);
1c1e45d1
HV		 1099 }
1100
1101 if (aud_input)
6246d4e1
AW		 1102 CX18_INFO_DEV(sd, "Specified audio input: Tuner (In%d)\n",
1103 aud_input);
1c1e45d1 1104 else
6246d4e1 1105 CX18_INFO_DEV(sd, "Specified audio input: External\n");
1c1e45d1
HV		 1106
1107 switch (pref_mode & 0xf) {
1108 case 0: p = "mono/language A"; break;
1109 case 1: p = "language B"; break;
1110 case 2: p = "language C"; break;
1111 case 3: p = "analog fallback"; break;
1112 case 4: p = "stereo"; break;
1113 case 5: p = "language AC"; break;
1114 case 6: p = "language BC"; break;
1115 case 7: p = "language AB"; break;
63b8c709 1116 default: p = "undefined"; break;
1c1e45d1 1117 }
6246d4e1 1118 CX18_INFO_DEV(sd, "Preferred audio mode: %s\n", p);
1c1e45d1
HV		 1119
1120 if ((audio_config & 0xf) == 0xf) {
63b8c709 1121 switch ((afc0 >> 3) & 0x1) {
1c1e45d1
HV		 1122 case 0: p = "system DK"; break;
1123 case 1: p = "system L"; break;
1124 }
6246d4e1 1125 CX18_INFO_DEV(sd, "Selected 65 MHz format: %s\n", p);
1c1e45d1 1126
63b8c709
HV		 1127 switch (afc0 & 0x7) {
1128 case 0: p = "Chroma"; break;
1129 case 1: p = "BTSC"; break;
1130 case 2: p = "EIAJ"; break;
1131 case 3: p = "A2-M"; break;
1132 case 4: p = "autodetect"; break;
1133 default: p = "undefined"; break;
1c1e45d1 1134 }
6246d4e1 1135 CX18_INFO_DEV(sd, "Selected 45 MHz format: %s\n", p);
1c1e45d1
HV		 1136 }
1137}
1a267046
AW		 1138
1139static int cx18_av_log_status(struct v4l2_subdev *sd)
1140{
1141 struct cx18 *cx = v4l2_get_subdevdata(sd);
1142 log_video_status(cx);
1143 log_audio_status(cx);
1144 return 0;
1145}
1146
1147static inline int cx18_av_dbg_match(const struct v4l2_dbg_match *match)
1148{
1149 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 1;
1150}
1151
1152static int cx18_av_g_chip_ident(struct v4l2_subdev *sd,
1153 struct v4l2_dbg_chip_ident *chip)
1154{
fa3e7036
AW		 1155 struct cx18_av_state *state = to_cx18_av_state(sd);
1156
1a267046 1157 if (cx18_av_dbg_match(&chip->match)) {
fa3e7036
AW		 1158 chip->ident = state->id;
1159 chip->revision = state->rev;
1a267046
AW		 1160 }
1161 return 0;
1162}
1163
1164#ifdef CONFIG_VIDEO_ADV_DEBUG
1165static int cx18_av_g_register(struct v4l2_subdev *sd,
1166 struct v4l2_dbg_register *reg)
1167{
1168 struct cx18 *cx = v4l2_get_subdevdata(sd);
1169
1170 if (!cx18_av_dbg_match(&reg->match))
1171 return -EINVAL;
1172 if ((reg->reg & 0x3) != 0)
1173 return -EINVAL;
1174 if (!capable(CAP_SYS_ADMIN))
1175 return -EPERM;
1176 reg->size = 4;
1177 reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
1178 return 0;
1179}
1180
1181static int cx18_av_s_register(struct v4l2_subdev *sd,
1182 struct v4l2_dbg_register *reg)
1183{
1184 struct cx18 *cx = v4l2_get_subdevdata(sd);
1185
1186 if (!cx18_av_dbg_match(&reg->match))
1187 return -EINVAL;
1188 if ((reg->reg & 0x3) != 0)
1189 return -EINVAL;
1190 if (!capable(CAP_SYS_ADMIN))
1191 return -EPERM;
1192 cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
1193 return 0;
1194}
1195#endif
1196
1197static const struct v4l2_subdev_core_ops cx18_av_general_ops = {
1198 .g_chip_ident = cx18_av_g_chip_ident,
1199 .log_status = cx18_av_log_status,
fa3e7036 1200 .init = cx18_av_init,
1a267046
AW		 1201 .reset = cx18_av_reset,
1202 .queryctrl = cx18_av_queryctrl,
1203 .g_ctrl = cx18_av_g_ctrl,
1204 .s_ctrl = cx18_av_s_ctrl,
1205#ifdef CONFIG_VIDEO_ADV_DEBUG
1206 .g_register = cx18_av_g_register,
1207 .s_register = cx18_av_s_register,
1208#endif
1209};
1210
1211static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = {
1212 .s_radio = cx18_av_s_radio,
1213 .s_frequency = cx18_av_s_frequency,
1214 .g_tuner = cx18_av_g_tuner,
1215 .s_tuner = cx18_av_s_tuner,
1216 .s_std = cx18_av_s_std,
1217};
1218
1219static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = {
1220 .s_clock_freq = cx18_av_s_clock_freq,
1221 .s_routing = cx18_av_s_audio_routing,
1222};
1223
1224static const struct v4l2_subdev_video_ops cx18_av_video_ops = {
1225 .s_routing = cx18_av_s_video_routing,
1226 .decode_vbi_line = cx18_av_decode_vbi_line,
1227 .s_stream = cx18_av_s_stream,
1228 .g_fmt = cx18_av_g_fmt,
1229 .s_fmt = cx18_av_s_fmt,
1230};
1231
1232static const struct v4l2_subdev_ops cx18_av_ops = {
1233 .core = &cx18_av_general_ops,
1234 .tuner = &cx18_av_tuner_ops,
1235 .audio = &cx18_av_audio_ops,
1236 .video = &cx18_av_video_ops,
1237};
1238
ff2a2001 1239int cx18_av_probe(struct cx18 *cx)
1a267046 1240{
fa3e7036 1241 struct cx18_av_state *state = &cx->av_state;
ff2a2001 1242 struct v4l2_subdev *sd;
fa3e7036
AW		 1243
1244 state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
1245 state->id = ((state->rev >> 4) == CXADEC_CHIP_TYPE_MAKO)
1246 ? V4L2_IDENT_CX23418_843 : V4L2_IDENT_UNKNOWN;
1247
1248 state->vid_input = CX18_AV_COMPOSITE7;
1249 state->aud_input = CX18_AV_AUDIO8;
1250 state->audclk_freq = 48000;
1251 state->audmode = V4L2_TUNER_MODE_LANG1;
1252 state->slicer_line_delay = 0;
1253 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
1254
ff2a2001
AW		 1255 sd = &state->sd;
1256 v4l2_subdev_init(sd, &cx18_av_ops);
1257 v4l2_set_subdevdata(sd, cx);
1258 snprintf(sd->name, sizeof(sd->name),
6246d4e1 1259 "%s %03x", cx->v4l2_dev.name, (state->rev >> 4));
ff2a2001
AW		 1260 sd->grp_id = CX18_HW_418_AV;
1261 return v4l2_device_register_subdev(&cx->v4l2_dev, sd);
1a267046 1262}
Linux 6.x block layer and io_uring tree(s)