Commit | Line | Data |
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64fbf444 PB |
1 | /* |
2 | * | |
3 | * Support for a cx23417 mpeg encoder via cx231xx host port. | |
4 | * | |
5 | * (c) 2004 Jelle Foks <jelle@foks.us> | |
6 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> | |
7 | * (c) 2008 Steven Toth <stoth@linuxtv.org> | |
8 | * - CX23885/7/8 support | |
9 | * | |
10 | * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/), | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
64fbf444 PB |
21 | */ |
22 | ||
589dadf2 MCC |
23 | #include "cx231xx.h" |
24 | ||
64fbf444 PB |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/device.h> | |
31 | #include <linux/firmware.h> | |
94399431 | 32 | #include <linux/vmalloc.h> |
64fbf444 PB |
33 | #include <media/v4l2-common.h> |
34 | #include <media/v4l2-ioctl.h> | |
88b6ffed | 35 | #include <media/v4l2-event.h> |
d647f0b7 | 36 | #include <media/drv-intf/cx2341x.h> |
b86d1544 | 37 | #include <media/tuner.h> |
64fbf444 | 38 | |
64fbf444 PB |
39 | #define CX231xx_FIRM_IMAGE_SIZE 376836 |
40 | #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" | |
41 | ||
955e6ed8 | 42 | /* for polaris ITVC */ |
64fbf444 PB |
43 | #define ITVC_WRITE_DIR 0x03FDFC00 |
44 | #define ITVC_READ_DIR 0x0001FC00 | |
45 | ||
46 | #define MCI_MEMORY_DATA_BYTE0 0x00 | |
47 | #define MCI_MEMORY_DATA_BYTE1 0x08 | |
48 | #define MCI_MEMORY_DATA_BYTE2 0x10 | |
49 | #define MCI_MEMORY_DATA_BYTE3 0x18 | |
50 | ||
51 | #define MCI_MEMORY_ADDRESS_BYTE2 0x20 | |
52 | #define MCI_MEMORY_ADDRESS_BYTE1 0x28 | |
53 | #define MCI_MEMORY_ADDRESS_BYTE0 0x30 | |
54 | ||
55 | #define MCI_REGISTER_DATA_BYTE0 0x40 | |
56 | #define MCI_REGISTER_DATA_BYTE1 0x48 | |
57 | #define MCI_REGISTER_DATA_BYTE2 0x50 | |
58 | #define MCI_REGISTER_DATA_BYTE3 0x58 | |
59 | ||
60 | #define MCI_REGISTER_ADDRESS_BYTE0 0x60 | |
61 | #define MCI_REGISTER_ADDRESS_BYTE1 0x68 | |
62 | ||
63 | #define MCI_REGISTER_MODE 0x70 | |
64 | ||
955e6ed8 | 65 | /* Read and write modes for polaris ITVC */ |
64fbf444 PB |
66 | #define MCI_MODE_REGISTER_READ 0x000 |
67 | #define MCI_MODE_REGISTER_WRITE 0x100 | |
68 | #define MCI_MODE_MEMORY_READ 0x000 | |
69 | #define MCI_MODE_MEMORY_WRITE 0x4000 | |
70 | ||
71 | static unsigned int mpegbufs = 8; | |
72 | module_param(mpegbufs, int, 0644); | |
73 | MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); | |
5b8acdc5 | 74 | |
64fbf444 PB |
75 | static unsigned int mpeglines = 128; |
76 | module_param(mpeglines, int, 0644); | |
77 | MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); | |
5b8acdc5 | 78 | |
64fbf444 PB |
79 | static unsigned int mpeglinesize = 512; |
80 | module_param(mpeglinesize, int, 0644); | |
81 | MODULE_PARM_DESC(mpeglinesize, | |
82 | "number of bytes in each line of an MPEG buffer, range 512-1024"); | |
83 | ||
84 | static unsigned int v4l_debug = 1; | |
85 | module_param(v4l_debug, int, 0644); | |
86 | MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); | |
5b8acdc5 | 87 | |
ed0e3729 MCC |
88 | #define dprintk(level, fmt, arg...) \ |
89 | do { \ | |
90 | if (v4l_debug >= level) \ | |
91 | printk(KERN_DEBUG pr_fmt(fmt), ## arg); \ | |
64fbf444 PB |
92 | } while (0) |
93 | ||
94 | static struct cx231xx_tvnorm cx231xx_tvnorms[] = { | |
95 | { | |
96 | .name = "NTSC-M", | |
97 | .id = V4L2_STD_NTSC_M, | |
98 | }, { | |
99 | .name = "NTSC-JP", | |
100 | .id = V4L2_STD_NTSC_M_JP, | |
101 | }, { | |
102 | .name = "PAL-BG", | |
103 | .id = V4L2_STD_PAL_BG, | |
104 | }, { | |
105 | .name = "PAL-DK", | |
106 | .id = V4L2_STD_PAL_DK, | |
107 | }, { | |
108 | .name = "PAL-I", | |
109 | .id = V4L2_STD_PAL_I, | |
110 | }, { | |
111 | .name = "PAL-M", | |
112 | .id = V4L2_STD_PAL_M, | |
113 | }, { | |
114 | .name = "PAL-N", | |
115 | .id = V4L2_STD_PAL_N, | |
116 | }, { | |
117 | .name = "PAL-Nc", | |
118 | .id = V4L2_STD_PAL_Nc, | |
119 | }, { | |
120 | .name = "PAL-60", | |
121 | .id = V4L2_STD_PAL_60, | |
122 | }, { | |
123 | .name = "SECAM-L", | |
124 | .id = V4L2_STD_SECAM_L, | |
125 | }, { | |
126 | .name = "SECAM-DK", | |
127 | .id = V4L2_STD_SECAM_DK, | |
128 | } | |
129 | }; | |
130 | ||
131 | /* ------------------------------------------------------------------ */ | |
5b8acdc5 | 132 | |
64fbf444 PB |
133 | enum cx231xx_capture_type { |
134 | CX231xx_MPEG_CAPTURE, | |
135 | CX231xx_RAW_CAPTURE, | |
136 | CX231xx_RAW_PASSTHRU_CAPTURE | |
137 | }; | |
5b8acdc5 | 138 | |
64fbf444 PB |
139 | enum cx231xx_capture_bits { |
140 | CX231xx_RAW_BITS_NONE = 0x00, | |
141 | CX231xx_RAW_BITS_YUV_CAPTURE = 0x01, | |
142 | CX231xx_RAW_BITS_PCM_CAPTURE = 0x02, | |
143 | CX231xx_RAW_BITS_VBI_CAPTURE = 0x04, | |
144 | CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08, | |
145 | CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10 | |
146 | }; | |
5b8acdc5 | 147 | |
64fbf444 PB |
148 | enum cx231xx_capture_end { |
149 | CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */ | |
150 | CX231xx_END_NOW, /* stop immediately, no irq */ | |
151 | }; | |
5b8acdc5 | 152 | |
64fbf444 PB |
153 | enum cx231xx_framerate { |
154 | CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */ | |
155 | CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */ | |
156 | }; | |
5b8acdc5 | 157 | |
64fbf444 PB |
158 | enum cx231xx_stream_port { |
159 | CX231xx_OUTPUT_PORT_MEMORY, | |
160 | CX231xx_OUTPUT_PORT_STREAMING, | |
161 | CX231xx_OUTPUT_PORT_SERIAL | |
162 | }; | |
5b8acdc5 | 163 | |
64fbf444 PB |
164 | enum cx231xx_data_xfer_status { |
165 | CX231xx_MORE_BUFFERS_FOLLOW, | |
166 | CX231xx_LAST_BUFFER, | |
167 | }; | |
5b8acdc5 | 168 | |
64fbf444 PB |
169 | enum cx231xx_picture_mask { |
170 | CX231xx_PICTURE_MASK_NONE, | |
171 | CX231xx_PICTURE_MASK_I_FRAMES, | |
172 | CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3, | |
173 | CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7, | |
174 | }; | |
5b8acdc5 | 175 | |
64fbf444 PB |
176 | enum cx231xx_vbi_mode_bits { |
177 | CX231xx_VBI_BITS_SLICED, | |
178 | CX231xx_VBI_BITS_RAW, | |
179 | }; | |
5b8acdc5 | 180 | |
64fbf444 PB |
181 | enum cx231xx_vbi_insertion_bits { |
182 | CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, | |
183 | CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, | |
184 | CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1, | |
185 | CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, | |
186 | CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, | |
187 | }; | |
5b8acdc5 | 188 | |
64fbf444 PB |
189 | enum cx231xx_dma_unit { |
190 | CX231xx_DMA_BYTES, | |
191 | CX231xx_DMA_FRAMES, | |
192 | }; | |
5b8acdc5 | 193 | |
64fbf444 PB |
194 | enum cx231xx_dma_transfer_status_bits { |
195 | CX231xx_DMA_TRANSFER_BITS_DONE = 0x01, | |
196 | CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04, | |
197 | CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10, | |
198 | }; | |
5b8acdc5 | 199 | |
64fbf444 PB |
200 | enum cx231xx_pause { |
201 | CX231xx_PAUSE_ENCODING, | |
202 | CX231xx_RESUME_ENCODING, | |
203 | }; | |
5b8acdc5 | 204 | |
64fbf444 PB |
205 | enum cx231xx_copyright { |
206 | CX231xx_COPYRIGHT_OFF, | |
207 | CX231xx_COPYRIGHT_ON, | |
208 | }; | |
5b8acdc5 | 209 | |
64fbf444 PB |
210 | enum cx231xx_notification_type { |
211 | CX231xx_NOTIFICATION_REFRESH, | |
212 | }; | |
5b8acdc5 | 213 | |
64fbf444 PB |
214 | enum cx231xx_notification_status { |
215 | CX231xx_NOTIFICATION_OFF, | |
216 | CX231xx_NOTIFICATION_ON, | |
217 | }; | |
5b8acdc5 | 218 | |
64fbf444 PB |
219 | enum cx231xx_notification_mailbox { |
220 | CX231xx_NOTIFICATION_NO_MAILBOX = -1, | |
221 | }; | |
5b8acdc5 | 222 | |
64fbf444 PB |
223 | enum cx231xx_field1_lines { |
224 | CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */ | |
225 | CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */ | |
226 | CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */ | |
227 | }; | |
5b8acdc5 | 228 | |
64fbf444 PB |
229 | enum cx231xx_field2_lines { |
230 | CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */ | |
231 | CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */ | |
232 | CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */ | |
233 | }; | |
5b8acdc5 | 234 | |
64fbf444 PB |
235 | enum cx231xx_custom_data_type { |
236 | CX231xx_CUSTOM_EXTENSION_USR_DATA, | |
237 | CX231xx_CUSTOM_PRIVATE_PACKET, | |
238 | }; | |
5b8acdc5 | 239 | |
64fbf444 PB |
240 | enum cx231xx_mute { |
241 | CX231xx_UNMUTE, | |
242 | CX231xx_MUTE, | |
243 | }; | |
5b8acdc5 | 244 | |
64fbf444 PB |
245 | enum cx231xx_mute_video_mask { |
246 | CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00, | |
247 | CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000, | |
248 | CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000, | |
249 | }; | |
5b8acdc5 | 250 | |
64fbf444 PB |
251 | enum cx231xx_mute_video_shift { |
252 | CX231xx_MUTE_VIDEO_V_SHIFT = 8, | |
253 | CX231xx_MUTE_VIDEO_U_SHIFT = 16, | |
254 | CX231xx_MUTE_VIDEO_Y_SHIFT = 24, | |
255 | }; | |
256 | ||
257 | /* defines below are from ivtv-driver.h */ | |
258 | #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF | |
259 | ||
260 | /* Firmware API commands */ | |
261 | #define IVTV_API_STD_TIMEOUT 500 | |
262 | ||
263 | /* Registers */ | |
264 | /* IVTV_REG_OFFSET */ | |
265 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) | |
266 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) | |
267 | #define IVTV_REG_SPU (0x9050) | |
268 | #define IVTV_REG_HW_BLOCKS (0x9054) | |
269 | #define IVTV_REG_VPU (0x9058) | |
270 | #define IVTV_REG_APU (0xA064) | |
271 | ||
955e6ed8 MCC |
272 | /* |
273 | * Bit definitions for MC417_RWD and MC417_OEN registers | |
274 | * | |
275 | * bits 31-16 | |
276 | *+-----------+ | |
277 | *| Reserved | | |
278 | *|+-----------+ | |
279 | *| bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 | |
280 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
281 | *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| | |
282 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
283 | *| bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 | |
284 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
285 | *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| | |
286 | *|+-------+-------+-------+-------+-------+-------+-------+-------+ | |
287 | */ | |
64fbf444 PB |
288 | #define MC417_MIWR 0x8000 |
289 | #define MC417_MIRD 0x4000 | |
290 | #define MC417_MICS 0x2000 | |
291 | #define MC417_MIRDY 0x1000 | |
292 | #define MC417_MIADDR 0x0F00 | |
293 | #define MC417_MIDATA 0x00FF | |
294 | ||
295 | ||
955e6ed8 MCC |
296 | /* Bit definitions for MC417_CTL register **** |
297 | *bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 | |
298 | *+--------+-------------+--------+--------------+------------+ | |
299 | *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| | |
300 | *+--------+-------------+--------+--------------+------------+ | |
301 | */ | |
64fbf444 PB |
302 | #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) |
303 | #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) | |
304 | #define MC417_UART_GPIO_EN 0x00000001 | |
305 | ||
306 | /* Values for speed control */ | |
307 | #define MC417_SPD_CTL_SLOW 0x1 | |
308 | #define MC417_SPD_CTL_MEDIUM 0x0 | |
309 | #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */ | |
310 | ||
311 | /* Values for GPIO select */ | |
312 | #define MC417_GPIO_SEL_GPIO3 0x3 | |
313 | #define MC417_GPIO_SEL_GPIO2 0x2 | |
314 | #define MC417_GPIO_SEL_GPIO1 0x1 | |
315 | #define MC417_GPIO_SEL_GPIO0 0x0 | |
316 | ||
317 | ||
318 | #define CX23417_GPIO_MASK 0xFC0003FF | |
5b8acdc5 HV |
319 | |
320 | static int set_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 value) | |
64fbf444 PB |
321 | { |
322 | int status = 0; | |
323 | u32 _gpio_direction = 0; | |
324 | ||
325 | _gpio_direction = _gpio_direction & CX23417_GPIO_MASK; | |
5b8acdc5 | 326 | _gpio_direction = _gpio_direction | gpio_direction; |
64fbf444 PB |
327 | status = cx231xx_send_gpio_cmd(dev, _gpio_direction, |
328 | (u8 *)&value, 4, 0, 0); | |
329 | return status; | |
330 | } | |
5b8acdc5 HV |
331 | |
332 | static int get_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 *val_ptr) | |
64fbf444 PB |
333 | { |
334 | int status = 0; | |
335 | u32 _gpio_direction = 0; | |
336 | ||
337 | _gpio_direction = _gpio_direction & CX23417_GPIO_MASK; | |
5b8acdc5 | 338 | _gpio_direction = _gpio_direction | gpio_direction; |
64fbf444 PB |
339 | |
340 | status = cx231xx_send_gpio_cmd(dev, _gpio_direction, | |
5b8acdc5 | 341 | (u8 *)val_ptr, 4, 0, 1); |
64fbf444 PB |
342 | return status; |
343 | } | |
82c3ccaa | 344 | |
5b8acdc5 | 345 | static int wait_for_mci_complete(struct cx231xx *dev) |
64fbf444 | 346 | { |
955e6ed8 | 347 | u32 gpio; |
5b8acdc5 | 348 | u32 gpio_direction = 0; |
955e6ed8 | 349 | u8 count = 0; |
5b8acdc5 | 350 | get_itvc_reg(dev, gpio_direction, &gpio); |
64fbf444 | 351 | |
955e6ed8 MCC |
352 | while (!(gpio&0x020000)) { |
353 | msleep(10); | |
64fbf444 | 354 | |
5b8acdc5 | 355 | get_itvc_reg(dev, gpio_direction, &gpio); |
64fbf444 | 356 | |
955e6ed8 MCC |
357 | if (count++ > 100) { |
358 | dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio); | |
ccc5429f | 359 | return -EIO; |
955e6ed8 | 360 | } |
64fbf444 | 361 | } |
64fbf444 PB |
362 | return 0; |
363 | } | |
955e6ed8 | 364 | |
82c3ccaa | 365 | static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value) |
64fbf444 | 366 | { |
955e6ed8 | 367 | u32 temp; |
64fbf444 PB |
368 | int status = 0; |
369 | ||
5b8acdc5 HV |
370 | temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8); |
371 | temp = temp << 10; | |
372 | status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
64fbf444 PB |
373 | if (status < 0) |
374 | return status; | |
5b8acdc5 HV |
375 | temp = temp | (0x05 << 10); |
376 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
377 | |
378 | /*write data byte 1;*/ | |
5b8acdc5 HV |
379 | temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00); |
380 | temp = temp << 10; | |
381 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
382 | temp = temp | (0x05 << 10); | |
383 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
384 | |
385 | /*write data byte 2;*/ | |
5b8acdc5 HV |
386 | temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8); |
387 | temp = temp << 10; | |
388 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
389 | temp = temp | (0x05 << 10); | |
390 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
391 | |
392 | /*write data byte 3;*/ | |
5b8acdc5 HV |
393 | temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16); |
394 | temp = temp << 10; | |
395 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
396 | temp = temp | (0x05 << 10); | |
397 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
398 | |
399 | /*write address byte 0;*/ | |
5b8acdc5 HV |
400 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8); |
401 | temp = temp << 10; | |
402 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
403 | temp = temp | (0x05 << 10); | |
404 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
405 | |
406 | /*write address byte 1;*/ | |
5b8acdc5 HV |
407 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00); |
408 | temp = temp << 10; | |
409 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
410 | temp = temp | (0x05 << 10); | |
411 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
412 | |
413 | /*Write that the mode is write.*/ | |
414 | temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE; | |
5b8acdc5 HV |
415 | temp = temp << 10; |
416 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
417 | temp = temp | (0x05 << 10); | |
418 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 | 419 | |
5b8acdc5 | 420 | return wait_for_mci_complete(dev); |
64fbf444 PB |
421 | } |
422 | ||
82c3ccaa | 423 | static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value) |
64fbf444 | 424 | { |
955e6ed8 MCC |
425 | /*write address byte 0;*/ |
426 | u32 temp; | |
427 | u32 return_value = 0; | |
64fbf444 PB |
428 | int ret = 0; |
429 | ||
955e6ed8 MCC |
430 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
431 | temp = temp << 10; | |
5b8acdc5 | 432 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 | 433 | temp = temp | ((0x05) << 10); |
5b8acdc5 | 434 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 MCC |
435 | |
436 | /*write address byte 1;*/ | |
437 | temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00); | |
438 | temp = temp << 10; | |
5b8acdc5 | 439 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 | 440 | temp = temp | ((0x05) << 10); |
5b8acdc5 | 441 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 MCC |
442 | |
443 | /*write that the mode is read;*/ | |
444 | temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ; | |
445 | temp = temp << 10; | |
5b8acdc5 | 446 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 | 447 | temp = temp | ((0x05) << 10); |
5b8acdc5 | 448 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
955e6ed8 MCC |
449 | |
450 | /*wait for the MIRDY line to be asserted , | |
451 | signalling that the read is done;*/ | |
5b8acdc5 | 452 | ret = wait_for_mci_complete(dev); |
955e6ed8 MCC |
453 | |
454 | /*switch the DATA- GPIO to input mode;*/ | |
455 | ||
456 | /*Read data byte 0;*/ | |
457 | temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10; | |
5b8acdc5 | 458 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 459 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10); |
5b8acdc5 HV |
460 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
461 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 | 462 | return_value |= ((temp & 0x03FC0000) >> 18); |
5b8acdc5 | 463 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
955e6ed8 MCC |
464 | |
465 | /* Read data byte 1;*/ | |
466 | temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10; | |
5b8acdc5 | 467 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 468 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10); |
5b8acdc5 HV |
469 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
470 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 MCC |
471 | |
472 | return_value |= ((temp & 0x03FC0000) >> 10); | |
5b8acdc5 | 473 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
955e6ed8 MCC |
474 | |
475 | /*Read data byte 2;*/ | |
476 | temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10; | |
5b8acdc5 | 477 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 478 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10); |
5b8acdc5 HV |
479 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
480 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 | 481 | return_value |= ((temp & 0x03FC0000) >> 2); |
5b8acdc5 | 482 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
955e6ed8 MCC |
483 | |
484 | /*Read data byte 3;*/ | |
485 | temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10; | |
5b8acdc5 | 486 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
955e6ed8 | 487 | temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10); |
5b8acdc5 HV |
488 | set_itvc_reg(dev, ITVC_READ_DIR, temp); |
489 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
955e6ed8 | 490 | return_value |= ((temp & 0x03FC0000) << 6); |
5b8acdc5 | 491 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); |
64fbf444 PB |
492 | |
493 | *value = return_value; | |
955e6ed8 | 494 | return ret; |
64fbf444 PB |
495 | } |
496 | ||
82c3ccaa | 497 | static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value) |
64fbf444 | 498 | { |
955e6ed8 | 499 | /*write data byte 0;*/ |
64fbf444 | 500 | |
955e6ed8 | 501 | u32 temp; |
64fbf444 PB |
502 | int ret = 0; |
503 | ||
5b8acdc5 | 504 | temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8); |
955e6ed8 | 505 | temp = temp << 10; |
5b8acdc5 | 506 | ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
64fbf444 PB |
507 | if (ret < 0) |
508 | return ret; | |
5b8acdc5 HV |
509 | temp = temp | (0x05 << 10); |
510 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
511 | |
512 | /*write data byte 1;*/ | |
513 | temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00); | |
514 | temp = temp << 10; | |
5b8acdc5 HV |
515 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); |
516 | temp = temp | (0x05 << 10); | |
517 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
518 | |
519 | /*write data byte 2;*/ | |
5b8acdc5 HV |
520 | temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8); |
521 | temp = temp << 10; | |
522 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
523 | temp = temp | (0x05 << 10); | |
524 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
525 | |
526 | /*write data byte 3;*/ | |
5b8acdc5 HV |
527 | temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16); |
528 | temp = temp << 10; | |
529 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
530 | temp = temp | (0x05 << 10); | |
531 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
532 | |
533 | /* write address byte 2;*/ | |
5b8acdc5 HV |
534 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | |
535 | ((address & 0x003F0000) >> 8); | |
536 | temp = temp << 10; | |
537 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
538 | temp = temp | (0x05 << 10); | |
539 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
540 | |
541 | /* write address byte 1;*/ | |
5b8acdc5 HV |
542 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
543 | temp = temp << 10; | |
544 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
545 | temp = temp | (0x05 << 10); | |
546 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
547 | |
548 | /* write address byte 0;*/ | |
5b8acdc5 HV |
549 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
550 | temp = temp << 10; | |
551 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
552 | temp = temp | (0x05 << 10); | |
553 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
554 | |
555 | /*wait for MIRDY line;*/ | |
5b8acdc5 | 556 | wait_for_mci_complete(dev); |
64fbf444 | 557 | |
955e6ed8 | 558 | return 0; |
64fbf444 PB |
559 | } |
560 | ||
82c3ccaa | 561 | static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value) |
64fbf444 | 562 | { |
955e6ed8 MCC |
563 | u32 temp = 0; |
564 | u32 return_value = 0; | |
64fbf444 PB |
565 | int ret = 0; |
566 | ||
955e6ed8 | 567 | /*write address byte 2;*/ |
5b8acdc5 HV |
568 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ | |
569 | ((address & 0x003F0000) >> 8); | |
570 | temp = temp << 10; | |
571 | ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
64fbf444 PB |
572 | if (ret < 0) |
573 | return ret; | |
5b8acdc5 HV |
574 | temp = temp | (0x05 << 10); |
575 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
576 | |
577 | /*write address byte 1*/ | |
5b8acdc5 HV |
578 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
579 | temp = temp << 10; | |
580 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
581 | temp = temp | (0x05 << 10); | |
582 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
583 | |
584 | /*write address byte 0*/ | |
5b8acdc5 HV |
585 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
586 | temp = temp << 10; | |
587 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
588 | temp = temp | (0x05 << 10); | |
589 | set_itvc_reg(dev, ITVC_WRITE_DIR, temp); | |
955e6ed8 MCC |
590 | |
591 | /*Wait for MIRDY line*/ | |
5b8acdc5 | 592 | ret = wait_for_mci_complete(dev); |
955e6ed8 MCC |
593 | |
594 | ||
595 | /*Read data byte 3;*/ | |
5b8acdc5 HV |
596 | temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10; |
597 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
598 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10); | |
599 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
600 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
601 | return_value |= ((temp & 0x03FC0000) << 6); | |
602 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
955e6ed8 MCC |
603 | |
604 | /*Read data byte 2;*/ | |
5b8acdc5 HV |
605 | temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10; |
606 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
607 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10); | |
608 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
609 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
610 | return_value |= ((temp & 0x03FC0000) >> 2); | |
611 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
955e6ed8 MCC |
612 | |
613 | /* Read data byte 1;*/ | |
5b8acdc5 HV |
614 | temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10; |
615 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
616 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10); | |
617 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
618 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
619 | return_value |= ((temp & 0x03FC0000) >> 10); | |
620 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
955e6ed8 MCC |
621 | |
622 | /*Read data byte 0;*/ | |
5b8acdc5 HV |
623 | temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10; |
624 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
625 | temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10); | |
626 | set_itvc_reg(dev, ITVC_READ_DIR, temp); | |
627 | get_itvc_reg(dev, ITVC_READ_DIR, &temp); | |
628 | return_value |= ((temp & 0x03FC0000) >> 18); | |
629 | set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10)); | |
64fbf444 PB |
630 | |
631 | *value = return_value; | |
955e6ed8 | 632 | return ret; |
64fbf444 PB |
633 | } |
634 | ||
64fbf444 PB |
635 | /* ------------------------------------------------------------------ */ |
636 | ||
637 | /* MPEG encoder API */ | |
638 | static char *cmd_to_str(int cmd) | |
639 | { | |
640 | switch (cmd) { | |
641 | case CX2341X_ENC_PING_FW: | |
5b8acdc5 | 642 | return "PING_FW"; |
64fbf444 | 643 | case CX2341X_ENC_START_CAPTURE: |
5b8acdc5 | 644 | return "START_CAPTURE"; |
64fbf444 | 645 | case CX2341X_ENC_STOP_CAPTURE: |
5b8acdc5 | 646 | return "STOP_CAPTURE"; |
64fbf444 | 647 | case CX2341X_ENC_SET_AUDIO_ID: |
5b8acdc5 | 648 | return "SET_AUDIO_ID"; |
64fbf444 | 649 | case CX2341X_ENC_SET_VIDEO_ID: |
5b8acdc5 | 650 | return "SET_VIDEO_ID"; |
64fbf444 | 651 | case CX2341X_ENC_SET_PCR_ID: |
5b8acdc5 | 652 | return "SET_PCR_PID"; |
64fbf444 | 653 | case CX2341X_ENC_SET_FRAME_RATE: |
5b8acdc5 | 654 | return "SET_FRAME_RATE"; |
64fbf444 | 655 | case CX2341X_ENC_SET_FRAME_SIZE: |
5b8acdc5 | 656 | return "SET_FRAME_SIZE"; |
64fbf444 | 657 | case CX2341X_ENC_SET_BIT_RATE: |
5b8acdc5 | 658 | return "SET_BIT_RATE"; |
64fbf444 | 659 | case CX2341X_ENC_SET_GOP_PROPERTIES: |
5b8acdc5 | 660 | return "SET_GOP_PROPERTIES"; |
64fbf444 | 661 | case CX2341X_ENC_SET_ASPECT_RATIO: |
5b8acdc5 | 662 | return "SET_ASPECT_RATIO"; |
64fbf444 | 663 | case CX2341X_ENC_SET_DNR_FILTER_MODE: |
5b8acdc5 | 664 | return "SET_DNR_FILTER_PROPS"; |
64fbf444 | 665 | case CX2341X_ENC_SET_DNR_FILTER_PROPS: |
5b8acdc5 | 666 | return "SET_DNR_FILTER_PROPS"; |
64fbf444 | 667 | case CX2341X_ENC_SET_CORING_LEVELS: |
5b8acdc5 | 668 | return "SET_CORING_LEVELS"; |
64fbf444 | 669 | case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: |
5b8acdc5 | 670 | return "SET_SPATIAL_FILTER_TYPE"; |
64fbf444 | 671 | case CX2341X_ENC_SET_VBI_LINE: |
5b8acdc5 | 672 | return "SET_VBI_LINE"; |
64fbf444 | 673 | case CX2341X_ENC_SET_STREAM_TYPE: |
5b8acdc5 | 674 | return "SET_STREAM_TYPE"; |
64fbf444 | 675 | case CX2341X_ENC_SET_OUTPUT_PORT: |
5b8acdc5 | 676 | return "SET_OUTPUT_PORT"; |
64fbf444 | 677 | case CX2341X_ENC_SET_AUDIO_PROPERTIES: |
5b8acdc5 | 678 | return "SET_AUDIO_PROPERTIES"; |
64fbf444 | 679 | case CX2341X_ENC_HALT_FW: |
5b8acdc5 | 680 | return "HALT_FW"; |
64fbf444 | 681 | case CX2341X_ENC_GET_VERSION: |
5b8acdc5 | 682 | return "GET_VERSION"; |
64fbf444 | 683 | case CX2341X_ENC_SET_GOP_CLOSURE: |
5b8acdc5 | 684 | return "SET_GOP_CLOSURE"; |
64fbf444 | 685 | case CX2341X_ENC_GET_SEQ_END: |
5b8acdc5 | 686 | return "GET_SEQ_END"; |
64fbf444 | 687 | case CX2341X_ENC_SET_PGM_INDEX_INFO: |
5b8acdc5 | 688 | return "SET_PGM_INDEX_INFO"; |
64fbf444 | 689 | case CX2341X_ENC_SET_VBI_CONFIG: |
5b8acdc5 | 690 | return "SET_VBI_CONFIG"; |
64fbf444 | 691 | case CX2341X_ENC_SET_DMA_BLOCK_SIZE: |
5b8acdc5 | 692 | return "SET_DMA_BLOCK_SIZE"; |
64fbf444 | 693 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10: |
5b8acdc5 | 694 | return "GET_PREV_DMA_INFO_MB_10"; |
64fbf444 | 695 | case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9: |
5b8acdc5 | 696 | return "GET_PREV_DMA_INFO_MB_9"; |
64fbf444 | 697 | case CX2341X_ENC_SCHED_DMA_TO_HOST: |
5b8acdc5 | 698 | return "SCHED_DMA_TO_HOST"; |
64fbf444 | 699 | case CX2341X_ENC_INITIALIZE_INPUT: |
5b8acdc5 | 700 | return "INITIALIZE_INPUT"; |
64fbf444 | 701 | case CX2341X_ENC_SET_FRAME_DROP_RATE: |
5b8acdc5 | 702 | return "SET_FRAME_DROP_RATE"; |
64fbf444 | 703 | case CX2341X_ENC_PAUSE_ENCODER: |
5b8acdc5 | 704 | return "PAUSE_ENCODER"; |
64fbf444 | 705 | case CX2341X_ENC_REFRESH_INPUT: |
5b8acdc5 | 706 | return "REFRESH_INPUT"; |
64fbf444 | 707 | case CX2341X_ENC_SET_COPYRIGHT: |
5b8acdc5 | 708 | return "SET_COPYRIGHT"; |
64fbf444 | 709 | case CX2341X_ENC_SET_EVENT_NOTIFICATION: |
5b8acdc5 | 710 | return "SET_EVENT_NOTIFICATION"; |
64fbf444 | 711 | case CX2341X_ENC_SET_NUM_VSYNC_LINES: |
5b8acdc5 | 712 | return "SET_NUM_VSYNC_LINES"; |
64fbf444 | 713 | case CX2341X_ENC_SET_PLACEHOLDER: |
5b8acdc5 | 714 | return "SET_PLACEHOLDER"; |
64fbf444 | 715 | case CX2341X_ENC_MUTE_VIDEO: |
5b8acdc5 | 716 | return "MUTE_VIDEO"; |
64fbf444 | 717 | case CX2341X_ENC_MUTE_AUDIO: |
5b8acdc5 | 718 | return "MUTE_AUDIO"; |
64fbf444 | 719 | case CX2341X_ENC_MISC: |
5b8acdc5 | 720 | return "MISC"; |
64fbf444 PB |
721 | default: |
722 | return "UNKNOWN"; | |
723 | } | |
724 | } | |
725 | ||
5b8acdc5 | 726 | static int cx231xx_mbox_func(void *priv, u32 command, int in, int out, |
64fbf444 PB |
727 | u32 data[CX2341X_MBOX_MAX_DATA]) |
728 | { | |
729 | struct cx231xx *dev = priv; | |
730 | unsigned long timeout; | |
731 | u32 value, flag, retval = 0; | |
732 | int i; | |
733 | ||
734 | dprintk(3, "%s: command(0x%X) = %s\n", __func__, command, | |
735 | cmd_to_str(command)); | |
736 | ||
737 | /* this may not be 100% safe if we can't read any memory location | |
738 | without side effects */ | |
739 | mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); | |
740 | if (value != 0x12345678) { | |
5b8acdc5 HV |
741 | dprintk(3, "Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n", |
742 | value, cmd_to_str(command)); | |
88b6ffed | 743 | return -EIO; |
64fbf444 PB |
744 | } |
745 | ||
746 | /* This read looks at 32 bits, but flag is only 8 bits. | |
747 | * Seems we also bail if CMD or TIMEOUT bytes are set??? | |
748 | */ | |
749 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
750 | if (flag) { | |
5b8acdc5 HV |
751 | dprintk(3, "ERROR: Mailbox appears to be in use (%x), cmd = %s\n", |
752 | flag, cmd_to_str(command)); | |
88b6ffed | 753 | return -EBUSY; |
64fbf444 PB |
754 | } |
755 | ||
756 | flag |= 1; /* tell 'em we're working on it */ | |
757 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
758 | ||
759 | /* write command + args + fill remaining with zeros */ | |
760 | /* command code */ | |
761 | mc417_memory_write(dev, dev->cx23417_mailbox + 1, command); | |
762 | mc417_memory_write(dev, dev->cx23417_mailbox + 3, | |
763 | IVTV_API_STD_TIMEOUT); /* timeout */ | |
764 | for (i = 0; i < in; i++) { | |
765 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]); | |
766 | dprintk(3, "API Input %d = %d\n", i, data[i]); | |
767 | } | |
768 | for (; i < CX2341X_MBOX_MAX_DATA; i++) | |
769 | mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0); | |
770 | ||
771 | flag |= 3; /* tell 'em we're done writing */ | |
772 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
773 | ||
774 | /* wait for firmware to handle the API command */ | |
775 | timeout = jiffies + msecs_to_jiffies(10); | |
776 | for (;;) { | |
777 | mc417_memory_read(dev, dev->cx23417_mailbox, &flag); | |
778 | if (0 != (flag & 4)) | |
779 | break; | |
780 | if (time_after(jiffies, timeout)) { | |
781 | dprintk(3, "ERROR: API Mailbox timeout\n"); | |
88b6ffed | 782 | return -EIO; |
64fbf444 PB |
783 | } |
784 | udelay(10); | |
785 | } | |
786 | ||
787 | /* read output values */ | |
788 | for (i = 0; i < out; i++) { | |
789 | mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i); | |
790 | dprintk(3, "API Output %d = %d\n", i, data[i]); | |
791 | } | |
792 | ||
793 | mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval); | |
794 | dprintk(3, "API result = %d\n", retval); | |
795 | ||
796 | flag = 0; | |
797 | mc417_memory_write(dev, dev->cx23417_mailbox, flag); | |
798 | ||
88b6ffed | 799 | return 0; |
64fbf444 PB |
800 | } |
801 | ||
802 | /* We don't need to call the API often, so using just one | |
803 | * mailbox will probably suffice | |
804 | */ | |
5b8acdc5 HV |
805 | static int cx231xx_api_cmd(struct cx231xx *dev, u32 command, |
806 | u32 inputcnt, u32 outputcnt, ...) | |
64fbf444 PB |
807 | { |
808 | u32 data[CX2341X_MBOX_MAX_DATA]; | |
809 | va_list vargs; | |
810 | int i, err; | |
811 | ||
812 | dprintk(3, "%s() cmds = 0x%08x\n", __func__, command); | |
813 | ||
814 | va_start(vargs, outputcnt); | |
815 | for (i = 0; i < inputcnt; i++) | |
816 | data[i] = va_arg(vargs, int); | |
817 | ||
818 | err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data); | |
819 | for (i = 0; i < outputcnt; i++) { | |
820 | int *vptr = va_arg(vargs, int *); | |
821 | *vptr = data[i]; | |
822 | } | |
823 | va_end(vargs); | |
824 | ||
825 | return err; | |
826 | } | |
827 | ||
88b6ffed | 828 | |
64fbf444 PB |
829 | static int cx231xx_find_mailbox(struct cx231xx *dev) |
830 | { | |
831 | u32 signature[4] = { | |
832 | 0x12345678, 0x34567812, 0x56781234, 0x78123456 | |
833 | }; | |
834 | int signaturecnt = 0; | |
835 | u32 value; | |
836 | int i; | |
837 | int ret = 0; | |
838 | ||
839 | dprintk(2, "%s()\n", __func__); | |
840 | ||
841 | for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/ | |
842 | ret = mc417_memory_read(dev, i, &value); | |
843 | if (ret < 0) | |
844 | return ret; | |
845 | if (value == signature[signaturecnt]) | |
846 | signaturecnt++; | |
847 | else | |
848 | signaturecnt = 0; | |
849 | if (4 == signaturecnt) { | |
5b8acdc5 HV |
850 | dprintk(1, "Mailbox signature found at 0x%x\n", i + 1); |
851 | return i + 1; | |
64fbf444 PB |
852 | } |
853 | } | |
854 | dprintk(3, "Mailbox signature values not found!\n"); | |
ccc5429f | 855 | return -EIO; |
64fbf444 | 856 | } |
82c3ccaa | 857 | |
5b8acdc5 | 858 | static void mci_write_memory_to_gpio(struct cx231xx *dev, u32 address, u32 value, |
64fbf444 PB |
859 | u32 *p_fw_image) |
860 | { | |
64fbf444 PB |
861 | u32 temp = 0; |
862 | int i = 0; | |
863 | ||
5b8acdc5 HV |
864 | temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8); |
865 | temp = temp << 10; | |
955e6ed8 MCC |
866 | *p_fw_image = temp; |
867 | p_fw_image++; | |
5b8acdc5 | 868 | temp = temp | (0x05 << 10); |
955e6ed8 | 869 | *p_fw_image = temp; |
64fbf444 | 870 | p_fw_image++; |
64fbf444 | 871 | |
955e6ed8 | 872 | /*write data byte 1;*/ |
5b8acdc5 HV |
873 | temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00); |
874 | temp = temp << 10; | |
955e6ed8 MCC |
875 | *p_fw_image = temp; |
876 | p_fw_image++; | |
5b8acdc5 | 877 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
878 | *p_fw_image = temp; |
879 | p_fw_image++; | |
880 | ||
881 | /*write data byte 2;*/ | |
5b8acdc5 HV |
882 | temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8); |
883 | temp = temp << 10; | |
955e6ed8 MCC |
884 | *p_fw_image = temp; |
885 | p_fw_image++; | |
5b8acdc5 | 886 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
887 | *p_fw_image = temp; |
888 | p_fw_image++; | |
889 | ||
890 | /*write data byte 3;*/ | |
5b8acdc5 HV |
891 | temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16); |
892 | temp = temp << 10; | |
955e6ed8 MCC |
893 | *p_fw_image = temp; |
894 | p_fw_image++; | |
5b8acdc5 | 895 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
896 | *p_fw_image = temp; |
897 | p_fw_image++; | |
898 | ||
899 | /* write address byte 2;*/ | |
5b8acdc5 HV |
900 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | |
901 | ((address & 0x003F0000) >> 8); | |
902 | temp = temp << 10; | |
955e6ed8 MCC |
903 | *p_fw_image = temp; |
904 | p_fw_image++; | |
5b8acdc5 | 905 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
906 | *p_fw_image = temp; |
907 | p_fw_image++; | |
908 | ||
909 | /* write address byte 1;*/ | |
5b8acdc5 HV |
910 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); |
911 | temp = temp << 10; | |
955e6ed8 MCC |
912 | *p_fw_image = temp; |
913 | p_fw_image++; | |
5b8acdc5 | 914 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
915 | *p_fw_image = temp; |
916 | p_fw_image++; | |
917 | ||
918 | /* write address byte 0;*/ | |
5b8acdc5 HV |
919 | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); |
920 | temp = temp << 10; | |
955e6ed8 MCC |
921 | *p_fw_image = temp; |
922 | p_fw_image++; | |
5b8acdc5 | 923 | temp = temp | (0x05 << 10); |
955e6ed8 MCC |
924 | *p_fw_image = temp; |
925 | p_fw_image++; | |
926 | ||
927 | for (i = 0; i < 6; i++) { | |
928 | *p_fw_image = 0xFFFFFFFF; | |
929 | p_fw_image++; | |
930 | } | |
64fbf444 PB |
931 | } |
932 | ||
933 | ||
934 | static int cx231xx_load_firmware(struct cx231xx *dev) | |
935 | { | |
936 | static const unsigned char magic[8] = { | |
937 | 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa | |
938 | }; | |
939 | const struct firmware *firmware; | |
940 | int i, retval = 0; | |
941 | u32 value = 0; | |
942 | u32 gpio_output = 0; | |
943 | /*u32 checksum = 0;*/ | |
944 | /*u32 *dataptr;*/ | |
945 | u32 transfer_size = 0; | |
946 | u32 fw_data = 0; | |
947 | u32 address = 0; | |
948 | /*u32 current_fw[800];*/ | |
949 | u32 *p_current_fw, *p_fw; | |
950 | u32 *p_fw_data; | |
951 | int frame = 0; | |
952 | u16 _buffer_size = 4096; | |
953 | u8 *p_buffer; | |
954 | ||
9a9dcb4a | 955 | p_current_fw = vmalloc(1884180 * 4); |
64fbf444 | 956 | p_fw = p_current_fw; |
f72cfd85 | 957 | if (p_current_fw == NULL) { |
64fbf444 | 958 | dprintk(2, "FAIL!!!\n"); |
ccc5429f | 959 | return -ENOMEM; |
64fbf444 PB |
960 | } |
961 | ||
9a9dcb4a | 962 | p_buffer = vmalloc(4096); |
f72cfd85 | 963 | if (p_buffer == NULL) { |
64fbf444 | 964 | dprintk(2, "FAIL!!!\n"); |
12548808 | 965 | vfree(p_current_fw); |
ccc5429f | 966 | return -ENOMEM; |
64fbf444 PB |
967 | } |
968 | ||
969 | dprintk(2, "%s()\n", __func__); | |
970 | ||
971 | /* Save GPIO settings before reset of APU */ | |
972 | retval |= mc417_memory_read(dev, 0x9020, &gpio_output); | |
973 | retval |= mc417_memory_read(dev, 0x900C, &value); | |
974 | ||
975 | retval = mc417_register_write(dev, | |
976 | IVTV_REG_VPU, 0xFFFFFFED); | |
977 | retval |= mc417_register_write(dev, | |
978 | IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST); | |
979 | retval |= mc417_register_write(dev, | |
980 | IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800); | |
981 | retval |= mc417_register_write(dev, | |
982 | IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A); | |
983 | retval |= mc417_register_write(dev, | |
984 | IVTV_REG_APU, 0); | |
985 | ||
986 | if (retval != 0) { | |
336fea92 | 987 | dev_err(dev->dev, |
b7085c08 | 988 | "%s: Error with mc417_register_write\n", __func__); |
12548808 SM |
989 | vfree(p_current_fw); |
990 | vfree(p_buffer); | |
ccc5429f | 991 | return retval; |
64fbf444 PB |
992 | } |
993 | ||
994 | retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME, | |
336fea92 | 995 | dev->dev); |
64fbf444 PB |
996 | |
997 | if (retval != 0) { | |
336fea92 | 998 | dev_err(dev->dev, |
b7085c08 | 999 | "ERROR: Hotplug firmware request failed (%s).\n", |
64fbf444 | 1000 | CX231xx_FIRM_IMAGE_NAME); |
336fea92 | 1001 | dev_err(dev->dev, |
b7085c08 | 1002 | "Please fix your hotplug setup, the board will not work without firmware loaded!\n"); |
12548808 SM |
1003 | vfree(p_current_fw); |
1004 | vfree(p_buffer); | |
ccc5429f | 1005 | return retval; |
64fbf444 PB |
1006 | } |
1007 | ||
1008 | if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) { | |
336fea92 | 1009 | dev_err(dev->dev, |
b7085c08 | 1010 | "ERROR: Firmware size mismatch (have %zd, expected %d)\n", |
64fbf444 PB |
1011 | firmware->size, CX231xx_FIRM_IMAGE_SIZE); |
1012 | release_firmware(firmware); | |
12548808 SM |
1013 | vfree(p_current_fw); |
1014 | vfree(p_buffer); | |
ccc5429f | 1015 | return -EINVAL; |
64fbf444 PB |
1016 | } |
1017 | ||
1018 | if (0 != memcmp(firmware->data, magic, 8)) { | |
336fea92 | 1019 | dev_err(dev->dev, |
b7085c08 | 1020 | "ERROR: Firmware magic mismatch, wrong file?\n"); |
64fbf444 | 1021 | release_firmware(firmware); |
12548808 SM |
1022 | vfree(p_current_fw); |
1023 | vfree(p_buffer); | |
ccc5429f | 1024 | return -EINVAL; |
64fbf444 PB |
1025 | } |
1026 | ||
1027 | initGPIO(dev); | |
1028 | ||
1029 | /* transfer to the chip */ | |
1030 | dprintk(2, "Loading firmware to GPIO...\n"); | |
1031 | p_fw_data = (u32 *)firmware->data; | |
62c78c96 | 1032 | dprintk(2, "firmware->size=%zd\n", firmware->size); |
64fbf444 PB |
1033 | for (transfer_size = 0; transfer_size < firmware->size; |
1034 | transfer_size += 4) { | |
1035 | fw_data = *p_fw_data; | |
1036 | ||
5b8acdc5 | 1037 | mci_write_memory_to_gpio(dev, address, fw_data, p_current_fw); |
64fbf444 PB |
1038 | address = address + 1; |
1039 | p_current_fw += 20; | |
1040 | p_fw_data += 1; | |
1041 | } | |
1042 | ||
955e6ed8 | 1043 | /*download the firmware by ep5-out*/ |
64fbf444 PB |
1044 | |
1045 | for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size); | |
bae94dc3 | 1046 | frame++) { |
64fbf444 | 1047 | for (i = 0; i < _buffer_size; i++) { |
bae94dc3 MCC |
1048 | *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF); |
1049 | i++; | |
1050 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8); | |
1051 | i++; | |
1052 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16); | |
1053 | i++; | |
1054 | *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24); | |
64fbf444 PB |
1055 | } |
1056 | cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size); | |
1057 | } | |
1058 | ||
1059 | p_current_fw = p_fw; | |
1060 | vfree(p_current_fw); | |
1061 | p_current_fw = NULL; | |
1062 | uninitGPIO(dev); | |
1063 | release_firmware(firmware); | |
1064 | dprintk(1, "Firmware upload successful.\n"); | |
1065 | ||
1066 | retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, | |
1067 | IVTV_CMD_HW_BLOCKS_RST); | |
1068 | if (retval < 0) { | |
336fea92 | 1069 | dev_err(dev->dev, |
b7085c08 | 1070 | "%s: Error with mc417_register_write\n", |
64fbf444 PB |
1071 | __func__); |
1072 | return retval; | |
1073 | } | |
1074 | /* F/W power up disturbs the GPIOs, restore state */ | |
1075 | retval |= mc417_register_write(dev, 0x9020, gpio_output); | |
1076 | retval |= mc417_register_write(dev, 0x900C, value); | |
1077 | ||
1078 | retval |= mc417_register_read(dev, IVTV_REG_VPU, &value); | |
1079 | retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); | |
1080 | ||
1081 | if (retval < 0) { | |
336fea92 | 1082 | dev_err(dev->dev, |
b7085c08 | 1083 | "%s: Error with mc417_register_write\n", |
64fbf444 PB |
1084 | __func__); |
1085 | return retval; | |
1086 | } | |
1087 | return 0; | |
1088 | } | |
1089 | ||
82c3ccaa | 1090 | static void cx231xx_417_check_encoder(struct cx231xx *dev) |
64fbf444 PB |
1091 | { |
1092 | u32 status, seq; | |
1093 | ||
1094 | status = 0; | |
1095 | seq = 0; | |
1096 | cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq); | |
1097 | dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq); | |
1098 | } | |
1099 | ||
1100 | static void cx231xx_codec_settings(struct cx231xx *dev) | |
1101 | { | |
1102 | dprintk(1, "%s()\n", __func__); | |
1103 | ||
1104 | /* assign frame size */ | |
1105 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0, | |
1106 | dev->ts1.height, dev->ts1.width); | |
1107 | ||
88b6ffed HV |
1108 | dev->mpeg_ctrl_handler.width = dev->ts1.width; |
1109 | dev->mpeg_ctrl_handler.height = dev->ts1.height; | |
64fbf444 | 1110 | |
88b6ffed | 1111 | cx2341x_handler_setup(&dev->mpeg_ctrl_handler); |
64fbf444 PB |
1112 | |
1113 | cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1); | |
1114 | cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1); | |
1115 | } | |
1116 | ||
1117 | static int cx231xx_initialize_codec(struct cx231xx *dev) | |
1118 | { | |
1119 | int version; | |
1120 | int retval; | |
da983503 | 1121 | u32 i; |
64fbf444 PB |
1122 | u32 val = 0; |
1123 | ||
1124 | dprintk(1, "%s()\n", __func__); | |
1125 | cx231xx_disable656(dev); | |
1126 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */ | |
1127 | if (retval < 0) { | |
ed0e3729 | 1128 | dprintk(2, "%s: PING OK\n", __func__); |
64fbf444 PB |
1129 | retval = cx231xx_load_firmware(dev); |
1130 | if (retval < 0) { | |
336fea92 | 1131 | dev_err(dev->dev, |
b7085c08 | 1132 | "%s: f/w load failed\n", __func__); |
64fbf444 PB |
1133 | return retval; |
1134 | } | |
1135 | retval = cx231xx_find_mailbox(dev); | |
1136 | if (retval < 0) { | |
336fea92 | 1137 | dev_err(dev->dev, "%s: mailbox < 0, error\n", |
64fbf444 | 1138 | __func__); |
ccc5429f | 1139 | return retval; |
64fbf444 PB |
1140 | } |
1141 | dev->cx23417_mailbox = retval; | |
1142 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); | |
1143 | if (retval < 0) { | |
336fea92 | 1144 | dev_err(dev->dev, |
b7085c08 | 1145 | "ERROR: cx23417 firmware ping failed!\n"); |
ccc5429f | 1146 | return retval; |
64fbf444 PB |
1147 | } |
1148 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, | |
1149 | &version); | |
1150 | if (retval < 0) { | |
336fea92 | 1151 | dev_err(dev->dev, |
b7085c08 | 1152 | "ERROR: cx23417 firmware get encoder: version failed!\n"); |
ccc5429f | 1153 | return retval; |
64fbf444 PB |
1154 | } |
1155 | dprintk(1, "cx23417 firmware version is 0x%08x\n", version); | |
1156 | msleep(200); | |
1157 | } | |
1158 | ||
1159 | for (i = 0; i < 1; i++) { | |
1160 | retval = mc417_register_read(dev, 0x20f8, &val); | |
5b8acdc5 | 1161 | dprintk(3, "***before enable656() VIM Capture Lines = %d ***\n", |
64fbf444 PB |
1162 | val); |
1163 | if (retval < 0) | |
1164 | return retval; | |
1165 | } | |
1166 | ||
1167 | cx231xx_enable656(dev); | |
69626853 MCC |
1168 | |
1169 | /* stop mpeg capture */ | |
1170 | cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, 1, 3, 4); | |
64fbf444 PB |
1171 | |
1172 | cx231xx_codec_settings(dev); | |
1173 | msleep(60); | |
1174 | ||
1175 | /* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0, | |
1176 | CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115); | |
1177 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0, | |
1178 | CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1179 | 0, 0); | |
1180 | */ | |
da983503 HV |
1181 | |
1182 | #if 0 | |
1183 | /* TODO */ | |
1184 | u32 data[7]; | |
1185 | ||
64fbf444 PB |
1186 | /* Setup to capture VBI */ |
1187 | data[0] = 0x0001BD00; | |
1188 | data[1] = 1; /* frames per interrupt */ | |
1189 | data[2] = 4; /* total bufs */ | |
1190 | data[3] = 0x91559155; /* start codes */ | |
1191 | data[4] = 0x206080C0; /* stop codes */ | |
1192 | data[5] = 6; /* lines */ | |
1193 | data[6] = 64; /* BPL */ | |
da983503 | 1194 | |
64fbf444 PB |
1195 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1], |
1196 | data[2], data[3], data[4], data[5], data[6]); | |
1197 | ||
1198 | for (i = 2; i <= 24; i++) { | |
1199 | int valid; | |
1200 | ||
1201 | valid = ((i >= 19) && (i <= 21)); | |
1202 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i, | |
1203 | valid, 0 , 0, 0); | |
1204 | cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, | |
1205 | i | 0x80000000, valid, 0, 0, 0); | |
1206 | } | |
da983503 | 1207 | #endif |
64fbf444 PB |
1208 | /* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE); |
1209 | msleep(60); | |
1210 | */ | |
1211 | /* initialize the video input */ | |
1212 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0); | |
1213 | if (retval < 0) | |
1214 | return retval; | |
1215 | msleep(60); | |
1216 | ||
1217 | /* Enable VIP style pixel invalidation so we work with scaled mode */ | |
1218 | mc417_memory_write(dev, 2120, 0x00000080); | |
1219 | ||
1220 | /* start capturing to the host interface */ | |
1221 | retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0, | |
1222 | CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE); | |
1223 | if (retval < 0) | |
1224 | return retval; | |
1225 | msleep(10); | |
1226 | ||
1227 | for (i = 0; i < 1; i++) { | |
1228 | mc417_register_read(dev, 0x20f8, &val); | |
5b8acdc5 | 1229 | dprintk(3, "***VIM Capture Lines =%d ***\n", val); |
64fbf444 PB |
1230 | } |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | /* ------------------------------------------------------------------ */ | |
1236 | ||
1237 | static int bb_buf_setup(struct videobuf_queue *q, | |
1238 | unsigned int *count, unsigned int *size) | |
1239 | { | |
1240 | struct cx231xx_fh *fh = q->priv_data; | |
1241 | ||
1242 | fh->dev->ts1.ts_packet_size = mpeglinesize; | |
1243 | fh->dev->ts1.ts_packet_count = mpeglines; | |
1244 | ||
1245 | *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; | |
1246 | *count = mpegbufs; | |
1247 | ||
1248 | return 0; | |
1249 | } | |
5aa95991 | 1250 | |
64fbf444 PB |
1251 | static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf) |
1252 | { | |
1253 | struct cx231xx_fh *fh = vq->priv_data; | |
1254 | struct cx231xx *dev = fh->dev; | |
1255 | unsigned long flags = 0; | |
1256 | ||
09f2082e | 1257 | BUG_ON(in_interrupt()); |
64fbf444 PB |
1258 | |
1259 | spin_lock_irqsave(&dev->video_mode.slock, flags); | |
1260 | if (dev->USE_ISO) { | |
1261 | if (dev->video_mode.isoc_ctl.buf == buf) | |
1262 | dev->video_mode.isoc_ctl.buf = NULL; | |
1263 | } else { | |
1264 | if (dev->video_mode.bulk_ctl.buf == buf) | |
1265 | dev->video_mode.bulk_ctl.buf = NULL; | |
1266 | } | |
1267 | spin_unlock_irqrestore(&dev->video_mode.slock, flags); | |
1268 | videobuf_waiton(vq, &buf->vb, 0, 0); | |
1269 | videobuf_vmalloc_free(&buf->vb); | |
1270 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
1271 | } | |
1272 | ||
82c3ccaa | 1273 | static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb, |
64fbf444 PB |
1274 | struct cx231xx_dmaqueue *dma_q) |
1275 | { | |
5b8acdc5 HV |
1276 | void *vbuf; |
1277 | struct cx231xx_buffer *buf; | |
1278 | u32 tail_data = 0; | |
1279 | char *p_data; | |
64fbf444 | 1280 | |
5b8acdc5 | 1281 | if (dma_q->mpeg_buffer_done == 0) { |
64fbf444 PB |
1282 | if (list_empty(&dma_q->active)) |
1283 | return; | |
1284 | ||
64fbf444 | 1285 | buf = list_entry(dma_q->active.next, |
5b8acdc5 HV |
1286 | struct cx231xx_buffer, vb.queue); |
1287 | dev->video_mode.isoc_ctl.buf = buf; | |
1288 | dma_q->mpeg_buffer_done = 1; | |
1289 | } | |
1290 | /* Fill buffer */ | |
1291 | buf = dev->video_mode.isoc_ctl.buf; | |
1292 | vbuf = videobuf_to_vmalloc(&buf->vb); | |
1293 | ||
1294 | if ((dma_q->mpeg_buffer_completed+len) < | |
1295 | mpeglines*mpeglinesize) { | |
1296 | if (dma_q->add_ps_package_head == | |
1297 | CX231XX_NEED_ADD_PS_PACKAGE_HEAD) { | |
1298 | memcpy(vbuf+dma_q->mpeg_buffer_completed, | |
1299 | dma_q->ps_head, 3); | |
1300 | dma_q->mpeg_buffer_completed = | |
1301 | dma_q->mpeg_buffer_completed + 3; | |
1302 | dma_q->add_ps_package_head = | |
1303 | CX231XX_NONEED_PS_PACKAGE_HEAD; | |
1304 | } | |
1305 | memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len); | |
1306 | dma_q->mpeg_buffer_completed = | |
1307 | dma_q->mpeg_buffer_completed + len; | |
1308 | } else { | |
1309 | dma_q->mpeg_buffer_done = 0; | |
64fbf444 | 1310 | |
5b8acdc5 HV |
1311 | tail_data = |
1312 | mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed; | |
1313 | memcpy(vbuf+dma_q->mpeg_buffer_completed, | |
1314 | data, tail_data); | |
64fbf444 | 1315 | |
64fbf444 PB |
1316 | buf->vb.state = VIDEOBUF_DONE; |
1317 | buf->vb.field_count++; | |
8e6057b5 | 1318 | v4l2_get_timestamp(&buf->vb.ts); |
64fbf444 PB |
1319 | list_del(&buf->vb.queue); |
1320 | wake_up(&buf->vb.done); | |
5b8acdc5 HV |
1321 | dma_q->mpeg_buffer_completed = 0; |
1322 | ||
1323 | if (len - tail_data > 0) { | |
1324 | p_data = data + tail_data; | |
1325 | dma_q->left_data_count = len - tail_data; | |
1326 | memcpy(dma_q->p_left_data, | |
1327 | p_data, len - tail_data); | |
1328 | } | |
1329 | } | |
1330 | } | |
64fbf444 | 1331 | |
5b8acdc5 HV |
1332 | static void buffer_filled(char *data, int len, struct urb *urb, |
1333 | struct cx231xx_dmaqueue *dma_q) | |
1334 | { | |
1335 | void *vbuf; | |
1336 | struct cx231xx_buffer *buf; | |
1337 | ||
1338 | if (list_empty(&dma_q->active)) | |
1339 | return; | |
1340 | ||
1341 | buf = list_entry(dma_q->active.next, | |
1342 | struct cx231xx_buffer, vb.queue); | |
1343 | ||
1344 | /* Fill buffer */ | |
1345 | vbuf = videobuf_to_vmalloc(&buf->vb); | |
1346 | memcpy(vbuf, data, len); | |
1347 | buf->vb.state = VIDEOBUF_DONE; | |
1348 | buf->vb.field_count++; | |
1349 | v4l2_get_timestamp(&buf->vb.ts); | |
1350 | list_del(&buf->vb.queue); | |
1351 | wake_up(&buf->vb.done); | |
64fbf444 | 1352 | } |
5b8acdc5 HV |
1353 | |
1354 | static int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb) | |
64fbf444 PB |
1355 | { |
1356 | struct cx231xx_dmaqueue *dma_q = urb->context; | |
1357 | unsigned char *p_buffer; | |
1358 | u32 buffer_size = 0; | |
1359 | u32 i = 0; | |
1360 | ||
1361 | for (i = 0; i < urb->number_of_packets; i++) { | |
1362 | if (dma_q->left_data_count > 0) { | |
1363 | buffer_copy(dev, dma_q->p_left_data, | |
1364 | dma_q->left_data_count, urb, dma_q); | |
1365 | dma_q->mpeg_buffer_completed = dma_q->left_data_count; | |
1366 | dma_q->left_data_count = 0; | |
1367 | } | |
1368 | ||
1369 | p_buffer = urb->transfer_buffer + | |
1370 | urb->iso_frame_desc[i].offset; | |
1371 | buffer_size = urb->iso_frame_desc[i].actual_length; | |
1372 | ||
1373 | if (buffer_size > 0) | |
1374 | buffer_copy(dev, p_buffer, buffer_size, urb, dma_q); | |
1375 | } | |
1376 | ||
1377 | return 0; | |
1378 | } | |
64fbf444 | 1379 | |
5b8acdc5 HV |
1380 | static int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb) |
1381 | { | |
64fbf444 PB |
1382 | struct cx231xx_dmaqueue *dma_q = urb->context; |
1383 | unsigned char *p_buffer, *buffer; | |
1384 | u32 buffer_size = 0; | |
1385 | ||
1386 | p_buffer = urb->transfer_buffer; | |
1387 | buffer_size = urb->actual_length; | |
1388 | ||
1389 | buffer = kmalloc(buffer_size, GFP_ATOMIC); | |
f8433226 IY |
1390 | if (!buffer) |
1391 | return -ENOMEM; | |
64fbf444 PB |
1392 | |
1393 | memcpy(buffer, dma_q->ps_head, 3); | |
1394 | memcpy(buffer+3, p_buffer, buffer_size-3); | |
1395 | memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3); | |
1396 | ||
1397 | p_buffer = buffer; | |
1398 | buffer_filled(p_buffer, buffer_size, urb, dma_q); | |
1399 | ||
1400 | kfree(buffer); | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | static int bb_buf_prepare(struct videobuf_queue *q, | |
1405 | struct videobuf_buffer *vb, enum v4l2_field field) | |
1406 | { | |
1407 | struct cx231xx_fh *fh = q->priv_data; | |
1408 | struct cx231xx_buffer *buf = | |
1409 | container_of(vb, struct cx231xx_buffer, vb); | |
1410 | struct cx231xx *dev = fh->dev; | |
1411 | int rc = 0, urb_init = 0; | |
1412 | int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; | |
1413 | ||
64fbf444 PB |
1414 | if (0 != buf->vb.baddr && buf->vb.bsize < size) |
1415 | return -EINVAL; | |
1416 | buf->vb.width = fh->dev->ts1.ts_packet_size; | |
1417 | buf->vb.height = fh->dev->ts1.ts_packet_count; | |
1418 | buf->vb.size = size; | |
1419 | buf->vb.field = field; | |
1420 | ||
1421 | if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { | |
1422 | rc = videobuf_iolock(q, &buf->vb, NULL); | |
1423 | if (rc < 0) | |
1424 | goto fail; | |
1425 | } | |
1426 | ||
1427 | if (dev->USE_ISO) { | |
1428 | if (!dev->video_mode.isoc_ctl.num_bufs) | |
1429 | urb_init = 1; | |
1430 | } else { | |
1431 | if (!dev->video_mode.bulk_ctl.num_bufs) | |
1432 | urb_init = 1; | |
1433 | } | |
336fea92 | 1434 | dev_dbg(dev->dev, |
b7085c08 MCC |
1435 | "urb_init=%d dev->video_mode.max_pkt_size=%d\n", |
1436 | urb_init, dev->video_mode.max_pkt_size); | |
64fbf444 PB |
1437 | dev->mode_tv = 1; |
1438 | ||
1439 | if (urb_init) { | |
1440 | rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); | |
1441 | rc = cx231xx_unmute_audio(dev); | |
1442 | if (dev->USE_ISO) { | |
1443 | cx231xx_set_alt_setting(dev, INDEX_TS1, 4); | |
1444 | rc = cx231xx_init_isoc(dev, mpeglines, | |
1445 | mpegbufs, | |
1446 | dev->ts1_mode.max_pkt_size, | |
1447 | cx231xx_isoc_copy); | |
1448 | } else { | |
1449 | cx231xx_set_alt_setting(dev, INDEX_TS1, 0); | |
1450 | rc = cx231xx_init_bulk(dev, mpeglines, | |
1451 | mpegbufs, | |
1452 | dev->ts1_mode.max_pkt_size, | |
1453 | cx231xx_bulk_copy); | |
1454 | } | |
1455 | if (rc < 0) | |
1456 | goto fail; | |
1457 | } | |
1458 | ||
1459 | buf->vb.state = VIDEOBUF_PREPARED; | |
1460 | return 0; | |
1461 | ||
1462 | fail: | |
1463 | free_buffer(q, buf); | |
1464 | return rc; | |
1465 | } | |
1466 | ||
1467 | static void bb_buf_queue(struct videobuf_queue *q, | |
1468 | struct videobuf_buffer *vb) | |
1469 | { | |
1470 | struct cx231xx_fh *fh = q->priv_data; | |
1471 | ||
1472 | struct cx231xx_buffer *buf = | |
1473 | container_of(vb, struct cx231xx_buffer, vb); | |
1474 | struct cx231xx *dev = fh->dev; | |
1475 | struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq; | |
1476 | ||
1477 | buf->vb.state = VIDEOBUF_QUEUED; | |
1478 | list_add_tail(&buf->vb.queue, &vidq->active); | |
1479 | ||
1480 | } | |
1481 | ||
1482 | static void bb_buf_release(struct videobuf_queue *q, | |
1483 | struct videobuf_buffer *vb) | |
1484 | { | |
1485 | struct cx231xx_buffer *buf = | |
1486 | container_of(vb, struct cx231xx_buffer, vb); | |
1487 | /*struct cx231xx_fh *fh = q->priv_data;*/ | |
1488 | /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/ | |
1489 | ||
1490 | free_buffer(q, buf); | |
1491 | } | |
1492 | ||
177267a9 | 1493 | static const struct videobuf_queue_ops cx231xx_qops = { |
64fbf444 PB |
1494 | .buf_setup = bb_buf_setup, |
1495 | .buf_prepare = bb_buf_prepare, | |
1496 | .buf_queue = bb_buf_queue, | |
1497 | .buf_release = bb_buf_release, | |
1498 | }; | |
1499 | ||
1500 | /* ------------------------------------------------------------------ */ | |
1501 | ||
e25cb200 HV |
1502 | static int vidioc_cropcap(struct file *file, void *priv, |
1503 | struct v4l2_cropcap *cc) | |
1504 | { | |
1505 | struct cx231xx_fh *fh = priv; | |
1506 | struct cx231xx *dev = fh->dev; | |
1507 | bool is_50hz = dev->encodernorm.id & V4L2_STD_625_50; | |
1508 | ||
1509 | if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1510 | return -EINVAL; | |
1511 | ||
1512 | cc->bounds.left = 0; | |
1513 | cc->bounds.top = 0; | |
1514 | cc->bounds.width = dev->ts1.width; | |
1515 | cc->bounds.height = dev->ts1.height; | |
1516 | cc->defrect = cc->bounds; | |
1517 | cc->pixelaspect.numerator = is_50hz ? 54 : 11; | |
1518 | cc->pixelaspect.denominator = is_50hz ? 59 : 10; | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
64fbf444 PB |
1523 | static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm) |
1524 | { | |
1525 | struct cx231xx_fh *fh = file->private_data; | |
1526 | struct cx231xx *dev = fh->dev; | |
1527 | ||
1528 | *norm = dev->encodernorm.id; | |
1529 | return 0; | |
1530 | } | |
5b8acdc5 | 1531 | |
314527ac | 1532 | static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id) |
64fbf444 PB |
1533 | { |
1534 | struct cx231xx_fh *fh = file->private_data; | |
1535 | struct cx231xx *dev = fh->dev; | |
1536 | unsigned int i; | |
1537 | ||
1538 | for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++) | |
314527ac | 1539 | if (id & cx231xx_tvnorms[i].id) |
64fbf444 PB |
1540 | break; |
1541 | if (i == ARRAY_SIZE(cx231xx_tvnorms)) | |
1542 | return -EINVAL; | |
1543 | dev->encodernorm = cx231xx_tvnorms[i]; | |
1544 | ||
1545 | if (dev->encodernorm.id & 0xb000) { | |
1546 | dprintk(3, "encodernorm set to NTSC\n"); | |
1547 | dev->norm = V4L2_STD_NTSC; | |
1548 | dev->ts1.height = 480; | |
88b6ffed | 1549 | cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false); |
64fbf444 PB |
1550 | } else { |
1551 | dprintk(3, "encodernorm set to PAL\n"); | |
1552 | dev->norm = V4L2_STD_PAL_B; | |
1553 | dev->ts1.height = 576; | |
88b6ffed | 1554 | cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, true); |
64fbf444 | 1555 | } |
8774bed9 | 1556 | call_all(dev, video, s_std, dev->norm); |
64fbf444 PB |
1557 | /* do mode control overrides */ |
1558 | cx231xx_do_mode_ctrl_overrides(dev); | |
1559 | ||
1560 | dprintk(3, "exit vidioc_s_std() i=0x%x\n", i); | |
1561 | return 0; | |
1562 | } | |
5b8acdc5 | 1563 | |
64fbf444 PB |
1564 | static int vidioc_s_ctrl(struct file *file, void *priv, |
1565 | struct v4l2_control *ctl) | |
1566 | { | |
1567 | struct cx231xx_fh *fh = file->private_data; | |
1568 | struct cx231xx *dev = fh->dev; | |
d715758d | 1569 | struct v4l2_subdev *sd; |
5b8acdc5 | 1570 | |
64fbf444 PB |
1571 | dprintk(3, "enter vidioc_s_ctrl()\n"); |
1572 | /* Update the A/V core */ | |
d715758d HV |
1573 | v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) |
1574 | v4l2_s_ctrl(NULL, sd->ctrl_handler, ctl); | |
64fbf444 PB |
1575 | dprintk(3, "exit vidioc_s_ctrl()\n"); |
1576 | return 0; | |
1577 | } | |
64fbf444 PB |
1578 | |
1579 | static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, | |
1580 | struct v4l2_fmtdesc *f) | |
1581 | { | |
64fbf444 PB |
1582 | if (f->index != 0) |
1583 | return -EINVAL; | |
1584 | ||
1585 | strlcpy(f->description, "MPEG", sizeof(f->description)); | |
1586 | f->pixelformat = V4L2_PIX_FMT_MPEG; | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
1591 | static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, | |
1592 | struct v4l2_format *f) | |
1593 | { | |
1594 | struct cx231xx_fh *fh = file->private_data; | |
1595 | struct cx231xx *dev = fh->dev; | |
5aa95991 | 1596 | |
64fbf444 | 1597 | dprintk(3, "enter vidioc_g_fmt_vid_cap()\n"); |
5aa95991 | 1598 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
64fbf444 | 1599 | f->fmt.pix.bytesperline = 0; |
5aa95991 HV |
1600 | f->fmt.pix.sizeimage = mpeglines * mpeglinesize; |
1601 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
1602 | f->fmt.pix.width = dev->ts1.width; | |
1603 | f->fmt.pix.height = dev->ts1.height; | |
1604 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; | |
5aa95991 HV |
1605 | dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n", |
1606 | dev->ts1.width, dev->ts1.height); | |
64fbf444 PB |
1607 | dprintk(3, "exit vidioc_g_fmt_vid_cap()\n"); |
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, | |
1612 | struct v4l2_format *f) | |
1613 | { | |
1614 | struct cx231xx_fh *fh = file->private_data; | |
1615 | struct cx231xx *dev = fh->dev; | |
5aa95991 | 1616 | |
64fbf444 | 1617 | dprintk(3, "enter vidioc_try_fmt_vid_cap()\n"); |
5aa95991 | 1618 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; |
64fbf444 | 1619 | f->fmt.pix.bytesperline = 0; |
5aa95991 HV |
1620 | f->fmt.pix.sizeimage = mpeglines * mpeglinesize; |
1621 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; | |
1622 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
5aa95991 HV |
1623 | dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n", |
1624 | dev->ts1.width, dev->ts1.height); | |
64fbf444 PB |
1625 | dprintk(3, "exit vidioc_try_fmt_vid_cap()\n"); |
1626 | return 0; | |
1627 | } | |
1628 | ||
64fbf444 PB |
1629 | static int vidioc_reqbufs(struct file *file, void *priv, |
1630 | struct v4l2_requestbuffers *p) | |
1631 | { | |
1632 | struct cx231xx_fh *fh = file->private_data; | |
1633 | ||
1634 | return videobuf_reqbufs(&fh->vidq, p); | |
1635 | } | |
1636 | ||
1637 | static int vidioc_querybuf(struct file *file, void *priv, | |
1638 | struct v4l2_buffer *p) | |
1639 | { | |
1640 | struct cx231xx_fh *fh = file->private_data; | |
1641 | ||
1642 | return videobuf_querybuf(&fh->vidq, p); | |
1643 | } | |
1644 | ||
1645 | static int vidioc_qbuf(struct file *file, void *priv, | |
1646 | struct v4l2_buffer *p) | |
1647 | { | |
1648 | struct cx231xx_fh *fh = file->private_data; | |
1649 | ||
1650 | return videobuf_qbuf(&fh->vidq, p); | |
1651 | } | |
1652 | ||
1653 | static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) | |
1654 | { | |
1655 | struct cx231xx_fh *fh = priv; | |
1656 | ||
1657 | return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK); | |
1658 | } | |
1659 | ||
1660 | ||
1661 | static int vidioc_streamon(struct file *file, void *priv, | |
1662 | enum v4l2_buf_type i) | |
1663 | { | |
1664 | struct cx231xx_fh *fh = file->private_data; | |
64fbf444 | 1665 | struct cx231xx *dev = fh->dev; |
5b8acdc5 | 1666 | |
64fbf444 | 1667 | dprintk(3, "enter vidioc_streamon()\n"); |
5b8acdc5 HV |
1668 | cx231xx_set_alt_setting(dev, INDEX_TS1, 0); |
1669 | cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); | |
1670 | if (dev->USE_ISO) | |
1671 | cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS, | |
1672 | CX231XX_NUM_BUFS, | |
1673 | dev->video_mode.max_pkt_size, | |
1674 | cx231xx_isoc_copy); | |
1675 | else { | |
1676 | cx231xx_init_bulk(dev, 320, | |
1677 | 5, | |
1678 | dev->ts1_mode.max_pkt_size, | |
1679 | cx231xx_bulk_copy); | |
1680 | } | |
64fbf444 PB |
1681 | dprintk(3, "exit vidioc_streamon()\n"); |
1682 | return videobuf_streamon(&fh->vidq); | |
1683 | } | |
1684 | ||
1685 | static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) | |
1686 | { | |
1687 | struct cx231xx_fh *fh = file->private_data; | |
1688 | ||
1689 | return videobuf_streamoff(&fh->vidq); | |
1690 | } | |
1691 | ||
64fbf444 PB |
1692 | static int vidioc_log_status(struct file *file, void *priv) |
1693 | { | |
1694 | struct cx231xx_fh *fh = priv; | |
1695 | struct cx231xx *dev = fh->dev; | |
64fbf444 | 1696 | |
64fbf444 | 1697 | call_all(dev, core, log_status); |
88b6ffed | 1698 | return v4l2_ctrl_log_status(file, priv); |
64fbf444 PB |
1699 | } |
1700 | ||
1701 | static int mpeg_open(struct file *file) | |
1702 | { | |
b86d1544 HV |
1703 | struct video_device *vdev = video_devdata(file); |
1704 | struct cx231xx *dev = video_drvdata(file); | |
64fbf444 | 1705 | struct cx231xx_fh *fh; |
64fbf444 PB |
1706 | |
1707 | dprintk(2, "%s()\n", __func__); | |
1708 | ||
1265f080 HV |
1709 | if (mutex_lock_interruptible(&dev->lock)) |
1710 | return -ERESTARTSYS; | |
64fbf444 PB |
1711 | |
1712 | /* allocate + initialize per filehandle data */ | |
1713 | fh = kzalloc(sizeof(*fh), GFP_KERNEL); | |
1714 | if (NULL == fh) { | |
1715 | mutex_unlock(&dev->lock); | |
1716 | return -ENOMEM; | |
1717 | } | |
1718 | ||
1719 | file->private_data = fh; | |
b86d1544 HV |
1720 | v4l2_fh_init(&fh->fh, vdev); |
1721 | fh->dev = dev; | |
64fbf444 PB |
1722 | |
1723 | ||
1724 | videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops, | |
1725 | NULL, &dev->video_mode.slock, | |
1726 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED, | |
1265f080 | 1727 | sizeof(struct cx231xx_buffer), fh, &dev->lock); |
64fbf444 PB |
1728 | /* |
1729 | videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops, | |
336fea92 | 1730 | dev->dev, &dev->ts1.slock, |
64fbf444 PB |
1731 | V4L2_BUF_TYPE_VIDEO_CAPTURE, |
1732 | V4L2_FIELD_INTERLACED, | |
1733 | sizeof(struct cx231xx_buffer), | |
1265f080 | 1734 | fh, &dev->lock); |
64fbf444 PB |
1735 | */ |
1736 | ||
64fbf444 PB |
1737 | cx231xx_set_alt_setting(dev, INDEX_VANC, 1); |
1738 | cx231xx_set_gpio_value(dev, 2, 0); | |
1739 | ||
1740 | cx231xx_initialize_codec(dev); | |
1741 | ||
1742 | mutex_unlock(&dev->lock); | |
b86d1544 | 1743 | v4l2_fh_add(&fh->fh); |
64fbf444 PB |
1744 | cx231xx_start_TS1(dev); |
1745 | ||
1746 | return 0; | |
1747 | } | |
1748 | ||
1749 | static int mpeg_release(struct file *file) | |
1750 | { | |
1751 | struct cx231xx_fh *fh = file->private_data; | |
1752 | struct cx231xx *dev = fh->dev; | |
1753 | ||
dd067a8d | 1754 | dprintk(3, "mpeg_release()! dev=0x%p\n", dev); |
64fbf444 | 1755 | |
64fbf444 PB |
1756 | mutex_lock(&dev->lock); |
1757 | ||
1758 | cx231xx_stop_TS1(dev); | |
1759 | ||
5b8acdc5 HV |
1760 | /* do this before setting alternate! */ |
1761 | if (dev->USE_ISO) | |
1762 | cx231xx_uninit_isoc(dev); | |
1763 | else | |
1764 | cx231xx_uninit_bulk(dev); | |
1765 | cx231xx_set_mode(dev, CX231XX_SUSPEND); | |
64fbf444 | 1766 | |
5b8acdc5 HV |
1767 | cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, |
1768 | CX231xx_END_NOW, CX231xx_MPEG_CAPTURE, | |
1769 | CX231xx_RAW_BITS_NONE); | |
64fbf444 PB |
1770 | |
1771 | /* FIXME: Review this crap */ | |
1772 | /* Shut device down on last close */ | |
1773 | if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) { | |
1774 | if (atomic_dec_return(&dev->v4l_reader_count) == 0) { | |
1775 | /* stop mpeg capture */ | |
1776 | ||
1777 | msleep(500); | |
1778 | cx231xx_417_check_encoder(dev); | |
1779 | ||
1780 | } | |
1781 | } | |
1782 | ||
1783 | if (fh->vidq.streaming) | |
1784 | videobuf_streamoff(&fh->vidq); | |
1785 | if (fh->vidq.reading) | |
1786 | videobuf_read_stop(&fh->vidq); | |
1787 | ||
1788 | videobuf_mmap_free(&fh->vidq); | |
b86d1544 HV |
1789 | v4l2_fh_del(&fh->fh); |
1790 | v4l2_fh_exit(&fh->fh); | |
64fbf444 PB |
1791 | kfree(fh); |
1792 | mutex_unlock(&dev->lock); | |
1793 | return 0; | |
1794 | } | |
1795 | ||
1796 | static ssize_t mpeg_read(struct file *file, char __user *data, | |
1797 | size_t count, loff_t *ppos) | |
1798 | { | |
1799 | struct cx231xx_fh *fh = file->private_data; | |
1800 | struct cx231xx *dev = fh->dev; | |
1801 | ||
64fbf444 PB |
1802 | /* Deal w/ A/V decoder * and mpeg encoder sync issues. */ |
1803 | /* Start mpeg encoder on first read. */ | |
1804 | if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) { | |
1805 | if (atomic_inc_return(&dev->v4l_reader_count) == 1) { | |
1806 | if (cx231xx_initialize_codec(dev) < 0) | |
1807 | return -EINVAL; | |
1808 | } | |
1809 | } | |
1810 | ||
1811 | return videobuf_read_stream(&fh->vidq, data, count, ppos, 0, | |
1812 | file->f_flags & O_NONBLOCK); | |
1813 | } | |
1814 | ||
c23e0cb8 | 1815 | static __poll_t mpeg_poll(struct file *file, |
64fbf444 PB |
1816 | struct poll_table_struct *wait) |
1817 | { | |
01699437 | 1818 | __poll_t req_events = poll_requested_events(wait); |
64fbf444 | 1819 | struct cx231xx_fh *fh = file->private_data; |
88b6ffed | 1820 | struct cx231xx *dev = fh->dev; |
c23e0cb8 | 1821 | __poll_t res = 0; |
64fbf444 | 1822 | |
88b6ffed | 1823 | if (v4l2_event_pending(&fh->fh)) |
a9a08845 | 1824 | res |= EPOLLPRI; |
88b6ffed HV |
1825 | else |
1826 | poll_wait(file, &fh->fh.wait, wait); | |
1827 | ||
a9a08845 | 1828 | if (!(req_events & (EPOLLIN | EPOLLRDNORM))) |
88b6ffed HV |
1829 | return res; |
1830 | ||
1831 | mutex_lock(&dev->lock); | |
1832 | res |= videobuf_poll_stream(file, &fh->vidq, wait); | |
1833 | mutex_unlock(&dev->lock); | |
1834 | return res; | |
64fbf444 PB |
1835 | } |
1836 | ||
1837 | static int mpeg_mmap(struct file *file, struct vm_area_struct *vma) | |
1838 | { | |
1839 | struct cx231xx_fh *fh = file->private_data; | |
64fbf444 PB |
1840 | |
1841 | dprintk(2, "%s()\n", __func__); | |
1842 | ||
1843 | return videobuf_mmap_mapper(&fh->vidq, vma); | |
1844 | } | |
1845 | ||
ff05c984 | 1846 | static const struct v4l2_file_operations mpeg_fops = { |
64fbf444 PB |
1847 | .owner = THIS_MODULE, |
1848 | .open = mpeg_open, | |
1849 | .release = mpeg_release, | |
1850 | .read = mpeg_read, | |
1851 | .poll = mpeg_poll, | |
1852 | .mmap = mpeg_mmap, | |
1265f080 | 1853 | .unlocked_ioctl = video_ioctl2, |
64fbf444 PB |
1854 | }; |
1855 | ||
1856 | static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { | |
1857 | .vidioc_s_std = vidioc_s_std, | |
1858 | .vidioc_g_std = vidioc_g_std, | |
b86d1544 HV |
1859 | .vidioc_g_tuner = cx231xx_g_tuner, |
1860 | .vidioc_s_tuner = cx231xx_s_tuner, | |
1861 | .vidioc_g_frequency = cx231xx_g_frequency, | |
1862 | .vidioc_s_frequency = cx231xx_s_frequency, | |
1863 | .vidioc_enum_input = cx231xx_enum_input, | |
1864 | .vidioc_g_input = cx231xx_g_input, | |
1865 | .vidioc_s_input = cx231xx_s_input, | |
64fbf444 | 1866 | .vidioc_s_ctrl = vidioc_s_ctrl, |
e25cb200 | 1867 | .vidioc_cropcap = vidioc_cropcap, |
bc08734c | 1868 | .vidioc_querycap = cx231xx_querycap, |
64fbf444 PB |
1869 | .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, |
1870 | .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, | |
1871 | .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, | |
3f926e32 | 1872 | .vidioc_s_fmt_vid_cap = vidioc_try_fmt_vid_cap, |
64fbf444 PB |
1873 | .vidioc_reqbufs = vidioc_reqbufs, |
1874 | .vidioc_querybuf = vidioc_querybuf, | |
1875 | .vidioc_qbuf = vidioc_qbuf, | |
1876 | .vidioc_dqbuf = vidioc_dqbuf, | |
1877 | .vidioc_streamon = vidioc_streamon, | |
1878 | .vidioc_streamoff = vidioc_streamoff, | |
64fbf444 | 1879 | .vidioc_log_status = vidioc_log_status, |
64fbf444 | 1880 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
b86d1544 HV |
1881 | .vidioc_g_register = cx231xx_g_register, |
1882 | .vidioc_s_register = cx231xx_s_register, | |
64fbf444 | 1883 | #endif |
88b6ffed HV |
1884 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
1885 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
64fbf444 PB |
1886 | }; |
1887 | ||
1888 | static struct video_device cx231xx_mpeg_template = { | |
1889 | .name = "cx231xx", | |
1890 | .fops = &mpeg_fops, | |
1891 | .ioctl_ops = &mpeg_ioctl_ops, | |
1892 | .minor = -1, | |
88b6ffed | 1893 | .tvnorms = V4L2_STD_ALL, |
64fbf444 PB |
1894 | }; |
1895 | ||
1896 | void cx231xx_417_unregister(struct cx231xx *dev) | |
1897 | { | |
1898 | dprintk(1, "%s()\n", __func__); | |
1899 | dprintk(3, "%s()\n", __func__); | |
1900 | ||
60acf187 HV |
1901 | if (video_is_registered(&dev->v4l_device)) { |
1902 | video_unregister_device(&dev->v4l_device); | |
88b6ffed | 1903 | v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl); |
64fbf444 PB |
1904 | } |
1905 | } | |
1906 | ||
88b6ffed HV |
1907 | static int cx231xx_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val) |
1908 | { | |
1909 | struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler); | |
1910 | int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1; | |
ebf984bb HV |
1911 | struct v4l2_subdev_format format = { |
1912 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1913 | }; | |
88b6ffed HV |
1914 | |
1915 | /* fix videodecoder resolution */ | |
ebf984bb HV |
1916 | format.format.width = cxhdl->width / (is_mpeg1 ? 2 : 1); |
1917 | format.format.height = cxhdl->height; | |
1918 | format.format.code = MEDIA_BUS_FMT_FIXED; | |
1919 | v4l2_subdev_call(dev->sd_cx25840, pad, set_fmt, NULL, &format); | |
88b6ffed HV |
1920 | return 0; |
1921 | } | |
1922 | ||
1923 | static int cx231xx_s_audio_sampling_freq(struct cx2341x_handler *cxhdl, u32 idx) | |
1924 | { | |
1925 | static const u32 freqs[3] = { 44100, 48000, 32000 }; | |
1926 | struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler); | |
1927 | ||
1928 | /* The audio clock of the digitizer must match the codec sample | |
1929 | rate otherwise you get some very strange effects. */ | |
1930 | if (idx < ARRAY_SIZE(freqs)) | |
1931 | call_all(dev, audio, s_clock_freq, freqs[idx]); | |
1932 | return 0; | |
1933 | } | |
1934 | ||
083206fc | 1935 | static const struct cx2341x_handler_ops cx231xx_ops = { |
88b6ffed HV |
1936 | /* needed for the video clock freq */ |
1937 | .s_audio_sampling_freq = cx231xx_s_audio_sampling_freq, | |
1938 | /* needed for setting up the video resolution */ | |
1939 | .s_video_encoding = cx231xx_s_video_encoding, | |
1940 | }; | |
1941 | ||
60acf187 | 1942 | static void cx231xx_video_dev_init( |
64fbf444 PB |
1943 | struct cx231xx *dev, |
1944 | struct usb_device *usbdev, | |
60acf187 HV |
1945 | struct video_device *vfd, |
1946 | const struct video_device *template, | |
1947 | const char *type) | |
64fbf444 | 1948 | { |
64fbf444 | 1949 | dprintk(1, "%s()\n", __func__); |
64fbf444 | 1950 | *vfd = *template; |
64fbf444 PB |
1951 | snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, |
1952 | type, cx231xx_boards[dev->model].name); | |
1953 | ||
1954 | vfd->v4l2_dev = &dev->v4l2_dev; | |
1265f080 | 1955 | vfd->lock = &dev->lock; |
60acf187 | 1956 | vfd->release = video_device_release_empty; |
88b6ffed | 1957 | vfd->ctrl_handler = &dev->mpeg_ctrl_handler.hdl; |
b86d1544 HV |
1958 | video_set_drvdata(vfd, dev); |
1959 | if (dev->tuner_type == TUNER_ABSENT) { | |
1960 | v4l2_disable_ioctl(vfd, VIDIOC_G_FREQUENCY); | |
1961 | v4l2_disable_ioctl(vfd, VIDIOC_S_FREQUENCY); | |
1962 | v4l2_disable_ioctl(vfd, VIDIOC_G_TUNER); | |
1963 | v4l2_disable_ioctl(vfd, VIDIOC_S_TUNER); | |
1964 | } | |
64fbf444 PB |
1965 | } |
1966 | ||
1967 | int cx231xx_417_register(struct cx231xx *dev) | |
1968 | { | |
1969 | /* FIXME: Port1 hardcoded here */ | |
1970 | int err = -ENODEV; | |
1971 | struct cx231xx_tsport *tsport = &dev->ts1; | |
1972 | ||
1973 | dprintk(1, "%s()\n", __func__); | |
1974 | ||
1975 | /* Set default TV standard */ | |
1976 | dev->encodernorm = cx231xx_tvnorms[0]; | |
1977 | ||
1978 | if (dev->encodernorm.id & V4L2_STD_525_60) | |
1979 | tsport->height = 480; | |
1980 | else | |
1981 | tsport->height = 576; | |
1982 | ||
1983 | tsport->width = 720; | |
88b6ffed HV |
1984 | err = cx2341x_handler_init(&dev->mpeg_ctrl_handler, 50); |
1985 | if (err) { | |
1986 | dprintk(3, "%s: can't init cx2341x controls\n", dev->name); | |
1987 | return err; | |
1988 | } | |
1989 | dev->mpeg_ctrl_handler.func = cx231xx_mbox_func; | |
1990 | dev->mpeg_ctrl_handler.priv = dev; | |
1991 | dev->mpeg_ctrl_handler.ops = &cx231xx_ops; | |
1992 | if (dev->sd_cx25840) | |
1993 | v4l2_ctrl_add_handler(&dev->mpeg_ctrl_handler.hdl, | |
1994 | dev->sd_cx25840->ctrl_handler, NULL); | |
1995 | if (dev->mpeg_ctrl_handler.hdl.error) { | |
1996 | err = dev->mpeg_ctrl_handler.hdl.error; | |
1997 | dprintk(3, "%s: can't add cx25840 controls\n", dev->name); | |
1998 | v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl); | |
1999 | return err; | |
2000 | } | |
64fbf444 PB |
2001 | dev->norm = V4L2_STD_NTSC; |
2002 | ||
88b6ffed HV |
2003 | dev->mpeg_ctrl_handler.port = CX2341X_PORT_SERIAL; |
2004 | cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false); | |
64fbf444 PB |
2005 | |
2006 | /* Allocate and initialize V4L video device */ | |
60acf187 HV |
2007 | cx231xx_video_dev_init(dev, dev->udev, |
2008 | &dev->v4l_device, &cx231xx_mpeg_template, "mpeg"); | |
2009 | err = video_register_device(&dev->v4l_device, | |
64fbf444 PB |
2010 | VFL_TYPE_GRABBER, -1); |
2011 | if (err < 0) { | |
2012 | dprintk(3, "%s: can't register mpeg device\n", dev->name); | |
88b6ffed | 2013 | v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl); |
64fbf444 PB |
2014 | return err; |
2015 | } | |
2016 | ||
2017 | dprintk(3, "%s: registered device video%d [mpeg]\n", | |
60acf187 | 2018 | dev->name, dev->v4l_device.num); |
64fbf444 PB |
2019 | |
2020 | return 0; | |
2021 | } | |
b8320e95 TG |
2022 | |
2023 | MODULE_FIRMWARE(CX231xx_FIRM_IMAGE_NAME); |