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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6-block.git] / drivers / media / tuners / mxl5007t.c
CommitLineData
2a83e4d5
MK		 1/*
2 * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
3 *
7434ca43 4 * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
2a83e4d5
MK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
2a83e4d5
MK		 15 */
16
17#include <linux/i2c.h>
18#include <linux/types.h>
19#include <linux/videodev2.h>
20#include "tuner-i2c.h"
21#include "mxl5007t.h"
22
23static DEFINE_MUTEX(mxl5007t_list_mutex);
24static LIST_HEAD(hybrid_tuner_instance_list);
25
26static int mxl5007t_debug;
27module_param_named(debug, mxl5007t_debug, int, 0644);
28MODULE_PARM_DESC(debug, "set debug level");
29
30/* ------------------------------------------------------------------------- */
31
32#define mxl_printk(kern, fmt, arg...) \
33 printk(kern "%s: " fmt "\n", __func__, ##arg)
34
35#define mxl_err(fmt, arg...) \
36 mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
37
38#define mxl_warn(fmt, arg...) \
39 mxl_printk(KERN_WARNING, fmt, ##arg)
40
41#define mxl_info(fmt, arg...) \
42 mxl_printk(KERN_INFO, fmt, ##arg)
43
44#define mxl_debug(fmt, arg...) \
45({ \
46 if (mxl5007t_debug) \
47 mxl_printk(KERN_DEBUG, fmt, ##arg); \
48})
49
50#define mxl_fail(ret) \
51({ \
52 int __ret; \
53 __ret = (ret < 0); \
54 if (__ret) \
55 mxl_printk(KERN_ERR, "error %d on line %d", \
56 ret, __LINE__); \
57 __ret; \
58})
59
60/* ------------------------------------------------------------------------- */
61
2a83e4d5 62enum mxl5007t_mode {
7434ca43
MK		 63 MxL_MODE_ISDBT = 0,
64 MxL_MODE_DVBT = 1,
65 MxL_MODE_ATSC = 2,
66 MxL_MODE_CABLE = 0x10,
2a83e4d5
MK		 67};
68
69enum mxl5007t_chip_version {
70 MxL_UNKNOWN_ID = 0x00,
71 MxL_5007_V1_F1 = 0x11,
72 MxL_5007_V1_F2 = 0x12,
7434ca43 73 MxL_5007_V4 = 0x14,
2a83e4d5
MK		 74 MxL_5007_V2_100_F1 = 0x21,
75 MxL_5007_V2_100_F2 = 0x22,
76 MxL_5007_V2_200_F1 = 0x23,
77 MxL_5007_V2_200_F2 = 0x24,
78};
79
80struct reg_pair_t {
81 u8 reg;
82 u8 val;
83};
84
85/* ------------------------------------------------------------------------- */
86
87static struct reg_pair_t init_tab[] = {
7434ca43
MK		 88 { 0x02, 0x06 },
89 { 0x03, 0x48 },
90 { 0x05, 0x04 },
91 { 0x06, 0x10 },
92 { 0x2e, 0x15 }, /* OVERRIDE */
93 { 0x30, 0x10 }, /* OVERRIDE */
94 { 0x45, 0x58 }, /* OVERRIDE */
95 { 0x48, 0x19 }, /* OVERRIDE */
96 { 0x52, 0x03 }, /* OVERRIDE */
97 { 0x53, 0x44 }, /* OVERRIDE */
98 { 0x6a, 0x4b }, /* OVERRIDE */
99 { 0x76, 0x00 }, /* OVERRIDE */
100 { 0x78, 0x18 }, /* OVERRIDE */
101 { 0x7a, 0x17 }, /* OVERRIDE */
102 { 0x85, 0x06 }, /* OVERRIDE */
103 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
2a83e4d5
MK		 104 { 0, 0 }
105};
106
107static struct reg_pair_t init_tab_cable[] = {
7434ca43
MK		 108 { 0x02, 0x06 },
109 { 0x03, 0x48 },
110 { 0x05, 0x04 },
111 { 0x06, 0x10 },
112 { 0x09, 0x3f },
113 { 0x0a, 0x3f },
114 { 0x0b, 0x3f },
115 { 0x2e, 0x15 }, /* OVERRIDE */
116 { 0x30, 0x10 }, /* OVERRIDE */
117 { 0x45, 0x58 }, /* OVERRIDE */
118 { 0x48, 0x19 }, /* OVERRIDE */
119 { 0x52, 0x03 }, /* OVERRIDE */
120 { 0x53, 0x44 }, /* OVERRIDE */
121 { 0x6a, 0x4b }, /* OVERRIDE */
122 { 0x76, 0x00 }, /* OVERRIDE */
123 { 0x78, 0x18 }, /* OVERRIDE */
124 { 0x7a, 0x17 }, /* OVERRIDE */
125 { 0x85, 0x06 }, /* OVERRIDE */
126 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
2a83e4d5
MK		 127 { 0, 0 }
128};
129
130/* ------------------------------------------------------------------------- */
131
132static struct reg_pair_t reg_pair_rftune[] = {
7434ca43
MK		 133 { 0x0f, 0x00 }, /* abort tune */
134 { 0x0c, 0x15 },
135 { 0x0d, 0x40 },
136 { 0x0e, 0x0e },
137 { 0x1f, 0x87 }, /* OVERRIDE */
138 { 0x20, 0x1f }, /* OVERRIDE */
139 { 0x21, 0x87 }, /* OVERRIDE */
140 { 0x22, 0x1f }, /* OVERRIDE */
141 { 0x80, 0x01 }, /* freq dependent */
142 { 0x0f, 0x01 }, /* start tune */
2a83e4d5
MK		 143 { 0, 0 }
144};
145
146/* ------------------------------------------------------------------------- */
147
148struct mxl5007t_state {
149 struct list_head hybrid_tuner_instance_list;
150 struct tuner_i2c_props i2c_props;
151
152 struct mutex lock;
153
154 struct mxl5007t_config *config;
155
156 enum mxl5007t_chip_version chip_id;
157
158 struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
159 struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
160 struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
161
d697b4ce
MK		 162 enum mxl5007t_if_freq if_freq;
163
2a83e4d5
MK		 164 u32 frequency;
165 u32 bandwidth;
166};
167
168/* ------------------------------------------------------------------------- */
169
170/* called by _init and _rftun to manipulate the register arrays */
171
172static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
173{
174 unsigned int i = 0;
175
176 while (reg_pair[i].reg || reg_pair[i].val) {
177 if (reg_pair[i].reg == reg) {
178 reg_pair[i].val &= ~mask;
179 reg_pair[i].val |= val;
180 }
181 i++;
182
183 }
184 return;
185}
186
187static void copy_reg_bits(struct reg_pair_t *reg_pair1,
188 struct reg_pair_t *reg_pair2)
189{
190 unsigned int i, j;
191
192 i = j = 0;
193
194 while (reg_pair1[i].reg || reg_pair1[i].val) {
c95a419a 195 while (reg_pair2[j].reg || reg_pair2[j].val) {
2a83e4d5
MK		 196 if (reg_pair1[i].reg != reg_pair2[j].reg) {
197 j++;
198 continue;
199 }
200 reg_pair2[j].val = reg_pair1[i].val;
201 break;
202 }
203 i++;
204 }
205 return;
206}
207
208/* ------------------------------------------------------------------------- */
209
210static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
211 enum mxl5007t_mode mode,
212 s32 if_diff_out_level)
213{
214 switch (mode) {
7434ca43
MK		 215 case MxL_MODE_ATSC:
216 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
2a83e4d5 217 break;
7434ca43
MK		 218 case MxL_MODE_DVBT:
219 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
2a83e4d5 220 break;
7434ca43
MK		 221 case MxL_MODE_ISDBT:
222 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
223 break;
224 case MxL_MODE_CABLE:
225 set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
226 set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
2a83e4d5 227 8 - if_diff_out_level);
7434ca43 228 set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
2a83e4d5 229 break;
2a83e4d5
MK		 230 default:
231 mxl_fail(-EINVAL);
232 }
233 return;
234}
235
236static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
237 enum mxl5007t_if_freq if_freq,
238 int invert_if)
239{
240 u8 val;
241
242 switch (if_freq) {
243 case MxL_IF_4_MHZ:
244 val = 0x00;
245 break;
246 case MxL_IF_4_5_MHZ:
7434ca43 247 val = 0x02;
2a83e4d5
MK		 248 break;
249 case MxL_IF_4_57_MHZ:
7434ca43 250 val = 0x03;
2a83e4d5
MK		 251 break;
252 case MxL_IF_5_MHZ:
7434ca43 253 val = 0x04;
2a83e4d5
MK		 254 break;
255 case MxL_IF_5_38_MHZ:
7434ca43 256 val = 0x05;
2a83e4d5
MK		 257 break;
258 case MxL_IF_6_MHZ:
7434ca43 259 val = 0x06;
2a83e4d5
MK		 260 break;
261 case MxL_IF_6_28_MHZ:
7434ca43 262 val = 0x07;
2a83e4d5
MK		 263 break;
264 case MxL_IF_9_1915_MHZ:
7434ca43 265 val = 0x08;
2a83e4d5
MK		 266 break;
267 case MxL_IF_35_25_MHZ:
7434ca43 268 val = 0x09;
2a83e4d5
MK		 269 break;
270 case MxL_IF_36_15_MHZ:
7434ca43 271 val = 0x0a;
2a83e4d5
MK		 272 break;
273 case MxL_IF_44_MHZ:
7434ca43 274 val = 0x0b;
2a83e4d5
MK		 275 break;
276 default:
277 mxl_fail(-EINVAL);
278 return;
279 }
7434ca43 280 set_reg_bits(state->tab_init, 0x02, 0x0f, val);
2a83e4d5
MK		 281
282 /* set inverted IF or normal IF */
7434ca43 283 set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
2a83e4d5 284
d697b4ce
MK		 285 state->if_freq = if_freq;
286
2a83e4d5
MK		 287 return;
288}
289
290static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
291 enum mxl5007t_xtal_freq xtal_freq)
292{
2a83e4d5
MK		 293 switch (xtal_freq) {
294 case MxL_XTAL_16_MHZ:
7434ca43
MK		 295 /* select xtal freq & ref freq */
296 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
297 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
2a83e4d5
MK		 298 break;
299 case MxL_XTAL_20_MHZ:
7434ca43
MK		 300 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
301 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
2a83e4d5
MK		 302 break;
303 case MxL_XTAL_20_25_MHZ:
7434ca43
MK		 304 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
305 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
2a83e4d5
MK		 306 break;
307 case MxL_XTAL_20_48_MHZ:
7434ca43
MK		 308 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
309 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
2a83e4d5
MK		 310 break;
311 case MxL_XTAL_24_MHZ:
7434ca43
MK		 312 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
313 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
2a83e4d5
MK		 314 break;
315 case MxL_XTAL_25_MHZ:
7434ca43
MK		 316 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
317 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
2a83e4d5
MK		 318 break;
319 case MxL_XTAL_25_14_MHZ:
7434ca43
MK		 320 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
321 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
2a83e4d5
MK		 322 break;
323 case MxL_XTAL_27_MHZ:
7434ca43
MK		 324 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
325 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
2a83e4d5
MK		 326 break;
327 case MxL_XTAL_28_8_MHZ:
7434ca43
MK		 328 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
329 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
2a83e4d5
MK		 330 break;
331 case MxL_XTAL_32_MHZ:
7434ca43
MK		 332 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
333 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
2a83e4d5
MK		 334 break;
335 case MxL_XTAL_40_MHZ:
7434ca43
MK		 336 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
337 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
2a83e4d5
MK		 338 break;
339 case MxL_XTAL_44_MHZ:
7434ca43
MK		 340 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
341 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
2a83e4d5
MK		 342 break;
343 case MxL_XTAL_48_MHZ:
7434ca43
MK		 344 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
345 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
2a83e4d5
MK		 346 break;
347 case MxL_XTAL_49_3811_MHZ:
7434ca43
MK		 348 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
349 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
2a83e4d5
MK		 350 break;
351 default:
352 mxl_fail(-EINVAL);
353 return;
354 }
2a83e4d5
MK		 355
356 return;
357}
358
359static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
360 enum mxl5007t_mode mode)
361{
362 struct mxl5007t_config *cfg = state->config;
363
364 memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
365 memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
366
367 mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
368 mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
369 mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
370
7434ca43
MK		 371 set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
372 set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
2a83e4d5 373
7434ca43 374 if (mode >= MxL_MODE_CABLE) {
2a83e4d5
MK		 375 copy_reg_bits(state->tab_init, state->tab_init_cable);
376 return state->tab_init_cable;
377 } else
378 return state->tab_init;
379}
380
381/* ------------------------------------------------------------------------- */
382
383enum mxl5007t_bw_mhz {
384 MxL_BW_6MHz = 6,
385 MxL_BW_7MHz = 7,
386 MxL_BW_8MHz = 8,
387};
388
389static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
390 enum mxl5007t_bw_mhz bw)
391{
392 u8 val;
393
394 switch (bw) {
395 case MxL_BW_6MHz:
396 val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
397 * and DIG_MODEINDEX_CSF */
398 break;
399 case MxL_BW_7MHz:
7434ca43 400 val = 0x2a;
2a83e4d5
MK		 401 break;
402 case MxL_BW_8MHz:
403 val = 0x3f;
404 break;
405 default:
406 mxl_fail(-EINVAL);
407 return;
408 }
7434ca43 409 set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
2a83e4d5
MK		 410
411 return;
412}
413
414static struct
415reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
416 u32 rf_freq, enum mxl5007t_bw_mhz bw)
417{
418 u32 dig_rf_freq = 0;
419 u32 temp;
420 u32 frac_divider = 1000000;
421 unsigned int i;
422
423 memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune));
424
425 mxl5007t_set_bw_bits(state, bw);
426
427 /* Convert RF frequency into 16 bits =>
428 * 10 bit integer (MHz) + 6 bit fraction */
429 dig_rf_freq = rf_freq / MHz;
430
431 temp = rf_freq % MHz;
432
433 for (i = 0; i < 6; i++) {
434 dig_rf_freq <<= 1;
435 frac_divider /= 2;
436 if (temp > frac_divider) {
437 temp -= frac_divider;
438 dig_rf_freq++;
439 }
440 }
441
442 /* add to have shift center point by 7.8124 kHz */
443 if (temp > 7812)
444 dig_rf_freq++;
445
7434ca43
MK		 446 set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
447 set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
448
449 if (rf_freq >= 333000000)
450 set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
2a83e4d5
MK		 451
452 return state->tab_rftune;
453}
454
455/* ------------------------------------------------------------------------- */
456
457static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
458{
459 u8 buf[] = { reg, val };
460 struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
461 .buf = buf, .len = 2 };
462 int ret;
463
464 ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
465 if (ret != 1) {
466 mxl_err("failed!");
467 return -EREMOTEIO;
468 }
469 return 0;
470}
471
472static int mxl5007t_write_regs(struct mxl5007t_state *state,
473 struct reg_pair_t *reg_pair)
474{
475 unsigned int i = 0;
476 int ret = 0;
477
478 while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
479 ret = mxl5007t_write_reg(state,
480 reg_pair[i].reg, reg_pair[i].val);
481 i++;
482 }
483 return ret;
484}
485
486static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
487{
576b849e 488 u8 buf[2] = { 0xfb, reg };
2a83e4d5
MK		 489 struct i2c_msg msg[] = {
490 { .addr = state->i2c_props.addr, .flags = 0,
576b849e 491 .buf = buf, .len = 2 },
2a83e4d5
MK		 492 { .addr = state->i2c_props.addr, .flags = I2C_M_RD,
493 .buf = val, .len = 1 },
494 };
495 int ret;
496
497 ret = i2c_transfer(state->i2c_props.adap, msg, 2);
498 if (ret != 2) {
499 mxl_err("failed!");
500 return -EREMOTEIO;
501 }
502 return 0;
503}
504
505static int mxl5007t_soft_reset(struct mxl5007t_state *state)
506{
507 u8 d = 0xff;
7434ca43
MK		 508 struct i2c_msg msg = {
509 .addr = state->i2c_props.addr, .flags = 0,
510 .buf = &d, .len = 1
511 };
2a83e4d5
MK		 512 int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
513
514 if (ret != 1) {
515 mxl_err("failed!");
516 return -EREMOTEIO;
517 }
518 return 0;
519}
520
521static int mxl5007t_tuner_init(struct mxl5007t_state *state,
522 enum mxl5007t_mode mode)
523{
524 struct reg_pair_t *init_regs;
525 int ret;
526
2a83e4d5
MK		 527 /* calculate initialization reg array */
528 init_regs = mxl5007t_calc_init_regs(state, mode);
529
530 ret = mxl5007t_write_regs(state, init_regs);
531 if (mxl_fail(ret))
532 goto fail;
533 mdelay(1);
2a83e4d5
MK		 534fail:
535 return ret;
536}
537
538static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
539 enum mxl5007t_bw_mhz bw)
540{
541 struct reg_pair_t *rf_tune_regs;
542 int ret;
543
544 /* calculate channel change reg array */
545 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
546
547 ret = mxl5007t_write_regs(state, rf_tune_regs);
548 if (mxl_fail(ret))
549 goto fail;
550 msleep(3);
551fail:
552 return ret;
553}
554
555/* ------------------------------------------------------------------------- */
556
557static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
558 int *rf_locked, int *ref_locked)
559{
560 u8 d;
561 int ret;
562
563 *rf_locked = 0;
564 *ref_locked = 0;
565
7434ca43 566 ret = mxl5007t_read_reg(state, 0xd8, &d);
2a83e4d5
MK		 567 if (mxl_fail(ret))
568 goto fail;
569
570 if ((d & 0x0c) == 0x0c)
571 *rf_locked = 1;
572
573 if ((d & 0x03) == 0x03)
574 *ref_locked = 1;
575fail:
576 return ret;
577}
578
2a83e4d5
MK		 579/* ------------------------------------------------------------------------- */
580
581static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
582{
583 struct mxl5007t_state *state = fe->tuner_priv;
d90958e6
MK		 584 int rf_locked, ref_locked, ret;
585
586 *status = 0;
2a83e4d5 587
2a83e4d5
MK		 588 if (fe->ops.i2c_gate_ctrl)
589 fe->ops.i2c_gate_ctrl(fe, 1);
590
591 ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
592 if (mxl_fail(ret))
593 goto fail;
594 mxl_debug("%s%s", rf_locked ? "rf locked " : "",
595 ref_locked ? "ref locked" : "");
d90958e6
MK		 596
597 if ((rf_locked) || (ref_locked))
598 *status |= TUNER_STATUS_LOCKED;
2a83e4d5
MK		 599fail:
600 if (fe->ops.i2c_gate_ctrl)
601 fe->ops.i2c_gate_ctrl(fe, 0);
602
2a83e4d5
MK		 603 return ret;
604}
605
606/* ------------------------------------------------------------------------- */
607
14d24d14 608static int mxl5007t_set_params(struct dvb_frontend *fe)
2a83e4d5 609{
e12617e6
MCC		 610 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
611 u32 delsys = c->delivery_system;
2a83e4d5
MK		 612 struct mxl5007t_state *state = fe->tuner_priv;
613 enum mxl5007t_bw_mhz bw;
614 enum mxl5007t_mode mode;
615 int ret;
e12617e6 616 u32 freq = c->frequency;
2a83e4d5 617
e12617e6
MCC		 618 switch (delsys) {
619 case SYS_ATSC:
620 mode = MxL_MODE_ATSC;
621 bw = MxL_BW_6MHz;
622 break;
623 case SYS_DVBC_ANNEX_B:
624 mode = MxL_MODE_CABLE;
2a83e4d5 625 bw = MxL_BW_6MHz;
e12617e6
MCC		 626 break;
627 case SYS_DVBT:
628 case SYS_DVBT2:
629 mode = MxL_MODE_DVBT;
630 switch (c->bandwidth_hz) {
631 case 6000000:
2a83e4d5
MK		 632 bw = MxL_BW_6MHz;
633 break;
e12617e6 634 case 7000000:
2a83e4d5 635 bw = MxL_BW_7MHz;
9e94136d 636 break;
e12617e6 637 case 8000000:
2a83e4d5 638 bw = MxL_BW_8MHz;
9e94136d 639 break;
2a83e4d5 640 default:
2a83e4d5
MK		 641 return -EINVAL;
642 }
e12617e6
MCC		 643 break;
644 default:
2a83e4d5
MK		 645 mxl_err("modulation type not supported!");
646 return -EINVAL;
647 }
648
2a83e4d5
MK		 649 if (fe->ops.i2c_gate_ctrl)
650 fe->ops.i2c_gate_ctrl(fe, 1);
651
c39c1fd2
MK		 652 mutex_lock(&state->lock);
653
2a83e4d5
MK		 654 ret = mxl5007t_tuner_init(state, mode);
655 if (mxl_fail(ret))
656 goto fail;
657
658 ret = mxl5007t_tuner_rf_tune(state, freq, bw);
659 if (mxl_fail(ret))
660 goto fail;
661
662 state->frequency = freq;
c6f56e7d 663 state->bandwidth = c->bandwidth_hz;
2a83e4d5 664fail:
c39c1fd2
MK		 665 mutex_unlock(&state->lock);
666
2a83e4d5
MK		 667 if (fe->ops.i2c_gate_ctrl)
668 fe->ops.i2c_gate_ctrl(fe, 0);
669
2a83e4d5
MK		 670 return ret;
671}
672
2a83e4d5
MK		 673/* ------------------------------------------------------------------------- */
674
675static int mxl5007t_init(struct dvb_frontend *fe)
676{
677 struct mxl5007t_state *state = fe->tuner_priv;
452a53a2 678 int ret;
2a83e4d5 679
452a53a2
MK		 680 if (fe->ops.i2c_gate_ctrl)
681 fe->ops.i2c_gate_ctrl(fe, 1);
682
7434ca43
MK		 683 /* wake from standby */
684 ret = mxl5007t_write_reg(state, 0x01, 0x01);
452a53a2 685 mxl_fail(ret);
7434ca43 686
452a53a2
MK		 687 if (fe->ops.i2c_gate_ctrl)
688 fe->ops.i2c_gate_ctrl(fe, 0);
689
452a53a2 690 return ret;
2a83e4d5
MK		 691}
692
693static int mxl5007t_sleep(struct dvb_frontend *fe)
694{
695 struct mxl5007t_state *state = fe->tuner_priv;
452a53a2 696 int ret;
2a83e4d5 697
452a53a2
MK		 698 if (fe->ops.i2c_gate_ctrl)
699 fe->ops.i2c_gate_ctrl(fe, 1);
700
7434ca43
MK		 701 /* enter standby mode */
702 ret = mxl5007t_write_reg(state, 0x01, 0x00);
452a53a2 703 mxl_fail(ret);
7434ca43
MK		 704 ret = mxl5007t_write_reg(state, 0x0f, 0x00);
705 mxl_fail(ret);
706
452a53a2
MK		 707 if (fe->ops.i2c_gate_ctrl)
708 fe->ops.i2c_gate_ctrl(fe, 0);
709
452a53a2 710 return ret;
2a83e4d5
MK		 711}
712
713/* ------------------------------------------------------------------------- */
714
715static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
716{
717 struct mxl5007t_state *state = fe->tuner_priv;
718 *frequency = state->frequency;
719 return 0;
720}
721
722static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
723{
724 struct mxl5007t_state *state = fe->tuner_priv;
725 *bandwidth = state->bandwidth;
726 return 0;
727}
728
d697b4ce
MK		 729static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
730{
731 struct mxl5007t_state *state = fe->tuner_priv;
732
733 *frequency = 0;
734
735 switch (state->if_freq) {
736 case MxL_IF_4_MHZ:
737 *frequency = 4000000;
738 break;
739 case MxL_IF_4_5_MHZ:
740 *frequency = 4500000;
741 break;
742 case MxL_IF_4_57_MHZ:
743 *frequency = 4570000;
744 break;
745 case MxL_IF_5_MHZ:
746 *frequency = 5000000;
747 break;
748 case MxL_IF_5_38_MHZ:
749 *frequency = 5380000;
750 break;
751 case MxL_IF_6_MHZ:
752 *frequency = 6000000;
753 break;
754 case MxL_IF_6_28_MHZ:
755 *frequency = 6280000;
756 break;
757 case MxL_IF_9_1915_MHZ:
758 *frequency = 9191500;
759 break;
760 case MxL_IF_35_25_MHZ:
761 *frequency = 35250000;
762 break;
763 case MxL_IF_36_15_MHZ:
764 *frequency = 36150000;
765 break;
766 case MxL_IF_44_MHZ:
767 *frequency = 44000000;
768 break;
769 }
770 return 0;
771}
772
194ced7a 773static void mxl5007t_release(struct dvb_frontend *fe)
2a83e4d5
MK		 774{
775 struct mxl5007t_state *state = fe->tuner_priv;
776
777 mutex_lock(&mxl5007t_list_mutex);
778
779 if (state)
780 hybrid_tuner_release_state(state);
781
782 mutex_unlock(&mxl5007t_list_mutex);
783
784 fe->tuner_priv = NULL;
2a83e4d5
MK		 785}
786
787/* ------------------------------------------------------------------------- */
788
96105144 789static const struct dvb_tuner_ops mxl5007t_tuner_ops = {
2a83e4d5
MK		 790 .info = {
791 .name = "MaxLinear MxL5007T",
792 },
793 .init = mxl5007t_init,
794 .sleep = mxl5007t_sleep,
795 .set_params = mxl5007t_set_params,
2a83e4d5
MK		 796 .get_status = mxl5007t_get_status,
797 .get_frequency = mxl5007t_get_frequency,
798 .get_bandwidth = mxl5007t_get_bandwidth,
799 .release = mxl5007t_release,
d697b4ce 800 .get_if_frequency = mxl5007t_get_if_frequency,
2a83e4d5
MK		 801};
802
803static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
804{
805 char *name;
806 int ret;
807 u8 id;
808
7434ca43 809 ret = mxl5007t_read_reg(state, 0xd9, &id);
2a83e4d5
MK		 810 if (mxl_fail(ret))
811 goto fail;
812
813 switch (id) {
814 case MxL_5007_V1_F1:
815 name = "MxL5007.v1.f1";
816 break;
817 case MxL_5007_V1_F2:
818 name = "MxL5007.v1.f2";
819 break;
820 case MxL_5007_V2_100_F1:
821 name = "MxL5007.v2.100.f1";
822 break;
823 case MxL_5007_V2_100_F2:
824 name = "MxL5007.v2.100.f2";
825 break;
826 case MxL_5007_V2_200_F1:
827 name = "MxL5007.v2.200.f1";
828 break;
829 case MxL_5007_V2_200_F2:
830 name = "MxL5007.v2.200.f2";
831 break;
7434ca43
MK		 832 case MxL_5007_V4:
833 name = "MxL5007T.v4";
834 break;
2a83e4d5
MK		 835 default:
836 name = "MxL5007T";
d202515b 837 printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
2a83e4d5
MK		 838 id = MxL_UNKNOWN_ID;
839 }
840 state->chip_id = id;
841 mxl_info("%s detected @ %d-%04x", name,
842 i2c_adapter_id(state->i2c_props.adap),
843 state->i2c_props.addr);
844 return 0;
845fail:
846 mxl_warn("unable to identify device @ %d-%04x",
847 i2c_adapter_id(state->i2c_props.adap),
848 state->i2c_props.addr);
849
850 state->chip_id = MxL_UNKNOWN_ID;
851 return ret;
852}
853
854struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
855 struct i2c_adapter *i2c, u8 addr,
856 struct mxl5007t_config *cfg)
857{
858 struct mxl5007t_state *state = NULL;
859 int instance, ret;
860
861 mutex_lock(&mxl5007t_list_mutex);
862 instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
863 hybrid_tuner_instance_list,
3d0081dd 864 i2c, addr, "mxl5007t");
2a83e4d5
MK		 865 switch (instance) {
866 case 0:
867 goto fail;
2a83e4d5
MK		 868 case 1:
869 /* new tuner instance */
870 state->config = cfg;
871
872 mutex_init(&state->lock);
873
2a83e4d5
MK		 874 if (fe->ops.i2c_gate_ctrl)
875 fe->ops.i2c_gate_ctrl(fe, 1);
876
877 ret = mxl5007t_get_chip_id(state);
878
879 if (fe->ops.i2c_gate_ctrl)
880 fe->ops.i2c_gate_ctrl(fe, 0);
881
2a83e4d5
MK		 882 /* check return value of mxl5007t_get_chip_id */
883 if (mxl_fail(ret))
884 goto fail;
885 break;
886 default:
887 /* existing tuner instance */
888 break;
889 }
fe4860af
JAR		 890
891 if (fe->ops.i2c_gate_ctrl)
892 fe->ops.i2c_gate_ctrl(fe, 1);
893
894 ret = mxl5007t_soft_reset(state);
895
02f9cf96
JAR		 896 if (fe->ops.i2c_gate_ctrl)
897 fe->ops.i2c_gate_ctrl(fe, 0);
898
899 if (mxl_fail(ret))
900 goto fail;
901
902 if (fe->ops.i2c_gate_ctrl)
903 fe->ops.i2c_gate_ctrl(fe, 1);
904
905 ret = mxl5007t_write_reg(state, 0x04,
906 state->config->loop_thru_enable);
907
fe4860af
JAR		 908 if (fe->ops.i2c_gate_ctrl)
909 fe->ops.i2c_gate_ctrl(fe, 0);
910
911 if (mxl_fail(ret))
912 goto fail;
913
2a83e4d5 914 fe->tuner_priv = state;
fe4860af 915
2a83e4d5
MK		 916 mutex_unlock(&mxl5007t_list_mutex);
917
918 memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
919 sizeof(struct dvb_tuner_ops));
920
921 return fe;
922fail:
923 mutex_unlock(&mxl5007t_list_mutex);
924
925 mxl5007t_release(fe);
926 return NULL;
927}
928EXPORT_SYMBOL_GPL(mxl5007t_attach);
929MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
930MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
931MODULE_LICENSE("GPL");
7434ca43 932MODULE_VERSION("0.2");
Linux 6.x block layer and io_uring tree(s)