Commit | Line | Data |
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e258b80e DH |
1 | /* |
2 | * winbond-cir.c - Driver for the Consumer IR functionality of Winbond | |
3 | * SuperI/O chips. | |
4 | * | |
5 | * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but | |
6 | * could probably support others (Winbond WEC102X, NatSemi, etc) | |
7 | * with minor modifications. | |
8 | * | |
b87f2edd | 9 | * Original Author: David Härdeman <david@hardeman.nu> |
37b0b4e9 | 10 | * Copyright (C) 2012 Sean Young <sean@mess.org> |
b87f2edd | 11 | * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu> |
e258b80e | 12 | * |
5b2e303f DH |
13 | * Dedicated to my daughter Matilda, without whose loving attention this |
14 | * driver would have been finished in half the time and with a fraction | |
e258b80e DH |
15 | * of the bugs. |
16 | * | |
17 | * Written using: | |
18 | * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel | |
19 | * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) | |
20 | * o DSDT dumps | |
21 | * | |
22 | * Supported features: | |
c829f267 DH |
23 | * o IR Receive |
24 | * o IR Transmit | |
e258b80e | 25 | * o Wake-On-CIR functionality |
37b0b4e9 | 26 | * o Carrier detection |
e258b80e DH |
27 | * |
28 | * This program is free software; you can redistribute it and/or modify | |
29 | * it under the terms of the GNU General Public License as published by | |
30 | * the Free Software Foundation; either version 2 of the License, or | |
31 | * (at your option) any later version. | |
32 | * | |
33 | * This program is distributed in the hope that it will be useful, | |
34 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
35 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
36 | * GNU General Public License for more details. | |
37 | * | |
38 | * You should have received a copy of the GNU General Public License | |
39 | * along with this program; if not, write to the Free Software | |
40 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
41 | */ | |
42 | ||
d8a10ac9 JP |
43 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
44 | ||
e258b80e DH |
45 | #include <linux/module.h> |
46 | #include <linux/pnp.h> | |
47 | #include <linux/interrupt.h> | |
48 | #include <linux/timer.h> | |
e258b80e | 49 | #include <linux/leds.h> |
e258b80e DH |
50 | #include <linux/spinlock.h> |
51 | #include <linux/pci_ids.h> | |
52 | #include <linux/io.h> | |
53 | #include <linux/bitrev.h> | |
5a0e3ad6 | 54 | #include <linux/slab.h> |
c829f267 DH |
55 | #include <linux/wait.h> |
56 | #include <linux/sched.h> | |
6bda9644 | 57 | #include <media/rc-core.h> |
e258b80e DH |
58 | |
59 | #define DRVNAME "winbond-cir" | |
60 | ||
61 | /* CEIR Wake-Up Registers, relative to data->wbase */ | |
62 | #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ | |
63 | #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ | |
64 | #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ | |
65 | #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ | |
66 | #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ | |
67 | #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ | |
68 | #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ | |
69 | #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ | |
70 | #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ | |
71 | #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ | |
72 | ||
73 | /* CEIR Enhanced Functionality Registers, relative to data->ebase */ | |
74 | #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ | |
75 | #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ | |
76 | #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ | |
77 | #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ | |
78 | #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ | |
79 | ||
80 | /* SP3 Banked Registers, relative to data->sbase */ | |
81 | #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ | |
82 | /* Bank 0 */ | |
83 | #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ | |
84 | #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ | |
85 | #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ | |
86 | #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ | |
87 | #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ | |
88 | #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ | |
89 | #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ | |
90 | #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ | |
91 | #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ | |
92 | /* Bank 2 */ | |
93 | #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ | |
94 | #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ | |
95 | #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ | |
96 | #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ | |
97 | #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ | |
98 | #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ | |
99 | /* Bank 3 */ | |
100 | #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ | |
101 | #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ | |
102 | #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ | |
103 | /* Bank 4 */ | |
104 | #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ | |
105 | /* Bank 5 */ | |
106 | #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ | |
107 | /* Bank 6 */ | |
108 | #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ | |
5b2e303f | 109 | #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ |
e258b80e DH |
110 | /* Bank 7 */ |
111 | #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ | |
112 | #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ | |
113 | #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ | |
114 | #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ | |
115 | #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ | |
116 | ||
117 | /* | |
118 | * Magic values follow | |
119 | */ | |
120 | ||
121 | /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ | |
122 | #define WBCIR_IRQ_NONE 0x00 | |
123 | /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ | |
124 | #define WBCIR_IRQ_RX 0x01 | |
c829f267 DH |
125 | /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
126 | #define WBCIR_IRQ_TX_LOW 0x02 | |
e258b80e DH |
127 | /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
128 | #define WBCIR_IRQ_ERR 0x04 | |
c829f267 DH |
129 | /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
130 | #define WBCIR_IRQ_TX_EMPTY 0x20 | |
e258b80e DH |
131 | /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ |
132 | #define WBCIR_LED_ENABLE 0x80 | |
133 | /* RX data available bit for WBCIR_REG_SP3_LSR */ | |
134 | #define WBCIR_RX_AVAIL 0x01 | |
c829f267 DH |
135 | /* RX data overrun error bit for WBCIR_REG_SP3_LSR */ |
136 | #define WBCIR_RX_OVERRUN 0x02 | |
137 | /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ | |
138 | #define WBCIR_TX_EOT 0x04 | |
e258b80e DH |
139 | /* RX disable bit for WBCIR_REG_SP3_ASCR */ |
140 | #define WBCIR_RX_DISABLE 0x20 | |
c829f267 DH |
141 | /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ |
142 | #define WBCIR_TX_UNDERRUN 0x40 | |
e258b80e DH |
143 | /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ |
144 | #define WBCIR_EXT_ENABLE 0x01 | |
145 | /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ | |
146 | #define WBCIR_REGSEL_COMPARE 0x10 | |
147 | /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ | |
148 | #define WBCIR_REGSEL_MASK 0x20 | |
149 | /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ | |
150 | #define WBCIR_REG_ADDR0 0x00 | |
37b0b4e9 SY |
151 | /* Enable carrier counter */ |
152 | #define WBCIR_CNTR_EN 0x01 | |
153 | /* Reset carrier counter */ | |
154 | #define WBCIR_CNTR_R 0x02 | |
155 | /* Invert TX */ | |
156 | #define WBCIR_IRTX_INV 0x04 | |
6f2627c2 SY |
157 | /* Receiver oversampling */ |
158 | #define WBCIR_RX_T_OV 0x40 | |
e258b80e DH |
159 | |
160 | /* Valid banks for the SP3 UART */ | |
161 | enum wbcir_bank { | |
162 | WBCIR_BANK_0 = 0x00, | |
163 | WBCIR_BANK_1 = 0x80, | |
164 | WBCIR_BANK_2 = 0xE0, | |
165 | WBCIR_BANK_3 = 0xE4, | |
166 | WBCIR_BANK_4 = 0xE8, | |
167 | WBCIR_BANK_5 = 0xEC, | |
168 | WBCIR_BANK_6 = 0xF0, | |
169 | WBCIR_BANK_7 = 0xF4, | |
170 | }; | |
171 | ||
5b2e303f | 172 | /* Supported power-on IR Protocols */ |
e258b80e DH |
173 | enum wbcir_protocol { |
174 | IR_PROTOCOL_RC5 = 0x0, | |
175 | IR_PROTOCOL_NEC = 0x1, | |
176 | IR_PROTOCOL_RC6 = 0x2, | |
177 | }; | |
178 | ||
c829f267 DH |
179 | /* Possible states for IR reception */ |
180 | enum wbcir_rxstate { | |
181 | WBCIR_RXSTATE_INACTIVE = 0, | |
182 | WBCIR_RXSTATE_ACTIVE, | |
183 | WBCIR_RXSTATE_ERROR | |
184 | }; | |
185 | ||
186 | /* Possible states for IR transmission */ | |
187 | enum wbcir_txstate { | |
188 | WBCIR_TXSTATE_INACTIVE = 0, | |
189 | WBCIR_TXSTATE_ACTIVE, | |
c829f267 DH |
190 | WBCIR_TXSTATE_ERROR |
191 | }; | |
192 | ||
e258b80e | 193 | /* Misc */ |
a66cd0b6 | 194 | #define WBCIR_NAME "Winbond CIR" |
e258b80e DH |
195 | #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ |
196 | #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ | |
e258b80e DH |
197 | #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */ |
198 | #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ | |
199 | #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ | |
200 | #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ | |
e258b80e | 201 | |
5b2e303f | 202 | /* Per-device data */ |
e258b80e | 203 | struct wbcir_data { |
5b2e303f | 204 | spinlock_t spinlock; |
c829f267 DH |
205 | struct rc_dev *dev; |
206 | struct led_classdev led; | |
5b2e303f | 207 | |
e258b80e DH |
208 | unsigned long wbase; /* Wake-Up Baseaddr */ |
209 | unsigned long ebase; /* Enhanced Func. Baseaddr */ | |
210 | unsigned long sbase; /* Serial Port Baseaddr */ | |
211 | unsigned int irq; /* Serial Port IRQ */ | |
c829f267 | 212 | u8 irqmask; |
e258b80e | 213 | |
c829f267 DH |
214 | /* RX state */ |
215 | enum wbcir_rxstate rxstate; | |
37b0b4e9 SY |
216 | int carrier_report_enabled; |
217 | u32 pulse_duration; | |
e258b80e | 218 | |
c829f267 DH |
219 | /* TX state */ |
220 | enum wbcir_txstate txstate; | |
c829f267 DH |
221 | u32 txlen; |
222 | u32 txoff; | |
223 | u32 *txbuf; | |
c829f267 DH |
224 | u8 txmask; |
225 | u32 txcarrier; | |
e258b80e DH |
226 | }; |
227 | ||
228 | static enum wbcir_protocol protocol = IR_PROTOCOL_RC6; | |
229 | module_param(protocol, uint, 0444); | |
5b2e303f | 230 | MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command " |
e258b80e DH |
231 | "(0 = RC5, 1 = NEC, 2 = RC6A, default)"); |
232 | ||
90ab5ee9 | 233 | static bool invert; /* default = 0 */ |
e258b80e DH |
234 | module_param(invert, bool, 0444); |
235 | MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); | |
236 | ||
90ab5ee9 | 237 | static bool txandrx; /* default = 0 */ |
c829f267 | 238 | module_param(txandrx, bool, 0444); |
57f4422f | 239 | MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX"); |
c829f267 | 240 | |
e258b80e DH |
241 | static unsigned int wake_sc = 0x800F040C; |
242 | module_param(wake_sc, uint, 0644); | |
243 | MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command"); | |
244 | ||
245 | static unsigned int wake_rc6mode = 6; | |
246 | module_param(wake_rc6mode, uint, 0644); | |
247 | MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command " | |
248 | "(0 = 0, 6 = 6A, default)"); | |
249 | ||
250 | ||
251 | ||
252 | /***************************************************************************** | |
253 | * | |
254 | * UTILITY FUNCTIONS | |
255 | * | |
256 | *****************************************************************************/ | |
257 | ||
258 | /* Caller needs to hold wbcir_lock */ | |
259 | static void | |
260 | wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) | |
261 | { | |
262 | u8 val; | |
263 | ||
264 | val = inb(addr); | |
265 | val = ((val & ~mask) | (bits & mask)); | |
266 | outb(val, addr); | |
267 | } | |
268 | ||
269 | /* Selects the register bank for the serial port */ | |
270 | static inline void | |
271 | wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) | |
272 | { | |
273 | outb(bank, data->sbase + WBCIR_REG_SP3_BSR); | |
274 | } | |
275 | ||
c829f267 DH |
276 | static inline void |
277 | wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) | |
278 | { | |
279 | if (data->irqmask == irqmask) | |
280 | return; | |
281 | ||
282 | wbcir_select_bank(data, WBCIR_BANK_0); | |
283 | outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); | |
284 | data->irqmask = irqmask; | |
285 | } | |
286 | ||
e258b80e DH |
287 | static enum led_brightness |
288 | wbcir_led_brightness_get(struct led_classdev *led_cdev) | |
289 | { | |
290 | struct wbcir_data *data = container_of(led_cdev, | |
291 | struct wbcir_data, | |
292 | led); | |
293 | ||
294 | if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) | |
295 | return LED_FULL; | |
296 | else | |
297 | return LED_OFF; | |
298 | } | |
299 | ||
300 | static void | |
301 | wbcir_led_brightness_set(struct led_classdev *led_cdev, | |
5b2e303f | 302 | enum led_brightness brightness) |
e258b80e DH |
303 | { |
304 | struct wbcir_data *data = container_of(led_cdev, | |
305 | struct wbcir_data, | |
306 | led); | |
307 | ||
308 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, | |
309 | brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, | |
310 | WBCIR_LED_ENABLE); | |
311 | } | |
312 | ||
5b2e303f | 313 | /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ |
e258b80e DH |
314 | static u8 |
315 | wbcir_to_rc6cells(u8 val) | |
316 | { | |
317 | u8 coded = 0x00; | |
318 | int i; | |
319 | ||
320 | val &= 0x0F; | |
321 | for (i = 0; i < 4; i++) { | |
322 | if (val & 0x01) | |
323 | coded |= 0x02 << (i * 2); | |
324 | else | |
325 | coded |= 0x01 << (i * 2); | |
326 | val >>= 1; | |
327 | } | |
328 | ||
329 | return coded; | |
330 | } | |
331 | ||
e258b80e DH |
332 | /***************************************************************************** |
333 | * | |
334 | * INTERRUPT FUNCTIONS | |
335 | * | |
336 | *****************************************************************************/ | |
337 | ||
37b0b4e9 SY |
338 | static void |
339 | wbcir_carrier_report(struct wbcir_data *data) | |
340 | { | |
341 | unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) | | |
342 | inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8; | |
343 | ||
344 | if (counter > 0 && counter < 0xffff) { | |
345 | DEFINE_IR_RAW_EVENT(ev); | |
346 | ||
347 | ev.carrier_report = 1; | |
348 | ev.carrier = DIV_ROUND_CLOSEST(counter * 1000000u, | |
349 | data->pulse_duration); | |
350 | ||
351 | ir_raw_event_store(data->dev, &ev); | |
352 | } | |
353 | ||
354 | /* reset and restart the counter */ | |
355 | data->pulse_duration = 0; | |
356 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, | |
357 | WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
358 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN, | |
359 | WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
360 | } | |
361 | ||
c829f267 | 362 | static void |
488ebc48 | 363 | wbcir_idle_rx(struct rc_dev *dev, bool idle) |
e258b80e | 364 | { |
488ebc48 | 365 | struct wbcir_data *data = dev->priv; |
e258b80e | 366 | |
1ac7fdee | 367 | if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) |
c829f267 | 368 | data->rxstate = WBCIR_RXSTATE_ACTIVE; |
5b2e303f | 369 | |
e5eda7fa SY |
370 | if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) { |
371 | data->rxstate = WBCIR_RXSTATE_INACTIVE; | |
37b0b4e9 SY |
372 | |
373 | if (data->carrier_report_enabled) | |
374 | wbcir_carrier_report(data); | |
375 | ||
488ebc48 DH |
376 | /* Tell hardware to go idle by setting RXINACTIVE */ |
377 | outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); | |
e5eda7fa | 378 | } |
488ebc48 | 379 | } |
e258b80e | 380 | |
488ebc48 DH |
381 | static void |
382 | wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) | |
383 | { | |
384 | u8 irdata; | |
385 | DEFINE_IR_RAW_EVENT(rawir); | |
37b0b4e9 | 386 | unsigned duration; |
5b2e303f | 387 | |
488ebc48 DH |
388 | /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ |
389 | while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { | |
390 | irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); | |
c829f267 | 391 | if (data->rxstate == WBCIR_RXSTATE_ERROR) |
5b2e303f | 392 | continue; |
37b0b4e9 | 393 | |
6f2627c2 SY |
394 | duration = ((irdata & 0x7F) + 1) * |
395 | (data->carrier_report_enabled ? 2 : 10); | |
488ebc48 | 396 | rawir.pulse = irdata & 0x80 ? false : true; |
37b0b4e9 SY |
397 | rawir.duration = US_TO_NS(duration); |
398 | ||
399 | if (rawir.pulse) | |
400 | data->pulse_duration += duration; | |
401 | ||
488ebc48 | 402 | ir_raw_event_store_with_filter(data->dev, &rawir); |
e258b80e DH |
403 | } |
404 | ||
5b2e303f | 405 | ir_raw_event_handle(data->dev); |
c829f267 DH |
406 | } |
407 | ||
408 | static void | |
409 | wbcir_irq_tx(struct wbcir_data *data) | |
410 | { | |
411 | unsigned int space; | |
412 | unsigned int used; | |
413 | u8 bytes[16]; | |
414 | u8 byte; | |
415 | ||
416 | if (!data->txbuf) | |
417 | return; | |
418 | ||
419 | switch (data->txstate) { | |
420 | case WBCIR_TXSTATE_INACTIVE: | |
421 | /* TX FIFO empty */ | |
422 | space = 16; | |
c829f267 DH |
423 | break; |
424 | case WBCIR_TXSTATE_ACTIVE: | |
425 | /* TX FIFO low (3 bytes or less) */ | |
426 | space = 13; | |
427 | break; | |
428 | case WBCIR_TXSTATE_ERROR: | |
429 | space = 0; | |
430 | break; | |
431 | default: | |
432 | return; | |
433 | } | |
434 | ||
435 | /* | |
436 | * TX data is run-length coded in bytes: YXXXXXXX | |
437 | * Y = space (1) or pulse (0) | |
438 | * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) | |
439 | */ | |
440 | for (used = 0; used < space && data->txoff != data->txlen; used++) { | |
441 | if (data->txbuf[data->txoff] == 0) { | |
442 | data->txoff++; | |
443 | continue; | |
444 | } | |
445 | byte = min((u32)0x80, data->txbuf[data->txoff]); | |
446 | data->txbuf[data->txoff] -= byte; | |
447 | byte--; | |
448 | byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ | |
449 | bytes[used] = byte; | |
450 | } | |
451 | ||
452 | while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen) | |
453 | data->txoff++; | |
454 | ||
455 | if (used == 0) { | |
456 | /* Finished */ | |
457 | if (data->txstate == WBCIR_TXSTATE_ERROR) | |
458 | /* Clear TX underrun bit */ | |
459 | outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); | |
c829f267 | 460 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
7bfb5dc1 DH |
461 | kfree(data->txbuf); |
462 | data->txbuf = NULL; | |
463 | data->txstate = WBCIR_TXSTATE_INACTIVE; | |
c829f267 DH |
464 | } else if (data->txoff == data->txlen) { |
465 | /* At the end of transmission, tell the hw before last byte */ | |
466 | outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); | |
467 | outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); | |
468 | outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); | |
469 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | | |
470 | WBCIR_IRQ_TX_EMPTY); | |
471 | } else { | |
472 | /* More data to follow... */ | |
473 | outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); | |
474 | if (data->txstate == WBCIR_TXSTATE_INACTIVE) { | |
475 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | | |
476 | WBCIR_IRQ_TX_LOW); | |
477 | data->txstate = WBCIR_TXSTATE_ACTIVE; | |
478 | } | |
479 | } | |
480 | } | |
481 | ||
482 | static irqreturn_t | |
483 | wbcir_irq_handler(int irqno, void *cookie) | |
484 | { | |
485 | struct pnp_dev *device = cookie; | |
486 | struct wbcir_data *data = pnp_get_drvdata(device); | |
487 | unsigned long flags; | |
488 | u8 status; | |
489 | ||
490 | spin_lock_irqsave(&data->spinlock, flags); | |
491 | wbcir_select_bank(data, WBCIR_BANK_0); | |
492 | status = inb(data->sbase + WBCIR_REG_SP3_EIR); | |
493 | status &= data->irqmask; | |
494 | ||
495 | if (!status) { | |
496 | spin_unlock_irqrestore(&data->spinlock, flags); | |
497 | return IRQ_NONE; | |
498 | } | |
499 | ||
500 | if (status & WBCIR_IRQ_ERR) { | |
501 | /* RX overflow? (read clears bit) */ | |
502 | if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { | |
503 | data->rxstate = WBCIR_RXSTATE_ERROR; | |
504 | ir_raw_event_reset(data->dev); | |
505 | } | |
506 | ||
507 | /* TX underflow? */ | |
508 | if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) | |
509 | data->txstate = WBCIR_TXSTATE_ERROR; | |
510 | } | |
511 | ||
512 | if (status & WBCIR_IRQ_RX) | |
513 | wbcir_irq_rx(data, device); | |
514 | ||
515 | if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) | |
516 | wbcir_irq_tx(data); | |
5b2e303f | 517 | |
5b2e303f | 518 | spin_unlock_irqrestore(&data->spinlock, flags); |
e258b80e DH |
519 | return IRQ_HANDLED; |
520 | } | |
521 | ||
c829f267 DH |
522 | /***************************************************************************** |
523 | * | |
524 | * RC-CORE INTERFACE FUNCTIONS | |
525 | * | |
526 | *****************************************************************************/ | |
527 | ||
37b0b4e9 SY |
528 | static int |
529 | wbcir_set_carrier_report(struct rc_dev *dev, int enable) | |
530 | { | |
531 | struct wbcir_data *data = dev->priv; | |
532 | unsigned long flags; | |
533 | ||
534 | spin_lock_irqsave(&data->spinlock, flags); | |
535 | ||
536 | if (data->carrier_report_enabled == enable) { | |
537 | spin_unlock_irqrestore(&data->spinlock, flags); | |
538 | return 0; | |
539 | } | |
540 | ||
541 | data->pulse_duration = 0; | |
542 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, | |
543 | WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
544 | ||
545 | if (enable && data->dev->idle) | |
546 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, | |
547 | WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
548 | ||
6f2627c2 SY |
549 | /* Set a higher sampling resolution if carrier reports are enabled */ |
550 | wbcir_select_bank(data, WBCIR_BANK_2); | |
551 | data->dev->rx_resolution = US_TO_NS(enable ? 2 : 10); | |
552 | outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL); | |
553 | outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); | |
554 | ||
555 | /* Enable oversampling if carrier reports are enabled */ | |
556 | wbcir_select_bank(data, WBCIR_BANK_7); | |
557 | wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG, | |
558 | enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV); | |
559 | ||
37b0b4e9 SY |
560 | data->carrier_report_enabled = enable; |
561 | spin_unlock_irqrestore(&data->spinlock, flags); | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
c829f267 DH |
566 | static int |
567 | wbcir_txcarrier(struct rc_dev *dev, u32 carrier) | |
568 | { | |
569 | struct wbcir_data *data = dev->priv; | |
570 | unsigned long flags; | |
571 | u8 val; | |
572 | u32 freq; | |
573 | ||
574 | freq = DIV_ROUND_CLOSEST(carrier, 1000); | |
575 | if (freq < 30 || freq > 60) | |
576 | return -EINVAL; | |
577 | ||
578 | switch (freq) { | |
579 | case 58: | |
580 | case 59: | |
581 | case 60: | |
582 | val = freq - 58; | |
583 | freq *= 1000; | |
584 | break; | |
585 | case 57: | |
586 | val = freq - 27; | |
587 | freq = 56900; | |
588 | break; | |
589 | default: | |
590 | val = freq - 27; | |
591 | freq *= 1000; | |
592 | break; | |
593 | } | |
594 | ||
595 | spin_lock_irqsave(&data->spinlock, flags); | |
596 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
597 | spin_unlock_irqrestore(&data->spinlock, flags); | |
598 | return -EBUSY; | |
599 | } | |
600 | ||
601 | if (data->txcarrier != freq) { | |
602 | wbcir_select_bank(data, WBCIR_BANK_7); | |
603 | wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); | |
604 | data->txcarrier = freq; | |
605 | } | |
606 | ||
607 | spin_unlock_irqrestore(&data->spinlock, flags); | |
608 | return 0; | |
609 | } | |
610 | ||
611 | static int | |
612 | wbcir_txmask(struct rc_dev *dev, u32 mask) | |
613 | { | |
614 | struct wbcir_data *data = dev->priv; | |
615 | unsigned long flags; | |
616 | u8 val; | |
617 | ||
618 | /* Four outputs, only one output can be enabled at a time */ | |
619 | switch (mask) { | |
620 | case 0x1: | |
621 | val = 0x0; | |
622 | break; | |
623 | case 0x2: | |
624 | val = 0x1; | |
625 | break; | |
626 | case 0x4: | |
627 | val = 0x2; | |
628 | break; | |
629 | case 0x8: | |
630 | val = 0x3; | |
631 | break; | |
632 | default: | |
633 | return -EINVAL; | |
634 | } | |
635 | ||
636 | spin_lock_irqsave(&data->spinlock, flags); | |
637 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
638 | spin_unlock_irqrestore(&data->spinlock, flags); | |
639 | return -EBUSY; | |
640 | } | |
641 | ||
642 | if (data->txmask != mask) { | |
643 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); | |
644 | data->txmask = mask; | |
645 | } | |
646 | ||
647 | spin_unlock_irqrestore(&data->spinlock, flags); | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static int | |
7bfb5dc1 | 652 | wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count) |
c829f267 DH |
653 | { |
654 | struct wbcir_data *data = dev->priv; | |
7bfb5dc1 | 655 | unsigned *buf; |
c829f267 DH |
656 | unsigned i; |
657 | unsigned long flags; | |
658 | ||
7bfb5dc1 DH |
659 | buf = kmalloc(count * sizeof(*b), GFP_KERNEL); |
660 | if (!buf) | |
661 | return -ENOMEM; | |
662 | ||
663 | /* Convert values to multiples of 10us */ | |
664 | for (i = 0; i < count; i++) | |
665 | buf[i] = DIV_ROUND_CLOSEST(b[i], 10); | |
666 | ||
c829f267 DH |
667 | /* Not sure if this is possible, but better safe than sorry */ |
668 | spin_lock_irqsave(&data->spinlock, flags); | |
669 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
670 | spin_unlock_irqrestore(&data->spinlock, flags); | |
7bfb5dc1 | 671 | kfree(buf); |
c829f267 DH |
672 | return -EBUSY; |
673 | } | |
674 | ||
c829f267 DH |
675 | /* Fill the TX fifo once, the irq handler will do the rest */ |
676 | data->txbuf = buf; | |
677 | data->txlen = count; | |
678 | data->txoff = 0; | |
679 | wbcir_irq_tx(data); | |
680 | ||
c829f267 | 681 | /* We're done */ |
c829f267 | 682 | spin_unlock_irqrestore(&data->spinlock, flags); |
c829f267 DH |
683 | return count; |
684 | } | |
e258b80e DH |
685 | |
686 | /***************************************************************************** | |
687 | * | |
197d4db7 | 688 | * SETUP/INIT/SUSPEND/RESUME FUNCTIONS |
e258b80e DH |
689 | * |
690 | *****************************************************************************/ | |
691 | ||
692 | static void | |
693 | wbcir_shutdown(struct pnp_dev *device) | |
694 | { | |
695 | struct device *dev = &device->dev; | |
696 | struct wbcir_data *data = pnp_get_drvdata(device); | |
67cdd42e | 697 | bool do_wake = true; |
e258b80e DH |
698 | u8 match[11]; |
699 | u8 mask[11]; | |
700 | u8 rc6_csl = 0; | |
701 | int i; | |
702 | ||
703 | memset(match, 0, sizeof(match)); | |
704 | memset(mask, 0, sizeof(mask)); | |
705 | ||
706 | if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) { | |
67cdd42e | 707 | do_wake = false; |
e258b80e DH |
708 | goto finish; |
709 | } | |
710 | ||
711 | switch (protocol) { | |
712 | case IR_PROTOCOL_RC5: | |
713 | if (wake_sc > 0xFFF) { | |
67cdd42e | 714 | do_wake = false; |
e258b80e DH |
715 | dev_err(dev, "RC5 - Invalid wake scancode\n"); |
716 | break; | |
717 | } | |
718 | ||
719 | /* Mask = 13 bits, ex toggle */ | |
720 | mask[0] = 0xFF; | |
721 | mask[1] = 0x17; | |
722 | ||
723 | match[0] = (wake_sc & 0x003F); /* 6 command bits */ | |
724 | match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */ | |
725 | match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */ | |
726 | if (!(wake_sc & 0x0040)) /* 2nd start bit */ | |
727 | match[1] |= 0x10; | |
728 | ||
729 | break; | |
730 | ||
731 | case IR_PROTOCOL_NEC: | |
732 | if (wake_sc > 0xFFFFFF) { | |
67cdd42e | 733 | do_wake = false; |
e258b80e DH |
734 | dev_err(dev, "NEC - Invalid wake scancode\n"); |
735 | break; | |
736 | } | |
737 | ||
738 | mask[0] = mask[1] = mask[2] = mask[3] = 0xFF; | |
739 | ||
740 | match[1] = bitrev8((wake_sc & 0xFF)); | |
741 | match[0] = ~match[1]; | |
742 | ||
743 | match[3] = bitrev8((wake_sc & 0xFF00) >> 8); | |
744 | if (wake_sc > 0xFFFF) | |
745 | match[2] = bitrev8((wake_sc & 0xFF0000) >> 16); | |
746 | else | |
747 | match[2] = ~match[3]; | |
748 | ||
749 | break; | |
750 | ||
751 | case IR_PROTOCOL_RC6: | |
752 | ||
753 | if (wake_rc6mode == 0) { | |
754 | if (wake_sc > 0xFFFF) { | |
67cdd42e | 755 | do_wake = false; |
e258b80e DH |
756 | dev_err(dev, "RC6 - Invalid wake scancode\n"); |
757 | break; | |
758 | } | |
759 | ||
760 | /* Command */ | |
761 | match[0] = wbcir_to_rc6cells(wake_sc >> 0); | |
762 | mask[0] = 0xFF; | |
763 | match[1] = wbcir_to_rc6cells(wake_sc >> 4); | |
764 | mask[1] = 0xFF; | |
765 | ||
766 | /* Address */ | |
767 | match[2] = wbcir_to_rc6cells(wake_sc >> 8); | |
768 | mask[2] = 0xFF; | |
769 | match[3] = wbcir_to_rc6cells(wake_sc >> 12); | |
770 | mask[3] = 0xFF; | |
771 | ||
772 | /* Header */ | |
773 | match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ | |
774 | mask[4] = 0xF0; | |
775 | match[5] = 0x09; /* start bit = 1, mode2 = 0 */ | |
776 | mask[5] = 0x0F; | |
777 | ||
778 | rc6_csl = 44; | |
779 | ||
780 | } else if (wake_rc6mode == 6) { | |
781 | i = 0; | |
782 | ||
783 | /* Command */ | |
784 | match[i] = wbcir_to_rc6cells(wake_sc >> 0); | |
785 | mask[i++] = 0xFF; | |
786 | match[i] = wbcir_to_rc6cells(wake_sc >> 4); | |
787 | mask[i++] = 0xFF; | |
788 | ||
789 | /* Address + Toggle */ | |
790 | match[i] = wbcir_to_rc6cells(wake_sc >> 8); | |
791 | mask[i++] = 0xFF; | |
792 | match[i] = wbcir_to_rc6cells(wake_sc >> 12); | |
793 | mask[i++] = 0x3F; | |
794 | ||
795 | /* Customer bits 7 - 0 */ | |
796 | match[i] = wbcir_to_rc6cells(wake_sc >> 16); | |
797 | mask[i++] = 0xFF; | |
798 | match[i] = wbcir_to_rc6cells(wake_sc >> 20); | |
799 | mask[i++] = 0xFF; | |
800 | ||
801 | if (wake_sc & 0x80000000) { | |
802 | /* Customer range bit and bits 15 - 8 */ | |
803 | match[i] = wbcir_to_rc6cells(wake_sc >> 24); | |
804 | mask[i++] = 0xFF; | |
805 | match[i] = wbcir_to_rc6cells(wake_sc >> 28); | |
806 | mask[i++] = 0xFF; | |
807 | rc6_csl = 76; | |
808 | } else if (wake_sc <= 0x007FFFFF) { | |
809 | rc6_csl = 60; | |
810 | } else { | |
67cdd42e | 811 | do_wake = false; |
e258b80e DH |
812 | dev_err(dev, "RC6 - Invalid wake scancode\n"); |
813 | break; | |
814 | } | |
815 | ||
816 | /* Header */ | |
817 | match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ | |
818 | mask[i++] = 0xFF; | |
819 | match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ | |
820 | mask[i++] = 0x0F; | |
821 | ||
822 | } else { | |
67cdd42e | 823 | do_wake = false; |
e258b80e DH |
824 | dev_err(dev, "RC6 - Invalid wake mode\n"); |
825 | } | |
826 | ||
827 | break; | |
828 | ||
829 | default: | |
67cdd42e | 830 | do_wake = false; |
e258b80e DH |
831 | break; |
832 | } | |
833 | ||
834 | finish: | |
835 | if (do_wake) { | |
836 | /* Set compare and compare mask */ | |
837 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, | |
838 | WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, | |
839 | 0x3F); | |
840 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); | |
841 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, | |
842 | WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, | |
843 | 0x3F); | |
844 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); | |
845 | ||
846 | /* RC6 Compare String Len */ | |
847 | outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); | |
848 | ||
849 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
850 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
851 | ||
852 | /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ | |
853 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); | |
854 | ||
855 | /* Set CEIR_EN */ | |
856 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01); | |
857 | ||
858 | } else { | |
859 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ | |
860 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
861 | ||
862 | /* Clear CEIR_EN */ | |
863 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); | |
864 | } | |
865 | ||
197d4db7 DH |
866 | /* |
867 | * ACPI will set the HW disable bit for SP3 which means that the | |
868 | * output signals are left in an undefined state which may cause | |
869 | * spurious interrupts which we need to ignore until the hardware | |
870 | * is reinitialized. | |
871 | */ | |
c829f267 | 872 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
197d4db7 | 873 | disable_irq(data->irq); |
e258b80e DH |
874 | } |
875 | ||
876 | static int | |
877 | wbcir_suspend(struct pnp_dev *device, pm_message_t state) | |
878 | { | |
1ac7fdee SY |
879 | struct wbcir_data *data = pnp_get_drvdata(device); |
880 | led_classdev_suspend(&data->led); | |
e258b80e DH |
881 | wbcir_shutdown(device); |
882 | return 0; | |
883 | } | |
884 | ||
e258b80e | 885 | static void |
197d4db7 | 886 | wbcir_init_hw(struct wbcir_data *data) |
e258b80e DH |
887 | { |
888 | u8 tmp; | |
889 | ||
197d4db7 | 890 | /* Disable interrupts */ |
c829f267 | 891 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
197d4db7 | 892 | |
e258b80e DH |
893 | /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */ |
894 | tmp = protocol << 4; | |
895 | if (invert) | |
896 | tmp |= 0x08; | |
897 | outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL); | |
898 | ||
899 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
900 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
901 | ||
902 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ | |
903 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
904 | ||
905 | /* Set RC5 cell time to correspond to 36 kHz */ | |
906 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); | |
907 | ||
908 | /* Set IRTX_INV */ | |
909 | if (invert) | |
37b0b4e9 | 910 | outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL); |
e258b80e DH |
911 | else |
912 | outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); | |
913 | ||
914 | /* | |
c829f267 | 915 | * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, |
e258b80e DH |
916 | * set SP3_IRRX_SW to binary 01, helpfully not documented |
917 | */ | |
918 | outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); | |
c829f267 | 919 | data->txmask = 0x1; |
197d4db7 DH |
920 | |
921 | /* Enable extended mode */ | |
922 | wbcir_select_bank(data, WBCIR_BANK_2); | |
923 | outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); | |
924 | ||
925 | /* | |
926 | * Configure baud generator, IR data will be sampled at | |
927 | * a bitrate of: (24Mhz * prescaler) / (divisor * 16). | |
928 | * | |
929 | * The ECIR registers include a flag to change the | |
930 | * 24Mhz clock freq to 48Mhz. | |
931 | * | |
932 | * It's not documented in the specs, but fifo levels | |
933 | * other than 16 seems to be unsupported. | |
934 | */ | |
935 | ||
936 | /* prescaler 1.0, tx/rx fifo lvl 16 */ | |
937 | outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); | |
938 | ||
6f2627c2 SY |
939 | /* Set baud divisor to sample every 10 us */ |
940 | outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL); | |
197d4db7 DH |
941 | outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); |
942 | ||
943 | /* Set CEIR mode */ | |
944 | wbcir_select_bank(data, WBCIR_BANK_0); | |
945 | outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); | |
946 | inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ | |
947 | inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ | |
948 | ||
6f2627c2 | 949 | /* Disable RX demod, enable run-length enc/dec, set freq span */ |
197d4db7 | 950 | wbcir_select_bank(data, WBCIR_BANK_7); |
6f2627c2 | 951 | outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG); |
197d4db7 DH |
952 | |
953 | /* Disable timer */ | |
954 | wbcir_select_bank(data, WBCIR_BANK_4); | |
955 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); | |
956 | ||
c829f267 | 957 | /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ |
197d4db7 | 958 | wbcir_select_bank(data, WBCIR_BANK_5); |
c829f267 | 959 | outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); |
197d4db7 DH |
960 | |
961 | /* Disable CRC */ | |
962 | wbcir_select_bank(data, WBCIR_BANK_6); | |
963 | outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); | |
964 | ||
c829f267 | 965 | /* Set RX demodulation freq, not really used */ |
197d4db7 DH |
966 | wbcir_select_bank(data, WBCIR_BANK_7); |
967 | outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); | |
c829f267 DH |
968 | |
969 | /* Set TX modulation, 36kHz, 7us pulse width */ | |
197d4db7 | 970 | outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); |
c829f267 | 971 | data->txcarrier = 36000; |
197d4db7 DH |
972 | |
973 | /* Set invert and pin direction */ | |
974 | if (invert) | |
975 | outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); | |
976 | else | |
977 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); | |
978 | ||
979 | /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ | |
980 | wbcir_select_bank(data, WBCIR_BANK_0); | |
981 | outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); | |
982 | ||
983 | /* Clear AUX status bits */ | |
984 | outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); | |
985 | ||
c829f267 DH |
986 | /* Clear RX state */ |
987 | data->rxstate = WBCIR_RXSTATE_INACTIVE; | |
5b2e303f | 988 | ir_raw_event_reset(data->dev); |
e5eda7fa | 989 | ir_raw_event_set_idle(data->dev, true); |
5b2e303f | 990 | |
7bfb5dc1 | 991 | /* Clear TX state */ |
c829f267 | 992 | if (data->txstate == WBCIR_TXSTATE_ACTIVE) { |
7bfb5dc1 DH |
993 | kfree(data->txbuf); |
994 | data->txbuf = NULL; | |
995 | data->txstate = WBCIR_TXSTATE_INACTIVE; | |
c829f267 DH |
996 | } |
997 | ||
197d4db7 | 998 | /* Enable interrupts */ |
c829f267 | 999 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
197d4db7 DH |
1000 | } |
1001 | ||
1002 | static int | |
1003 | wbcir_resume(struct pnp_dev *device) | |
1004 | { | |
1005 | struct wbcir_data *data = pnp_get_drvdata(device); | |
1006 | ||
1007 | wbcir_init_hw(data); | |
1008 | enable_irq(data->irq); | |
1ac7fdee | 1009 | led_classdev_resume(&data->led); |
197d4db7 DH |
1010 | |
1011 | return 0; | |
e258b80e DH |
1012 | } |
1013 | ||
4c62e976 | 1014 | static int |
e258b80e DH |
1015 | wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) |
1016 | { | |
1017 | struct device *dev = &device->dev; | |
1018 | struct wbcir_data *data; | |
1019 | int err; | |
1020 | ||
1021 | if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && | |
1022 | pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && | |
1023 | pnp_port_len(device, 2) == SP_IOMEM_LEN)) { | |
1024 | dev_err(dev, "Invalid resources\n"); | |
1025 | return -ENODEV; | |
1026 | } | |
1027 | ||
1028 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1029 | if (!data) { | |
1030 | err = -ENOMEM; | |
1031 | goto exit; | |
1032 | } | |
1033 | ||
1034 | pnp_set_drvdata(device, data); | |
1035 | ||
5b2e303f | 1036 | spin_lock_init(&data->spinlock); |
e258b80e DH |
1037 | data->ebase = pnp_port_start(device, 0); |
1038 | data->wbase = pnp_port_start(device, 1); | |
1039 | data->sbase = pnp_port_start(device, 2); | |
1040 | data->irq = pnp_irq(device, 0); | |
1041 | ||
1042 | if (data->wbase == 0 || data->ebase == 0 || | |
1043 | data->sbase == 0 || data->irq == 0) { | |
1044 | err = -ENODEV; | |
1045 | dev_err(dev, "Invalid resources\n"); | |
1046 | goto exit_free_data; | |
1047 | } | |
1048 | ||
1049 | dev_dbg(&device->dev, "Found device " | |
1050 | "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", | |
1051 | data->wbase, data->ebase, data->sbase, data->irq); | |
1052 | ||
e258b80e | 1053 | data->led.name = "cir::activity"; |
1ac7fdee | 1054 | data->led.default_trigger = "rc-feedback"; |
e258b80e DH |
1055 | data->led.brightness_set = wbcir_led_brightness_set; |
1056 | data->led.brightness_get = wbcir_led_brightness_get; | |
1057 | err = led_classdev_register(&device->dev, &data->led); | |
1058 | if (err) | |
1ac7fdee | 1059 | goto exit_free_data; |
e258b80e | 1060 | |
5b2e303f DH |
1061 | data->dev = rc_allocate_device(); |
1062 | if (!data->dev) { | |
e258b80e DH |
1063 | err = -ENOMEM; |
1064 | goto exit_unregister_led; | |
1065 | } | |
1066 | ||
d9b78695 | 1067 | data->dev->driver_type = RC_DRIVER_IR_RAW; |
a66cd0b6 | 1068 | data->dev->driver_name = DRVNAME; |
5b2e303f DH |
1069 | data->dev->input_name = WBCIR_NAME; |
1070 | data->dev->input_phys = "wbcir/cir0"; | |
1071 | data->dev->input_id.bustype = BUS_HOST; | |
1072 | data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; | |
1073 | data->dev->input_id.product = WBCIR_ID_FAMILY; | |
1074 | data->dev->input_id.version = WBCIR_ID_CHIP; | |
c829f267 | 1075 | data->dev->map_name = RC_MAP_RC6_MCE; |
488ebc48 | 1076 | data->dev->s_idle = wbcir_idle_rx; |
37b0b4e9 | 1077 | data->dev->s_carrier_report = wbcir_set_carrier_report; |
c829f267 DH |
1078 | data->dev->s_tx_mask = wbcir_txmask; |
1079 | data->dev->s_tx_carrier = wbcir_txcarrier; | |
1080 | data->dev->tx_ir = wbcir_tx; | |
5b2e303f DH |
1081 | data->dev->priv = data; |
1082 | data->dev->dev.parent = &device->dev; | |
8299d628 | 1083 | data->dev->timeout = MS_TO_NS(100); |
c496e716 | 1084 | data->dev->rx_resolution = US_TO_NS(2); |
c5540fbb | 1085 | data->dev->allowed_protocols = RC_BIT_ALL; |
5b2e303f | 1086 | |
9fa35204 MK |
1087 | err = rc_register_device(data->dev); |
1088 | if (err) | |
1089 | goto exit_free_rc; | |
1090 | ||
9ef449c6 LH |
1091 | if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { |
1092 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1093 | data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); | |
1094 | err = -EBUSY; | |
9fa35204 | 1095 | goto exit_unregister_device; |
9ef449c6 LH |
1096 | } |
1097 | ||
1098 | if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { | |
1099 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1100 | data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); | |
1101 | err = -EBUSY; | |
1102 | goto exit_release_wbase; | |
1103 | } | |
1104 | ||
1105 | if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { | |
1106 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1107 | data->sbase, data->sbase + SP_IOMEM_LEN - 1); | |
1108 | err = -EBUSY; | |
1109 | goto exit_release_ebase; | |
1110 | } | |
1111 | ||
1112 | err = request_irq(data->irq, wbcir_irq_handler, | |
b9e9f02a | 1113 | 0, DRVNAME, device); |
9ef449c6 LH |
1114 | if (err) { |
1115 | dev_err(dev, "Failed to claim IRQ %u\n", data->irq); | |
1116 | err = -EBUSY; | |
1117 | goto exit_release_sbase; | |
1118 | } | |
1119 | ||
e258b80e DH |
1120 | device_init_wakeup(&device->dev, 1); |
1121 | ||
197d4db7 | 1122 | wbcir_init_hw(data); |
e258b80e DH |
1123 | |
1124 | return 0; | |
1125 | ||
e258b80e DH |
1126 | exit_release_sbase: |
1127 | release_region(data->sbase, SP_IOMEM_LEN); | |
1128 | exit_release_ebase: | |
1129 | release_region(data->ebase, EHFUNC_IOMEM_LEN); | |
1130 | exit_release_wbase: | |
1131 | release_region(data->wbase, WAKEUP_IOMEM_LEN); | |
9fa35204 MK |
1132 | exit_unregister_device: |
1133 | rc_unregister_device(data->dev); | |
4ec16da7 | 1134 | data->dev = NULL; |
9ef449c6 LH |
1135 | exit_free_rc: |
1136 | rc_free_device(data->dev); | |
1137 | exit_unregister_led: | |
1138 | led_classdev_unregister(&data->led); | |
e258b80e DH |
1139 | exit_free_data: |
1140 | kfree(data); | |
1141 | pnp_set_drvdata(device, NULL); | |
1142 | exit: | |
1143 | return err; | |
1144 | } | |
1145 | ||
4c62e976 | 1146 | static void |
e258b80e DH |
1147 | wbcir_remove(struct pnp_dev *device) |
1148 | { | |
1149 | struct wbcir_data *data = pnp_get_drvdata(device); | |
e258b80e DH |
1150 | |
1151 | /* Disable interrupts */ | |
c829f267 | 1152 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
e258b80e DH |
1153 | free_irq(data->irq, device); |
1154 | ||
1155 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
1156 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
1157 | ||
1158 | /* Clear CEIR_EN */ | |
1159 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); | |
1160 | ||
1161 | /* Clear BUFF_EN, END_EN, MATCH_EN */ | |
1162 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
1163 | ||
5b2e303f | 1164 | rc_unregister_device(data->dev); |
e258b80e | 1165 | |
e258b80e DH |
1166 | led_classdev_unregister(&data->led); |
1167 | ||
1168 | /* This is ok since &data->led isn't actually used */ | |
1169 | wbcir_led_brightness_set(&data->led, LED_OFF); | |
1170 | ||
1171 | release_region(data->wbase, WAKEUP_IOMEM_LEN); | |
1172 | release_region(data->ebase, EHFUNC_IOMEM_LEN); | |
1173 | release_region(data->sbase, SP_IOMEM_LEN); | |
1174 | ||
e258b80e DH |
1175 | kfree(data); |
1176 | ||
1177 | pnp_set_drvdata(device, NULL); | |
1178 | } | |
1179 | ||
1180 | static const struct pnp_device_id wbcir_ids[] = { | |
1181 | { "WEC1022", 0 }, | |
1182 | { "", 0 } | |
1183 | }; | |
1184 | MODULE_DEVICE_TABLE(pnp, wbcir_ids); | |
1185 | ||
1186 | static struct pnp_driver wbcir_driver = { | |
1187 | .name = WBCIR_NAME, | |
1188 | .id_table = wbcir_ids, | |
1189 | .probe = wbcir_probe, | |
4c62e976 | 1190 | .remove = wbcir_remove, |
e258b80e DH |
1191 | .suspend = wbcir_suspend, |
1192 | .resume = wbcir_resume, | |
1193 | .shutdown = wbcir_shutdown | |
1194 | }; | |
1195 | ||
1196 | static int __init | |
1197 | wbcir_init(void) | |
1198 | { | |
1199 | int ret; | |
1200 | ||
1201 | switch (protocol) { | |
1202 | case IR_PROTOCOL_RC5: | |
1203 | case IR_PROTOCOL_NEC: | |
1204 | case IR_PROTOCOL_RC6: | |
1205 | break; | |
1206 | default: | |
d8a10ac9 | 1207 | pr_err("Invalid power-on protocol\n"); |
e258b80e DH |
1208 | } |
1209 | ||
1210 | ret = pnp_register_driver(&wbcir_driver); | |
1211 | if (ret) | |
d8a10ac9 | 1212 | pr_err("Unable to register driver\n"); |
e258b80e DH |
1213 | |
1214 | return ret; | |
1215 | } | |
1216 | ||
1217 | static void __exit | |
1218 | wbcir_exit(void) | |
1219 | { | |
1220 | pnp_unregister_driver(&wbcir_driver); | |
1221 | } | |
1222 | ||
e258b80e DH |
1223 | module_init(wbcir_init); |
1224 | module_exit(wbcir_exit); | |
1225 | ||
d36b6910 | 1226 | MODULE_AUTHOR("David Härdeman <david@hardeman.nu>"); |
5b2e303f DH |
1227 | MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); |
1228 | MODULE_LICENSE("GPL"); |