[linux-block.git] / drivers / media / rc / sunxi-cir.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Allwinner sunXi IR controller
 *
 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
 * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
 *
 * Based on sun5i-ir.c:
 * Copyright (C) 2007-2012 Daniel Wang
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <media/rc-core.h>

#define SUNXI_IR_DEV "sunxi-ir"

/* Registers */
/* IR Control */
#define SUNXI_IR_CTL_REG      0x00
/* Global Enable */
#define REG_CTL_GEN			BIT(0)
/* RX block enable */
#define REG_CTL_RXEN			BIT(1)
/* CIR mode */
#define REG_CTL_MD			(BIT(4) | BIT(5))

/* Rx Config */
#define SUNXI_IR_RXCTL_REG    0x10
/* Pulse Polarity Invert flag */
#define REG_RXCTL_RPPI			BIT(2)

/* Rx Data */
#define SUNXI_IR_RXFIFO_REG   0x20

/* Rx Interrupt Enable */
#define SUNXI_IR_RXINT_REG    0x2C
/* Rx FIFO Overflow Interrupt Enable */
#define REG_RXINT_ROI_EN		BIT(0)
/* Rx Packet End Interrupt Enable */
#define REG_RXINT_RPEI_EN		BIT(1)
/* Rx FIFO Data Available Interrupt Enable */
#define REG_RXINT_RAI_EN		BIT(4)

/* Rx FIFO available byte level */
#define REG_RXINT_RAL(val)    ((val) << 8)

/* Rx Interrupt Status */
#define SUNXI_IR_RXSTA_REG    0x30
/* Rx FIFO Overflow */
#define REG_RXSTA_ROI			REG_RXINT_ROI_EN
/* Rx Packet End */
#define REG_RXSTA_RPE			REG_RXINT_RPEI_EN
/* Rx FIFO Data Available */
#define REG_RXSTA_RA			REG_RXINT_RAI_EN
/* RX FIFO Get Available Counter */
#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
/* Clear all interrupt status value */
#define REG_RXSTA_CLEARALL    0xff

/* IR Sample Config */
#define SUNXI_IR_CIR_REG      0x34
/* CIR_REG register noise threshold */
#define REG_CIR_NTHR(val)    (((val) << 2) & (GENMASK(7, 2)))
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)    (((val) << 8) & (GENMASK(15, 8)))

/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
#define SUNXI_IR_BASE_CLK     8000000
/* Noise threshold in samples  */
#define SUNXI_IR_RXNOISE      1

/**
 * struct sunxi_ir_quirks - Differences between SoC variants.
 *
 * @has_reset: SoC needs reset deasserted.
 * @fifo_size: size of the fifo.
 */
struct sunxi_ir_quirks {
	bool		has_reset;
	int		fifo_size;
};

struct sunxi_ir {
	struct rc_dev   *rc;
	void __iomem    *base;
	int             irq;
	int		fifo_size;
	struct clk      *clk;
	struct clk      *apb_clk;
	struct reset_control *rst;
	const char      *map_name;
};

static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
{
	unsigned long status;
	unsigned char dt;
	unsigned int cnt, rc;
	struct sunxi_ir *ir = dev_id;
	struct ir_raw_event rawir = {};

	status = readl(ir->base + SUNXI_IR_RXSTA_REG);

	/* clean all pending statuses */
	writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);

	if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) {
		/* How many messages in fifo */
		rc  = REG_RXSTA_GET_AC(status);
		/* Sanity check */
		rc = rc > ir->fifo_size ? ir->fifo_size : rc;
		/* If we have data */
		for (cnt = 0; cnt < rc; cnt++) {
			/* for each bit in fifo */
			dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
			rawir.pulse = (dt & 0x80) != 0;
			rawir.duration = ((dt & 0x7f) + 1) *
					 ir->rc->rx_resolution;
			ir_raw_event_store_with_filter(ir->rc, &rawir);
		}
	}

	if (status & REG_RXSTA_ROI) {
		ir_raw_event_overflow(ir->rc);
	} else if (status & REG_RXSTA_RPE) {
		ir_raw_event_set_idle(ir->rc, true);
		ir_raw_event_handle(ir->rc);
	} else {
		ir_raw_event_handle(ir->rc);
	}

	return IRQ_HANDLED;
}

/* Convert idle threshold to usec */
static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr)
{
	return DIV_ROUND_CLOSEST(USEC_PER_SEC * (ithr + 1),
				 base_clk / (128 * 64));
}

/* Convert usec to idle threshold */
static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec)
{
	/* make sure we don't end up with a timeout less than requested */
	return DIV_ROUND_UP((base_clk / (128 * 64)) * usec,  USEC_PER_SEC) - 1;
}

static int sunxi_ir_set_timeout(struct rc_dev *rc_dev, unsigned int timeout)
{
	struct sunxi_ir *ir = rc_dev->priv;
	unsigned int base_clk = clk_get_rate(ir->clk);

	unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout);

	dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr);

	/* Set noise threshold and idle threshold */
	writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr),
	       ir->base + SUNXI_IR_CIR_REG);

	rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr);

	return 0;
}

static int sunxi_ir_hw_init(struct device *dev)
{
	struct sunxi_ir *ir = dev_get_drvdata(dev);
	u32 tmp;
	int ret;

	ret = reset_control_deassert(ir->rst);
	if (ret)
		return ret;

	ret = clk_prepare_enable(ir->apb_clk);
	if (ret) {
		dev_err(dev, "failed to enable apb clk\n");
		goto exit_assert_reset;
	}

	ret = clk_prepare_enable(ir->clk);
	if (ret) {
		dev_err(dev, "failed to enable ir clk\n");
		goto exit_disable_apb_clk;
	}

	/* Enable CIR Mode */
	writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG);

	/* Set noise threshold and idle threshold */
	sunxi_ir_set_timeout(ir->rc, ir->rc->timeout);

	/* Invert Input Signal */
	writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);

	/* Clear All Rx Interrupt Status */
	writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);

	/*
	 * Enable IRQ on overflow, packet end, FIFO available with trigger
	 * level
	 */
	writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
	       REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
	       ir->base + SUNXI_IR_RXINT_REG);

	/* Enable IR Module */
	tmp = readl(ir->base + SUNXI_IR_CTL_REG);
	writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);

	return 0;

exit_disable_apb_clk:
	clk_disable_unprepare(ir->apb_clk);
exit_assert_reset:
	reset_control_assert(ir->rst);

	return ret;
}

static void sunxi_ir_hw_exit(struct device *dev)
{
	struct sunxi_ir *ir = dev_get_drvdata(dev);

	clk_disable_unprepare(ir->clk);
	clk_disable_unprepare(ir->apb_clk);
	reset_control_assert(ir->rst);
}

static int __maybe_unused sunxi_ir_suspend(struct device *dev)
{
	sunxi_ir_hw_exit(dev);

	return 0;
}

static int __maybe_unused sunxi_ir_resume(struct device *dev)
{
	return sunxi_ir_hw_init(dev);
}

static SIMPLE_DEV_PM_OPS(sunxi_ir_pm_ops, sunxi_ir_suspend, sunxi_ir_resume);

static int sunxi_ir_probe(struct platform_device *pdev)
{
	int ret = 0;

	struct device *dev = &pdev->dev;
	struct device_node *dn = dev->of_node;
	const struct sunxi_ir_quirks *quirks;
	struct sunxi_ir *ir;
	u32 b_clk_freq = SUNXI_IR_BASE_CLK;

	ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
	if (!ir)
		return -ENOMEM;

	quirks = of_device_get_match_data(&pdev->dev);
	if (!quirks) {
		dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
		return -ENODEV;
	}

	ir->fifo_size = quirks->fifo_size;

	/* Clock */
	ir->apb_clk = devm_clk_get(dev, "apb");
	if (IS_ERR(ir->apb_clk)) {
		dev_err(dev, "failed to get a apb clock.\n");
		return PTR_ERR(ir->apb_clk);
	}
	ir->clk = devm_clk_get(dev, "ir");
	if (IS_ERR(ir->clk)) {
		dev_err(dev, "failed to get a ir clock.\n");
		return PTR_ERR(ir->clk);
	}

	/* Base clock frequency (optional) */
	of_property_read_u32(dn, "clock-frequency", &b_clk_freq);

	/* Reset */
	if (quirks->has_reset) {
		ir->rst = devm_reset_control_get_exclusive(dev, NULL);
		if (IS_ERR(ir->rst))
			return PTR_ERR(ir->rst);
	}

	ret = clk_set_rate(ir->clk, b_clk_freq);
	if (ret) {
		dev_err(dev, "set ir base clock failed!\n");
		return ret;
	}
	dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);

	/* IO */
	ir->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(ir->base)) {
		return PTR_ERR(ir->base);
	}

	ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
	if (!ir->rc) {
		dev_err(dev, "failed to allocate device\n");
		return -ENOMEM;
	}

	ir->rc->priv = ir;
	ir->rc->device_name = SUNXI_IR_DEV;
	ir->rc->input_phys = "sunxi-ir/input0";
	ir->rc->input_id.bustype = BUS_HOST;
	ir->rc->input_id.vendor = 0x0001;
	ir->rc->input_id.product = 0x0001;
	ir->rc->input_id.version = 0x0100;
	ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
	ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
	ir->rc->dev.parent = dev;
	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
	/* Frequency after IR internal divider with sample period in us */
	ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
	ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0);
	ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255);
	ir->rc->s_timeout = sunxi_ir_set_timeout;
	ir->rc->driver_name = SUNXI_IR_DEV;

	ret = rc_register_device(ir->rc);
	if (ret) {
		dev_err(dev, "failed to register rc device\n");
		goto exit_free_dev;
	}

	platform_set_drvdata(pdev, ir);

	/* IRQ */
	ir->irq = platform_get_irq(pdev, 0);
	if (ir->irq < 0) {
		ret = ir->irq;
		goto exit_free_dev;
	}

	ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
	if (ret) {
		dev_err(dev, "failed request irq\n");
		goto exit_free_dev;
	}

	ret = sunxi_ir_hw_init(dev);
	if (ret)
		goto exit_free_dev;

	dev_info(dev, "initialized sunXi IR driver\n");
	return 0;

exit_free_dev:
	rc_free_device(ir->rc);

	return ret;
}

static void sunxi_ir_remove(struct platform_device *pdev)
{
	struct sunxi_ir *ir = platform_get_drvdata(pdev);

	rc_unregister_device(ir->rc);
	sunxi_ir_hw_exit(&pdev->dev);
}

static void sunxi_ir_shutdown(struct platform_device *pdev)
{
	sunxi_ir_hw_exit(&pdev->dev);
}

static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
	.has_reset = false,
	.fifo_size = 16,
};

static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
	.has_reset = false,
	.fifo_size = 64,
};

static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
	.has_reset = true,
	.fifo_size = 64,
};

static const struct of_device_id sunxi_ir_match[] = {
	{
		.compatible = "allwinner,sun4i-a10-ir",
		.data = &sun4i_a10_ir_quirks,
	},
	{
		.compatible = "allwinner,sun5i-a13-ir",
		.data = &sun5i_a13_ir_quirks,
	},
	{
		.compatible = "allwinner,sun6i-a31-ir",
		.data = &sun6i_a31_ir_quirks,
	},
	{}
};
MODULE_DEVICE_TABLE(of, sunxi_ir_match);

static struct platform_driver sunxi_ir_driver = {
	.probe          = sunxi_ir_probe,
	.remove_new     = sunxi_ir_remove,
	.shutdown       = sunxi_ir_shutdown,
	.driver = {
		.name = SUNXI_IR_DEV,
		.of_match_table = sunxi_ir_match,
		.pm = &sunxi_ir_pm_ops,
	},
};

module_platform_driver(sunxi_ir_driver);

MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
b4e3e59f AB	2	/*
	3	* Driver for Allwinner sunXi IR controller
	4	*
	5	* Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
	6	* Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
	7	*
	8	* Based on sun5i-ir.c:
	9	* Copyright (C) 2007-2012 Daniel Wang
	10	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
b4e3e59f AB	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/interrupt.h>
1f65ce65	15	#include <linux/io.h>
b4e3e59f	16	#include <linux/module.h>
7c7e33b7 RH	17	#include <linux/of.h>
7c7e33b7 RH	18	#include <linux/platform_device.h>
44f8af68	19	#include <linux/reset.h>
b4e3e59f AB	20	#include <media/rc-core.h>
	21
	22	#define SUNXI_IR_DEV "sunxi-ir"
	23
	24	/* Registers */
	25	/* IR Control */
	26	#define SUNXI_IR_CTL_REG 0x00
	27	/* Global Enable */
	28	#define REG_CTL_GEN BIT(0)
	29	/* RX block enable */
	30	#define REG_CTL_RXEN BIT(1)
	31	/* CIR mode */
	32	#define REG_CTL_MD (BIT(4) \| BIT(5))
	33
	34	/* Rx Config */
	35	#define SUNXI_IR_RXCTL_REG 0x10
	36	/* Pulse Polarity Invert flag */
	37	#define REG_RXCTL_RPPI BIT(2)
	38
	39	/* Rx Data */
	40	#define SUNXI_IR_RXFIFO_REG 0x20
	41
	42	/* Rx Interrupt Enable */
	43	#define SUNXI_IR_RXINT_REG 0x2C
b136d72c	44	/* Rx FIFO Overflow Interrupt Enable */
b4e3e59f	45	#define REG_RXINT_ROI_EN BIT(0)
b136d72c	46	/* Rx Packet End Interrupt Enable */
b4e3e59f	47	#define REG_RXINT_RPEI_EN BIT(1)
b136d72c	48	/* Rx FIFO Data Available Interrupt Enable */
b4e3e59f AB	49	#define REG_RXINT_RAI_EN BIT(4)
	50
	51	/* Rx FIFO available byte level */
a4bca4c7	52	#define REG_RXINT_RAL(val) ((val) << 8)
b4e3e59f AB	53
	54	/* Rx Interrupt Status */
	55	#define SUNXI_IR_RXSTA_REG 0x30
b136d72c CP	56	/* Rx FIFO Overflow */
	57	#define REG_RXSTA_ROI REG_RXINT_ROI_EN
	58	/* Rx Packet End */
	59	#define REG_RXSTA_RPE REG_RXINT_RPEI_EN
	60	/* Rx FIFO Data Available */
	61	#define REG_RXSTA_RA REG_RXINT_RAI_EN
b4e3e59f	62	/* RX FIFO Get Available Counter */
a4bca4c7	63	#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
b4e3e59f AB	64	/* Clear all interrupt status value */
	65	#define REG_RXSTA_CLEARALL 0xff
	66
	67	/* IR Sample Config */
	68	#define SUNXI_IR_CIR_REG 0x34
	69	/* CIR_REG register noise threshold */
	70	#define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))
	71	/* CIR_REG register idle threshold */
	72	#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
	73
10e71206	74	/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
b4e3e59f	75	#define SUNXI_IR_BASE_CLK 8000000
b4e3e59f AB	76	/* Noise threshold in samples */
b4e3e59f AB	77	#define SUNXI_IR_RXNOISE 1
b4e3e59f	78
6b197cb5 CP	79	/**
	80	* struct sunxi_ir_quirks - Differences between SoC variants.
	81	*
	82	* @has_reset: SoC needs reset deasserted.
	83	* @fifo_size: size of the fifo.
	84	*/
	85	struct sunxi_ir_quirks {
	86	bool has_reset;
	87	int fifo_size;
	88	};
	89
b4e3e59f	90	struct sunxi_ir {
b4e3e59f AB	91	struct rc_dev *rc;
	92	void __iomem *base;
	93	int irq;
a4bca4c7	94	int fifo_size;
b4e3e59f AB	95	struct clk *clk;
b4e3e59f AB	96	struct clk *apb_clk;
44f8af68	97	struct reset_control *rst;
b4e3e59f AB	98	const char *map_name;
	99	};
	100
	101	static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
	102	{
	103	unsigned long status;
	104	unsigned char dt;
	105	unsigned int cnt, rc;
	106	struct sunxi_ir *ir = dev_id;
183e19f5	107	struct ir_raw_event rawir = {};
b4e3e59f	108
b4e3e59f AB	109	status = readl(ir->base + SUNXI_IR_RXSTA_REG);
	110
	111	/* clean all pending statuses */
	112	writel(status \| REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
	113
b136d72c	114	if (status & (REG_RXSTA_RA \| REG_RXSTA_RPE)) {
b4e3e59f AB	115	/* How many messages in fifo */
	116	rc = REG_RXSTA_GET_AC(status);
	117	/* Sanity check */
a4bca4c7	118	rc = rc > ir->fifo_size ? ir->fifo_size : rc;
b4e3e59f AB	119	/* If we have data */
	120	for (cnt = 0; cnt < rc; cnt++) {
	121	/* for each bit in fifo */
	122	dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
	123	rawir.pulse = (dt & 0x80) != 0;
10e71206 PR	124	rawir.duration = ((dt & 0x7f) + 1) *
10e71206 PR	125	ir->rc->rx_resolution;
b4e3e59f AB	126	ir_raw_event_store_with_filter(ir->rc, &rawir);
	127	}
	128	}
	129
b136d72c	130	if (status & REG_RXSTA_ROI) {
950170d6	131	ir_raw_event_overflow(ir->rc);
b136d72c	132	} else if (status & REG_RXSTA_RPE) {
b4e3e59f AB	133	ir_raw_event_set_idle(ir->rc, true);
b4e3e59f AB	134	ir_raw_event_handle(ir->rc);
3f56df4c SY	135	} else {
3f56df4c SY	136	ir_raw_event_handle(ir->rc);
b4e3e59f AB	137	}
b4e3e59f AB	138
b4e3e59f AB	139	return IRQ_HANDLED;
	140	}
	141
371443de SY	142	/* Convert idle threshold to usec */
	143	static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr)
	144	{
	145	return DIV_ROUND_CLOSEST(USEC_PER_SEC * (ithr + 1),
	146	base_clk / (128 * 64));
	147	}
	148
	149	/* Convert usec to idle threshold */
	150	static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec)
	151	{
	152	/* make sure we don't end up with a timeout less than requested */
	153	return DIV_ROUND_UP((base_clk / (128 * 64)) * usec, USEC_PER_SEC) - 1;
	154	}
	155
	156	static int sunxi_ir_set_timeout(struct rc_dev *rc_dev, unsigned int timeout)
	157	{
	158	struct sunxi_ir *ir = rc_dev->priv;
	159	unsigned int base_clk = clk_get_rate(ir->clk);
371443de SY	160
	161	unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout);
	162
	163	dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr);
	164
371443de SY	165	/* Set noise threshold and idle threshold */
	166	writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) \| REG_CIR_ITHR(ithr),
	167	ir->base + SUNXI_IR_CIR_REG);
371443de SY	168
	169	rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr);
	170
	171	return 0;
	172	}
	173
8f9061fa SH	174	static int sunxi_ir_hw_init(struct device *dev)
	175	{
	176	struct sunxi_ir *ir = dev_get_drvdata(dev);
	177	u32 tmp;
	178	int ret;
	179
	180	ret = reset_control_deassert(ir->rst);
	181	if (ret)
	182	return ret;
	183
	184	ret = clk_prepare_enable(ir->apb_clk);
	185	if (ret) {
	186	dev_err(dev, "failed to enable apb clk\n");
	187	goto exit_assert_reset;
	188	}
	189
	190	ret = clk_prepare_enable(ir->clk);
	191	if (ret) {
	192	dev_err(dev, "failed to enable ir clk\n");
	193	goto exit_disable_apb_clk;
	194	}
	195
	196	/* Enable CIR Mode */
	197	writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG);
	198
	199	/* Set noise threshold and idle threshold */
	200	sunxi_ir_set_timeout(ir->rc, ir->rc->timeout);
	201
	202	/* Invert Input Signal */
	203	writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
	204
	205	/* Clear All Rx Interrupt Status */
	206	writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
	207
	208	/*
	209	* Enable IRQ on overflow, packet end, FIFO available with trigger
	210	* level
	211	*/
	212	writel(REG_RXINT_ROI_EN \| REG_RXINT_RPEI_EN \|
	213	REG_RXINT_RAI_EN \| REG_RXINT_RAL(ir->fifo_size / 2 - 1),
	214	ir->base + SUNXI_IR_RXINT_REG);
	215
	216	/* Enable IR Module */
	217	tmp = readl(ir->base + SUNXI_IR_CTL_REG);
	218	writel(tmp \| REG_CTL_GEN \| REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
	219
	220	return 0;
	221
	222	exit_disable_apb_clk:
	223	clk_disable_unprepare(ir->apb_clk);
	224	exit_assert_reset:
	225	reset_control_assert(ir->rst);
	226
	227	return ret;
	228	}
	229
	230	static void sunxi_ir_hw_exit(struct device *dev)
	231	{
	232	struct sunxi_ir *ir = dev_get_drvdata(dev);
	233
	234	clk_disable_unprepare(ir->clk);
	235	clk_disable_unprepare(ir->apb_clk);
	236	reset_control_assert(ir->rst);
	237	}
238
a6f42f5e SH	239	static int __maybe_unused sunxi_ir_suspend(struct device *dev)
	240	{
	241	sunxi_ir_hw_exit(dev);
	242
	243	return 0;
	244	}
	245
	246	static int __maybe_unused sunxi_ir_resume(struct device *dev)
	247	{
	248	return sunxi_ir_hw_init(dev);
	249	}
	250
	251	static SIMPLE_DEV_PM_OPS(sunxi_ir_pm_ops, sunxi_ir_suspend, sunxi_ir_resume);
	252
b4e3e59f AB	253	static int sunxi_ir_probe(struct platform_device *pdev)
	254	{
	255	int ret = 0;
b4e3e59f AB	256
	257	struct device *dev = &pdev->dev;
	258	struct device_node *dn = dev->of_node;
6b197cb5	259	const struct sunxi_ir_quirks *quirks;
b4e3e59f	260	struct sunxi_ir *ir;
10e71206	261	u32 b_clk_freq = SUNXI_IR_BASE_CLK;
b4e3e59f AB	262
	263	ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
	264	if (!ir)
	265	return -ENOMEM;
	266
6b197cb5 CP	267	quirks = of_device_get_match_data(&pdev->dev);
	268	if (!quirks) {
	269	dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
	270	return -ENODEV;
	271	}
	272
6b197cb5	273	ir->fifo_size = quirks->fifo_size;
a4bca4c7	274
b4e3e59f AB	275	/* Clock */
	276	ir->apb_clk = devm_clk_get(dev, "apb");
	277	if (IS_ERR(ir->apb_clk)) {
	278	dev_err(dev, "failed to get a apb clock.\n");
	279	return PTR_ERR(ir->apb_clk);
	280	}
	281	ir->clk = devm_clk_get(dev, "ir");
	282	if (IS_ERR(ir->clk)) {
	283	dev_err(dev, "failed to get a ir clock.\n");
	284	return PTR_ERR(ir->clk);
	285	}
	286
10e71206 PR	287	/* Base clock frequency (optional) */
	288	of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
	289
6b197cb5 CP	290	/* Reset */
	291	if (quirks->has_reset) {
	292	ir->rst = devm_reset_control_get_exclusive(dev, NULL);
	293	if (IS_ERR(ir->rst))
	294	return PTR_ERR(ir->rst);
6b197cb5	295	}
44f8af68	296
10e71206	297	ret = clk_set_rate(ir->clk, b_clk_freq);
b4e3e59f AB	298	if (ret) {
b4e3e59f AB	299	dev_err(dev, "set ir base clock failed!\n");
8f9061fa	300	return ret;
b4e3e59f	301	}
10e71206	302	dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
b4e3e59f	303
b4e3e59f	304	/* IO */
1c9b885c	305	ir->base = devm_platform_ioremap_resource(pdev, 0);
b4e3e59f	306	if (IS_ERR(ir->base)) {
8f9061fa	307	return PTR_ERR(ir->base);
b4e3e59f AB	308	}
b4e3e59f AB	309
0f7499fd	310	ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
b4e3e59f AB	311	if (!ir->rc) {
b4e3e59f AB	312	dev_err(dev, "failed to allocate device\n");
8f9061fa	313	return -ENOMEM;
b4e3e59f AB	314	}
	315
	316	ir->rc->priv = ir;
518f4b26	317	ir->rc->device_name = SUNXI_IR_DEV;
b4e3e59f AB	318	ir->rc->input_phys = "sunxi-ir/input0";
	319	ir->rc->input_id.bustype = BUS_HOST;
	320	ir->rc->input_id.vendor = 0x0001;
	321	ir->rc->input_id.product = 0x0001;
	322	ir->rc->input_id.version = 0x0100;
	323	ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
	324	ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
	325	ir->rc->dev.parent = dev;
6d741bfe	326	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
371443de	327	/* Frequency after IR internal divider with sample period in us */
528222d8	328	ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
8f9061fa	329	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
371443de SY	330	ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0);
	331	ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255);
	332	ir->rc->s_timeout = sunxi_ir_set_timeout;
b4e3e59f AB	333	ir->rc->driver_name = SUNXI_IR_DEV;
	334
	335	ret = rc_register_device(ir->rc);
	336	if (ret) {
	337	dev_err(dev, "failed to register rc device\n");
	338	goto exit_free_dev;
	339	}
	340
	341	platform_set_drvdata(pdev, ir);
	342
	343	/* IRQ */
	344	ir->irq = platform_get_irq(pdev, 0);
	345	if (ir->irq < 0) {
b4e3e59f AB	346	ret = ir->irq;
	347	goto exit_free_dev;
	348	}
	349
	350	ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
	351	if (ret) {
	352	dev_err(dev, "failed request irq\n");
	353	goto exit_free_dev;
	354	}
	355
8f9061fa SH	356	ret = sunxi_ir_hw_init(dev);
	357	if (ret)
	358	goto exit_free_dev;
b4e3e59f AB	359
	360	dev_info(dev, "initialized sunXi IR driver\n");
	361	return 0;
	362
	363	exit_free_dev:
	364	rc_free_device(ir->rc);
b4e3e59f AB	365
	366	return ret;
	367	}
	368
04b5c28b	369	static void sunxi_ir_remove(struct platform_device *pdev)
b4e3e59f	370	{
b4e3e59f AB	371	struct sunxi_ir *ir = platform_get_drvdata(pdev);
b4e3e59f AB	372
b4e3e59f	373	rc_unregister_device(ir->rc);
8f9061fa	374	sunxi_ir_hw_exit(&pdev->dev);
b4e3e59f AB	375	}
b4e3e59f AB	376
a6f42f5e SH	377	static void sunxi_ir_shutdown(struct platform_device *pdev)
	378	{
	379	sunxi_ir_hw_exit(&pdev->dev);
	380	}
	381
6b197cb5 CP	382	static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
	383	.has_reset = false,
	384	.fifo_size = 16,
	385	};
	386
	387	static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
	388	.has_reset = false,
	389	.fifo_size = 64,
	390	};
	391
87d06098 CP	392	static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
	393	.has_reset = true,
	394	.fifo_size = 64,
	395	};
	396
b4e3e59f	397	static const struct of_device_id sunxi_ir_match[] = {
6b197cb5 CP	398	{
	399	.compatible = "allwinner,sun4i-a10-ir",
	400	.data = &sun4i_a10_ir_quirks,
	401	},
	402	{
	403	.compatible = "allwinner,sun5i-a13-ir",
	404	.data = &sun5i_a13_ir_quirks,
	405	},
87d06098 CP	406	{
	407	.compatible = "allwinner,sun6i-a31-ir",
	408	.data = &sun6i_a31_ir_quirks,
	409	},
6b197cb5	410	{}
b4e3e59f	411	};
ea05e8b4	412	MODULE_DEVICE_TABLE(of, sunxi_ir_match);
b4e3e59f AB	413
	414	static struct platform_driver sunxi_ir_driver = {
	415	.probe = sunxi_ir_probe,
04b5c28b	416	.remove_new = sunxi_ir_remove,
a6f42f5e	417	.shutdown = sunxi_ir_shutdown,
b4e3e59f AB	418	.driver = {
b4e3e59f AB	419	.name = SUNXI_IR_DEV,
b4e3e59f	420	.of_match_table = sunxi_ir_match,
a6f42f5e	421	.pm = &sunxi_ir_pm_ops,
b4e3e59f AB	422	},
	423	};
	424
	425	module_platform_driver(sunxi_ir_driver);
	426
	427	MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
	428	MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
	429	MODULE_LICENSE("GPL");