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Merge tag 'iommu-fixes-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...
[linux-2.6-block.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
563cd5ce
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
6d2f5c27
JW		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pnp.h>
33#include <linux/io.h>
34#include <linux/interrupt.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
6bda9644 37#include <media/rc-core.h>
6d2f5c27
JW		 38#include <linux/pci_ids.h>
39
40#include "nuvoton-cir.h"
41
6d2f5c27
JW		 42/* write val to config reg */
43static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
44{
45 outb(reg, nvt->cr_efir);
46 outb(val, nvt->cr_efdr);
47}
48
49/* read val from config reg */
50static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
51{
52 outb(reg, nvt->cr_efir);
53 return inb(nvt->cr_efdr);
54}
55
56/* update config register bit without changing other bits */
57static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
58{
59 u8 tmp = nvt_cr_read(nvt, reg) | val;
60 nvt_cr_write(nvt, tmp, reg);
61}
62
63/* clear config register bit without changing other bits */
64static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
65{
66 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
67 nvt_cr_write(nvt, tmp, reg);
68}
69
70/* enter extended function mode */
71static inline void nvt_efm_enable(struct nvt_dev *nvt)
72{
73 /* Enabling Extended Function Mode explicitly requires writing 2x */
74 outb(EFER_EFM_ENABLE, nvt->cr_efir);
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76}
77
78/* exit extended function mode */
79static inline void nvt_efm_disable(struct nvt_dev *nvt)
80{
81 outb(EFER_EFM_DISABLE, nvt->cr_efir);
82}
83
84/*
85 * When you want to address a specific logical device, write its logical
86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
88 */
89static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
90{
91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
92 outb(ldev, nvt->cr_efdr);
93}
94
95/* write val to cir config register */
96static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
97{
98 outb(val, nvt->cir_addr + offset);
99}
100
101/* read val from cir config register */
102static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
103{
104 u8 val;
105
106 val = inb(nvt->cir_addr + offset);
107
108 return val;
109}
110
111/* write val to cir wake register */
112static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
113 u8 val, u8 offset)
114{
115 outb(val, nvt->cir_wake_addr + offset);
116}
117
118/* read val from cir wake config register */
119static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
120{
121 u8 val;
122
123 val = inb(nvt->cir_wake_addr + offset);
124
125 return val;
126}
127
128/* dump current cir register contents */
129static void cir_dump_regs(struct nvt_dev *nvt)
130{
131 nvt_efm_enable(nvt);
132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
133
563cd5ce
JP		 134 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
135 pr_info(" * CR CIR ACTIVE : 0x%x\n",
136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
137 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
6d2f5c27 139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 140 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 142
143 nvt_efm_disable(nvt);
144
563cd5ce
JP		 145 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 162}
163
164/* dump current cir wake register contents */
165static void cir_wake_dump_regs(struct nvt_dev *nvt)
166{
167 u8 i, fifo_len;
168
169 nvt_efm_enable(nvt);
170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
171
563cd5ce
JP		 172 pr_info("%s: Dump CIR WAKE logical device registers:\n",
173 NVT_DRIVER_NAME);
174 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad 178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 179 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 181
182 nvt_efm_disable(nvt);
183
563cd5ce
JP		 184 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
185 pr_info(" * IRCON: 0x%x\n",
186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
187 pr_info(" * IRSTS: 0x%x\n",
188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
189 pr_info(" * IREN: 0x%x\n",
190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
191 pr_info(" * FIFO CMP DEEP: 0x%x\n",
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
193 pr_info(" * FIFO CMP TOL: 0x%x\n",
194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
195 pr_info(" * FIFO COUNT: 0x%x\n",
196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
197 pr_info(" * SLCH: 0x%x\n",
198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
199 pr_info(" * SLCL: 0x%x\n",
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
201 pr_info(" * FIFOCON: 0x%x\n",
202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
203 pr_info(" * SRXFSTS: 0x%x\n",
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
205 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
207 pr_info(" * WR FIFO DATA: 0x%x\n",
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
209 pr_info(" * RD FIFO ONLY: 0x%x\n",
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
211 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
213 pr_info(" * FIFO IGNORE: 0x%x\n",
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
215 pr_info(" * IRFSM: 0x%x\n",
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
6d2f5c27
JW		 217
218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
563cd5ce
JP		 219 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
220 pr_info("* Contents =");
6d2f5c27 221 for (i = 0; i < fifo_len; i++)
563cd5ce
JP		 222 pr_cont(" %02x",
223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
224 pr_cont("\n");
6d2f5c27
JW		 225}
226
227/* detect hardware features */
228static int nvt_hw_detect(struct nvt_dev *nvt)
229{
230 unsigned long flags;
231 u8 chip_major, chip_minor;
362d3a3a
JW		 232 char chip_id[12];
233 bool chip_unknown = false;
6d2f5c27
JW		 234
235 nvt_efm_enable(nvt);
236
237 /* Check if we're wired for the alternate EFER setup */
238 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
239 if (chip_major == 0xff) {
240 nvt->cr_efir = CR_EFIR2;
241 nvt->cr_efdr = CR_EFDR2;
242 nvt_efm_enable(nvt);
243 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
244 }
245
246 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
6d2f5c27 247
362d3a3a
JW		 248 /* these are the known working chip revisions... */
249 switch (chip_major) {
250 case CHIP_ID_HIGH_667:
251 strcpy(chip_id, "w83667hg\0");
252 if (chip_minor != CHIP_ID_LOW_667)
253 chip_unknown = true;
254 break;
255 case CHIP_ID_HIGH_677B:
256 strcpy(chip_id, "w83677hg\0");
257 if (chip_minor != CHIP_ID_LOW_677B2 &&
258 chip_minor != CHIP_ID_LOW_677B3)
259 chip_unknown = true;
260 break;
261 case CHIP_ID_HIGH_677C:
262 strcpy(chip_id, "w83677hg-c\0");
263 if (chip_minor != CHIP_ID_LOW_677C)
264 chip_unknown = true;
265 break;
266 default:
267 strcpy(chip_id, "w836x7hg\0");
268 chip_unknown = true;
269 break;
5df465df 270 }
6d2f5c27 271
362d3a3a
JW		 272 /* warn, but still let the driver load, if we don't know this chip */
273 if (chip_unknown)
274 nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
275 "it may not work...", chip_id, chip_major, chip_minor);
276 else
277 nvt_dbg("%s: chip id: 0x%02x 0x%02x",
278 chip_id, chip_major, chip_minor);
279
6d2f5c27
JW		 280 nvt_efm_disable(nvt);
281
282 spin_lock_irqsave(&nvt->nvt_lock, flags);
283 nvt->chip_major = chip_major;
284 nvt->chip_minor = chip_minor;
285 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
286
f2747cf6 287 return 0;
6d2f5c27
JW		 288}
289
290static void nvt_cir_ldev_init(struct nvt_dev *nvt)
291{
39381d4f
JW		 292 u8 val, psreg, psmask, psval;
293
294 if (nvt->chip_major == CHIP_ID_HIGH_667) {
295 psreg = CR_MULTIFUNC_PIN_SEL;
296 psmask = MULTIFUNC_PIN_SEL_MASK;
297 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
298 } else {
299 psreg = CR_OUTPUT_PIN_SEL;
300 psmask = OUTPUT_PIN_SEL_MASK;
301 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
302 }
6d2f5c27 303
39381d4f
JW		 304 /* output pin selection: enable CIR, with WB sensor enabled */
305 val = nvt_cr_read(nvt, psreg);
306 val &= psmask;
307 val |= psval;
308 nvt_cr_write(nvt, val, psreg);
6d2f5c27
JW		 309
310 /* Select CIR logical device and enable */
311 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
312 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
313
314 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
315 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
316
317 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
318
319 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
320 nvt->cir_addr, nvt->cir_irq);
321}
322
323static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
324{
325 /* Select ACPI logical device, enable it and CIR Wake */
326 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
327 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
328
329 /* Enable CIR Wake via PSOUT# (Pin60) */
330 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
331
6d2f5c27
JW		 332 /* enable pme interrupt of cir wakeup event */
333 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
334
335 /* Select CIR Wake logical device and enable */
336 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
337 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
338
339 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
340 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
341
342 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
343
344 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
345 nvt->cir_wake_addr, nvt->cir_wake_irq);
346}
347
348/* clear out the hardware's cir rx fifo */
349static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
350{
351 u8 val;
352
353 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
354 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
355}
356
357/* clear out the hardware's cir wake rx fifo */
358static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
359{
360 u8 val;
361
362 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
363 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
364 CIR_WAKE_FIFOCON);
365}
366
367/* clear out the hardware's cir tx fifo */
368static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
369{
370 u8 val;
371
372 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
373 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
374}
375
fbdc781c
JW		 376/* enable RX Trigger Level Reach and Packet End interrupts */
377static void nvt_set_cir_iren(struct nvt_dev *nvt)
378{
379 u8 iren;
380
381 iren = CIR_IREN_RTR | CIR_IREN_PE;
382 nvt_cir_reg_write(nvt, iren, CIR_IREN);
383}
384
6d2f5c27
JW		 385static void nvt_cir_regs_init(struct nvt_dev *nvt)
386{
387 /* set sample limit count (PE interrupt raised when reached) */
388 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
389 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
390
391 /* set fifo irq trigger levels */
392 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
393 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
394
395 /*
396 * Enable TX and RX, specify carrier on = low, off = high, and set
397 * sample period (currently 50us)
398 */
4e6e29ad
JW		 399 nvt_cir_reg_write(nvt,
400 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
401 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
402 CIR_IRCON);
6d2f5c27
JW		 403
404 /* clear hardware rx and tx fifos */
405 nvt_clear_cir_fifo(nvt);
406 nvt_clear_tx_fifo(nvt);
407
408 /* clear any and all stray interrupts */
409 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
410
fbdc781c
JW		 411 /* and finally, enable interrupts */
412 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 413}
414
415static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
416{
3198ed16
JW		 417 /* set number of bytes needed for wake from s3 (default 65) */
418 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
419 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 420
421 /* set tolerance/variance allowed per byte during wake compare */
422 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
423 CIR_WAKE_FIFO_CMP_TOL);
424
425 /* set sample limit count (PE interrupt raised when reached) */
426 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
427 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
428
429 /* set cir wake fifo rx trigger level (currently 67) */
430 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
431 CIR_WAKE_FIFOCON);
432
433 /*
434 * Enable TX and RX, specific carrier on = low, off = high, and set
435 * sample period (currently 50us)
436 */
437 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
438 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
439 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
440 CIR_WAKE_IRCON);
441
442 /* clear cir wake rx fifo */
443 nvt_clear_cir_wake_fifo(nvt);
444
445 /* clear any and all stray interrupts */
446 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
447}
448
449static void nvt_enable_wake(struct nvt_dev *nvt)
450{
451 nvt_efm_enable(nvt);
452
453 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
454 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
6d2f5c27
JW		 455 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
456
457 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
458 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
459
460 nvt_efm_disable(nvt);
461
462 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
463 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 464 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
465 CIR_WAKE_IRCON);
6d2f5c27
JW		 466 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
467 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
468}
469
230dc94a 470#if 0 /* Currently unused */
6d2f5c27
JW		 471/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
472static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
473{
474 u32 count, carrier, duration = 0;
475 int i;
476
477 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
478 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
479
480 for (i = 0; i < nvt->pkts; i++) {
481 if (nvt->buf[i] & BUF_PULSE_BIT)
482 duration += nvt->buf[i] & BUF_LEN_MASK;
483 }
484
485 duration *= SAMPLE_PERIOD;
486
487 if (!count || !duration) {
488 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
489 count, duration);
490 return 0;
491 }
492
b4608fae 493 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 494
495 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
496 nvt_dbg("WTF? Carrier frequency out of range!");
497
498 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
499 carrier, count, duration);
500
501 return carrier;
502}
230dc94a 503#endif
6d2f5c27
JW		 504/*
505 * set carrier frequency
506 *
507 * set carrier on 2 registers: CP & CC
508 * always set CP as 0x81
509 * set CC by SPEC, CC = 3MHz/carrier - 1
510 */
d8b4b582 511static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 512{
d8b4b582 513 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 514 u16 val;
515
48cafec9
DC		 516 if (carrier == 0)
517 return -EINVAL;
518
6d2f5c27
JW		 519 nvt_cir_reg_write(nvt, 1, CIR_CP);
520 val = 3000000 / (carrier) - 1;
521 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
522
523 nvt_dbg("cp: 0x%x cc: 0x%x\n",
524 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
525
526 return 0;
527}
528
da7ee60b
AS		 529static int nvt_write_wakeup_codes(struct rc_dev *dev,
530 const u8 *wakeup_sample_buf, int count)
531{
532 int i = 0;
533 u8 reg, reg_learn_mode;
534 unsigned long flags;
535 struct nvt_dev *nvt = dev->priv;
536
537 nvt_dbg_wake("writing wakeup samples");
538
539 reg = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
540 reg_learn_mode = reg & ~CIR_WAKE_IRCON_MODE0;
541 reg_learn_mode |= CIR_WAKE_IRCON_MODE1;
542
543 /* Lock the learn area to prevent racing with wake-isr */
544 spin_lock_irqsave(&nvt->nvt_lock, flags);
545
546 /* Enable fifo writes */
547 nvt_cir_wake_reg_write(nvt, reg_learn_mode, CIR_WAKE_IRCON);
548
549 /* Clear cir wake rx fifo */
550 nvt_clear_cir_wake_fifo(nvt);
551
552 if (count > WAKE_FIFO_LEN) {
553 nvt_dbg_wake("HW FIFO too small for all wake samples");
554 count = WAKE_FIFO_LEN;
555 }
556
557 if (count)
558 pr_info("Wake samples (%d) =", count);
559 else
560 pr_info("Wake sample fifo cleared");
561
562 /* Write wake samples to fifo */
563 for (i = 0; i < count; i++) {
564 pr_cont(" %02x", wakeup_sample_buf[i]);
565 nvt_cir_wake_reg_write(nvt, wakeup_sample_buf[i],
566 CIR_WAKE_WR_FIFO_DATA);
567 }
568 pr_cont("\n");
569
570 /* Switch cir to wakeup mode and disable fifo writing */
571 nvt_cir_wake_reg_write(nvt, reg, CIR_WAKE_IRCON);
572
573 /* Set number of bytes needed for wake */
574 nvt_cir_wake_reg_write(nvt, count ? count :
575 CIR_WAKE_FIFO_CMP_BYTES,
576 CIR_WAKE_FIFO_CMP_DEEP);
577
578 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
579
580 return 0;
581}
582
583static int nvt_ir_raw_set_wakeup_filter(struct rc_dev *dev,
584 struct rc_scancode_filter *sc_filter)
585{
586 u8 *reg_buf;
587 u8 buf_val;
588 int i, ret, count;
589 unsigned int val;
590 struct ir_raw_event *raw;
591 bool complete;
592
593 /* Require both mask and data to be set before actually committing */
594 if (!sc_filter->mask || !sc_filter->data)
595 return 0;
596
597 raw = kmalloc_array(WAKE_FIFO_LEN, sizeof(*raw), GFP_KERNEL);
598 if (!raw)
599 return -ENOMEM;
600
601 ret = ir_raw_encode_scancode(dev->enabled_wakeup_protocols, sc_filter,
602 raw, WAKE_FIFO_LEN);
603 complete = (ret != -ENOBUFS);
604 if (!complete)
605 ret = WAKE_FIFO_LEN;
606 else if (ret < 0)
607 goto out_raw;
608
609 reg_buf = kmalloc_array(WAKE_FIFO_LEN, sizeof(*reg_buf), GFP_KERNEL);
610 if (!reg_buf) {
611 ret = -ENOMEM;
612 goto out_raw;
613 }
614
615 /* Inspect the ir samples */
616 for (i = 0, count = 0; i < ret && count < WAKE_FIFO_LEN; ++i) {
617 val = NS_TO_US((raw[i]).duration) / SAMPLE_PERIOD;
618
619 /* Split too large values into several smaller ones */
620 while (val > 0 && count < WAKE_FIFO_LEN) {
621
622 /* Skip last value for better comparison tolerance */
623 if (complete && i == ret - 1 && val < BUF_LEN_MASK)
624 break;
625
626 /* Clamp values to BUF_LEN_MASK at most */
627 buf_val = (val > BUF_LEN_MASK) ? BUF_LEN_MASK : val;
628
629 reg_buf[count] = buf_val;
630 val -= buf_val;
631 if ((raw[i]).pulse)
632 reg_buf[count] |= BUF_PULSE_BIT;
633 count++;
634 }
635 }
636
637 ret = nvt_write_wakeup_codes(dev, reg_buf, count);
638
639 kfree(reg_buf);
640out_raw:
641 kfree(raw);
642
643 return ret;
644}
645
646/* Dummy implementation. nuvoton is agnostic to the protocol used */
647static int nvt_ir_raw_change_wakeup_protocol(struct rc_dev *dev,
648 u64 *rc_type)
649{
650 return 0;
651}
652
6d2f5c27
JW		 653/*
654 * nvt_tx_ir
655 *
656 * 1) clean TX fifo first (handled by AP)
657 * 2) copy data from user space
658 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
659 * 4) send 9 packets to TX FIFO to open TTR
660 * in interrupt_handler:
661 * 5) send all data out
662 * go back to write():
663 * 6) disable TX interrupts, re-enable RX interupts
664 *
665 * The key problem of this function is user space data may larger than
666 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
667 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
668 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
669 * set TXFCONT as 0xff, until buf_count less than 0xff.
670 */
5588dc2b 671static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
6d2f5c27 672{
d8b4b582 673 struct nvt_dev *nvt = dev->priv;
6d2f5c27 674 unsigned long flags;
6d2f5c27
JW		 675 unsigned int i;
676 u8 iren;
677 int ret;
678
679 spin_lock_irqsave(&nvt->tx.lock, flags);
680
5588dc2b
DH		 681 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
682 nvt->tx.buf_count = (ret * sizeof(unsigned));
6d2f5c27
JW		 683
684 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
685
686 nvt->tx.cur_buf_num = 0;
687
688 /* save currently enabled interrupts */
689 iren = nvt_cir_reg_read(nvt, CIR_IREN);
690
691 /* now disable all interrupts, save TFU & TTR */
692 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
693
694 nvt->tx.tx_state = ST_TX_REPLY;
695
696 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
697 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
698
699 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
700 for (i = 0; i < 9; i++)
701 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
702
703 spin_unlock_irqrestore(&nvt->tx.lock, flags);
704
705 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
706
707 spin_lock_irqsave(&nvt->tx.lock, flags);
708 nvt->tx.tx_state = ST_TX_NONE;
709 spin_unlock_irqrestore(&nvt->tx.lock, flags);
710
711 /* restore enabled interrupts to prior state */
712 nvt_cir_reg_write(nvt, iren, CIR_IREN);
713
714 return ret;
715}
716
717/* dump contents of the last rx buffer we got from the hw rx fifo */
718static void nvt_dump_rx_buf(struct nvt_dev *nvt)
719{
720 int i;
721
4e6e29ad 722 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 723 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 724 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
725 printk(KERN_CONT "\n");
6d2f5c27
JW		 726}
727
728/*
729 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
730 * trigger decode when appropriate.
731 *
732 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
733 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
734 * (default 50us) intervals for that pulse/space. A discrete signal is
735 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
736 * to signal more IR coming (repeats) or end of IR, respectively. We store
737 * sample data in the raw event kfifo until we see 0x7<something> (except f)
738 * or 0x80, at which time, we trigger a decode operation.
739 */
740static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
741{
4651918a 742 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 743 u8 sample;
744 int i;
745
746 nvt_dbg_verbose("%s firing", __func__);
747
748 if (debug)
749 nvt_dump_rx_buf(nvt);
750
de4ed0c1 751 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
6d2f5c27 752
b7582815
JW		 753 init_ir_raw_event(&rawir);
754
de4ed0c1 755 for (i = 0; i < nvt->pkts; i++) {
6d2f5c27
JW		 756 sample = nvt->buf[i];
757
758 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 759 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
760 * SAMPLE_PERIOD);
6d2f5c27 761
de4ed0c1
JW		 762 nvt_dbg("Storing %s with duration %d",
763 rawir.pulse ? "pulse" : "space", rawir.duration);
4651918a 764
de4ed0c1 765 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
6d2f5c27
JW		 766
767 /*
768 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
769 * indicates end of IR signal, but new data incoming. In both
770 * cases, it means we're ready to call ir_raw_event_handle
771 */
de4ed0c1 772 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
b7582815 773 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 774 ir_raw_event_handle(nvt->rdev);
b7582815 775 }
6d2f5c27
JW		 776 }
777
de4ed0c1
JW		 778 nvt->pkts = 0;
779
b7582815
JW		 780 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
781 ir_raw_event_handle(nvt->rdev);
782
6d2f5c27
JW		 783 nvt_dbg_verbose("%s done", __func__);
784}
785
fbdc781c
JW		 786static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
787{
788 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
789
790 nvt->pkts = 0;
791 nvt_clear_cir_fifo(nvt);
792 ir_raw_event_reset(nvt->rdev);
793}
794
6d2f5c27
JW		 795/* copy data from hardware rx fifo into driver buffer */
796static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
797{
798 unsigned long flags;
799 u8 fifocount, val;
800 unsigned int b_idx;
fbdc781c 801 bool overrun = false;
6d2f5c27
JW		 802 int i;
803
804 /* Get count of how many bytes to read from RX FIFO */
805 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
806 /* if we get 0xff, probably means the logical dev is disabled */
807 if (fifocount == 0xff)
808 return;
fbdc781c 809 /* watch out for a fifo overrun condition */
6d2f5c27 810 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 811 overrun = true;
812 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 813 }
814
815 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
816
817 spin_lock_irqsave(&nvt->nvt_lock, flags);
818
819 b_idx = nvt->pkts;
820
821 /* This should never happen, but lets check anyway... */
822 if (b_idx + fifocount > RX_BUF_LEN) {
823 nvt_process_rx_ir_data(nvt);
824 b_idx = 0;
825 }
826
827 /* Read fifocount bytes from CIR Sample RX FIFO register */
828 for (i = 0; i < fifocount; i++) {
829 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
830 nvt->buf[b_idx + i] = val;
831 }
832
833 nvt->pkts += fifocount;
834 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
835
836 nvt_process_rx_ir_data(nvt);
837
fbdc781c
JW		 838 if (overrun)
839 nvt_handle_rx_fifo_overrun(nvt);
840
6d2f5c27
JW		 841 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
842}
843
844static void nvt_cir_log_irqs(u8 status, u8 iren)
845{
846 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
847 status, iren,
848 status & CIR_IRSTS_RDR ? " RDR" : "",
849 status & CIR_IRSTS_RTR ? " RTR" : "",
850 status & CIR_IRSTS_PE ? " PE" : "",
851 status & CIR_IRSTS_RFO ? " RFO" : "",
852 status & CIR_IRSTS_TE ? " TE" : "",
853 status & CIR_IRSTS_TTR ? " TTR" : "",
854 status & CIR_IRSTS_TFU ? " TFU" : "",
855 status & CIR_IRSTS_GH ? " GH" : "",
856 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
857 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
858 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
859}
860
861static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
862{
863 unsigned long flags;
864 bool tx_inactive;
865 u8 tx_state;
866
867 spin_lock_irqsave(&nvt->tx.lock, flags);
868 tx_state = nvt->tx.tx_state;
869 spin_unlock_irqrestore(&nvt->tx.lock, flags);
870
871 tx_inactive = (tx_state == ST_TX_NONE);
872
873 return tx_inactive;
874}
875
876/* interrupt service routine for incoming and outgoing CIR data */
877static irqreturn_t nvt_cir_isr(int irq, void *data)
878{
879 struct nvt_dev *nvt = data;
880 u8 status, iren, cur_state;
881 unsigned long flags;
882
883 nvt_dbg_verbose("%s firing", __func__);
884
885 nvt_efm_enable(nvt);
886 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
887 nvt_efm_disable(nvt);
888
889 /*
890 * Get IR Status register contents. Write 1 to ack/clear
891 *
892 * bit: reg name - description
893 * 7: CIR_IRSTS_RDR - RX Data Ready
894 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
895 * 5: CIR_IRSTS_PE - Packet End
896 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
897 * 3: CIR_IRSTS_TE - TX FIFO Empty
898 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
899 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
900 * 0: CIR_IRSTS_GH - Min Length Detected
901 */
902 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
903 if (!status) {
904 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
905 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
906 return IRQ_RETVAL(IRQ_NONE);
907 }
908
909 /* ack/clear all irq flags we've got */
910 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
911 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
912
913 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
914 iren = nvt_cir_reg_read(nvt, CIR_IREN);
915 if (!iren) {
916 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
917 return IRQ_RETVAL(IRQ_NONE);
918 }
919
920 if (debug)
921 nvt_cir_log_irqs(status, iren);
922
923 if (status & CIR_IRSTS_RTR) {
924 /* FIXME: add code for study/learn mode */
925 /* We only do rx if not tx'ing */
926 if (nvt_cir_tx_inactive(nvt))
927 nvt_get_rx_ir_data(nvt);
928 }
929
930 if (status & CIR_IRSTS_PE) {
931 if (nvt_cir_tx_inactive(nvt))
932 nvt_get_rx_ir_data(nvt);
933
934 spin_lock_irqsave(&nvt->nvt_lock, flags);
935
936 cur_state = nvt->study_state;
937
938 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
939
940 if (cur_state == ST_STUDY_NONE)
941 nvt_clear_cir_fifo(nvt);
942 }
943
944 if (status & CIR_IRSTS_TE)
945 nvt_clear_tx_fifo(nvt);
946
947 if (status & CIR_IRSTS_TTR) {
948 unsigned int pos, count;
949 u8 tmp;
950
951 spin_lock_irqsave(&nvt->tx.lock, flags);
952
953 pos = nvt->tx.cur_buf_num;
954 count = nvt->tx.buf_count;
955
956 /* Write data into the hardware tx fifo while pos < count */
957 if (pos < count) {
958 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
959 nvt->tx.cur_buf_num++;
960 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
961 } else {
962 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
963 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
964 }
965
966 spin_unlock_irqrestore(&nvt->tx.lock, flags);
967
968 }
969
970 if (status & CIR_IRSTS_TFU) {
971 spin_lock_irqsave(&nvt->tx.lock, flags);
972 if (nvt->tx.tx_state == ST_TX_REPLY) {
973 nvt->tx.tx_state = ST_TX_REQUEST;
974 wake_up(&nvt->tx.queue);
975 }
976 spin_unlock_irqrestore(&nvt->tx.lock, flags);
977 }
978
979 nvt_dbg_verbose("%s done", __func__);
980 return IRQ_RETVAL(IRQ_HANDLED);
981}
982
983/* Interrupt service routine for CIR Wake */
984static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
985{
986 u8 status, iren, val;
987 struct nvt_dev *nvt = data;
988 unsigned long flags;
989
990 nvt_dbg_wake("%s firing", __func__);
991
992 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
993 if (!status)
994 return IRQ_RETVAL(IRQ_NONE);
995
996 if (status & CIR_WAKE_IRSTS_IR_PENDING)
997 nvt_clear_cir_wake_fifo(nvt);
998
999 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
1000 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
1001
1002 /* Interrupt may be shared with CIR, bail if Wake not enabled */
1003 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
1004 if (!iren) {
1005 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
1006 return IRQ_RETVAL(IRQ_HANDLED);
1007 }
1008
1009 if ((status & CIR_WAKE_IRSTS_PE) &&
1010 (nvt->wake_state == ST_WAKE_START)) {
1011 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
1012 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
1013 nvt_dbg("setting wake up key: 0x%x", val);
1014 }
1015
1016 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
1017 spin_lock_irqsave(&nvt->nvt_lock, flags);
1018 nvt->wake_state = ST_WAKE_FINISH;
1019 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1020 }
1021
1022 nvt_dbg_wake("%s done", __func__);
1023 return IRQ_RETVAL(IRQ_HANDLED);
1024}
1025
1026static void nvt_enable_cir(struct nvt_dev *nvt)
1027{
1028 /* set function enable flags */
1029 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
1030 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
1031 CIR_IRCON);
1032
1033 nvt_efm_enable(nvt);
1034
1035 /* enable the CIR logical device */
1036 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1037 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1038
1039 nvt_efm_disable(nvt);
1040
1041 /* clear all pending interrupts */
1042 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1043
1044 /* enable interrupts */
fbdc781c 1045 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1046}
1047
1048static void nvt_disable_cir(struct nvt_dev *nvt)
1049{
1050 /* disable CIR interrupts */
1051 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1052
1053 /* clear any and all pending interrupts */
1054 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1055
1056 /* clear all function enable flags */
1057 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
1058
1059 /* clear hardware rx and tx fifos */
1060 nvt_clear_cir_fifo(nvt);
1061 nvt_clear_tx_fifo(nvt);
1062
1063 nvt_efm_enable(nvt);
1064
1065 /* disable the CIR logical device */
1066 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1067 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1068
1069 nvt_efm_disable(nvt);
1070}
1071
d8b4b582 1072static int nvt_open(struct rc_dev *dev)
6d2f5c27 1073{
d8b4b582 1074 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 1075 unsigned long flags;
1076
1077 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 1078 nvt_enable_cir(nvt);
1079 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1080
1081 return 0;
1082}
1083
d8b4b582 1084static void nvt_close(struct rc_dev *dev)
6d2f5c27 1085{
d8b4b582 1086 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 1090 nvt_disable_cir(nvt);
1091 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1092}
1093
1094/* Allocate memory, probe hardware, and initialize everything */
1095static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1096{
d8b4b582
DH		 1097 struct nvt_dev *nvt;
1098 struct rc_dev *rdev;
6d2f5c27
JW		 1099 int ret = -ENOMEM;
1100
1101 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
1102 if (!nvt)
1103 return ret;
1104
6d2f5c27 1105 /* input device for IR remote (and tx) */
d8b4b582 1106 rdev = rc_allocate_device();
6d2f5c27 1107 if (!rdev)
70ef6991 1108 goto exit_free_dev_rdev;
6d2f5c27
JW		 1109
1110 ret = -ENODEV;
c3c2077d
AS		 1111 /* activate pnp device */
1112 if (pnp_activate_dev(pdev) < 0) {
1113 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1114 goto exit_free_dev_rdev;
1115 }
1116
6d2f5c27
JW		 1117 /* validate pnp resources */
1118 if (!pnp_port_valid(pdev, 0) ||
1119 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1120 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991 1121 goto exit_free_dev_rdev;
6d2f5c27
JW		 1122 }
1123
1124 if (!pnp_irq_valid(pdev, 0)) {
1125 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
70ef6991 1126 goto exit_free_dev_rdev;
6d2f5c27
JW		 1127 }
1128
1129 if (!pnp_port_valid(pdev, 1) ||
1130 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1131 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
70ef6991 1132 goto exit_free_dev_rdev;
6d2f5c27
JW		 1133 }
1134
1135 nvt->cir_addr = pnp_port_start(pdev, 0);
1136 nvt->cir_irq = pnp_irq(pdev, 0);
1137
1138 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1139 /* irq is always shared between cir and cir wake */
1140 nvt->cir_wake_irq = nvt->cir_irq;
1141
1142 nvt->cr_efir = CR_EFIR;
1143 nvt->cr_efdr = CR_EFDR;
1144
1145 spin_lock_init(&nvt->nvt_lock);
1146 spin_lock_init(&nvt->tx.lock);
1147
6d2f5c27
JW		 1148 pnp_set_drvdata(pdev, nvt);
1149 nvt->pdev = pdev;
1150
1151 init_waitqueue_head(&nvt->tx.queue);
1152
1153 ret = nvt_hw_detect(nvt);
1154 if (ret)
70ef6991 1155 goto exit_free_dev_rdev;
6d2f5c27
JW		 1156
1157 /* Initialize CIR & CIR Wake Logical Devices */
1158 nvt_efm_enable(nvt);
1159 nvt_cir_ldev_init(nvt);
1160 nvt_cir_wake_ldev_init(nvt);
1161 nvt_efm_disable(nvt);
1162
1163 /* Initialize CIR & CIR Wake Config Registers */
1164 nvt_cir_regs_init(nvt);
1165 nvt_cir_wake_regs_init(nvt);
1166
d8b4b582
DH		 1167 /* Set up the rc device */
1168 rdev->priv = nvt;
1169 rdev->driver_type = RC_DRIVER_IR_RAW;
da7ee60b 1170 rdev->encode_wakeup = true;
c5540fbb 1171 rdev->allowed_protocols = RC_BIT_ALL;
d8b4b582
DH		 1172 rdev->open = nvt_open;
1173 rdev->close = nvt_close;
1174 rdev->tx_ir = nvt_tx_ir;
1175 rdev->s_tx_carrier = nvt_set_tx_carrier;
da7ee60b
AS		 1176 rdev->s_wakeup_filter = nvt_ir_raw_set_wakeup_filter;
1177 rdev->change_wakeup_protocol = nvt_ir_raw_change_wakeup_protocol;
d8b4b582 1178 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
46872d27 1179 rdev->input_phys = "nuvoton/cir0";
d8b4b582
DH		 1180 rdev->input_id.bustype = BUS_HOST;
1181 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1182 rdev->input_id.product = nvt->chip_major;
1183 rdev->input_id.version = nvt->chip_minor;
46872d27 1184 rdev->dev.parent = &pdev->dev;
d8b4b582
DH		 1185 rdev->driver_name = NVT_DRIVER_NAME;
1186 rdev->map_name = RC_MAP_RC6_MCE;
d7b290a1 1187 rdev->timeout = MS_TO_NS(100);
46872d27
JW		 1188 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1189 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
6d2f5c27 1190#if 0
d8b4b582
DH		 1191 rdev->min_timeout = XYZ;
1192 rdev->max_timeout = XYZ;
6d2f5c27 1193 /* tx bits */
d8b4b582 1194 rdev->tx_resolution = XYZ;
6d2f5c27 1195#endif
d62b6818 1196 nvt->rdev = rdev;
6d2f5c27 1197
9fa35204
MK		 1198 ret = rc_register_device(rdev);
1199 if (ret)
1200 goto exit_free_dev_rdev;
1201
9ef449c6
LH		 1202 ret = -EBUSY;
1203 /* now claim resources */
1204 if (!request_region(nvt->cir_addr,
1205 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
9fa35204 1206 goto exit_unregister_device;
9ef449c6
LH		 1207
1208 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1209 NVT_DRIVER_NAME, (void *)nvt))
70ef6991 1210 goto exit_release_cir_addr;
9ef449c6
LH		 1211
1212 if (!request_region(nvt->cir_wake_addr,
1213 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
70ef6991 1214 goto exit_free_irq;
9ef449c6
LH		 1215
1216 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1217 NVT_DRIVER_NAME, (void *)nvt))
70ef6991 1218 goto exit_release_cir_wake_addr;
9ef449c6 1219
46872d27 1220 device_init_wakeup(&pdev->dev, true);
d62b6818 1221
6d2f5c27
JW		 1222 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1223 if (debug) {
1224 cir_dump_regs(nvt);
1225 cir_wake_dump_regs(nvt);
1226 }
1227
1228 return 0;
1229
70ef6991 1230exit_release_cir_wake_addr:
f27b853e 1231 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
70ef6991 1232exit_free_irq:
f27b853e 1233 free_irq(nvt->cir_irq, nvt);
70ef6991 1234exit_release_cir_addr:
f27b853e 1235 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
9fa35204
MK		 1236exit_unregister_device:
1237 rc_unregister_device(rdev);
f73e1851 1238 rdev = NULL;
70ef6991 1239exit_free_dev_rdev:
d8b4b582 1240 rc_free_device(rdev);
6d2f5c27
JW		 1241 kfree(nvt);
1242
1243 return ret;
1244}
1245
4c62e976 1246static void nvt_remove(struct pnp_dev *pdev)
6d2f5c27
JW		 1247{
1248 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1249 unsigned long flags;
1250
1251 spin_lock_irqsave(&nvt->nvt_lock, flags);
1252 /* disable CIR */
1253 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1254 nvt_disable_cir(nvt);
1255 /* enable CIR Wake (for IR power-on) */
1256 nvt_enable_wake(nvt);
1257 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1258
1259 /* free resources */
1260 free_irq(nvt->cir_irq, nvt);
1261 free_irq(nvt->cir_wake_irq, nvt);
1262 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1263 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1264
d8b4b582 1265 rc_unregister_device(nvt->rdev);
6d2f5c27 1266
6d2f5c27
JW		 1267 kfree(nvt);
1268}
1269
1270static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1271{
1272 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1273 unsigned long flags;
1274
1275 nvt_dbg("%s called", __func__);
1276
1277 /* zero out misc state tracking */
1278 spin_lock_irqsave(&nvt->nvt_lock, flags);
1279 nvt->study_state = ST_STUDY_NONE;
1280 nvt->wake_state = ST_WAKE_NONE;
1281 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1282
1283 spin_lock_irqsave(&nvt->tx.lock, flags);
1284 nvt->tx.tx_state = ST_TX_NONE;
1285 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1286
1287 /* disable all CIR interrupts */
1288 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1289
1290 nvt_efm_enable(nvt);
1291
1292 /* disable cir logical dev */
1293 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1294 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1295
1296 nvt_efm_disable(nvt);
1297
1298 /* make sure wake is enabled */
1299 nvt_enable_wake(nvt);
1300
1301 return 0;
1302}
1303
1304static int nvt_resume(struct pnp_dev *pdev)
1305{
6d2f5c27
JW		 1306 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1307
1308 nvt_dbg("%s called", __func__);
1309
1310 /* open interrupt */
fbdc781c 1311 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1312
1313 /* Enable CIR logical device */
1314 nvt_efm_enable(nvt);
1315 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1316 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1317
1318 nvt_efm_disable(nvt);
1319
1320 nvt_cir_regs_init(nvt);
1321 nvt_cir_wake_regs_init(nvt);
1322
f2747cf6 1323 return 0;
6d2f5c27
JW		 1324}
1325
1326static void nvt_shutdown(struct pnp_dev *pdev)
1327{
1328 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1329 nvt_enable_wake(nvt);
1330}
1331
1332static const struct pnp_device_id nvt_ids[] = {
1333 { "WEC0530", 0 }, /* CIR */
1334 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1335 { "", 0 },
1336};
1337
1338static struct pnp_driver nvt_driver = {
1339 .name = NVT_DRIVER_NAME,
1340 .id_table = nvt_ids,
1341 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1342 .probe = nvt_probe,
4c62e976 1343 .remove = nvt_remove,
6d2f5c27
JW		 1344 .suspend = nvt_suspend,
1345 .resume = nvt_resume,
1346 .shutdown = nvt_shutdown,
1347};
1348
6d2f5c27
JW		 1349module_param(debug, int, S_IRUGO | S_IWUSR);
1350MODULE_PARM_DESC(debug, "Enable debugging output");
1351
1352MODULE_DEVICE_TABLE(pnp, nvt_ids);
1353MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1354
1355MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1356MODULE_LICENSE("GPL");
1357
af638a04 1358module_pnp_driver(nvt_driver);
Linux 6.x block layer and io_uring tree(s)