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9390467c | 1 | // SPDX-License-Identifier: GPL-2.0 |
12ddbadf BG |
2 | /* |
3 | * Driver for Amlogic Meson IR remote receiver | |
4 | * | |
5 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
12ddbadf BG |
6 | */ |
7 | ||
8 | #include <linux/device.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of_platform.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/spinlock.h> | |
e7a937b5 | 16 | #include <linux/bitfield.h> |
12ddbadf BG |
17 | |
18 | #include <media/rc-core.h> | |
19 | ||
20 | #define DRIVER_NAME "meson-ir" | |
21 | ||
6edf27ee | 22 | /* valid on all Meson platforms */ |
12ddbadf BG |
23 | #define IR_DEC_LDR_ACTIVE 0x00 |
24 | #define IR_DEC_LDR_IDLE 0x04 | |
25 | #define IR_DEC_LDR_REPEAT 0x08 | |
26 | #define IR_DEC_BIT_0 0x0c | |
27 | #define IR_DEC_REG0 0x10 | |
28 | #define IR_DEC_FRAME 0x14 | |
29 | #define IR_DEC_STATUS 0x18 | |
30 | #define IR_DEC_REG1 0x1c | |
6edf27ee NA |
31 | /* only available on Meson 8b and newer */ |
32 | #define IR_DEC_REG2 0x20 | |
12ddbadf | 33 | |
e7a937b5 | 34 | #define REG0_RATE_MASK GENMASK(11, 0) |
12ddbadf | 35 | |
6edf27ee NA |
36 | #define DECODE_MODE_NEC 0x0 |
37 | #define DECODE_MODE_RAW 0x2 | |
38 | ||
39 | /* Meson 6b uses REG1 to configure the mode */ | |
40 | #define REG1_MODE_MASK GENMASK(8, 7) | |
41 | #define REG1_MODE_SHIFT 7 | |
42 | ||
43 | /* Meson 8b / GXBB use REG2 to configure the mode */ | |
44 | #define REG2_MODE_MASK GENMASK(3, 0) | |
45 | #define REG2_MODE_SHIFT 0 | |
12ddbadf | 46 | |
e7a937b5 | 47 | #define REG1_TIME_IV_MASK GENMASK(28, 16) |
12ddbadf | 48 | |
e7a937b5 HK |
49 | #define REG1_IRQSEL_MASK GENMASK(3, 2) |
50 | #define REG1_IRQSEL_NEC_MODE 0 | |
51 | #define REG1_IRQSEL_RISE_FALL 1 | |
52 | #define REG1_IRQSEL_FALL 2 | |
53 | #define REG1_IRQSEL_RISE 3 | |
12ddbadf BG |
54 | |
55 | #define REG1_RESET BIT(0) | |
56 | #define REG1_ENABLE BIT(15) | |
57 | ||
58 | #define STATUS_IR_DEC_IN BIT(8) | |
59 | ||
60 | #define MESON_TRATE 10 /* us */ | |
61 | ||
62 | struct meson_ir { | |
63 | void __iomem *reg; | |
64 | struct rc_dev *rc; | |
12ddbadf BG |
65 | spinlock_t lock; |
66 | }; | |
67 | ||
68 | static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg, | |
69 | u32 mask, u32 value) | |
70 | { | |
71 | u32 data; | |
72 | ||
73 | data = readl(ir->reg + reg); | |
74 | data &= ~mask; | |
75 | data |= (value & mask); | |
76 | writel(data, ir->reg + reg); | |
77 | } | |
78 | ||
79 | static irqreturn_t meson_ir_irq(int irqno, void *dev_id) | |
80 | { | |
81 | struct meson_ir *ir = dev_id; | |
137edc02 | 82 | u32 duration, status; |
183e19f5 | 83 | struct ir_raw_event rawir = {}; |
12ddbadf BG |
84 | |
85 | spin_lock(&ir->lock); | |
86 | ||
137edc02 | 87 | duration = readl_relaxed(ir->reg + IR_DEC_REG1); |
e7a937b5 | 88 | duration = FIELD_GET(REG1_TIME_IV_MASK, duration); |
12ddbadf BG |
89 | rawir.duration = US_TO_NS(duration * MESON_TRATE); |
90 | ||
137edc02 HK |
91 | status = readl_relaxed(ir->reg + IR_DEC_STATUS); |
92 | rawir.pulse = !!(status & STATUS_IR_DEC_IN); | |
12ddbadf | 93 | |
8d7a77ce | 94 | ir_raw_event_store_with_timeout(ir->rc, &rawir); |
12ddbadf BG |
95 | |
96 | spin_unlock(&ir->lock); | |
97 | ||
98 | return IRQ_HANDLED; | |
99 | } | |
100 | ||
101 | static int meson_ir_probe(struct platform_device *pdev) | |
102 | { | |
103 | struct device *dev = &pdev->dev; | |
104 | struct device_node *node = dev->of_node; | |
105 | struct resource *res; | |
106 | const char *map_name; | |
107 | struct meson_ir *ir; | |
1ffc931c | 108 | int irq, ret; |
12ddbadf BG |
109 | |
110 | ir = devm_kzalloc(dev, sizeof(struct meson_ir), GFP_KERNEL); | |
111 | if (!ir) | |
112 | return -ENOMEM; | |
113 | ||
114 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
115 | ir->reg = devm_ioremap_resource(dev, res); | |
9e2e4382 | 116 | if (IS_ERR(ir->reg)) |
12ddbadf | 117 | return PTR_ERR(ir->reg); |
12ddbadf | 118 | |
1ffc931c HK |
119 | irq = platform_get_irq(pdev, 0); |
120 | if (irq < 0) { | |
12ddbadf | 121 | dev_err(dev, "no irq resource\n"); |
1ffc931c | 122 | return irq; |
12ddbadf BG |
123 | } |
124 | ||
705aa578 | 125 | ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); |
12ddbadf BG |
126 | if (!ir->rc) { |
127 | dev_err(dev, "failed to allocate rc device\n"); | |
128 | return -ENOMEM; | |
129 | } | |
130 | ||
131 | ir->rc->priv = ir; | |
518f4b26 | 132 | ir->rc->device_name = DRIVER_NAME; |
12ddbadf BG |
133 | ir->rc->input_phys = DRIVER_NAME "/input0"; |
134 | ir->rc->input_id.bustype = BUS_HOST; | |
135 | map_name = of_get_property(node, "linux,rc-map-name", NULL); | |
136 | ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY; | |
6d741bfe | 137 | ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
12ddbadf | 138 | ir->rc->rx_resolution = US_TO_NS(MESON_TRATE); |
b358e747 SY |
139 | ir->rc->min_timeout = 1; |
140 | ir->rc->timeout = IR_DEFAULT_TIMEOUT; | |
141 | ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT; | |
12ddbadf BG |
142 | ir->rc->driver_name = DRIVER_NAME; |
143 | ||
144 | spin_lock_init(&ir->lock); | |
145 | platform_set_drvdata(pdev, ir); | |
146 | ||
705aa578 | 147 | ret = devm_rc_register_device(dev, ir->rc); |
12ddbadf BG |
148 | if (ret) { |
149 | dev_err(dev, "failed to register rc device\n"); | |
705aa578 | 150 | return ret; |
12ddbadf BG |
151 | } |
152 | ||
611ee552 | 153 | ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir); |
12ddbadf BG |
154 | if (ret) { |
155 | dev_err(dev, "failed to request irq\n"); | |
705aa578 | 156 | return ret; |
12ddbadf BG |
157 | } |
158 | ||
159 | /* Reset the decoder */ | |
160 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET); | |
161 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0); | |
6edf27ee NA |
162 | |
163 | /* Set general operation mode (= raw/software decoding) */ | |
164 | if (of_device_is_compatible(node, "amlogic,meson6-ir")) | |
165 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, | |
e7a937b5 | 166 | FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW)); |
6edf27ee NA |
167 | else |
168 | meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK, | |
e7a937b5 | 169 | FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW)); |
6edf27ee | 170 | |
12ddbadf BG |
171 | /* Set rate */ |
172 | meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1); | |
173 | /* IRQ on rising and falling edges */ | |
174 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK, | |
e7a937b5 | 175 | FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL)); |
12ddbadf BG |
176 | /* Enable the decoder */ |
177 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE); | |
178 | ||
179 | dev_info(dev, "receiver initialized\n"); | |
180 | ||
181 | return 0; | |
12ddbadf BG |
182 | } |
183 | ||
184 | static int meson_ir_remove(struct platform_device *pdev) | |
185 | { | |
186 | struct meson_ir *ir = platform_get_drvdata(pdev); | |
187 | unsigned long flags; | |
188 | ||
189 | /* Disable the decoder */ | |
190 | spin_lock_irqsave(&ir->lock, flags); | |
191 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0); | |
192 | spin_unlock_irqrestore(&ir->lock, flags); | |
193 | ||
12ddbadf BG |
194 | return 0; |
195 | } | |
196 | ||
2aa1bd1c AD |
197 | static void meson_ir_shutdown(struct platform_device *pdev) |
198 | { | |
199 | struct device *dev = &pdev->dev; | |
200 | struct device_node *node = dev->of_node; | |
201 | struct meson_ir *ir = platform_get_drvdata(pdev); | |
202 | unsigned long flags; | |
203 | ||
204 | spin_lock_irqsave(&ir->lock, flags); | |
205 | ||
206 | /* | |
207 | * Set operation mode to NEC/hardware decoding to give | |
208 | * bootloader a chance to power the system back on | |
209 | */ | |
210 | if (of_device_is_compatible(node, "amlogic,meson6-ir")) | |
211 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, | |
212 | DECODE_MODE_NEC << REG1_MODE_SHIFT); | |
213 | else | |
214 | meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK, | |
215 | DECODE_MODE_NEC << REG2_MODE_SHIFT); | |
216 | ||
217 | /* Set rate to default value */ | |
218 | meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13); | |
219 | ||
220 | spin_unlock_irqrestore(&ir->lock, flags); | |
221 | } | |
222 | ||
12ddbadf BG |
223 | static const struct of_device_id meson_ir_match[] = { |
224 | { .compatible = "amlogic,meson6-ir" }, | |
6edf27ee NA |
225 | { .compatible = "amlogic,meson8b-ir" }, |
226 | { .compatible = "amlogic,meson-gxbb-ir" }, | |
12ddbadf BG |
227 | { }, |
228 | }; | |
5bb50fe7 | 229 | MODULE_DEVICE_TABLE(of, meson_ir_match); |
12ddbadf BG |
230 | |
231 | static struct platform_driver meson_ir_driver = { | |
232 | .probe = meson_ir_probe, | |
233 | .remove = meson_ir_remove, | |
2aa1bd1c | 234 | .shutdown = meson_ir_shutdown, |
12ddbadf BG |
235 | .driver = { |
236 | .name = DRIVER_NAME, | |
237 | .of_match_table = meson_ir_match, | |
238 | }, | |
239 | }; | |
240 | ||
241 | module_platform_driver(meson_ir_driver); | |
242 | ||
243 | MODULE_DESCRIPTION("Amlogic Meson IR remote receiver driver"); | |
244 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); | |
245 | MODULE_LICENSE("GPL v2"); |