[linux-2.6-block.git] / drivers / media / rc / fintek-cir.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
 *
 * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
 *
 * Special thanks to Fintek for providing hardware and spec sheets.
 * This driver is based upon the nuvoton, ite and ene drivers for
 * similar hardware.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pnp.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <media/rc-core.h>

#include "fintek-cir.h"

/* write val to config reg */
static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg)
{
	fit_dbg("%s: reg 0x%02x, val 0x%02x  (ip/dp: %02x/%02x)",
		__func__, reg, val, fintek->cr_ip, fintek->cr_dp);
	outb(reg, fintek->cr_ip);
	outb(val, fintek->cr_dp);
}

/* read val from config reg */
static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg)
{
	u8 val;

	outb(reg, fintek->cr_ip);
	val = inb(fintek->cr_dp);

	fit_dbg("%s: reg 0x%02x, val 0x%02x  (ip/dp: %02x/%02x)",
		__func__, reg, val, fintek->cr_ip, fintek->cr_dp);
	return val;
}

/* update config register bit without changing other bits */
static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
{
	u8 tmp = fintek_cr_read(fintek, reg) | val;
	fintek_cr_write(fintek, tmp, reg);
}

/* clear config register bit without changing other bits */
static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
{
	u8 tmp = fintek_cr_read(fintek, reg) & ~val;
	fintek_cr_write(fintek, tmp, reg);
}

/* enter config mode */
static inline void fintek_config_mode_enable(struct fintek_dev *fintek)
{
	/* Enabling Config Mode explicitly requires writing 2x */
	outb(CONFIG_REG_ENABLE, fintek->cr_ip);
	outb(CONFIG_REG_ENABLE, fintek->cr_ip);
}

/* exit config mode */
static inline void fintek_config_mode_disable(struct fintek_dev *fintek)
{
	outb(CONFIG_REG_DISABLE, fintek->cr_ip);
}

/*
 * When you want to address a specific logical device, write its logical
 * device number to GCR_LOGICAL_DEV_NO
 */
static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev)
{
	fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO);
}

/* write val to cir config register */
static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset)
{
	outb(val, fintek->cir_addr + offset);
}

/* read val from cir config register */
static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
{
	return inb(fintek->cir_addr + offset);
}

/* dump current cir register contents */
static void cir_dump_regs(struct fintek_dev *fintek)
{
	fintek_config_mode_enable(fintek);
	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);

	pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
	pr_info(" * CR CIR BASE ADDR: 0x%x\n",
		(fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
		fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
	pr_info(" * CR CIR IRQ NUM:   0x%x\n",
		fintek_cr_read(fintek, CIR_CR_IRQ_SEL));

	fintek_config_mode_disable(fintek);

	pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
	pr_info(" * STATUS:     0x%x\n",
		fintek_cir_reg_read(fintek, CIR_STATUS));
	pr_info(" * CONTROL:    0x%x\n",
		fintek_cir_reg_read(fintek, CIR_CONTROL));
	pr_info(" * RX_DATA:    0x%x\n",
		fintek_cir_reg_read(fintek, CIR_RX_DATA));
	pr_info(" * TX_CONTROL: 0x%x\n",
		fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
	pr_info(" * TX_DATA:    0x%x\n",
		fintek_cir_reg_read(fintek, CIR_TX_DATA));
}

/* detect hardware features */
static int fintek_hw_detect(struct fintek_dev *fintek)
{
	unsigned long flags;
	u8 chip_major, chip_minor;
	u8 vendor_major, vendor_minor;
	u8 portsel, ir_class;
	u16 vendor, chip;

	fintek_config_mode_enable(fintek);

	/* Check if we're using config port 0x4e or 0x2e */
	portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
	if (portsel == 0xff) {
		fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
		fintek_config_mode_disable(fintek);
		fintek->cr_ip = CR_INDEX_PORT2;
		fintek->cr_dp = CR_DATA_PORT2;
		fintek_config_mode_enable(fintek);
		portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
	}
	fit_dbg("portsel reg: 0x%02x", portsel);

	ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
	fit_dbg("ir_class reg: 0x%02x", ir_class);

	switch (ir_class) {
	case CLASS_RX_2TX:
	case CLASS_RX_1TX:
		fintek->hw_tx_capable = true;
		break;
	case CLASS_RX_ONLY:
	default:
		fintek->hw_tx_capable = false;
		break;
	}

	chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
	chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
	chip  = chip_major << 8 | chip_minor;

	vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
	vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
	vendor = vendor_major << 8 | vendor_minor;

	if (vendor != VENDOR_ID_FINTEK)
		fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
	else
		fit_dbg("Read Fintek vendor ID from chip");

	fintek_config_mode_disable(fintek);

	spin_lock_irqsave(&fintek->fintek_lock, flags);
	fintek->chip_major  = chip_major;
	fintek->chip_minor  = chip_minor;
	fintek->chip_vendor = vendor;

	/*
	 * Newer reviews of this chipset uses port 8 instead of 5
	 */
	if ((chip != 0x0408) && (chip != 0x0804))
		fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2;
	else
		fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1;

	spin_unlock_irqrestore(&fintek->fintek_lock, flags);

	return 0;
}

static void fintek_cir_ldev_init(struct fintek_dev *fintek)
{
	/* Select CIR logical device and enable */
	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
	fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);

	/* Write allocated CIR address and IRQ information to hardware */
	fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI);
	fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO);

	fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL);

	fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)",
		fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len);
}

/* enable CIR interrupts */
static void fintek_enable_cir_irq(struct fintek_dev *fintek)
{
	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
}

static void fintek_cir_regs_init(struct fintek_dev *fintek)
{
	/* clear any and all stray interrupts */
	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);

	/* and finally, enable interrupts */
	fintek_enable_cir_irq(fintek);
}

static void fintek_enable_wake(struct fintek_dev *fintek)
{
	fintek_config_mode_enable(fintek);
	fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI);

	/* Allow CIR PME's to wake system */
	fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG);
	/* Enable CIR PME's */
	fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG);
	/* Clear CIR PME status register */
	fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG);
	/* Save state */
	fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG);

	fintek_config_mode_disable(fintek);
}

static int fintek_cmdsize(u8 cmd, u8 subcmd)
{
	int datasize = 0;

	switch (cmd) {
	case BUF_COMMAND_NULL:
		if (subcmd == BUF_HW_CMD_HEADER)
			datasize = 1;
		break;
	case BUF_HW_CMD_HEADER:
		if (subcmd == BUF_CMD_G_REVISION)
			datasize = 2;
		break;
	case BUF_COMMAND_HEADER:
		switch (subcmd) {
		case BUF_CMD_S_CARRIER:
		case BUF_CMD_S_TIMEOUT:
		case BUF_RSP_PULSE_COUNT:
			datasize = 2;
			break;
		case BUF_CMD_SIG_END:
		case BUF_CMD_S_TXMASK:
		case BUF_CMD_S_RXSENSOR:
			datasize = 1;
			break;
		}
	}

	return datasize;
}

/* process ir data stored in driver buffer */
static void fintek_process_rx_ir_data(struct fintek_dev *fintek)
{
	struct ir_raw_event rawir = {};
	u8 sample;
	bool event = false;
	int i;

	for (i = 0; i < fintek->pkts; i++) {
		sample = fintek->buf[i];
		switch (fintek->parser_state) {
		case CMD_HEADER:
			fintek->cmd = sample;
			if ((fintek->cmd == BUF_COMMAND_HEADER) ||
			    ((fintek->cmd & BUF_COMMAND_MASK) !=
			     BUF_PULSE_BIT)) {
				fintek->parser_state = SUBCMD;
				continue;
			}
			fintek->rem = (fintek->cmd & BUF_LEN_MASK);
			fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem);
			if (fintek->rem)
				fintek->parser_state = PARSE_IRDATA;
			else
				ir_raw_event_reset(fintek->rdev);
			break;
		case SUBCMD:
			fintek->rem = fintek_cmdsize(fintek->cmd, sample);
			fintek->parser_state = CMD_DATA;
			break;
		case CMD_DATA:
			fintek->rem--;
			break;
		case PARSE_IRDATA:
			fintek->rem--;
			rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
			rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK)
					  * CIR_SAMPLE_PERIOD);

			fit_dbg("Storing %s with duration %d",
				rawir.pulse ? "pulse" : "space",
				rawir.duration);
			if (ir_raw_event_store_with_filter(fintek->rdev,
									&rawir))
				event = true;
			break;
		}

		if ((fintek->parser_state != CMD_HEADER) && !fintek->rem)
			fintek->parser_state = CMD_HEADER;
	}

	fintek->pkts = 0;

	if (event) {
		fit_dbg("Calling ir_raw_event_handle");
		ir_raw_event_handle(fintek->rdev);
	}
}

/* copy data from hardware rx register into driver buffer */
static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs)
{
	unsigned long flags;
	u8 sample, status;

	spin_lock_irqsave(&fintek->fintek_lock, flags);

	/*
	 * We must read data from CIR_RX_DATA until the hardware IR buffer
	 * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in
	 * the CIR_STATUS register
	 */
	do {
		sample = fintek_cir_reg_read(fintek, CIR_RX_DATA);
		fit_dbg("%s: sample: 0x%02x", __func__, sample);

		fintek->buf[fintek->pkts] = sample;
		fintek->pkts++;

		status = fintek_cir_reg_read(fintek, CIR_STATUS);
		if (!(status & CIR_STATUS_IRQ_EN))
			break;
	} while (status & rx_irqs);

	fintek_process_rx_ir_data(fintek);

	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
}

static void fintek_cir_log_irqs(u8 status)
{
	fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status,
		status & CIR_STATUS_IRQ_EN	? " IRQEN"	: "",
		status & CIR_STATUS_TX_FINISH	? " TXF"	: "",
		status & CIR_STATUS_TX_UNDERRUN	? " TXU"	: "",
		status & CIR_STATUS_RX_TIMEOUT	? " RXTO"	: "",
		status & CIR_STATUS_RX_RECEIVE	? " RXOK"	: "");
}

/* interrupt service routine for incoming and outgoing CIR data */
static irqreturn_t fintek_cir_isr(int irq, void *data)
{
	struct fintek_dev *fintek = data;
	u8 status, rx_irqs;

	fit_dbg_verbose("%s firing", __func__);

	fintek_config_mode_enable(fintek);
	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
	fintek_config_mode_disable(fintek);

	/*
	 * Get IR Status register contents. Write 1 to ack/clear
	 *
	 * bit: reg name    - description
	 *   3: TX_FINISH   - TX is finished
	 *   2: TX_UNDERRUN - TX underrun
	 *   1: RX_TIMEOUT  - RX data timeout
	 *   0: RX_RECEIVE  - RX data received
	 */
	status = fintek_cir_reg_read(fintek, CIR_STATUS);
	if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) {
		fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status);
		fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
		return IRQ_RETVAL(IRQ_NONE);
	}

	if (debug)
		fintek_cir_log_irqs(status);

	rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT);
	if (rx_irqs)
		fintek_get_rx_ir_data(fintek, rx_irqs);

	/* ack/clear all irq flags we've got */
	fintek_cir_reg_write(fintek, status, CIR_STATUS);

	fit_dbg_verbose("%s done", __func__);
	return IRQ_RETVAL(IRQ_HANDLED);
}

static void fintek_enable_cir(struct fintek_dev *fintek)
{
	/* set IRQ enabled */
	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);

	fintek_config_mode_enable(fintek);

	/* enable the CIR logical device */
	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
	fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);

	fintek_config_mode_disable(fintek);

	/* clear all pending interrupts */
	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);

	/* enable interrupts */
	fintek_enable_cir_irq(fintek);
}

static void fintek_disable_cir(struct fintek_dev *fintek)
{
	fintek_config_mode_enable(fintek);

	/* disable the CIR logical device */
	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
	fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);

	fintek_config_mode_disable(fintek);
}

static int fintek_open(struct rc_dev *dev)
{
	struct fintek_dev *fintek = dev->priv;
	unsigned long flags;

	spin_lock_irqsave(&fintek->fintek_lock, flags);
	fintek_enable_cir(fintek);
	spin_unlock_irqrestore(&fintek->fintek_lock, flags);

	return 0;
}

static void fintek_close(struct rc_dev *dev)
{
	struct fintek_dev *fintek = dev->priv;
	unsigned long flags;

	spin_lock_irqsave(&fintek->fintek_lock, flags);
	fintek_disable_cir(fintek);
	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
}

/* Allocate memory, probe hardware, and initialize everything */
static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
{
	struct fintek_dev *fintek;
	struct rc_dev *rdev;
	int ret = -ENOMEM;

	fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL);
	if (!fintek)
		return ret;

	/* input device for IR remote (and tx) */
	rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
	if (!rdev)
		goto exit_free_dev_rdev;

	ret = -ENODEV;
	/* validate pnp resources */
	if (!pnp_port_valid(pdev, 0)) {
		dev_err(&pdev->dev, "IR PNP Port not valid!\n");
		goto exit_free_dev_rdev;
	}

	if (!pnp_irq_valid(pdev, 0)) {
		dev_err(&pdev->dev, "IR PNP IRQ not valid!\n");
		goto exit_free_dev_rdev;
	}

	fintek->cir_addr = pnp_port_start(pdev, 0);
	fintek->cir_irq  = pnp_irq(pdev, 0);
	fintek->cir_port_len = pnp_port_len(pdev, 0);

	fintek->cr_ip = CR_INDEX_PORT;
	fintek->cr_dp = CR_DATA_PORT;

	spin_lock_init(&fintek->fintek_lock);

	pnp_set_drvdata(pdev, fintek);
	fintek->pdev = pdev;

	ret = fintek_hw_detect(fintek);
	if (ret)
		goto exit_free_dev_rdev;

	/* Initialize CIR & CIR Wake Logical Devices */
	fintek_config_mode_enable(fintek);
	fintek_cir_ldev_init(fintek);
	fintek_config_mode_disable(fintek);

	/* Initialize CIR & CIR Wake Config Registers */
	fintek_cir_regs_init(fintek);

	/* Set up the rc device */
	rdev->priv = fintek;
	rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
	rdev->open = fintek_open;
	rdev->close = fintek_close;
	rdev->device_name = FINTEK_DESCRIPTION;
	rdev->input_phys = "fintek/cir0";
	rdev->input_id.bustype = BUS_HOST;
	rdev->input_id.vendor = VENDOR_ID_FINTEK;
	rdev->input_id.product = fintek->chip_major;
	rdev->input_id.version = fintek->chip_minor;
	rdev->dev.parent = &pdev->dev;
	rdev->driver_name = FINTEK_DRIVER_NAME;
	rdev->map_name = RC_MAP_RC6_MCE;
	rdev->timeout = US_TO_NS(1000);
	/* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
	rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);

	fintek->rdev = rdev;

	ret = -EBUSY;
	/* now claim resources */
	if (!request_region(fintek->cir_addr,
			    fintek->cir_port_len, FINTEK_DRIVER_NAME))
		goto exit_free_dev_rdev;

	if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED,
			FINTEK_DRIVER_NAME, (void *)fintek))
		goto exit_free_cir_addr;

	ret = rc_register_device(rdev);
	if (ret)
		goto exit_free_irq;

	device_init_wakeup(&pdev->dev, true);

	fit_pr(KERN_NOTICE, "driver has been successfully loaded\n");
	if (debug)
		cir_dump_regs(fintek);

	return 0;

exit_free_irq:
	free_irq(fintek->cir_irq, fintek);
exit_free_cir_addr:
	release_region(fintek->cir_addr, fintek->cir_port_len);
exit_free_dev_rdev:
	rc_free_device(rdev);
	kfree(fintek);

	return ret;
}

static void fintek_remove(struct pnp_dev *pdev)
{
	struct fintek_dev *fintek = pnp_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&fintek->fintek_lock, flags);
	/* disable CIR */
	fintek_disable_cir(fintek);
	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
	/* enable CIR Wake (for IR power-on) */
	fintek_enable_wake(fintek);
	spin_unlock_irqrestore(&fintek->fintek_lock, flags);

	/* free resources */
	free_irq(fintek->cir_irq, fintek);
	release_region(fintek->cir_addr, fintek->cir_port_len);

	rc_unregister_device(fintek->rdev);

	kfree(fintek);
}

static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state)
{
	struct fintek_dev *fintek = pnp_get_drvdata(pdev);
	unsigned long flags;

	fit_dbg("%s called", __func__);

	spin_lock_irqsave(&fintek->fintek_lock, flags);

	/* disable all CIR interrupts */
	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);

	spin_unlock_irqrestore(&fintek->fintek_lock, flags);

	fintek_config_mode_enable(fintek);

	/* disable cir logical dev */
	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
	fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);

	fintek_config_mode_disable(fintek);

	/* make sure wake is enabled */
	fintek_enable_wake(fintek);

	return 0;
}

static int fintek_resume(struct pnp_dev *pdev)
{
	struct fintek_dev *fintek = pnp_get_drvdata(pdev);

	fit_dbg("%s called", __func__);

	/* open interrupt */
	fintek_enable_cir_irq(fintek);

	/* Enable CIR logical device */
	fintek_config_mode_enable(fintek);
	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
	fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);

	fintek_config_mode_disable(fintek);

	fintek_cir_regs_init(fintek);

	return 0;
}

static void fintek_shutdown(struct pnp_dev *pdev)
{
	struct fintek_dev *fintek = pnp_get_drvdata(pdev);
	fintek_enable_wake(fintek);
}

static const struct pnp_device_id fintek_ids[] = {
	{ "FIT0002", 0 },   /* CIR */
	{ "", 0 },
};

static struct pnp_driver fintek_driver = {
	.name		= FINTEK_DRIVER_NAME,
	.id_table	= fintek_ids,
	.flags		= PNP_DRIVER_RES_DO_NOT_CHANGE,
	.probe		= fintek_probe,
	.remove		= fintek_remove,
	.suspend	= fintek_suspend,
	.resume		= fintek_resume,
	.shutdown	= fintek_shutdown,
};

module_param(debug, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(debug, "Enable debugging output");

MODULE_DEVICE_TABLE(pnp, fintek_ids);
MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver");

MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
MODULE_LICENSE("GPL");

module_pnp_driver(fintek_driver);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
9bdc79ea JW	2	/*
	3	* Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
	4	*
	5	* Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
	6	*
	7	* Special thanks to Fintek for providing hardware and spec sheets.
	8	* This driver is based upon the nuvoton, ite and ene drivers for
	9	* similar hardware.
9bdc79ea JW	10	*/
9bdc79ea JW	11
563cd5ce JP	12	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
563cd5ce JP	13
9bdc79ea JW	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/pnp.h>
	17	#include <linux/io.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/sched.h>
	20	#include <linux/slab.h>
	21	#include <media/rc-core.h>
9bdc79ea JW	22
	23	#include "fintek-cir.h"
	24
	25	/* write val to config reg */
	26	static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg)
	27	{
	28	fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
	29	__func__, reg, val, fintek->cr_ip, fintek->cr_dp);
	30	outb(reg, fintek->cr_ip);
	31	outb(val, fintek->cr_dp);
	32	}
	33
	34	/* read val from config reg */
	35	static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg)
	36	{
	37	u8 val;
	38
	39	outb(reg, fintek->cr_ip);
	40	val = inb(fintek->cr_dp);
	41
	42	fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)",
	43	__func__, reg, val, fintek->cr_ip, fintek->cr_dp);
	44	return val;
	45	}
	46
	47	/* update config register bit without changing other bits */
	48	static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
	49	{
	50	u8 tmp = fintek_cr_read(fintek, reg) \| val;
	51	fintek_cr_write(fintek, tmp, reg);
	52	}
	53
	54	/* clear config register bit without changing other bits */
	55	static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
	56	{
	57	u8 tmp = fintek_cr_read(fintek, reg) & ~val;
	58	fintek_cr_write(fintek, tmp, reg);
	59	}
	60
	61	/* enter config mode */
	62	static inline void fintek_config_mode_enable(struct fintek_dev *fintek)
	63	{
	64	/* Enabling Config Mode explicitly requires writing 2x */
	65	outb(CONFIG_REG_ENABLE, fintek->cr_ip);
	66	outb(CONFIG_REG_ENABLE, fintek->cr_ip);
	67	}
	68
	69	/* exit config mode */
	70	static inline void fintek_config_mode_disable(struct fintek_dev *fintek)
	71	{
	72	outb(CONFIG_REG_DISABLE, fintek->cr_ip);
	73	}
	74
	75	/*
	76	* When you want to address a specific logical device, write its logical
	77	* device number to GCR_LOGICAL_DEV_NO
	78	*/
	79	static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev)
	80	{
	81	fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO);
	82	}
	83
	84	/* write val to cir config register */
	85	static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset)
86	{
87	outb(val, fintek->cir_addr + offset);
88	}
89
90	/* read val from cir config register */
91	static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
92	{
29a8d979	93	return inb(fintek->cir_addr + offset);
9bdc79ea JW	94	}
9bdc79ea JW	95
9bdc79ea JW	96	/* dump current cir register contents */
	97	static void cir_dump_regs(struct fintek_dev *fintek)
	98	{
	99	fintek_config_mode_enable(fintek);
83ec8225	100	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea	101
563cd5ce JP	102	pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
	103	pr_info(" * CR CIR BASE ADDR: 0x%x\n",
	104	(fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) \|
9bdc79ea	105	fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
563cd5ce JP	106	pr_info(" * CR CIR IRQ NUM: 0x%x\n",
563cd5ce JP	107	fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
9bdc79ea JW	108
	109	fintek_config_mode_disable(fintek);
	110
563cd5ce JP	111	pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
	112	pr_info(" * STATUS: 0x%x\n",
	113	fintek_cir_reg_read(fintek, CIR_STATUS));
	114	pr_info(" * CONTROL: 0x%x\n",
	115	fintek_cir_reg_read(fintek, CIR_CONTROL));
	116	pr_info(" * RX_DATA: 0x%x\n",
	117	fintek_cir_reg_read(fintek, CIR_RX_DATA));
	118	pr_info(" * TX_CONTROL: 0x%x\n",
	119	fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
	120	pr_info(" * TX_DATA: 0x%x\n",
	121	fintek_cir_reg_read(fintek, CIR_TX_DATA));
9bdc79ea JW	122	}
	123
	124	/* detect hardware features */
	125	static int fintek_hw_detect(struct fintek_dev *fintek)
	126	{
	127	unsigned long flags;
	128	u8 chip_major, chip_minor;
	129	u8 vendor_major, vendor_minor;
	130	u8 portsel, ir_class;
83ec8225	131	u16 vendor, chip;
9bdc79ea JW	132
	133	fintek_config_mode_enable(fintek);
	134
	135	/* Check if we're using config port 0x4e or 0x2e */
	136	portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
	137	if (portsel == 0xff) {
	138	fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
	139	fintek_config_mode_disable(fintek);
	140	fintek->cr_ip = CR_INDEX_PORT2;
	141	fintek->cr_dp = CR_DATA_PORT2;
	142	fintek_config_mode_enable(fintek);
	143	portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
	144	}
	145	fit_dbg("portsel reg: 0x%02x", portsel);
	146
	147	ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
	148	fit_dbg("ir_class reg: 0x%02x", ir_class);
	149
	150	switch (ir_class) {
	151	case CLASS_RX_2TX:
	152	case CLASS_RX_1TX:
	153	fintek->hw_tx_capable = true;
	154	break;
	155	case CLASS_RX_ONLY:
	156	default:
	157	fintek->hw_tx_capable = false;
	158	break;
	159	}
	160
	161	chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
	162	chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
83ec8225	163	chip = chip_major << 8 \| chip_minor;
9bdc79ea JW	164
	165	vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
	166	vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
	167	vendor = vendor_major << 8 \| vendor_minor;
	168
	169	if (vendor != VENDOR_ID_FINTEK)
	170	fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
	171	else
	172	fit_dbg("Read Fintek vendor ID from chip");
	173
	174	fintek_config_mode_disable(fintek);
	175
	176	spin_lock_irqsave(&fintek->fintek_lock, flags);
	177	fintek->chip_major = chip_major;
	178	fintek->chip_minor = chip_minor;
	179	fintek->chip_vendor = vendor;
83ec8225 MCC	180
	181	/*
	182	* Newer reviews of this chipset uses port 8 instead of 5
	183	*/
3e1fd478	184	if ((chip != 0x0408) && (chip != 0x0804))
83ec8225 MCC	185	fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2;
	186	else
	187	fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1;
	188
9bdc79ea JW	189	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
9bdc79ea JW	190
9b08f417	191	return 0;
9bdc79ea JW	192	}
	193
	194	static void fintek_cir_ldev_init(struct fintek_dev *fintek)
	195	{
	196	/* Select CIR logical device and enable */
83ec8225	197	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea JW	198	fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
	199
	200	/* Write allocated CIR address and IRQ information to hardware */
	201	fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI);
	202	fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO);
	203
	204	fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL);
	205
	206	fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)",
	207	fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len);
	208	}
	209
	210	/* enable CIR interrupts */
	211	static void fintek_enable_cir_irq(struct fintek_dev *fintek)
	212	{
	213	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
	214	}
	215
	216	static void fintek_cir_regs_init(struct fintek_dev *fintek)
	217	{
	218	/* clear any and all stray interrupts */
	219	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
	220
	221	/* and finally, enable interrupts */
	222	fintek_enable_cir_irq(fintek);
	223	}
	224
	225	static void fintek_enable_wake(struct fintek_dev *fintek)
	226	{
	227	fintek_config_mode_enable(fintek);
	228	fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI);
	229
	230	/* Allow CIR PME's to wake system */
	231	fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG);
	232	/* Enable CIR PME's */
	233	fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG);
	234	/* Clear CIR PME status register */
	235	fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG);
	236	/* Save state */
	237	fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG);
	238
	239	fintek_config_mode_disable(fintek);
	240	}
	241
	242	static int fintek_cmdsize(u8 cmd, u8 subcmd)
	243	{
	244	int datasize = 0;
	245
	246	switch (cmd) {
	247	case BUF_COMMAND_NULL:
	248	if (subcmd == BUF_HW_CMD_HEADER)
	249	datasize = 1;
	250	break;
	251	case BUF_HW_CMD_HEADER:
	252	if (subcmd == BUF_CMD_G_REVISION)
	253	datasize = 2;
	254	break;
	255	case BUF_COMMAND_HEADER:
	256	switch (subcmd) {
	257	case BUF_CMD_S_CARRIER:
	258	case BUF_CMD_S_TIMEOUT:
	259	case BUF_RSP_PULSE_COUNT:
	260	datasize = 2;
	261	break;
262	case BUF_CMD_SIG_END:
263	case BUF_CMD_S_TXMASK:
264	case BUF_CMD_S_RXSENSOR:
265	datasize = 1;
266	break;
267	}
268	}
269
270	return datasize;
271	}
272
273	/* process ir data stored in driver buffer */
274	static void fintek_process_rx_ir_data(struct fintek_dev *fintek)
275	{
183e19f5	276	struct ir_raw_event rawir = {};
9bdc79ea	277	u8 sample;
b83bfd1b	278	bool event = false;
9bdc79ea JW	279	int i;
	280
	281	for (i = 0; i < fintek->pkts; i++) {
	282	sample = fintek->buf[i];
	283	switch (fintek->parser_state) {
	284	case CMD_HEADER:
	285	fintek->cmd = sample;
	286	if ((fintek->cmd == BUF_COMMAND_HEADER) \|\|
	287	((fintek->cmd & BUF_COMMAND_MASK) !=
	288	BUF_PULSE_BIT)) {
	289	fintek->parser_state = SUBCMD;
	290	continue;
	291	}
	292	fintek->rem = (fintek->cmd & BUF_LEN_MASK);
	293	fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem);
	294	if (fintek->rem)
	295	fintek->parser_state = PARSE_IRDATA;
	296	else
	297	ir_raw_event_reset(fintek->rdev);
	298	break;
	299	case SUBCMD:
	300	fintek->rem = fintek_cmdsize(fintek->cmd, sample);
	301	fintek->parser_state = CMD_DATA;
	302	break;
	303	case CMD_DATA:
	304	fintek->rem--;
	305	break;
	306	case PARSE_IRDATA:
	307	fintek->rem--;
9bdc79ea JW	308	rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
	309	rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK)
	310	* CIR_SAMPLE_PERIOD);
	311
	312	fit_dbg("Storing %s with duration %d",
	313	rawir.pulse ? "pulse" : "space",
	314	rawir.duration);
b83bfd1b SY	315	if (ir_raw_event_store_with_filter(fintek->rdev,
	316	&rawir))
	317	event = true;
9bdc79ea JW	318	break;
	319	}
	320
	321	if ((fintek->parser_state != CMD_HEADER) && !fintek->rem)
	322	fintek->parser_state = CMD_HEADER;
	323	}
	324
	325	fintek->pkts = 0;
	326
b83bfd1b SY	327	if (event) {
	328	fit_dbg("Calling ir_raw_event_handle");
	329	ir_raw_event_handle(fintek->rdev);
	330	}
9bdc79ea JW	331	}
	332
	333	/* copy data from hardware rx register into driver buffer */
	334	static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs)
	335	{
	336	unsigned long flags;
	337	u8 sample, status;
	338
	339	spin_lock_irqsave(&fintek->fintek_lock, flags);
	340
	341	/*
	342	* We must read data from CIR_RX_DATA until the hardware IR buffer
	343	* is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in
	344	* the CIR_STATUS register
	345	*/
	346	do {
	347	sample = fintek_cir_reg_read(fintek, CIR_RX_DATA);
	348	fit_dbg("%s: sample: 0x%02x", __func__, sample);
	349
	350	fintek->buf[fintek->pkts] = sample;
	351	fintek->pkts++;
	352
	353	status = fintek_cir_reg_read(fintek, CIR_STATUS);
	354	if (!(status & CIR_STATUS_IRQ_EN))
	355	break;
	356	} while (status & rx_irqs);
	357
	358	fintek_process_rx_ir_data(fintek);
	359
	360	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
	361	}
	362
	363	static void fintek_cir_log_irqs(u8 status)
	364	{
	365	fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status,
	366	status & CIR_STATUS_IRQ_EN ? " IRQEN" : "",
	367	status & CIR_STATUS_TX_FINISH ? " TXF" : "",
	368	status & CIR_STATUS_TX_UNDERRUN ? " TXU" : "",
	369	status & CIR_STATUS_RX_TIMEOUT ? " RXTO" : "",
	370	status & CIR_STATUS_RX_RECEIVE ? " RXOK" : "");
	371	}
	372
	373	/* interrupt service routine for incoming and outgoing CIR data */
	374	static irqreturn_t fintek_cir_isr(int irq, void *data)
	375	{
	376	struct fintek_dev *fintek = data;
	377	u8 status, rx_irqs;
	378
	379	fit_dbg_verbose("%s firing", __func__);
	380
	381	fintek_config_mode_enable(fintek);
83ec8225	382	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea JW	383	fintek_config_mode_disable(fintek);
	384
	385	/*
	386	* Get IR Status register contents. Write 1 to ack/clear
	387	*
	388	* bit: reg name - description
	389	* 3: TX_FINISH - TX is finished
	390	* 2: TX_UNDERRUN - TX underrun
	391	* 1: RX_TIMEOUT - RX data timeout
	392	* 0: RX_RECEIVE - RX data received
	393	*/
	394	status = fintek_cir_reg_read(fintek, CIR_STATUS);
	395	if (!(status & CIR_STATUS_IRQ_MASK) \|\| status == 0xff) {
	396	fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status);
	397	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
	398	return IRQ_RETVAL(IRQ_NONE);
	399	}
	400
	401	if (debug)
	402	fintek_cir_log_irqs(status);
	403
	404	rx_irqs = status & (CIR_STATUS_RX_RECEIVE \| CIR_STATUS_RX_TIMEOUT);
	405	if (rx_irqs)
	406	fintek_get_rx_ir_data(fintek, rx_irqs);
	407
	408	/* ack/clear all irq flags we've got */
	409	fintek_cir_reg_write(fintek, status, CIR_STATUS);
	410
	411	fit_dbg_verbose("%s done", __func__);
	412	return IRQ_RETVAL(IRQ_HANDLED);
	413	}
	414
	415	static void fintek_enable_cir(struct fintek_dev *fintek)
	416	{
	417	/* set IRQ enabled */
	418	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
	419
	420	fintek_config_mode_enable(fintek);
	421
	422	/* enable the CIR logical device */
83ec8225	423	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea JW	424	fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
	425
	426	fintek_config_mode_disable(fintek);
	427
	428	/* clear all pending interrupts */
	429	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
	430
	431	/* enable interrupts */
	432	fintek_enable_cir_irq(fintek);
	433	}
	434
	435	static void fintek_disable_cir(struct fintek_dev *fintek)
	436	{
	437	fintek_config_mode_enable(fintek);
	438
	439	/* disable the CIR logical device */
83ec8225	440	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea JW	441	fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
	442
	443	fintek_config_mode_disable(fintek);
	444	}
	445
	446	static int fintek_open(struct rc_dev *dev)
	447	{
	448	struct fintek_dev *fintek = dev->priv;
	449	unsigned long flags;
	450
	451	spin_lock_irqsave(&fintek->fintek_lock, flags);
	452	fintek_enable_cir(fintek);
	453	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
	454
	455	return 0;
	456	}
	457
	458	static void fintek_close(struct rc_dev *dev)
	459	{
	460	struct fintek_dev *fintek = dev->priv;
	461	unsigned long flags;
	462
	463	spin_lock_irqsave(&fintek->fintek_lock, flags);
	464	fintek_disable_cir(fintek);
	465	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
	466	}
	467
	468	/* Allocate memory, probe hardware, and initialize everything */
	469	static int fintek_probe(struct pnp_dev pdev, const struct pnp_device_id dev_id)
	470	{
	471	struct fintek_dev *fintek;
	472	struct rc_dev *rdev;
	473	int ret = -ENOMEM;
	474
	475	fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL);
	476	if (!fintek)
	477	return ret;
	478
	479	/* input device for IR remote (and tx) */
0f7499fd	480	rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
9bdc79ea	481	if (!rdev)
70ef6991	482	goto exit_free_dev_rdev;
9bdc79ea JW	483
	484	ret = -ENODEV;
	485	/* validate pnp resources */
	486	if (!pnp_port_valid(pdev, 0)) {
	487	dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991	488	goto exit_free_dev_rdev;
9bdc79ea JW	489	}
	490
	491	if (!pnp_irq_valid(pdev, 0)) {
	492	dev_err(&pdev->dev, "IR PNP IRQ not valid!\n");
70ef6991	493	goto exit_free_dev_rdev;
9bdc79ea JW	494	}
	495
	496	fintek->cir_addr = pnp_port_start(pdev, 0);
	497	fintek->cir_irq = pnp_irq(pdev, 0);
	498	fintek->cir_port_len = pnp_port_len(pdev, 0);
	499
	500	fintek->cr_ip = CR_INDEX_PORT;
	501	fintek->cr_dp = CR_DATA_PORT;
	502
	503	spin_lock_init(&fintek->fintek_lock);
	504
9bdc79ea JW	505	pnp_set_drvdata(pdev, fintek);
	506	fintek->pdev = pdev;
	507
	508	ret = fintek_hw_detect(fintek);
	509	if (ret)
70ef6991	510	goto exit_free_dev_rdev;
9bdc79ea JW	511
	512	/* Initialize CIR & CIR Wake Logical Devices */
	513	fintek_config_mode_enable(fintek);
	514	fintek_cir_ldev_init(fintek);
	515	fintek_config_mode_disable(fintek);
	516
	517	/* Initialize CIR & CIR Wake Config Registers */
	518	fintek_cir_regs_init(fintek);
	519
	520	/* Set up the rc device */
	521	rdev->priv = fintek;
6d741bfe	522	rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
9bdc79ea JW	523	rdev->open = fintek_open;
9bdc79ea JW	524	rdev->close = fintek_close;
518f4b26	525	rdev->device_name = FINTEK_DESCRIPTION;
9bdc79ea JW	526	rdev->input_phys = "fintek/cir0";
	527	rdev->input_id.bustype = BUS_HOST;
	528	rdev->input_id.vendor = VENDOR_ID_FINTEK;
	529	rdev->input_id.product = fintek->chip_major;
	530	rdev->input_id.version = fintek->chip_minor;
	531	rdev->dev.parent = &pdev->dev;
	532	rdev->driver_name = FINTEK_DRIVER_NAME;
	533	rdev->map_name = RC_MAP_RC6_MCE;
	534	rdev->timeout = US_TO_NS(1000);
	535	/* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
	536	rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
	537
d62b6818 MK	538	fintek->rdev = rdev;
d62b6818 MK	539
9ef449c6 LH	540	ret = -EBUSY;
	541	/* now claim resources */
	542	if (!request_region(fintek->cir_addr,
	543	fintek->cir_port_len, FINTEK_DRIVER_NAME))
70ef6991	544	goto exit_free_dev_rdev;
9ef449c6 LH	545
	546	if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED,
	547	FINTEK_DRIVER_NAME, (void *)fintek))
70ef6991	548	goto exit_free_cir_addr;
9ef449c6	549
9bdc79ea JW	550	ret = rc_register_device(rdev);
9bdc79ea JW	551	if (ret)
70ef6991	552	goto exit_free_irq;
9bdc79ea JW	553
9bdc79ea JW	554	device_init_wakeup(&pdev->dev, true);
d62b6818	555
9bdc79ea JW	556	fit_pr(KERN_NOTICE, "driver has been successfully loaded\n");
	557	if (debug)
	558	cir_dump_regs(fintek);
	559
	560	return 0;
	561
70ef6991	562	exit_free_irq:
f27b853e	563	free_irq(fintek->cir_irq, fintek);
70ef6991	564	exit_free_cir_addr:
f27b853e	565	release_region(fintek->cir_addr, fintek->cir_port_len);
70ef6991	566	exit_free_dev_rdev:
9bdc79ea JW	567	rc_free_device(rdev);
	568	kfree(fintek);
	569
	570	return ret;
	571	}
	572
4c62e976	573	static void fintek_remove(struct pnp_dev *pdev)
9bdc79ea JW	574	{
	575	struct fintek_dev *fintek = pnp_get_drvdata(pdev);
	576	unsigned long flags;
	577
	578	spin_lock_irqsave(&fintek->fintek_lock, flags);
	579	/* disable CIR */
	580	fintek_disable_cir(fintek);
	581	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
	582	/* enable CIR Wake (for IR power-on) */
	583	fintek_enable_wake(fintek);
	584	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
	585
	586	/* free resources */
	587	free_irq(fintek->cir_irq, fintek);
	588	release_region(fintek->cir_addr, fintek->cir_port_len);
	589
	590	rc_unregister_device(fintek->rdev);
	591
	592	kfree(fintek);
	593	}
	594
	595	static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state)
	596	{
	597	struct fintek_dev *fintek = pnp_get_drvdata(pdev);
0ae90252	598	unsigned long flags;
9bdc79ea JW	599
	600	fit_dbg("%s called", __func__);
	601
0ae90252 JW	602	spin_lock_irqsave(&fintek->fintek_lock, flags);
0ae90252 JW	603
9bdc79ea JW	604	/* disable all CIR interrupts */
	605	fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
	606
0ae90252 JW	607	spin_unlock_irqrestore(&fintek->fintek_lock, flags);
0ae90252 JW	608
9bdc79ea JW	609	fintek_config_mode_enable(fintek);
	610
	611	/* disable cir logical dev */
83ec8225	612	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea JW	613	fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
	614
	615	fintek_config_mode_disable(fintek);
	616
	617	/* make sure wake is enabled */
	618	fintek_enable_wake(fintek);
	619
	620	return 0;
	621	}
	622
	623	static int fintek_resume(struct pnp_dev *pdev)
	624	{
9bdc79ea JW	625	struct fintek_dev *fintek = pnp_get_drvdata(pdev);
	626
	627	fit_dbg("%s called", __func__);
	628
	629	/* open interrupt */
	630	fintek_enable_cir_irq(fintek);
	631
	632	/* Enable CIR logical device */
	633	fintek_config_mode_enable(fintek);
83ec8225	634	fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
9bdc79ea JW	635	fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
	636
	637	fintek_config_mode_disable(fintek);
	638
	639	fintek_cir_regs_init(fintek);
	640
9b08f417	641	return 0;
9bdc79ea JW	642	}
	643
	644	static void fintek_shutdown(struct pnp_dev *pdev)
	645	{
	646	struct fintek_dev *fintek = pnp_get_drvdata(pdev);
	647	fintek_enable_wake(fintek);
	648	}
	649
	650	static const struct pnp_device_id fintek_ids[] = {
	651	{ "FIT0002", 0 }, /* CIR */
	652	{ "", 0 },
	653	};
	654
	655	static struct pnp_driver fintek_driver = {
	656	.name = FINTEK_DRIVER_NAME,
	657	.id_table = fintek_ids,
	658	.flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
	659	.probe = fintek_probe,
4c62e976	660	.remove = fintek_remove,
9bdc79ea JW	661	.suspend = fintek_suspend,
	662	.resume = fintek_resume,
	663	.shutdown = fintek_shutdown,
	664	};
	665
9bdc79ea JW	666	module_param(debug, int, S_IRUGO \| S_IWUSR);
	667	MODULE_PARM_DESC(debug, "Enable debugging output");
	668
	669	MODULE_DEVICE_TABLE(pnp, fintek_ids);
	670	MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver");
	671
	672	MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
	673	MODULE_LICENSE("GPL");
	674
af638a04	675	module_pnp_driver(fintek_driver);