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[media] v4l: ti-vpe: make vpe driver load scaler coefficients
[linux-block.git] / drivers / media / platform / ti-vpe / vpe.c
CommitLineData
45719127
AT		 1/*
2 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
3 *
4 * Copyright (c) 2013 Texas Instruments Inc.
5 * David Griego, <dagriego@biglakesoftware.com>
6 * Dale Farnsworth, <dale@farnsworth.org>
7 * Archit Taneja, <archit@ti.com>
8 *
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
12 *
13 * Based on the virtual v4l2-mem2mem example device
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published by
17 * the Free Software Foundation
18 */
19
20#include <linux/delay.h>
21#include <linux/dma-mapping.h>
22#include <linux/err.h>
23#include <linux/fs.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/ioctl.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/videodev2.h>
a51cd8f5 33#include <linux/log2.h>
45719127
AT		 34
35#include <media/v4l2-common.h>
36#include <media/v4l2-ctrls.h>
37#include <media/v4l2-device.h>
38#include <media/v4l2-event.h>
39#include <media/v4l2-ioctl.h>
40#include <media/v4l2-mem2mem.h>
41#include <media/videobuf2-core.h>
42#include <media/videobuf2-dma-contig.h>
43
44#include "vpdma.h"
45#include "vpe_regs.h"
44687b2e 46#include "sc.h"
45719127
AT		 47
48#define VPE_MODULE_NAME "vpe"
49
50/* minimum and maximum frame sizes */
51#define MIN_W 128
52#define MIN_H 128
53#define MAX_W 1920
54#define MAX_H 1080
55
56/* required alignments */
57#define S_ALIGN 0 /* multiple of 1 */
58#define H_ALIGN 1 /* multiple of 2 */
45719127
AT		 59
60/* flags that indicate a format can be used for capture/output */
61#define VPE_FMT_TYPE_CAPTURE (1 << 0)
62#define VPE_FMT_TYPE_OUTPUT (1 << 1)
63
64/* used as plane indices */
65#define VPE_MAX_PLANES 2
66#define VPE_LUMA 0
67#define VPE_CHROMA 1
68
69/* per m2m context info */
585e6f01
AT		 70#define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
71
45719127
AT		 72#define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
73
74/*
75 * each VPE context can need up to 3 config desciptors, 7 input descriptors,
76 * 3 output descriptors, and 10 control descriptors
77 */
78#define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
79 13 * VPDMA_CFD_CTD_DESC_SIZE)
80
81#define vpe_dbg(vpedev, fmt, arg...) \
82 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
83#define vpe_err(vpedev, fmt, arg...) \
84 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
85
86struct vpe_us_coeffs {
87 unsigned short anchor_fid0_c0;
88 unsigned short anchor_fid0_c1;
89 unsigned short anchor_fid0_c2;
90 unsigned short anchor_fid0_c3;
91 unsigned short interp_fid0_c0;
92 unsigned short interp_fid0_c1;
93 unsigned short interp_fid0_c2;
94 unsigned short interp_fid0_c3;
95 unsigned short anchor_fid1_c0;
96 unsigned short anchor_fid1_c1;
97 unsigned short anchor_fid1_c2;
98 unsigned short anchor_fid1_c3;
99 unsigned short interp_fid1_c0;
100 unsigned short interp_fid1_c1;
101 unsigned short interp_fid1_c2;
102 unsigned short interp_fid1_c3;
103};
104
105/*
106 * Default upsampler coefficients
107 */
108static const struct vpe_us_coeffs us_coeffs[] = {
109 {
110 /* Coefficients for progressive input */
111 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
112 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
113 },
585e6f01
AT		 114 {
115 /* Coefficients for Top Field Interlaced input */
116 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
117 /* Coefficients for Bottom Field Interlaced input */
118 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
119 },
120};
121
122/*
123 * the following registers are for configuring some of the parameters of the
124 * motion and edge detection blocks inside DEI, these generally remain the same,
125 * these could be passed later via userspace if some one needs to tweak these.
126 */
127struct vpe_dei_regs {
128 unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
129 unsigned long edi_config_reg; /* VPE_DEI_REG3 */
130 unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
131 unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
132 unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
133 unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
134};
135
136/*
137 * default expert DEI register values, unlikely to be modified.
138 */
139static const struct vpe_dei_regs dei_regs = {
140 0x020C0804u,
141 0x0118100Fu,
142 0x08040200u,
143 0x1010100Cu,
144 0x10101010u,
145 0x10101010u,
45719127
AT		 146};
147
148/*
149 * The port_data structure contains per-port data.
150 */
151struct vpe_port_data {
152 enum vpdma_channel channel; /* VPDMA channel */
585e6f01 153 u8 vb_index; /* input frame f, f-1, f-2 index */
45719127
AT		 154 u8 vb_part; /* plane index for co-panar formats */
155};
156
157/*
158 * Define indices into the port_data tables
159 */
160#define VPE_PORT_LUMA1_IN 0
161#define VPE_PORT_CHROMA1_IN 1
585e6f01
AT		 162#define VPE_PORT_LUMA2_IN 2
163#define VPE_PORT_CHROMA2_IN 3
164#define VPE_PORT_LUMA3_IN 4
165#define VPE_PORT_CHROMA3_IN 5
166#define VPE_PORT_MV_IN 6
167#define VPE_PORT_MV_OUT 7
45719127
AT		 168#define VPE_PORT_LUMA_OUT 8
169#define VPE_PORT_CHROMA_OUT 9
170#define VPE_PORT_RGB_OUT 10
171
172static const struct vpe_port_data port_data[11] = {
173 [VPE_PORT_LUMA1_IN] = {
174 .channel = VPE_CHAN_LUMA1_IN,
585e6f01 175 .vb_index = 0,
45719127
AT		 176 .vb_part = VPE_LUMA,
177 },
178 [VPE_PORT_CHROMA1_IN] = {
179 .channel = VPE_CHAN_CHROMA1_IN,
585e6f01
AT		 180 .vb_index = 0,
181 .vb_part = VPE_CHROMA,
182 },
183 [VPE_PORT_LUMA2_IN] = {
184 .channel = VPE_CHAN_LUMA2_IN,
185 .vb_index = 1,
186 .vb_part = VPE_LUMA,
187 },
188 [VPE_PORT_CHROMA2_IN] = {
189 .channel = VPE_CHAN_CHROMA2_IN,
190 .vb_index = 1,
191 .vb_part = VPE_CHROMA,
192 },
193 [VPE_PORT_LUMA3_IN] = {
194 .channel = VPE_CHAN_LUMA3_IN,
195 .vb_index = 2,
196 .vb_part = VPE_LUMA,
197 },
198 [VPE_PORT_CHROMA3_IN] = {
199 .channel = VPE_CHAN_CHROMA3_IN,
200 .vb_index = 2,
45719127
AT		 201 .vb_part = VPE_CHROMA,
202 },
585e6f01
AT		 203 [VPE_PORT_MV_IN] = {
204 .channel = VPE_CHAN_MV_IN,
205 },
206 [VPE_PORT_MV_OUT] = {
207 .channel = VPE_CHAN_MV_OUT,
208 },
45719127
AT		 209 [VPE_PORT_LUMA_OUT] = {
210 .channel = VPE_CHAN_LUMA_OUT,
211 .vb_part = VPE_LUMA,
212 },
213 [VPE_PORT_CHROMA_OUT] = {
214 .channel = VPE_CHAN_CHROMA_OUT,
215 .vb_part = VPE_CHROMA,
216 },
217 [VPE_PORT_RGB_OUT] = {
218 .channel = VPE_CHAN_RGB_OUT,
219 .vb_part = VPE_LUMA,
220 },
221};
222
223
224/* driver info for each of the supported video formats */
225struct vpe_fmt {
226 char *name; /* human-readable name */
227 u32 fourcc; /* standard format identifier */
228 u8 types; /* CAPTURE and/or OUTPUT */
229 u8 coplanar; /* set for unpacked Luma and Chroma */
230 /* vpdma format info for each plane */
231 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
232};
233
234static struct vpe_fmt vpe_formats[] = {
235 {
236 .name = "YUV 422 co-planar",
237 .fourcc = V4L2_PIX_FMT_NV16,
238 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
239 .coplanar = 1,
240 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
241 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
242 },
243 },
244 {
245 .name = "YUV 420 co-planar",
246 .fourcc = V4L2_PIX_FMT_NV12,
247 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
248 .coplanar = 1,
249 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
250 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
251 },
252 },
253 {
254 .name = "YUYV 422 packed",
255 .fourcc = V4L2_PIX_FMT_YUYV,
256 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
257 .coplanar = 0,
258 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YC422],
259 },
260 },
261 {
262 .name = "UYVY 422 packed",
263 .fourcc = V4L2_PIX_FMT_UYVY,
264 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
265 .coplanar = 0,
266 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CY422],
267 },
268 },
269};
270
271/*
272 * per-queue, driver-specific private data.
273 * there is one source queue and one destination queue for each m2m context.
274 */
275struct vpe_q_data {
276 unsigned int width; /* frame width */
277 unsigned int height; /* frame height */
278 unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */
279 enum v4l2_colorspace colorspace;
585e6f01 280 enum v4l2_field field; /* supported field value */
45719127
AT		 281 unsigned int flags;
282 unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */
283 struct v4l2_rect c_rect; /* crop/compose rectangle */
284 struct vpe_fmt *fmt; /* format info */
285};
286
287/* vpe_q_data flag bits */
288#define Q_DATA_FRAME_1D (1 << 0)
289#define Q_DATA_MODE_TILED (1 << 1)
585e6f01 290#define Q_DATA_INTERLACED (1 << 2)
45719127
AT		 291
292enum {
293 Q_DATA_SRC = 0,
294 Q_DATA_DST = 1,
295};
296
297/* find our format description corresponding to the passed v4l2_format */
298static struct vpe_fmt *find_format(struct v4l2_format *f)
299{
300 struct vpe_fmt *fmt;
301 unsigned int k;
302
303 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
304 fmt = &vpe_formats[k];
305 if (fmt->fourcc == f->fmt.pix.pixelformat)
306 return fmt;
307 }
308
309 return NULL;
310}
311
312/*
313 * there is one vpe_dev structure in the driver, it is shared by
314 * all instances.
315 */
316struct vpe_dev {
317 struct v4l2_device v4l2_dev;
318 struct video_device vfd;
319 struct v4l2_m2m_dev *m2m_dev;
320
321 atomic_t num_instances; /* count of driver instances */
322 dma_addr_t loaded_mmrs; /* shadow mmrs in device */
323 struct mutex dev_mutex;
324 spinlock_t lock;
325
326 int irq;
327 void __iomem *base;
44687b2e 328 struct resource *res;
45719127
AT		 329
330 struct vb2_alloc_ctx *alloc_ctx;
331 struct vpdma_data *vpdma; /* vpdma data handle */
44687b2e 332 struct sc_data *sc; /* scaler data handle */
45719127
AT		 333};
334
335/*
336 * There is one vpe_ctx structure for each m2m context.
337 */
338struct vpe_ctx {
339 struct v4l2_fh fh;
340 struct vpe_dev *dev;
341 struct v4l2_m2m_ctx *m2m_ctx;
342 struct v4l2_ctrl_handler hdl;
343
585e6f01 344 unsigned int field; /* current field */
45719127
AT		 345 unsigned int sequence; /* current frame/field seq */
346 unsigned int aborting; /* abort after next irq */
347
348 unsigned int bufs_per_job; /* input buffers per batch */
349 unsigned int bufs_completed; /* bufs done in this batch */
350
351 struct vpe_q_data q_data[2]; /* src & dst queue data */
585e6f01 352 struct vb2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
45719127
AT		 353 struct vb2_buffer *dst_vb;
354
585e6f01
AT		 355 dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
356 void *mv_buf[2]; /* virtual addrs of motion vector bufs */
357 size_t mv_buf_size; /* current motion vector buffer size */
45719127 358 struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
773f0657
AT		 359 struct vpdma_buf sc_coeff_h; /* h coeff buffer */
360 struct vpdma_buf sc_coeff_v; /* v coeff buffer */
45719127
AT		 361 struct vpdma_desc_list desc_list; /* DMA descriptor list */
362
585e6f01 363 bool deinterlacing; /* using de-interlacer */
45719127 364 bool load_mmrs; /* have new shadow reg values */
585e6f01
AT		 365
366 unsigned int src_mv_buf_selector;
45719127
AT		 367};
368
369
370/*
371 * M2M devices get 2 queues.
372 * Return the queue given the type.
373 */
374static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
375 enum v4l2_buf_type type)
376{
377 switch (type) {
378 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
379 return &ctx->q_data[Q_DATA_SRC];
380 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
381 return &ctx->q_data[Q_DATA_DST];
382 default:
383 BUG();
384 }
385 return NULL;
386}
387
388static u32 read_reg(struct vpe_dev *dev, int offset)
389{
390 return ioread32(dev->base + offset);
391}
392
393static void write_reg(struct vpe_dev *dev, int offset, u32 value)
394{
395 iowrite32(value, dev->base + offset);
396}
397
398/* register field read/write helpers */
399static int get_field(u32 value, u32 mask, int shift)
400{
401 return (value & (mask << shift)) >> shift;
402}
403
404static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
405{
406 return get_field(read_reg(dev, offset), mask, shift);
407}
408
409static void write_field(u32 *valp, u32 field, u32 mask, int shift)
410{
411 u32 val = *valp;
412
413 val &= ~(mask << shift);
414 val |= (field & mask) << shift;
415 *valp = val;
416}
417
418static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
419 u32 mask, int shift)
420{
421 u32 val = read_reg(dev, offset);
422
423 write_field(&val, field, mask, shift);
424
425 write_reg(dev, offset, val);
426}
427
428/*
429 * DMA address/data block for the shadow registers
430 */
431struct vpe_mmr_adb {
432 struct vpdma_adb_hdr out_fmt_hdr;
433 u32 out_fmt_reg[1];
434 u32 out_fmt_pad[3];
435 struct vpdma_adb_hdr us1_hdr;
436 u32 us1_regs[8];
437 struct vpdma_adb_hdr us2_hdr;
438 u32 us2_regs[8];
439 struct vpdma_adb_hdr us3_hdr;
440 u32 us3_regs[8];
441 struct vpdma_adb_hdr dei_hdr;
585e6f01 442 u32 dei_regs[8];
45719127
AT		 443 struct vpdma_adb_hdr sc_hdr;
444 u32 sc_regs[1];
445 u32 sc_pad[3];
446 struct vpdma_adb_hdr csc_hdr;
447 u32 csc_regs[6];
448 u32 csc_pad[2];
449};
450
44687b2e
AT		 451#define GET_OFFSET_TOP(ctx, obj, reg) \
452 ((obj)->res->start - ctx->dev->res->start + reg)
453
45719127
AT		 454#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
455 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
456/*
457 * Set the headers for all of the address/data block structures.
458 */
459static void init_adb_hdrs(struct vpe_ctx *ctx)
460{
461 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
462 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
463 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
464 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
465 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
44687b2e
AT		 466 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr, sc_regs,
467 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
45719127
AT		 468 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, VPE_CSC_CSC00);
469};
470
585e6f01
AT		 471/*
472 * Allocate or re-allocate the motion vector DMA buffers
473 * There are two buffers, one for input and one for output.
474 * However, the roles are reversed after each field is processed.
475 * In other words, after each field is processed, the previous
476 * output (dst) MV buffer becomes the new input (src) MV buffer.
477 */
478static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
479{
480 struct device *dev = ctx->dev->v4l2_dev.dev;
481
482 if (ctx->mv_buf_size == size)
483 return 0;
484
485 if (ctx->mv_buf[0])
486 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
487 ctx->mv_buf_dma[0]);
488
489 if (ctx->mv_buf[1])
490 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
491 ctx->mv_buf_dma[1]);
492
493 if (size == 0)
494 return 0;
495
496 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
497 GFP_KERNEL);
498 if (!ctx->mv_buf[0]) {
499 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
500 return -ENOMEM;
501 }
502
503 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
504 GFP_KERNEL);
505 if (!ctx->mv_buf[1]) {
506 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
507 dma_free_coherent(dev, size, ctx->mv_buf[0],
508 ctx->mv_buf_dma[0]);
509
510 return -ENOMEM;
511 }
512
513 ctx->mv_buf_size = size;
514 ctx->src_mv_buf_selector = 0;
515
516 return 0;
517}
518
519static void free_mv_buffers(struct vpe_ctx *ctx)
520{
521 realloc_mv_buffers(ctx, 0);
522}
523
524/*
525 * While de-interlacing, we keep the two most recent input buffers
526 * around. This function frees those two buffers when we have
527 * finished processing the current stream.
528 */
529static void free_vbs(struct vpe_ctx *ctx)
530{
531 struct vpe_dev *dev = ctx->dev;
532 unsigned long flags;
533
534 if (ctx->src_vbs[2] == NULL)
535 return;
536
537 spin_lock_irqsave(&dev->lock, flags);
538 if (ctx->src_vbs[2]) {
539 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
540 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
541 }
542 spin_unlock_irqrestore(&dev->lock, flags);
543}
544
45719127
AT		 545/*
546 * Enable or disable the VPE clocks
547 */
548static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
549{
550 u32 val = 0;
551
552 if (on)
553 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
554 write_reg(dev, VPE_CLK_ENABLE, val);
555}
556
557static void vpe_top_reset(struct vpe_dev *dev)
558{
559
560 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
561 VPE_DATA_PATH_CLK_RESET_SHIFT);
562
563 usleep_range(100, 150);
564
565 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
566 VPE_DATA_PATH_CLK_RESET_SHIFT);
567}
568
569static void vpe_top_vpdma_reset(struct vpe_dev *dev)
570{
571 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
572 VPE_VPDMA_CLK_RESET_SHIFT);
573
574 usleep_range(100, 150);
575
576 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
577 VPE_VPDMA_CLK_RESET_SHIFT);
578}
579
580/*
581 * Load the correct of upsampler coefficients into the shadow MMRs
582 */
583static void set_us_coefficients(struct vpe_ctx *ctx)
584{
585 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
585e6f01 586 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
45719127
AT		 587 u32 *us1_reg = &mmr_adb->us1_regs[0];
588 u32 *us2_reg = &mmr_adb->us2_regs[0];
589 u32 *us3_reg = &mmr_adb->us3_regs[0];
590 const unsigned short *cp, *end_cp;
591
592 cp = &us_coeffs[0].anchor_fid0_c0;
593
585e6f01
AT		 594 if (s_q_data->flags & Q_DATA_INTERLACED) /* interlaced */
595 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
596
45719127
AT		 597 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
598
599 while (cp < end_cp) {
600 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
601 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
602 *us2_reg++ = *us1_reg;
603 *us3_reg++ = *us1_reg++;
604 }
605 ctx->load_mmrs = true;
606}
607
608/*
609 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
610 */
611static void set_cfg_and_line_modes(struct vpe_ctx *ctx)
612{
613 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
614 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
615 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
616 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
617 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
618 int line_mode = 1;
619 int cfg_mode = 1;
620
621 /*
622 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
623 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
624 */
625
626 if (fmt->fourcc == V4L2_PIX_FMT_NV12) {
627 cfg_mode = 0;
628 line_mode = 0; /* double lines to line buffer */
629 }
630
631 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
632 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
633 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
634
635 /* regs for now */
636 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
585e6f01
AT		 637 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
638 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
45719127
AT		 639
640 /* frame start for input luma */
641 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
642 VPE_CHAN_LUMA1_IN);
585e6f01
AT		 643 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
644 VPE_CHAN_LUMA2_IN);
645 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
646 VPE_CHAN_LUMA3_IN);
45719127
AT		 647
648 /* frame start for input chroma */
649 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
650 VPE_CHAN_CHROMA1_IN);
585e6f01
AT		 651 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
652 VPE_CHAN_CHROMA2_IN);
653 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
654 VPE_CHAN_CHROMA3_IN);
655
656 /* frame start for MV in client */
657 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
658 VPE_CHAN_MV_IN);
45719127
AT		 659
660 ctx->load_mmrs = true;
661}
662
663/*
664 * Set the shadow registers that are modified when the source
665 * format changes.
666 */
667static void set_src_registers(struct vpe_ctx *ctx)
668{
669 set_us_coefficients(ctx);
670}
671
672/*
673 * Set the shadow registers that are modified when the destination
674 * format changes.
675 */
676static void set_dst_registers(struct vpe_ctx *ctx)
677{
678 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
679 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
680 u32 val = 0;
681
682 /* select RGB path when color space conversion is supported in future */
683 if (fmt->fourcc == V4L2_PIX_FMT_RGB24)
684 val |= VPE_RGB_OUT_SELECT | VPE_CSC_SRC_DEI_SCALER;
685 else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
686 val |= VPE_COLOR_SEPARATE_422;
687
688 /* The source of CHR_DS is always the scaler, whether it's used or not */
689 val |= VPE_DS_SRC_DEI_SCALER;
690
691 if (fmt->fourcc != V4L2_PIX_FMT_NV12)
692 val |= VPE_DS_BYPASS;
693
694 mmr_adb->out_fmt_reg[0] = val;
695
696 ctx->load_mmrs = true;
697}
698
699/*
700 * Set the de-interlacer shadow register values
701 */
585e6f01 702static void set_dei_regs(struct vpe_ctx *ctx)
45719127
AT		 703{
704 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
705 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
706 unsigned int src_h = s_q_data->c_rect.height;
707 unsigned int src_w = s_q_data->c_rect.width;
708 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
585e6f01 709 bool deinterlace = true;
45719127
AT		 710 u32 val = 0;
711
712 /*
713 * according to TRM, we should set DEI in progressive bypass mode when
714 * the input content is progressive, however, DEI is bypassed correctly
715 * for both progressive and interlace content in interlace bypass mode.
716 * It has been recommended not to use progressive bypass mode.
717 */
585e6f01
AT		 718 if ((!ctx->deinterlacing && (s_q_data->flags & Q_DATA_INTERLACED)) ||
719 !(s_q_data->flags & Q_DATA_INTERLACED)) {
720 deinterlace = false;
721 val = VPE_DEI_INTERLACE_BYPASS;
722 }
723
724 src_h = deinterlace ? src_h * 2 : src_h;
45719127
AT		 725
726 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
727 (src_w << VPE_DEI_WIDTH_SHIFT) |
728 VPE_DEI_FIELD_FLUSH;
729
730 *dei_mmr0 = val;
731
732 ctx->load_mmrs = true;
733}
734
585e6f01
AT		 735static void set_dei_shadow_registers(struct vpe_ctx *ctx)
736{
737 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
738 u32 *dei_mmr = &mmr_adb->dei_regs[0];
739 const struct vpe_dei_regs *cur = &dei_regs;
740
741 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
742 dei_mmr[3] = cur->edi_config_reg;
743 dei_mmr[4] = cur->edi_lut_reg0;
744 dei_mmr[5] = cur->edi_lut_reg1;
745 dei_mmr[6] = cur->edi_lut_reg2;
746 dei_mmr[7] = cur->edi_lut_reg3;
747
748 ctx->load_mmrs = true;
749}
750
45719127
AT		 751static void set_csc_coeff_bypass(struct vpe_ctx *ctx)
752{
753 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
754 u32 *shadow_csc_reg5 = &mmr_adb->csc_regs[5];
755
756 *shadow_csc_reg5 |= VPE_CSC_BYPASS;
757
758 ctx->load_mmrs = true;
759}
760
45719127
AT		 761/*
762 * Set the shadow registers whose values are modified when either the
763 * source or destination format is changed.
764 */
765static int set_srcdst_params(struct vpe_ctx *ctx)
766{
585e6f01
AT		 767 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
768 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
44687b2e 769 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
773f0657
AT		 770 unsigned int src_w = s_q_data->c_rect.width;
771 unsigned int src_h = s_q_data->c_rect.height;
772 unsigned int dst_w = d_q_data->c_rect.width;
773 unsigned int dst_h = d_q_data->c_rect.height;
585e6f01
AT		 774 size_t mv_buf_size;
775 int ret;
776
45719127 777 ctx->sequence = 0;
585e6f01
AT		 778 ctx->field = V4L2_FIELD_TOP;
779
780 if ((s_q_data->flags & Q_DATA_INTERLACED) &&
781 !(d_q_data->flags & Q_DATA_INTERLACED)) {
a51cd8f5 782 int bytes_per_line;
585e6f01
AT		 783 const struct vpdma_data_format *mv =
784 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
785
a51cd8f5
AT		 786 /*
787 * we make sure that the source image has a 16 byte aligned
788 * stride, we need to do the same for the motion vector buffer
789 * by aligning it's stride to the next 16 byte boundry. this
790 * extra space will not be used by the de-interlacer, but will
791 * ensure that vpdma operates correctly
792 */
793 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
794 VPDMA_STRIDE_ALIGN);
795 mv_buf_size = bytes_per_line * s_q_data->height;
773f0657
AT		 796
797 ctx->deinterlacing = 1;
798 src_h <<= 1;
585e6f01
AT		 799 } else {
800 ctx->deinterlacing = 0;
801 mv_buf_size = 0;
802 }
803
804 free_vbs(ctx);
805
806 ret = realloc_mv_buffers(ctx, mv_buf_size);
807 if (ret)
808 return ret;
45719127
AT		 809
810 set_cfg_and_line_modes(ctx);
585e6f01 811 set_dei_regs(ctx);
45719127 812 set_csc_coeff_bypass(ctx);
773f0657
AT		 813 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
814 sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
44687b2e 815 sc_set_regs_bypass(ctx->dev->sc, &mmr_adb->sc_regs[0]);
45719127
AT		 816
817 return 0;
818}
819
820/*
821 * Return the vpe_ctx structure for a given struct file
822 */
823static struct vpe_ctx *file2ctx(struct file *file)
824{
825 return container_of(file->private_data, struct vpe_ctx, fh);
826}
827
828/*
829 * mem2mem callbacks
830 */
831
832/**
833 * job_ready() - check whether an instance is ready to be scheduled to run
834 */
835static int job_ready(void *priv)
836{
837 struct vpe_ctx *ctx = priv;
838 int needed = ctx->bufs_per_job;
839
585e6f01
AT		 840 if (ctx->deinterlacing && ctx->src_vbs[2] == NULL)
841 needed += 2; /* need additional two most recent fields */
842
45719127
AT		 843 if (v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) < needed)
844 return 0;
845
846 return 1;
847}
848
849static void job_abort(void *priv)
850{
851 struct vpe_ctx *ctx = priv;
852
853 /* Will cancel the transaction in the next interrupt handler */
854 ctx->aborting = 1;
855}
856
857/*
858 * Lock access to the device
859 */
860static void vpe_lock(void *priv)
861{
862 struct vpe_ctx *ctx = priv;
863 struct vpe_dev *dev = ctx->dev;
864 mutex_lock(&dev->dev_mutex);
865}
866
867static void vpe_unlock(void *priv)
868{
869 struct vpe_ctx *ctx = priv;
870 struct vpe_dev *dev = ctx->dev;
871 mutex_unlock(&dev->dev_mutex);
872}
873
874static void vpe_dump_regs(struct vpe_dev *dev)
875{
876#define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
877
878 vpe_dbg(dev, "VPE Registers:\n");
879
880 DUMPREG(PID);
881 DUMPREG(SYSCONFIG);
882 DUMPREG(INT0_STATUS0_RAW);
883 DUMPREG(INT0_STATUS0);
884 DUMPREG(INT0_ENABLE0);
885 DUMPREG(INT0_STATUS1_RAW);
886 DUMPREG(INT0_STATUS1);
887 DUMPREG(INT0_ENABLE1);
888 DUMPREG(CLK_ENABLE);
889 DUMPREG(CLK_RESET);
890 DUMPREG(CLK_FORMAT_SELECT);
891 DUMPREG(CLK_RANGE_MAP);
892 DUMPREG(US1_R0);
893 DUMPREG(US1_R1);
894 DUMPREG(US1_R2);
895 DUMPREG(US1_R3);
896 DUMPREG(US1_R4);
897 DUMPREG(US1_R5);
898 DUMPREG(US1_R6);
899 DUMPREG(US1_R7);
900 DUMPREG(US2_R0);
901 DUMPREG(US2_R1);
902 DUMPREG(US2_R2);
903 DUMPREG(US2_R3);
904 DUMPREG(US2_R4);
905 DUMPREG(US2_R5);
906 DUMPREG(US2_R6);
907 DUMPREG(US2_R7);
908 DUMPREG(US3_R0);
909 DUMPREG(US3_R1);
910 DUMPREG(US3_R2);
911 DUMPREG(US3_R3);
912 DUMPREG(US3_R4);
913 DUMPREG(US3_R5);
914 DUMPREG(US3_R6);
915 DUMPREG(US3_R7);
916 DUMPREG(DEI_FRAME_SIZE);
917 DUMPREG(MDT_BYPASS);
918 DUMPREG(MDT_SF_THRESHOLD);
919 DUMPREG(EDI_CONFIG);
920 DUMPREG(DEI_EDI_LUT_R0);
921 DUMPREG(DEI_EDI_LUT_R1);
922 DUMPREG(DEI_EDI_LUT_R2);
923 DUMPREG(DEI_EDI_LUT_R3);
924 DUMPREG(DEI_FMD_WINDOW_R0);
925 DUMPREG(DEI_FMD_WINDOW_R1);
926 DUMPREG(DEI_FMD_CONTROL_R0);
927 DUMPREG(DEI_FMD_CONTROL_R1);
928 DUMPREG(DEI_FMD_STATUS_R0);
929 DUMPREG(DEI_FMD_STATUS_R1);
930 DUMPREG(DEI_FMD_STATUS_R2);
45719127
AT		 931 DUMPREG(CSC_CSC00);
932 DUMPREG(CSC_CSC01);
933 DUMPREG(CSC_CSC02);
934 DUMPREG(CSC_CSC03);
935 DUMPREG(CSC_CSC04);
936 DUMPREG(CSC_CSC05);
937#undef DUMPREG
44687b2e
AT		 938
939 sc_dump_regs(dev->sc);
45719127
AT		 940}
941
942static void add_out_dtd(struct vpe_ctx *ctx, int port)
943{
944 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
945 const struct vpe_port_data *p_data = &port_data[port];
946 struct vb2_buffer *vb = ctx->dst_vb;
947 struct v4l2_rect *c_rect = &q_data->c_rect;
948 struct vpe_fmt *fmt = q_data->fmt;
949 const struct vpdma_data_format *vpdma_fmt;
585e6f01 950 int mv_buf_selector = !ctx->src_mv_buf_selector;
45719127
AT		 951 dma_addr_t dma_addr;
952 u32 flags = 0;
953
585e6f01
AT		 954 if (port == VPE_PORT_MV_OUT) {
955 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
956 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
957 } else {
958 /* to incorporate interleaved formats */
959 int plane = fmt->coplanar ? p_data->vb_part : 0;
960
961 vpdma_fmt = fmt->vpdma_fmt[plane];
962 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
963 if (!dma_addr) {
964 vpe_err(ctx->dev,
965 "acquiring output buffer(%d) dma_addr failed\n",
966 port);
967 return;
968 }
45719127
AT		 969 }
970
971 if (q_data->flags & Q_DATA_FRAME_1D)
972 flags |= VPDMA_DATA_FRAME_1D;
973 if (q_data->flags & Q_DATA_MODE_TILED)
974 flags |= VPDMA_DATA_MODE_TILED;
975
976 vpdma_add_out_dtd(&ctx->desc_list, c_rect, vpdma_fmt, dma_addr,
977 p_data->channel, flags);
978}
979
980static void add_in_dtd(struct vpe_ctx *ctx, int port)
981{
982 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
983 const struct vpe_port_data *p_data = &port_data[port];
585e6f01 984 struct vb2_buffer *vb = ctx->src_vbs[p_data->vb_index];
45719127
AT		 985 struct v4l2_rect *c_rect = &q_data->c_rect;
986 struct vpe_fmt *fmt = q_data->fmt;
987 const struct vpdma_data_format *vpdma_fmt;
585e6f01
AT		 988 int mv_buf_selector = ctx->src_mv_buf_selector;
989 int field = vb->v4l2_buf.field == V4L2_FIELD_BOTTOM;
45719127
AT		 990 dma_addr_t dma_addr;
991 u32 flags = 0;
992
585e6f01
AT		 993 if (port == VPE_PORT_MV_IN) {
994 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
995 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
996 } else {
997 /* to incorporate interleaved formats */
998 int plane = fmt->coplanar ? p_data->vb_part : 0;
45719127 999
585e6f01
AT		 1000 vpdma_fmt = fmt->vpdma_fmt[plane];
1001
1002 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1003 if (!dma_addr) {
1004 vpe_err(ctx->dev,
1005 "acquiring input buffer(%d) dma_addr failed\n",
1006 port);
1007 return;
1008 }
45719127
AT		 1009 }
1010
1011 if (q_data->flags & Q_DATA_FRAME_1D)
1012 flags |= VPDMA_DATA_FRAME_1D;
1013 if (q_data->flags & Q_DATA_MODE_TILED)
1014 flags |= VPDMA_DATA_MODE_TILED;
1015
1016 vpdma_add_in_dtd(&ctx->desc_list, q_data->width, q_data->height,
1017 c_rect, vpdma_fmt, dma_addr, p_data->channel, field, flags);
1018}
1019
1020/*
1021 * Enable the expected IRQ sources
1022 */
1023static void enable_irqs(struct vpe_ctx *ctx)
1024{
1025 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
585e6f01
AT		 1026 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1027 VPE_DS1_UV_ERROR_INT);
45719127
AT		 1028
1029 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, true);
1030}
1031
1032static void disable_irqs(struct vpe_ctx *ctx)
1033{
1034 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1035 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1036
1037 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, false);
1038}
1039
1040/* device_run() - prepares and starts the device
1041 *
1042 * This function is only called when both the source and destination
1043 * buffers are in place.
1044 */
1045static void device_run(void *priv)
1046{
1047 struct vpe_ctx *ctx = priv;
773f0657 1048 struct sc_data *sc = ctx->dev->sc;
45719127
AT		 1049 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1050
585e6f01
AT		 1051 if (ctx->deinterlacing && ctx->src_vbs[2] == NULL) {
1052 ctx->src_vbs[2] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1053 WARN_ON(ctx->src_vbs[2] == NULL);
1054 ctx->src_vbs[1] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1055 WARN_ON(ctx->src_vbs[1] == NULL);
1056 }
1057
1058 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1059 WARN_ON(ctx->src_vbs[0] == NULL);
45719127
AT		 1060 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
1061 WARN_ON(ctx->dst_vb == NULL);
1062
1063 /* config descriptors */
1064 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1065 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1066 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1067 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1068 ctx->load_mmrs = false;
1069 }
1070
773f0657
AT		 1071 if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1072 sc->load_coeff_h) {
1073 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1074 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1075 &ctx->sc_coeff_h, 0);
1076
1077 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1078 sc->load_coeff_h = false;
1079 }
1080
1081 if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1082 sc->load_coeff_v) {
1083 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1084 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1085 &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1086
1087 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1088 sc->load_coeff_v = false;
1089 }
1090
585e6f01
AT		 1091 /* output data descriptors */
1092 if (ctx->deinterlacing)
1093 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1094
45719127
AT		 1095 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1096 if (d_q_data->fmt->coplanar)
1097 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1098
585e6f01
AT		 1099 /* input data descriptors */
1100 if (ctx->deinterlacing) {
1101 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1102 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1103
1104 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1105 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1106 }
1107
45719127
AT		 1108 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1109 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1110
585e6f01
AT		 1111 if (ctx->deinterlacing)
1112 add_in_dtd(ctx, VPE_PORT_MV_IN);
1113
45719127
AT		 1114 /* sync on channel control descriptors for input ports */
1115 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1116 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1117
585e6f01
AT		 1118 if (ctx->deinterlacing) {
1119 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1120 VPE_CHAN_LUMA2_IN);
1121 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1122 VPE_CHAN_CHROMA2_IN);
1123
1124 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1125 VPE_CHAN_LUMA3_IN);
1126 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1127 VPE_CHAN_CHROMA3_IN);
1128
1129 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1130 }
1131
45719127
AT		 1132 /* sync on channel control descriptors for output ports */
1133 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA_OUT);
1134 if (d_q_data->fmt->coplanar)
1135 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA_OUT);
1136
585e6f01
AT		 1137 if (ctx->deinterlacing)
1138 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1139
45719127
AT		 1140 enable_irqs(ctx);
1141
1142 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1143 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list);
1144}
1145
585e6f01
AT		 1146static void dei_error(struct vpe_ctx *ctx)
1147{
1148 dev_warn(ctx->dev->v4l2_dev.dev,
1149 "received DEI error interrupt\n");
1150}
1151
45719127
AT		 1152static void ds1_uv_error(struct vpe_ctx *ctx)
1153{
1154 dev_warn(ctx->dev->v4l2_dev.dev,
1155 "received downsampler error interrupt\n");
1156}
1157
1158static irqreturn_t vpe_irq(int irq_vpe, void *data)
1159{
1160 struct vpe_dev *dev = (struct vpe_dev *)data;
1161 struct vpe_ctx *ctx;
585e6f01 1162 struct vpe_q_data *d_q_data;
45719127
AT		 1163 struct vb2_buffer *s_vb, *d_vb;
1164 struct v4l2_buffer *s_buf, *d_buf;
1165 unsigned long flags;
1166 u32 irqst0, irqst1;
1167
1168 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1169 if (irqst0) {
1170 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1171 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1172 }
1173
1174 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1175 if (irqst1) {
1176 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1177 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1178 }
1179
1180 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1181 if (!ctx) {
1182 vpe_err(dev, "instance released before end of transaction\n");
1183 goto handled;
1184 }
1185
585e6f01
AT		 1186 if (irqst1) {
1187 if (irqst1 & VPE_DEI_ERROR_INT) {
1188 irqst1 &= ~VPE_DEI_ERROR_INT;
1189 dei_error(ctx);
1190 }
1191 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1192 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1193 ds1_uv_error(ctx);
1194 }
45719127
AT		 1195 }
1196
1197 if (irqst0) {
1198 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1199 vpdma_clear_list_stat(ctx->dev->vpdma);
1200
1201 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1202 }
1203
1204 if (irqst0 | irqst1) {
1205 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: "
1206 "INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1207 irqst0, irqst1);
1208 }
1209
1210 disable_irqs(ctx);
1211
1212 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1213 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
773f0657
AT		 1214 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1215 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
45719127
AT		 1216
1217 vpdma_reset_desc_list(&ctx->desc_list);
1218
585e6f01
AT		 1219 /* the previous dst mv buffer becomes the next src mv buffer */
1220 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1221
45719127
AT		 1222 if (ctx->aborting)
1223 goto finished;
1224
585e6f01 1225 s_vb = ctx->src_vbs[0];
45719127
AT		 1226 d_vb = ctx->dst_vb;
1227 s_buf = &s_vb->v4l2_buf;
1228 d_buf = &d_vb->v4l2_buf;
1229
1230 d_buf->timestamp = s_buf->timestamp;
1231 if (s_buf->flags & V4L2_BUF_FLAG_TIMECODE) {
1232 d_buf->flags |= V4L2_BUF_FLAG_TIMECODE;
1233 d_buf->timecode = s_buf->timecode;
1234 }
45719127 1235 d_buf->sequence = ctx->sequence;
585e6f01
AT		 1236 d_buf->field = ctx->field;
1237
1238 d_q_data = &ctx->q_data[Q_DATA_DST];
1239 if (d_q_data->flags & Q_DATA_INTERLACED) {
1240 if (ctx->field == V4L2_FIELD_BOTTOM) {
1241 ctx->sequence++;
1242 ctx->field = V4L2_FIELD_TOP;
1243 } else {
1244 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1245 ctx->field = V4L2_FIELD_BOTTOM;
1246 }
1247 } else {
1248 ctx->sequence++;
1249 }
45719127 1250
585e6f01
AT		 1251 if (ctx->deinterlacing)
1252 s_vb = ctx->src_vbs[2];
45719127
AT		 1253
1254 spin_lock_irqsave(&dev->lock, flags);
1255 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1256 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1257 spin_unlock_irqrestore(&dev->lock, flags);
1258
585e6f01
AT		 1259 if (ctx->deinterlacing) {
1260 ctx->src_vbs[2] = ctx->src_vbs[1];
1261 ctx->src_vbs[1] = ctx->src_vbs[0];
1262 }
1263
45719127
AT		 1264 ctx->bufs_completed++;
1265 if (ctx->bufs_completed < ctx->bufs_per_job) {
1266 device_run(ctx);
1267 goto handled;
1268 }
1269
1270finished:
1271 vpe_dbg(ctx->dev, "finishing transaction\n");
1272 ctx->bufs_completed = 0;
1273 v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
1274handled:
1275 return IRQ_HANDLED;
1276}
1277
1278/*
1279 * video ioctls
1280 */
1281static int vpe_querycap(struct file *file, void *priv,
1282 struct v4l2_capability *cap)
1283{
1284 strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
1285 strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
1286 strlcpy(cap->bus_info, VPE_MODULE_NAME, sizeof(cap->bus_info));
1287 cap->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
1288 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1289 return 0;
1290}
1291
1292static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1293{
1294 int i, index;
1295 struct vpe_fmt *fmt = NULL;
1296
1297 index = 0;
1298 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1299 if (vpe_formats[i].types & type) {
1300 if (index == f->index) {
1301 fmt = &vpe_formats[i];
1302 break;
1303 }
1304 index++;
1305 }
1306 }
1307
1308 if (!fmt)
1309 return -EINVAL;
1310
1311 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
1312 f->pixelformat = fmt->fourcc;
1313 return 0;
1314}
1315
1316static int vpe_enum_fmt(struct file *file, void *priv,
1317 struct v4l2_fmtdesc *f)
1318{
1319 if (V4L2_TYPE_IS_OUTPUT(f->type))
1320 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1321
1322 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1323}
1324
1325static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1326{
1327 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1328 struct vpe_ctx *ctx = file2ctx(file);
1329 struct vb2_queue *vq;
1330 struct vpe_q_data *q_data;
1331 int i;
1332
1333 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1334 if (!vq)
1335 return -EINVAL;
1336
1337 q_data = get_q_data(ctx, f->type);
1338
1339 pix->width = q_data->width;
1340 pix->height = q_data->height;
1341 pix->pixelformat = q_data->fmt->fourcc;
585e6f01 1342 pix->field = q_data->field;
45719127
AT		 1343
1344 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1345 pix->colorspace = q_data->colorspace;
1346 } else {
1347 struct vpe_q_data *s_q_data;
1348
1349 /* get colorspace from the source queue */
1350 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1351
1352 pix->colorspace = s_q_data->colorspace;
1353 }
1354
1355 pix->num_planes = q_data->fmt->coplanar ? 2 : 1;
1356
1357 for (i = 0; i < pix->num_planes; i++) {
1358 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1359 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1360 }
1361
1362 return 0;
1363}
1364
1365static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1366 struct vpe_fmt *fmt, int type)
1367{
1368 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1369 struct v4l2_plane_pix_format *plane_fmt;
a51cd8f5
AT		 1370 unsigned int w_align;
1371 int i, depth, depth_bytes;
45719127
AT		 1372
1373 if (!fmt || !(fmt->types & type)) {
1374 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1375 pix->pixelformat);
1376 return -EINVAL;
1377 }
1378
585e6f01
AT		 1379 if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE)
1380 pix->field = V4L2_FIELD_NONE;
45719127 1381
a51cd8f5
AT		 1382 depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1383
1384 /*
1385 * the line stride should 16 byte aligned for VPDMA to work, based on
1386 * the bytes per pixel, figure out how much the width should be aligned
1387 * to make sure line stride is 16 byte aligned
1388 */
1389 depth_bytes = depth >> 3;
1390
1391 if (depth_bytes == 3)
1392 /*
1393 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1394 * really help in ensuring line stride is 16 byte aligned
1395 */
1396 w_align = 4;
1397 else
1398 /*
1399 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1400 * can ensure a line stride alignment of 16 bytes. For example,
1401 * if bpp is 2, then the line stride can be 16 byte aligned if
1402 * the width is 8 byte aligned
1403 */
1404 w_align = order_base_2(VPDMA_DESC_ALIGN / depth_bytes);
1405
1406 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
45719127
AT		 1407 &pix->height, MIN_H, MAX_H, H_ALIGN,
1408 S_ALIGN);
1409
1410 pix->num_planes = fmt->coplanar ? 2 : 1;
1411 pix->pixelformat = fmt->fourcc;
1412
1413 if (type == VPE_FMT_TYPE_CAPTURE) {
1414 struct vpe_q_data *s_q_data;
1415
1416 /* get colorspace from the source queue */
1417 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1418
1419 pix->colorspace = s_q_data->colorspace;
1420 } else {
1421 if (!pix->colorspace)
1422 pix->colorspace = V4L2_COLORSPACE_SMPTE240M;
1423 }
1424
1425 for (i = 0; i < pix->num_planes; i++) {
45719127
AT		 1426 plane_fmt = &pix->plane_fmt[i];
1427 depth = fmt->vpdma_fmt[i]->depth;
1428
1429 if (i == VPE_LUMA)
a51cd8f5 1430 plane_fmt->bytesperline = (pix->width * depth) >> 3;
45719127
AT		 1431 else
1432 plane_fmt->bytesperline = pix->width;
1433
1434 plane_fmt->sizeimage =
1435 (pix->height * pix->width * depth) >> 3;
1436 }
1437
1438 return 0;
1439}
1440
1441static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1442{
1443 struct vpe_ctx *ctx = file2ctx(file);
1444 struct vpe_fmt *fmt = find_format(f);
1445
1446 if (V4L2_TYPE_IS_OUTPUT(f->type))
1447 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1448 else
1449 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1450}
1451
1452static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1453{
1454 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1455 struct v4l2_plane_pix_format *plane_fmt;
1456 struct vpe_q_data *q_data;
1457 struct vb2_queue *vq;
1458 int i;
1459
1460 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1461 if (!vq)
1462 return -EINVAL;
1463
1464 if (vb2_is_busy(vq)) {
1465 vpe_err(ctx->dev, "queue busy\n");
1466 return -EBUSY;
1467 }
1468
1469 q_data = get_q_data(ctx, f->type);
1470 if (!q_data)
1471 return -EINVAL;
1472
1473 q_data->fmt = find_format(f);
1474 q_data->width = pix->width;
1475 q_data->height = pix->height;
1476 q_data->colorspace = pix->colorspace;
585e6f01 1477 q_data->field = pix->field;
45719127
AT		 1478
1479 for (i = 0; i < pix->num_planes; i++) {
1480 plane_fmt = &pix->plane_fmt[i];
1481
1482 q_data->bytesperline[i] = plane_fmt->bytesperline;
1483 q_data->sizeimage[i] = plane_fmt->sizeimage;
1484 }
1485
1486 q_data->c_rect.left = 0;
1487 q_data->c_rect.top = 0;
1488 q_data->c_rect.width = q_data->width;
1489 q_data->c_rect.height = q_data->height;
1490
585e6f01
AT		 1491 if (q_data->field == V4L2_FIELD_ALTERNATE)
1492 q_data->flags |= Q_DATA_INTERLACED;
1493 else
1494 q_data->flags &= ~Q_DATA_INTERLACED;
1495
45719127
AT		 1496 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1497 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1498 q_data->bytesperline[VPE_LUMA]);
1499 if (q_data->fmt->coplanar)
1500 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1501 q_data->bytesperline[VPE_CHROMA]);
1502
1503 return 0;
1504}
1505
1506static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1507{
1508 int ret;
1509 struct vpe_ctx *ctx = file2ctx(file);
1510
1511 ret = vpe_try_fmt(file, priv, f);
1512 if (ret)
1513 return ret;
1514
1515 ret = __vpe_s_fmt(ctx, f);
1516 if (ret)
1517 return ret;
1518
1519 if (V4L2_TYPE_IS_OUTPUT(f->type))
1520 set_src_registers(ctx);
1521 else
1522 set_dst_registers(ctx);
1523
1524 return set_srcdst_params(ctx);
1525}
1526
1527static int vpe_reqbufs(struct file *file, void *priv,
1528 struct v4l2_requestbuffers *reqbufs)
1529{
1530 struct vpe_ctx *ctx = file2ctx(file);
1531
1532 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1533}
1534
1535static int vpe_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1536{
1537 struct vpe_ctx *ctx = file2ctx(file);
1538
1539 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1540}
1541
1542static int vpe_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1543{
1544 struct vpe_ctx *ctx = file2ctx(file);
1545
1546 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1547}
1548
1549static int vpe_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1550{
1551 struct vpe_ctx *ctx = file2ctx(file);
1552
1553 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1554}
1555
1556static int vpe_streamon(struct file *file, void *priv, enum v4l2_buf_type type)
1557{
1558 struct vpe_ctx *ctx = file2ctx(file);
1559
1560 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1561}
1562
1563static int vpe_streamoff(struct file *file, void *priv, enum v4l2_buf_type type)
1564{
1565 struct vpe_ctx *ctx = file2ctx(file);
1566
1567 vpe_dump_regs(ctx->dev);
1568 vpdma_dump_regs(ctx->dev->vpdma);
1569
1570 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1571}
1572
1573/*
1574 * defines number of buffers/frames a context can process with VPE before
1575 * switching to a different context. default value is 1 buffer per context
1576 */
1577#define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1578
1579static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1580{
1581 struct vpe_ctx *ctx =
1582 container_of(ctrl->handler, struct vpe_ctx, hdl);
1583
1584 switch (ctrl->id) {
1585 case V4L2_CID_VPE_BUFS_PER_JOB:
1586 ctx->bufs_per_job = ctrl->val;
1587 break;
1588
1589 default:
1590 vpe_err(ctx->dev, "Invalid control\n");
1591 return -EINVAL;
1592 }
1593
1594 return 0;
1595}
1596
1597static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1598 .s_ctrl = vpe_s_ctrl,
1599};
1600
1601static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1602 .vidioc_querycap = vpe_querycap,
1603
1604 .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
1605 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
1606 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
1607 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
1608
1609 .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
1610 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
1611 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
1612 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
1613
1614 .vidioc_reqbufs = vpe_reqbufs,
1615 .vidioc_querybuf = vpe_querybuf,
1616
1617 .vidioc_qbuf = vpe_qbuf,
1618 .vidioc_dqbuf = vpe_dqbuf,
1619
1620 .vidioc_streamon = vpe_streamon,
1621 .vidioc_streamoff = vpe_streamoff,
1622 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1623 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1624};
1625
1626/*
1627 * Queue operations
1628 */
1629static int vpe_queue_setup(struct vb2_queue *vq,
1630 const struct v4l2_format *fmt,
1631 unsigned int *nbuffers, unsigned int *nplanes,
1632 unsigned int sizes[], void *alloc_ctxs[])
1633{
1634 int i;
1635 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
1636 struct vpe_q_data *q_data;
1637
1638 q_data = get_q_data(ctx, vq->type);
1639
1640 *nplanes = q_data->fmt->coplanar ? 2 : 1;
1641
1642 for (i = 0; i < *nplanes; i++) {
1643 sizes[i] = q_data->sizeimage[i];
1644 alloc_ctxs[i] = ctx->dev->alloc_ctx;
1645 }
1646
1647 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
1648 sizes[VPE_LUMA]);
1649 if (q_data->fmt->coplanar)
1650 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
1651
1652 return 0;
1653}
1654
1655static int vpe_buf_prepare(struct vb2_buffer *vb)
1656{
1657 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1658 struct vpe_q_data *q_data;
1659 int i, num_planes;
1660
1661 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1662
1663 q_data = get_q_data(ctx, vb->vb2_queue->type);
1664 num_planes = q_data->fmt->coplanar ? 2 : 1;
1665
1666 for (i = 0; i < num_planes; i++) {
1667 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
1668 vpe_err(ctx->dev,
1669 "data will not fit into plane (%lu < %lu)\n",
1670 vb2_plane_size(vb, i),
1671 (long) q_data->sizeimage[i]);
1672 return -EINVAL;
1673 }
1674 }
1675
1676 for (i = 0; i < num_planes; i++)
1677 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
1678
1679 return 0;
1680}
1681
1682static void vpe_buf_queue(struct vb2_buffer *vb)
1683{
1684 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1685 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
1686}
1687
1688static void vpe_wait_prepare(struct vb2_queue *q)
1689{
1690 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
1691 vpe_unlock(ctx);
1692}
1693
1694static void vpe_wait_finish(struct vb2_queue *q)
1695{
1696 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
1697 vpe_lock(ctx);
1698}
1699
1700static struct vb2_ops vpe_qops = {
1701 .queue_setup = vpe_queue_setup,
1702 .buf_prepare = vpe_buf_prepare,
1703 .buf_queue = vpe_buf_queue,
1704 .wait_prepare = vpe_wait_prepare,
1705 .wait_finish = vpe_wait_finish,
1706};
1707
1708static int queue_init(void *priv, struct vb2_queue *src_vq,
1709 struct vb2_queue *dst_vq)
1710{
1711 struct vpe_ctx *ctx = priv;
1712 int ret;
1713
1714 memset(src_vq, 0, sizeof(*src_vq));
1715 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1716 src_vq->io_modes = VB2_MMAP;
1717 src_vq->drv_priv = ctx;
1718 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1719 src_vq->ops = &vpe_qops;
1720 src_vq->mem_ops = &vb2_dma_contig_memops;
1721 src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1722
1723 ret = vb2_queue_init(src_vq);
1724 if (ret)
1725 return ret;
1726
1727 memset(dst_vq, 0, sizeof(*dst_vq));
1728 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1729 dst_vq->io_modes = VB2_MMAP;
1730 dst_vq->drv_priv = ctx;
1731 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1732 dst_vq->ops = &vpe_qops;
1733 dst_vq->mem_ops = &vb2_dma_contig_memops;
1734 dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1735
1736 return vb2_queue_init(dst_vq);
1737}
1738
1739static const struct v4l2_ctrl_config vpe_bufs_per_job = {
1740 .ops = &vpe_ctrl_ops,
1741 .id = V4L2_CID_VPE_BUFS_PER_JOB,
1742 .name = "Buffers Per Transaction",
1743 .type = V4L2_CTRL_TYPE_INTEGER,
1744 .def = VPE_DEF_BUFS_PER_JOB,
1745 .min = 1,
1746 .max = VIDEO_MAX_FRAME,
1747 .step = 1,
1748};
1749
1750/*
1751 * File operations
1752 */
1753static int vpe_open(struct file *file)
1754{
1755 struct vpe_dev *dev = video_drvdata(file);
1756 struct vpe_ctx *ctx = NULL;
1757 struct vpe_q_data *s_q_data;
1758 struct v4l2_ctrl_handler *hdl;
1759 int ret;
1760
1761 vpe_dbg(dev, "vpe_open\n");
1762
1763 if (!dev->vpdma->ready) {
1764 vpe_err(dev, "vpdma firmware not loaded\n");
1765 return -ENODEV;
1766 }
1767
1768 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1769 if (!ctx)
1770 return -ENOMEM;
1771
1772 ctx->dev = dev;
1773
1774 if (mutex_lock_interruptible(&dev->dev_mutex)) {
1775 ret = -ERESTARTSYS;
1776 goto free_ctx;
1777 }
1778
1779 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
1780 VPDMA_LIST_TYPE_NORMAL);
1781 if (ret != 0)
1782 goto unlock;
1783
1784 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
1785 if (ret != 0)
1786 goto free_desc_list;
1787
773f0657
AT		 1788 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
1789 if (ret != 0)
1790 goto free_mmr_adb;
1791
1792 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
1793 if (ret != 0)
1794 goto free_sc_h;
1795
45719127
AT		 1796 init_adb_hdrs(ctx);
1797
1798 v4l2_fh_init(&ctx->fh, video_devdata(file));
1799 file->private_data = &ctx->fh;
1800
1801 hdl = &ctx->hdl;
1802 v4l2_ctrl_handler_init(hdl, 1);
1803 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
1804 if (hdl->error) {
1805 ret = hdl->error;
1806 goto exit_fh;
1807 }
1808 ctx->fh.ctrl_handler = hdl;
1809 v4l2_ctrl_handler_setup(hdl);
1810
1811 s_q_data = &ctx->q_data[Q_DATA_SRC];
1812 s_q_data->fmt = &vpe_formats[2];
1813 s_q_data->width = 1920;
1814 s_q_data->height = 1080;
1815 s_q_data->sizeimage[VPE_LUMA] = (s_q_data->width * s_q_data->height *
1816 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
1817 s_q_data->colorspace = V4L2_COLORSPACE_SMPTE240M;
585e6f01 1818 s_q_data->field = V4L2_FIELD_NONE;
45719127
AT		 1819 s_q_data->c_rect.left = 0;
1820 s_q_data->c_rect.top = 0;
1821 s_q_data->c_rect.width = s_q_data->width;
1822 s_q_data->c_rect.height = s_q_data->height;
1823 s_q_data->flags = 0;
1824
1825 ctx->q_data[Q_DATA_DST] = *s_q_data;
1826
585e6f01 1827 set_dei_shadow_registers(ctx);
45719127
AT		 1828 set_src_registers(ctx);
1829 set_dst_registers(ctx);
1830 ret = set_srcdst_params(ctx);
1831 if (ret)
1832 goto exit_fh;
1833
1834 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
1835
1836 if (IS_ERR(ctx->m2m_ctx)) {
1837 ret = PTR_ERR(ctx->m2m_ctx);
1838 goto exit_fh;
1839 }
1840
1841 v4l2_fh_add(&ctx->fh);
1842
1843 /*
1844 * for now, just report the creation of the first instance, we can later
1845 * optimize the driver to enable or disable clocks when the first
1846 * instance is created or the last instance released
1847 */
1848 if (atomic_inc_return(&dev->num_instances) == 1)
1849 vpe_dbg(dev, "first instance created\n");
1850
1851 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
1852
1853 ctx->load_mmrs = true;
1854
1855 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
1856 ctx, ctx->m2m_ctx);
1857
1858 mutex_unlock(&dev->dev_mutex);
1859
1860 return 0;
1861exit_fh:
1862 v4l2_ctrl_handler_free(hdl);
1863 v4l2_fh_exit(&ctx->fh);
773f0657
AT		 1864 vpdma_free_desc_buf(&ctx->sc_coeff_v);
1865free_sc_h:
1866 vpdma_free_desc_buf(&ctx->sc_coeff_h);
1867free_mmr_adb:
45719127
AT		 1868 vpdma_free_desc_buf(&ctx->mmr_adb);
1869free_desc_list:
1870 vpdma_free_desc_list(&ctx->desc_list);
1871unlock:
1872 mutex_unlock(&dev->dev_mutex);
1873free_ctx:
1874 kfree(ctx);
1875 return ret;
1876}
1877
1878static int vpe_release(struct file *file)
1879{
1880 struct vpe_dev *dev = video_drvdata(file);
1881 struct vpe_ctx *ctx = file2ctx(file);
1882
1883 vpe_dbg(dev, "releasing instance %p\n", ctx);
1884
1885 mutex_lock(&dev->dev_mutex);
585e6f01
AT		 1886 free_vbs(ctx);
1887 free_mv_buffers(ctx);
45719127
AT		 1888 vpdma_free_desc_list(&ctx->desc_list);
1889 vpdma_free_desc_buf(&ctx->mmr_adb);
1890
1891 v4l2_fh_del(&ctx->fh);
1892 v4l2_fh_exit(&ctx->fh);
1893 v4l2_ctrl_handler_free(&ctx->hdl);
1894 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1895
1896 kfree(ctx);
1897
1898 /*
1899 * for now, just report the release of the last instance, we can later
1900 * optimize the driver to enable or disable clocks when the first
1901 * instance is created or the last instance released
1902 */
1903 if (atomic_dec_return(&dev->num_instances) == 0)
1904 vpe_dbg(dev, "last instance released\n");
1905
1906 mutex_unlock(&dev->dev_mutex);
1907
1908 return 0;
1909}
1910
1911static unsigned int vpe_poll(struct file *file,
1912 struct poll_table_struct *wait)
1913{
1914 struct vpe_ctx *ctx = file2ctx(file);
1915 struct vpe_dev *dev = ctx->dev;
1916 int ret;
1917
1918 mutex_lock(&dev->dev_mutex);
1919 ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1920 mutex_unlock(&dev->dev_mutex);
1921 return ret;
1922}
1923
1924static int vpe_mmap(struct file *file, struct vm_area_struct *vma)
1925{
1926 struct vpe_ctx *ctx = file2ctx(file);
1927 struct vpe_dev *dev = ctx->dev;
1928 int ret;
1929
1930 if (mutex_lock_interruptible(&dev->dev_mutex))
1931 return -ERESTARTSYS;
1932 ret = v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1933 mutex_unlock(&dev->dev_mutex);
1934 return ret;
1935}
1936
1937static const struct v4l2_file_operations vpe_fops = {
1938 .owner = THIS_MODULE,
1939 .open = vpe_open,
1940 .release = vpe_release,
1941 .poll = vpe_poll,
1942 .unlocked_ioctl = video_ioctl2,
1943 .mmap = vpe_mmap,
1944};
1945
1946static struct video_device vpe_videodev = {
1947 .name = VPE_MODULE_NAME,
1948 .fops = &vpe_fops,
1949 .ioctl_ops = &vpe_ioctl_ops,
1950 .minor = -1,
1951 .release = video_device_release,
1952 .vfl_dir = VFL_DIR_M2M,
1953};
1954
1955static struct v4l2_m2m_ops m2m_ops = {
1956 .device_run = device_run,
1957 .job_ready = job_ready,
1958 .job_abort = job_abort,
1959 .lock = vpe_lock,
1960 .unlock = vpe_unlock,
1961};
1962
1963static int vpe_runtime_get(struct platform_device *pdev)
1964{
1965 int r;
1966
1967 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
1968
1969 r = pm_runtime_get_sync(&pdev->dev);
1970 WARN_ON(r < 0);
1971 return r < 0 ? r : 0;
1972}
1973
1974static void vpe_runtime_put(struct platform_device *pdev)
1975{
1976
1977 int r;
1978
1979 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
1980
1981 r = pm_runtime_put_sync(&pdev->dev);
1982 WARN_ON(r < 0 && r != -ENOSYS);
1983}
1984
1985static int vpe_probe(struct platform_device *pdev)
1986{
1987 struct vpe_dev *dev;
1988 struct video_device *vfd;
45719127
AT		 1989 int ret, irq, func;
1990
1991 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
b68231a1
WY		 1992 if (!dev)
1993 return -ENOMEM;
45719127
AT		 1994
1995 spin_lock_init(&dev->lock);
1996
1997 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1998 if (ret)
1999 return ret;
2000
2001 atomic_set(&dev->num_instances, 0);
2002 mutex_init(&dev->dev_mutex);
2003
44687b2e
AT		 2004 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2005 "vpe_top");
45719127
AT		 2006 /*
2007 * HACK: we get resource info from device tree in the form of a list of
2008 * VPE sub blocks, the driver currently uses only the base of vpe_top
2009 * for register access, the driver should be changed later to access
2010 * registers based on the sub block base addresses
2011 */
44687b2e 2012 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
b68231a1
WY		 2013 if (!dev->base) {
2014 ret = -ENOMEM;
45719127
AT		 2015 goto v4l2_dev_unreg;
2016 }
2017
2018 irq = platform_get_irq(pdev, 0);
2019 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2020 dev);
2021 if (ret)
2022 goto v4l2_dev_unreg;
2023
2024 platform_set_drvdata(pdev, dev);
2025
2026 dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
2027 if (IS_ERR(dev->alloc_ctx)) {
2028 vpe_err(dev, "Failed to alloc vb2 context\n");
2029 ret = PTR_ERR(dev->alloc_ctx);
2030 goto v4l2_dev_unreg;
2031 }
2032
2033 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2034 if (IS_ERR(dev->m2m_dev)) {
2035 vpe_err(dev, "Failed to init mem2mem device\n");
2036 ret = PTR_ERR(dev->m2m_dev);
2037 goto rel_ctx;
2038 }
2039
2040 pm_runtime_enable(&pdev->dev);
2041
2042 ret = vpe_runtime_get(pdev);
2043 if (ret)
2044 goto rel_m2m;
2045
2046 /* Perform clk enable followed by reset */
2047 vpe_set_clock_enable(dev, 1);
2048
2049 vpe_top_reset(dev);
2050
2051 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2052 VPE_PID_FUNC_SHIFT);
2053 vpe_dbg(dev, "VPE PID function %x\n", func);
2054
2055 vpe_top_vpdma_reset(dev);
2056
44687b2e
AT		 2057 dev->sc = sc_create(pdev);
2058 if (IS_ERR(dev->sc)) {
2059 ret = PTR_ERR(dev->sc);
2060 goto runtime_put;
2061 }
2062
45719127 2063 dev->vpdma = vpdma_create(pdev);
6676cafe
WY		 2064 if (IS_ERR(dev->vpdma)) {
2065 ret = PTR_ERR(dev->vpdma);
45719127 2066 goto runtime_put;
6676cafe 2067 }
45719127
AT		 2068
2069 vfd = &dev->vfd;
2070 *vfd = vpe_videodev;
2071 vfd->lock = &dev->dev_mutex;
2072 vfd->v4l2_dev = &dev->v4l2_dev;
2073
2074 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2075 if (ret) {
2076 vpe_err(dev, "Failed to register video device\n");
2077 goto runtime_put;
2078 }
2079
2080 video_set_drvdata(vfd, dev);
2081 snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name);
2082 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2083 vfd->num);
2084
2085 return 0;
2086
2087runtime_put:
2088 vpe_runtime_put(pdev);
2089rel_m2m:
2090 pm_runtime_disable(&pdev->dev);
2091 v4l2_m2m_release(dev->m2m_dev);
2092rel_ctx:
2093 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2094v4l2_dev_unreg:
2095 v4l2_device_unregister(&dev->v4l2_dev);
2096
2097 return ret;
2098}
2099
2100static int vpe_remove(struct platform_device *pdev)
2101{
2102 struct vpe_dev *dev =
2103 (struct vpe_dev *) platform_get_drvdata(pdev);
2104
2105 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2106
2107 v4l2_m2m_release(dev->m2m_dev);
2108 video_unregister_device(&dev->vfd);
2109 v4l2_device_unregister(&dev->v4l2_dev);
2110 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2111
2112 vpe_set_clock_enable(dev, 0);
2113 vpe_runtime_put(pdev);
2114 pm_runtime_disable(&pdev->dev);
2115
2116 return 0;
2117}
2118
2119#if defined(CONFIG_OF)
2120static const struct of_device_id vpe_of_match[] = {
2121 {
2122 .compatible = "ti,vpe",
2123 },
2124 {},
2125};
2126#else
2127#define vpe_of_match NULL
2128#endif
2129
2130static struct platform_driver vpe_pdrv = {
2131 .probe = vpe_probe,
2132 .remove = vpe_remove,
2133 .driver = {
2134 .name = VPE_MODULE_NAME,
2135 .owner = THIS_MODULE,
2136 .of_match_table = vpe_of_match,
2137 },
2138};
2139
903cbb83 2140module_platform_driver(vpe_pdrv);
45719127
AT		 2141
2142MODULE_DESCRIPTION("TI VPE driver");
2143MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2144MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)