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[media] radio-bcm2048: fix signal of value
[linux-block.git] / drivers / media / platform / ti-vpe / vpe.c
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45719127
AT		 1/*
2 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
3 *
4 * Copyright (c) 2013 Texas Instruments Inc.
5 * David Griego, <dagriego@biglakesoftware.com>
6 * Dale Farnsworth, <dale@farnsworth.org>
7 * Archit Taneja, <archit@ti.com>
8 *
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
12 *
13 * Based on the virtual v4l2-mem2mem example device
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published by
17 * the Free Software Foundation
18 */
19
20#include <linux/delay.h>
21#include <linux/dma-mapping.h>
22#include <linux/err.h>
23#include <linux/fs.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/ioctl.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/videodev2.h>
33
34#include <media/v4l2-common.h>
35#include <media/v4l2-ctrls.h>
36#include <media/v4l2-device.h>
37#include <media/v4l2-event.h>
38#include <media/v4l2-ioctl.h>
39#include <media/v4l2-mem2mem.h>
40#include <media/videobuf2-core.h>
41#include <media/videobuf2-dma-contig.h>
42
43#include "vpdma.h"
44#include "vpe_regs.h"
45
46#define VPE_MODULE_NAME "vpe"
47
48/* minimum and maximum frame sizes */
49#define MIN_W 128
50#define MIN_H 128
51#define MAX_W 1920
52#define MAX_H 1080
53
54/* required alignments */
55#define S_ALIGN 0 /* multiple of 1 */
56#define H_ALIGN 1 /* multiple of 2 */
57#define W_ALIGN 1 /* multiple of 2 */
58
59/* multiple of 128 bits, line stride, 16 bytes */
60#define L_ALIGN 4
61
62/* flags that indicate a format can be used for capture/output */
63#define VPE_FMT_TYPE_CAPTURE (1 << 0)
64#define VPE_FMT_TYPE_OUTPUT (1 << 1)
65
66/* used as plane indices */
67#define VPE_MAX_PLANES 2
68#define VPE_LUMA 0
69#define VPE_CHROMA 1
70
71/* per m2m context info */
585e6f01
AT		 72#define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
73
45719127
AT		 74#define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
75
76/*
77 * each VPE context can need up to 3 config desciptors, 7 input descriptors,
78 * 3 output descriptors, and 10 control descriptors
79 */
80#define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
81 13 * VPDMA_CFD_CTD_DESC_SIZE)
82
83#define vpe_dbg(vpedev, fmt, arg...) \
84 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
85#define vpe_err(vpedev, fmt, arg...) \
86 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
87
88struct vpe_us_coeffs {
89 unsigned short anchor_fid0_c0;
90 unsigned short anchor_fid0_c1;
91 unsigned short anchor_fid0_c2;
92 unsigned short anchor_fid0_c3;
93 unsigned short interp_fid0_c0;
94 unsigned short interp_fid0_c1;
95 unsigned short interp_fid0_c2;
96 unsigned short interp_fid0_c3;
97 unsigned short anchor_fid1_c0;
98 unsigned short anchor_fid1_c1;
99 unsigned short anchor_fid1_c2;
100 unsigned short anchor_fid1_c3;
101 unsigned short interp_fid1_c0;
102 unsigned short interp_fid1_c1;
103 unsigned short interp_fid1_c2;
104 unsigned short interp_fid1_c3;
105};
106
107/*
108 * Default upsampler coefficients
109 */
110static const struct vpe_us_coeffs us_coeffs[] = {
111 {
112 /* Coefficients for progressive input */
113 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
114 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
115 },
585e6f01
AT		 116 {
117 /* Coefficients for Top Field Interlaced input */
118 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
119 /* Coefficients for Bottom Field Interlaced input */
120 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
121 },
122};
123
124/*
125 * the following registers are for configuring some of the parameters of the
126 * motion and edge detection blocks inside DEI, these generally remain the same,
127 * these could be passed later via userspace if some one needs to tweak these.
128 */
129struct vpe_dei_regs {
130 unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
131 unsigned long edi_config_reg; /* VPE_DEI_REG3 */
132 unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
133 unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
134 unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
135 unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
136};
137
138/*
139 * default expert DEI register values, unlikely to be modified.
140 */
141static const struct vpe_dei_regs dei_regs = {
142 0x020C0804u,
143 0x0118100Fu,
144 0x08040200u,
145 0x1010100Cu,
146 0x10101010u,
147 0x10101010u,
45719127
AT		 148};
149
150/*
151 * The port_data structure contains per-port data.
152 */
153struct vpe_port_data {
154 enum vpdma_channel channel; /* VPDMA channel */
585e6f01 155 u8 vb_index; /* input frame f, f-1, f-2 index */
45719127
AT		 156 u8 vb_part; /* plane index for co-panar formats */
157};
158
159/*
160 * Define indices into the port_data tables
161 */
162#define VPE_PORT_LUMA1_IN 0
163#define VPE_PORT_CHROMA1_IN 1
585e6f01
AT		 164#define VPE_PORT_LUMA2_IN 2
165#define VPE_PORT_CHROMA2_IN 3
166#define VPE_PORT_LUMA3_IN 4
167#define VPE_PORT_CHROMA3_IN 5
168#define VPE_PORT_MV_IN 6
169#define VPE_PORT_MV_OUT 7
45719127
AT		 170#define VPE_PORT_LUMA_OUT 8
171#define VPE_PORT_CHROMA_OUT 9
172#define VPE_PORT_RGB_OUT 10
173
174static const struct vpe_port_data port_data[11] = {
175 [VPE_PORT_LUMA1_IN] = {
176 .channel = VPE_CHAN_LUMA1_IN,
585e6f01 177 .vb_index = 0,
45719127
AT		 178 .vb_part = VPE_LUMA,
179 },
180 [VPE_PORT_CHROMA1_IN] = {
181 .channel = VPE_CHAN_CHROMA1_IN,
585e6f01
AT		 182 .vb_index = 0,
183 .vb_part = VPE_CHROMA,
184 },
185 [VPE_PORT_LUMA2_IN] = {
186 .channel = VPE_CHAN_LUMA2_IN,
187 .vb_index = 1,
188 .vb_part = VPE_LUMA,
189 },
190 [VPE_PORT_CHROMA2_IN] = {
191 .channel = VPE_CHAN_CHROMA2_IN,
192 .vb_index = 1,
193 .vb_part = VPE_CHROMA,
194 },
195 [VPE_PORT_LUMA3_IN] = {
196 .channel = VPE_CHAN_LUMA3_IN,
197 .vb_index = 2,
198 .vb_part = VPE_LUMA,
199 },
200 [VPE_PORT_CHROMA3_IN] = {
201 .channel = VPE_CHAN_CHROMA3_IN,
202 .vb_index = 2,
45719127
AT		 203 .vb_part = VPE_CHROMA,
204 },
585e6f01
AT		 205 [VPE_PORT_MV_IN] = {
206 .channel = VPE_CHAN_MV_IN,
207 },
208 [VPE_PORT_MV_OUT] = {
209 .channel = VPE_CHAN_MV_OUT,
210 },
45719127
AT		 211 [VPE_PORT_LUMA_OUT] = {
212 .channel = VPE_CHAN_LUMA_OUT,
213 .vb_part = VPE_LUMA,
214 },
215 [VPE_PORT_CHROMA_OUT] = {
216 .channel = VPE_CHAN_CHROMA_OUT,
217 .vb_part = VPE_CHROMA,
218 },
219 [VPE_PORT_RGB_OUT] = {
220 .channel = VPE_CHAN_RGB_OUT,
221 .vb_part = VPE_LUMA,
222 },
223};
224
225
226/* driver info for each of the supported video formats */
227struct vpe_fmt {
228 char *name; /* human-readable name */
229 u32 fourcc; /* standard format identifier */
230 u8 types; /* CAPTURE and/or OUTPUT */
231 u8 coplanar; /* set for unpacked Luma and Chroma */
232 /* vpdma format info for each plane */
233 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
234};
235
236static struct vpe_fmt vpe_formats[] = {
237 {
238 .name = "YUV 422 co-planar",
239 .fourcc = V4L2_PIX_FMT_NV16,
240 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
241 .coplanar = 1,
242 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
243 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
244 },
245 },
246 {
247 .name = "YUV 420 co-planar",
248 .fourcc = V4L2_PIX_FMT_NV12,
249 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
250 .coplanar = 1,
251 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
252 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
253 },
254 },
255 {
256 .name = "YUYV 422 packed",
257 .fourcc = V4L2_PIX_FMT_YUYV,
258 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
259 .coplanar = 0,
260 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YC422],
261 },
262 },
263 {
264 .name = "UYVY 422 packed",
265 .fourcc = V4L2_PIX_FMT_UYVY,
266 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
267 .coplanar = 0,
268 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CY422],
269 },
270 },
271};
272
273/*
274 * per-queue, driver-specific private data.
275 * there is one source queue and one destination queue for each m2m context.
276 */
277struct vpe_q_data {
278 unsigned int width; /* frame width */
279 unsigned int height; /* frame height */
280 unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */
281 enum v4l2_colorspace colorspace;
585e6f01 282 enum v4l2_field field; /* supported field value */
45719127
AT		 283 unsigned int flags;
284 unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */
285 struct v4l2_rect c_rect; /* crop/compose rectangle */
286 struct vpe_fmt *fmt; /* format info */
287};
288
289/* vpe_q_data flag bits */
290#define Q_DATA_FRAME_1D (1 << 0)
291#define Q_DATA_MODE_TILED (1 << 1)
585e6f01 292#define Q_DATA_INTERLACED (1 << 2)
45719127
AT		 293
294enum {
295 Q_DATA_SRC = 0,
296 Q_DATA_DST = 1,
297};
298
299/* find our format description corresponding to the passed v4l2_format */
300static struct vpe_fmt *find_format(struct v4l2_format *f)
301{
302 struct vpe_fmt *fmt;
303 unsigned int k;
304
305 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
306 fmt = &vpe_formats[k];
307 if (fmt->fourcc == f->fmt.pix.pixelformat)
308 return fmt;
309 }
310
311 return NULL;
312}
313
314/*
315 * there is one vpe_dev structure in the driver, it is shared by
316 * all instances.
317 */
318struct vpe_dev {
319 struct v4l2_device v4l2_dev;
320 struct video_device vfd;
321 struct v4l2_m2m_dev *m2m_dev;
322
323 atomic_t num_instances; /* count of driver instances */
324 dma_addr_t loaded_mmrs; /* shadow mmrs in device */
325 struct mutex dev_mutex;
326 spinlock_t lock;
327
328 int irq;
329 void __iomem *base;
330
331 struct vb2_alloc_ctx *alloc_ctx;
332 struct vpdma_data *vpdma; /* vpdma data handle */
333};
334
335/*
336 * There is one vpe_ctx structure for each m2m context.
337 */
338struct vpe_ctx {
339 struct v4l2_fh fh;
340 struct vpe_dev *dev;
341 struct v4l2_m2m_ctx *m2m_ctx;
342 struct v4l2_ctrl_handler hdl;
343
585e6f01 344 unsigned int field; /* current field */
45719127
AT		 345 unsigned int sequence; /* current frame/field seq */
346 unsigned int aborting; /* abort after next irq */
347
348 unsigned int bufs_per_job; /* input buffers per batch */
349 unsigned int bufs_completed; /* bufs done in this batch */
350
351 struct vpe_q_data q_data[2]; /* src & dst queue data */
585e6f01 352 struct vb2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
45719127
AT		 353 struct vb2_buffer *dst_vb;
354
585e6f01
AT		 355 dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
356 void *mv_buf[2]; /* virtual addrs of motion vector bufs */
357 size_t mv_buf_size; /* current motion vector buffer size */
45719127
AT		 358 struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
359 struct vpdma_desc_list desc_list; /* DMA descriptor list */
360
585e6f01 361 bool deinterlacing; /* using de-interlacer */
45719127 362 bool load_mmrs; /* have new shadow reg values */
585e6f01
AT		 363
364 unsigned int src_mv_buf_selector;
45719127
AT		 365};
366
367
368/*
369 * M2M devices get 2 queues.
370 * Return the queue given the type.
371 */
372static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
373 enum v4l2_buf_type type)
374{
375 switch (type) {
376 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
377 return &ctx->q_data[Q_DATA_SRC];
378 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
379 return &ctx->q_data[Q_DATA_DST];
380 default:
381 BUG();
382 }
383 return NULL;
384}
385
386static u32 read_reg(struct vpe_dev *dev, int offset)
387{
388 return ioread32(dev->base + offset);
389}
390
391static void write_reg(struct vpe_dev *dev, int offset, u32 value)
392{
393 iowrite32(value, dev->base + offset);
394}
395
396/* register field read/write helpers */
397static int get_field(u32 value, u32 mask, int shift)
398{
399 return (value & (mask << shift)) >> shift;
400}
401
402static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
403{
404 return get_field(read_reg(dev, offset), mask, shift);
405}
406
407static void write_field(u32 *valp, u32 field, u32 mask, int shift)
408{
409 u32 val = *valp;
410
411 val &= ~(mask << shift);
412 val |= (field & mask) << shift;
413 *valp = val;
414}
415
416static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
417 u32 mask, int shift)
418{
419 u32 val = read_reg(dev, offset);
420
421 write_field(&val, field, mask, shift);
422
423 write_reg(dev, offset, val);
424}
425
426/*
427 * DMA address/data block for the shadow registers
428 */
429struct vpe_mmr_adb {
430 struct vpdma_adb_hdr out_fmt_hdr;
431 u32 out_fmt_reg[1];
432 u32 out_fmt_pad[3];
433 struct vpdma_adb_hdr us1_hdr;
434 u32 us1_regs[8];
435 struct vpdma_adb_hdr us2_hdr;
436 u32 us2_regs[8];
437 struct vpdma_adb_hdr us3_hdr;
438 u32 us3_regs[8];
439 struct vpdma_adb_hdr dei_hdr;
585e6f01 440 u32 dei_regs[8];
45719127
AT		 441 struct vpdma_adb_hdr sc_hdr;
442 u32 sc_regs[1];
443 u32 sc_pad[3];
444 struct vpdma_adb_hdr csc_hdr;
445 u32 csc_regs[6];
446 u32 csc_pad[2];
447};
448
449#define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
450 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
451/*
452 * Set the headers for all of the address/data block structures.
453 */
454static void init_adb_hdrs(struct vpe_ctx *ctx)
455{
456 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
457 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
458 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
459 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
460 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
461 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr, sc_regs, VPE_SC_MP_SC0);
462 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, VPE_CSC_CSC00);
463};
464
585e6f01
AT		 465/*
466 * Allocate or re-allocate the motion vector DMA buffers
467 * There are two buffers, one for input and one for output.
468 * However, the roles are reversed after each field is processed.
469 * In other words, after each field is processed, the previous
470 * output (dst) MV buffer becomes the new input (src) MV buffer.
471 */
472static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
473{
474 struct device *dev = ctx->dev->v4l2_dev.dev;
475
476 if (ctx->mv_buf_size == size)
477 return 0;
478
479 if (ctx->mv_buf[0])
480 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
481 ctx->mv_buf_dma[0]);
482
483 if (ctx->mv_buf[1])
484 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
485 ctx->mv_buf_dma[1]);
486
487 if (size == 0)
488 return 0;
489
490 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
491 GFP_KERNEL);
492 if (!ctx->mv_buf[0]) {
493 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
494 return -ENOMEM;
495 }
496
497 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
498 GFP_KERNEL);
499 if (!ctx->mv_buf[1]) {
500 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
501 dma_free_coherent(dev, size, ctx->mv_buf[0],
502 ctx->mv_buf_dma[0]);
503
504 return -ENOMEM;
505 }
506
507 ctx->mv_buf_size = size;
508 ctx->src_mv_buf_selector = 0;
509
510 return 0;
511}
512
513static void free_mv_buffers(struct vpe_ctx *ctx)
514{
515 realloc_mv_buffers(ctx, 0);
516}
517
518/*
519 * While de-interlacing, we keep the two most recent input buffers
520 * around. This function frees those two buffers when we have
521 * finished processing the current stream.
522 */
523static void free_vbs(struct vpe_ctx *ctx)
524{
525 struct vpe_dev *dev = ctx->dev;
526 unsigned long flags;
527
528 if (ctx->src_vbs[2] == NULL)
529 return;
530
531 spin_lock_irqsave(&dev->lock, flags);
532 if (ctx->src_vbs[2]) {
533 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
534 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
535 }
536 spin_unlock_irqrestore(&dev->lock, flags);
537}
538
45719127
AT		 539/*
540 * Enable or disable the VPE clocks
541 */
542static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
543{
544 u32 val = 0;
545
546 if (on)
547 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
548 write_reg(dev, VPE_CLK_ENABLE, val);
549}
550
551static void vpe_top_reset(struct vpe_dev *dev)
552{
553
554 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
555 VPE_DATA_PATH_CLK_RESET_SHIFT);
556
557 usleep_range(100, 150);
558
559 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
560 VPE_DATA_PATH_CLK_RESET_SHIFT);
561}
562
563static void vpe_top_vpdma_reset(struct vpe_dev *dev)
564{
565 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
566 VPE_VPDMA_CLK_RESET_SHIFT);
567
568 usleep_range(100, 150);
569
570 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
571 VPE_VPDMA_CLK_RESET_SHIFT);
572}
573
574/*
575 * Load the correct of upsampler coefficients into the shadow MMRs
576 */
577static void set_us_coefficients(struct vpe_ctx *ctx)
578{
579 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
585e6f01 580 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
45719127
AT		 581 u32 *us1_reg = &mmr_adb->us1_regs[0];
582 u32 *us2_reg = &mmr_adb->us2_regs[0];
583 u32 *us3_reg = &mmr_adb->us3_regs[0];
584 const unsigned short *cp, *end_cp;
585
586 cp = &us_coeffs[0].anchor_fid0_c0;
587
585e6f01
AT		 588 if (s_q_data->flags & Q_DATA_INTERLACED) /* interlaced */
589 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
590
45719127
AT		 591 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
592
593 while (cp < end_cp) {
594 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
595 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
596 *us2_reg++ = *us1_reg;
597 *us3_reg++ = *us1_reg++;
598 }
599 ctx->load_mmrs = true;
600}
601
602/*
603 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
604 */
605static void set_cfg_and_line_modes(struct vpe_ctx *ctx)
606{
607 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
608 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
609 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
610 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
611 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
612 int line_mode = 1;
613 int cfg_mode = 1;
614
615 /*
616 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
617 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
618 */
619
620 if (fmt->fourcc == V4L2_PIX_FMT_NV12) {
621 cfg_mode = 0;
622 line_mode = 0; /* double lines to line buffer */
623 }
624
625 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
626 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
627 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
628
629 /* regs for now */
630 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
585e6f01
AT		 631 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
632 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
45719127
AT		 633
634 /* frame start for input luma */
635 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
636 VPE_CHAN_LUMA1_IN);
585e6f01
AT		 637 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
638 VPE_CHAN_LUMA2_IN);
639 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
640 VPE_CHAN_LUMA3_IN);
45719127
AT		 641
642 /* frame start for input chroma */
643 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
644 VPE_CHAN_CHROMA1_IN);
585e6f01
AT		 645 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
646 VPE_CHAN_CHROMA2_IN);
647 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
648 VPE_CHAN_CHROMA3_IN);
649
650 /* frame start for MV in client */
651 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
652 VPE_CHAN_MV_IN);
45719127
AT		 653
654 ctx->load_mmrs = true;
655}
656
657/*
658 * Set the shadow registers that are modified when the source
659 * format changes.
660 */
661static void set_src_registers(struct vpe_ctx *ctx)
662{
663 set_us_coefficients(ctx);
664}
665
666/*
667 * Set the shadow registers that are modified when the destination
668 * format changes.
669 */
670static void set_dst_registers(struct vpe_ctx *ctx)
671{
672 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
673 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
674 u32 val = 0;
675
676 /* select RGB path when color space conversion is supported in future */
677 if (fmt->fourcc == V4L2_PIX_FMT_RGB24)
678 val |= VPE_RGB_OUT_SELECT | VPE_CSC_SRC_DEI_SCALER;
679 else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
680 val |= VPE_COLOR_SEPARATE_422;
681
682 /* The source of CHR_DS is always the scaler, whether it's used or not */
683 val |= VPE_DS_SRC_DEI_SCALER;
684
685 if (fmt->fourcc != V4L2_PIX_FMT_NV12)
686 val |= VPE_DS_BYPASS;
687
688 mmr_adb->out_fmt_reg[0] = val;
689
690 ctx->load_mmrs = true;
691}
692
693/*
694 * Set the de-interlacer shadow register values
695 */
585e6f01 696static void set_dei_regs(struct vpe_ctx *ctx)
45719127
AT		 697{
698 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
699 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
700 unsigned int src_h = s_q_data->c_rect.height;
701 unsigned int src_w = s_q_data->c_rect.width;
702 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
585e6f01 703 bool deinterlace = true;
45719127
AT		 704 u32 val = 0;
705
706 /*
707 * according to TRM, we should set DEI in progressive bypass mode when
708 * the input content is progressive, however, DEI is bypassed correctly
709 * for both progressive and interlace content in interlace bypass mode.
710 * It has been recommended not to use progressive bypass mode.
711 */
585e6f01
AT		 712 if ((!ctx->deinterlacing && (s_q_data->flags & Q_DATA_INTERLACED)) ||
713 !(s_q_data->flags & Q_DATA_INTERLACED)) {
714 deinterlace = false;
715 val = VPE_DEI_INTERLACE_BYPASS;
716 }
717
718 src_h = deinterlace ? src_h * 2 : src_h;
45719127
AT		 719
720 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
721 (src_w << VPE_DEI_WIDTH_SHIFT) |
722 VPE_DEI_FIELD_FLUSH;
723
724 *dei_mmr0 = val;
725
726 ctx->load_mmrs = true;
727}
728
585e6f01
AT		 729static void set_dei_shadow_registers(struct vpe_ctx *ctx)
730{
731 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
732 u32 *dei_mmr = &mmr_adb->dei_regs[0];
733 const struct vpe_dei_regs *cur = &dei_regs;
734
735 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
736 dei_mmr[3] = cur->edi_config_reg;
737 dei_mmr[4] = cur->edi_lut_reg0;
738 dei_mmr[5] = cur->edi_lut_reg1;
739 dei_mmr[6] = cur->edi_lut_reg2;
740 dei_mmr[7] = cur->edi_lut_reg3;
741
742 ctx->load_mmrs = true;
743}
744
45719127
AT		 745static void set_csc_coeff_bypass(struct vpe_ctx *ctx)
746{
747 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
748 u32 *shadow_csc_reg5 = &mmr_adb->csc_regs[5];
749
750 *shadow_csc_reg5 |= VPE_CSC_BYPASS;
751
752 ctx->load_mmrs = true;
753}
754
755static void set_sc_regs_bypass(struct vpe_ctx *ctx)
756{
757 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
758 u32 *sc_reg0 = &mmr_adb->sc_regs[0];
759 u32 val = 0;
760
761 val |= VPE_SC_BYPASS;
762 *sc_reg0 = val;
763
764 ctx->load_mmrs = true;
765}
766
767/*
768 * Set the shadow registers whose values are modified when either the
769 * source or destination format is changed.
770 */
771static int set_srcdst_params(struct vpe_ctx *ctx)
772{
585e6f01
AT		 773 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
774 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
775 size_t mv_buf_size;
776 int ret;
777
45719127 778 ctx->sequence = 0;
585e6f01
AT		 779 ctx->field = V4L2_FIELD_TOP;
780
781 if ((s_q_data->flags & Q_DATA_INTERLACED) &&
782 !(d_q_data->flags & Q_DATA_INTERLACED)) {
783 const struct vpdma_data_format *mv =
784 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
785
786 ctx->deinterlacing = 1;
787 mv_buf_size =
788 (s_q_data->width * s_q_data->height * mv->depth) >> 3;
789 } else {
790 ctx->deinterlacing = 0;
791 mv_buf_size = 0;
792 }
793
794 free_vbs(ctx);
795
796 ret = realloc_mv_buffers(ctx, mv_buf_size);
797 if (ret)
798 return ret;
45719127
AT		 799
800 set_cfg_and_line_modes(ctx);
585e6f01 801 set_dei_regs(ctx);
45719127
AT		 802 set_csc_coeff_bypass(ctx);
803 set_sc_regs_bypass(ctx);
804
805 return 0;
806}
807
808/*
809 * Return the vpe_ctx structure for a given struct file
810 */
811static struct vpe_ctx *file2ctx(struct file *file)
812{
813 return container_of(file->private_data, struct vpe_ctx, fh);
814}
815
816/*
817 * mem2mem callbacks
818 */
819
820/**
821 * job_ready() - check whether an instance is ready to be scheduled to run
822 */
823static int job_ready(void *priv)
824{
825 struct vpe_ctx *ctx = priv;
826 int needed = ctx->bufs_per_job;
827
585e6f01
AT		 828 if (ctx->deinterlacing && ctx->src_vbs[2] == NULL)
829 needed += 2; /* need additional two most recent fields */
830
45719127
AT		 831 if (v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) < needed)
832 return 0;
833
834 return 1;
835}
836
837static void job_abort(void *priv)
838{
839 struct vpe_ctx *ctx = priv;
840
841 /* Will cancel the transaction in the next interrupt handler */
842 ctx->aborting = 1;
843}
844
845/*
846 * Lock access to the device
847 */
848static void vpe_lock(void *priv)
849{
850 struct vpe_ctx *ctx = priv;
851 struct vpe_dev *dev = ctx->dev;
852 mutex_lock(&dev->dev_mutex);
853}
854
855static void vpe_unlock(void *priv)
856{
857 struct vpe_ctx *ctx = priv;
858 struct vpe_dev *dev = ctx->dev;
859 mutex_unlock(&dev->dev_mutex);
860}
861
862static void vpe_dump_regs(struct vpe_dev *dev)
863{
864#define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
865
866 vpe_dbg(dev, "VPE Registers:\n");
867
868 DUMPREG(PID);
869 DUMPREG(SYSCONFIG);
870 DUMPREG(INT0_STATUS0_RAW);
871 DUMPREG(INT0_STATUS0);
872 DUMPREG(INT0_ENABLE0);
873 DUMPREG(INT0_STATUS1_RAW);
874 DUMPREG(INT0_STATUS1);
875 DUMPREG(INT0_ENABLE1);
876 DUMPREG(CLK_ENABLE);
877 DUMPREG(CLK_RESET);
878 DUMPREG(CLK_FORMAT_SELECT);
879 DUMPREG(CLK_RANGE_MAP);
880 DUMPREG(US1_R0);
881 DUMPREG(US1_R1);
882 DUMPREG(US1_R2);
883 DUMPREG(US1_R3);
884 DUMPREG(US1_R4);
885 DUMPREG(US1_R5);
886 DUMPREG(US1_R6);
887 DUMPREG(US1_R7);
888 DUMPREG(US2_R0);
889 DUMPREG(US2_R1);
890 DUMPREG(US2_R2);
891 DUMPREG(US2_R3);
892 DUMPREG(US2_R4);
893 DUMPREG(US2_R5);
894 DUMPREG(US2_R6);
895 DUMPREG(US2_R7);
896 DUMPREG(US3_R0);
897 DUMPREG(US3_R1);
898 DUMPREG(US3_R2);
899 DUMPREG(US3_R3);
900 DUMPREG(US3_R4);
901 DUMPREG(US3_R5);
902 DUMPREG(US3_R6);
903 DUMPREG(US3_R7);
904 DUMPREG(DEI_FRAME_SIZE);
905 DUMPREG(MDT_BYPASS);
906 DUMPREG(MDT_SF_THRESHOLD);
907 DUMPREG(EDI_CONFIG);
908 DUMPREG(DEI_EDI_LUT_R0);
909 DUMPREG(DEI_EDI_LUT_R1);
910 DUMPREG(DEI_EDI_LUT_R2);
911 DUMPREG(DEI_EDI_LUT_R3);
912 DUMPREG(DEI_FMD_WINDOW_R0);
913 DUMPREG(DEI_FMD_WINDOW_R1);
914 DUMPREG(DEI_FMD_CONTROL_R0);
915 DUMPREG(DEI_FMD_CONTROL_R1);
916 DUMPREG(DEI_FMD_STATUS_R0);
917 DUMPREG(DEI_FMD_STATUS_R1);
918 DUMPREG(DEI_FMD_STATUS_R2);
919 DUMPREG(SC_MP_SC0);
920 DUMPREG(SC_MP_SC1);
921 DUMPREG(SC_MP_SC2);
922 DUMPREG(SC_MP_SC3);
923 DUMPREG(SC_MP_SC4);
924 DUMPREG(SC_MP_SC5);
925 DUMPREG(SC_MP_SC6);
926 DUMPREG(SC_MP_SC8);
927 DUMPREG(SC_MP_SC9);
928 DUMPREG(SC_MP_SC10);
929 DUMPREG(SC_MP_SC11);
930 DUMPREG(SC_MP_SC12);
931 DUMPREG(SC_MP_SC13);
932 DUMPREG(SC_MP_SC17);
933 DUMPREG(SC_MP_SC18);
934 DUMPREG(SC_MP_SC19);
935 DUMPREG(SC_MP_SC20);
936 DUMPREG(SC_MP_SC21);
937 DUMPREG(SC_MP_SC22);
938 DUMPREG(SC_MP_SC23);
939 DUMPREG(SC_MP_SC24);
940 DUMPREG(SC_MP_SC25);
941 DUMPREG(CSC_CSC00);
942 DUMPREG(CSC_CSC01);
943 DUMPREG(CSC_CSC02);
944 DUMPREG(CSC_CSC03);
945 DUMPREG(CSC_CSC04);
946 DUMPREG(CSC_CSC05);
947#undef DUMPREG
948}
949
950static void add_out_dtd(struct vpe_ctx *ctx, int port)
951{
952 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
953 const struct vpe_port_data *p_data = &port_data[port];
954 struct vb2_buffer *vb = ctx->dst_vb;
955 struct v4l2_rect *c_rect = &q_data->c_rect;
956 struct vpe_fmt *fmt = q_data->fmt;
957 const struct vpdma_data_format *vpdma_fmt;
585e6f01 958 int mv_buf_selector = !ctx->src_mv_buf_selector;
45719127
AT		 959 dma_addr_t dma_addr;
960 u32 flags = 0;
961
585e6f01
AT		 962 if (port == VPE_PORT_MV_OUT) {
963 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
964 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
965 } else {
966 /* to incorporate interleaved formats */
967 int plane = fmt->coplanar ? p_data->vb_part : 0;
968
969 vpdma_fmt = fmt->vpdma_fmt[plane];
970 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
971 if (!dma_addr) {
972 vpe_err(ctx->dev,
973 "acquiring output buffer(%d) dma_addr failed\n",
974 port);
975 return;
976 }
45719127
AT		 977 }
978
979 if (q_data->flags & Q_DATA_FRAME_1D)
980 flags |= VPDMA_DATA_FRAME_1D;
981 if (q_data->flags & Q_DATA_MODE_TILED)
982 flags |= VPDMA_DATA_MODE_TILED;
983
984 vpdma_add_out_dtd(&ctx->desc_list, c_rect, vpdma_fmt, dma_addr,
985 p_data->channel, flags);
986}
987
988static void add_in_dtd(struct vpe_ctx *ctx, int port)
989{
990 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
991 const struct vpe_port_data *p_data = &port_data[port];
585e6f01 992 struct vb2_buffer *vb = ctx->src_vbs[p_data->vb_index];
45719127
AT		 993 struct v4l2_rect *c_rect = &q_data->c_rect;
994 struct vpe_fmt *fmt = q_data->fmt;
995 const struct vpdma_data_format *vpdma_fmt;
585e6f01
AT		 996 int mv_buf_selector = ctx->src_mv_buf_selector;
997 int field = vb->v4l2_buf.field == V4L2_FIELD_BOTTOM;
45719127
AT		 998 dma_addr_t dma_addr;
999 u32 flags = 0;
1000
585e6f01
AT		 1001 if (port == VPE_PORT_MV_IN) {
1002 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1003 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1004 } else {
1005 /* to incorporate interleaved formats */
1006 int plane = fmt->coplanar ? p_data->vb_part : 0;
45719127 1007
585e6f01
AT		 1008 vpdma_fmt = fmt->vpdma_fmt[plane];
1009
1010 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1011 if (!dma_addr) {
1012 vpe_err(ctx->dev,
1013 "acquiring input buffer(%d) dma_addr failed\n",
1014 port);
1015 return;
1016 }
45719127
AT		 1017 }
1018
1019 if (q_data->flags & Q_DATA_FRAME_1D)
1020 flags |= VPDMA_DATA_FRAME_1D;
1021 if (q_data->flags & Q_DATA_MODE_TILED)
1022 flags |= VPDMA_DATA_MODE_TILED;
1023
1024 vpdma_add_in_dtd(&ctx->desc_list, q_data->width, q_data->height,
1025 c_rect, vpdma_fmt, dma_addr, p_data->channel, field, flags);
1026}
1027
1028/*
1029 * Enable the expected IRQ sources
1030 */
1031static void enable_irqs(struct vpe_ctx *ctx)
1032{
1033 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
585e6f01
AT		 1034 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1035 VPE_DS1_UV_ERROR_INT);
45719127
AT		 1036
1037 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, true);
1038}
1039
1040static void disable_irqs(struct vpe_ctx *ctx)
1041{
1042 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1043 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1044
1045 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, false);
1046}
1047
1048/* device_run() - prepares and starts the device
1049 *
1050 * This function is only called when both the source and destination
1051 * buffers are in place.
1052 */
1053static void device_run(void *priv)
1054{
1055 struct vpe_ctx *ctx = priv;
1056 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1057
585e6f01
AT		 1058 if (ctx->deinterlacing && ctx->src_vbs[2] == NULL) {
1059 ctx->src_vbs[2] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1060 WARN_ON(ctx->src_vbs[2] == NULL);
1061 ctx->src_vbs[1] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1062 WARN_ON(ctx->src_vbs[1] == NULL);
1063 }
1064
1065 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1066 WARN_ON(ctx->src_vbs[0] == NULL);
45719127
AT		 1067 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
1068 WARN_ON(ctx->dst_vb == NULL);
1069
1070 /* config descriptors */
1071 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1072 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1073 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1074 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1075 ctx->load_mmrs = false;
1076 }
1077
585e6f01
AT		 1078 /* output data descriptors */
1079 if (ctx->deinterlacing)
1080 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1081
45719127
AT		 1082 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1083 if (d_q_data->fmt->coplanar)
1084 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1085
585e6f01
AT		 1086 /* input data descriptors */
1087 if (ctx->deinterlacing) {
1088 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1089 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1090
1091 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1092 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1093 }
1094
45719127
AT		 1095 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1096 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1097
585e6f01
AT		 1098 if (ctx->deinterlacing)
1099 add_in_dtd(ctx, VPE_PORT_MV_IN);
1100
45719127
AT		 1101 /* sync on channel control descriptors for input ports */
1102 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1103 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1104
585e6f01
AT		 1105 if (ctx->deinterlacing) {
1106 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1107 VPE_CHAN_LUMA2_IN);
1108 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1109 VPE_CHAN_CHROMA2_IN);
1110
1111 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1112 VPE_CHAN_LUMA3_IN);
1113 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1114 VPE_CHAN_CHROMA3_IN);
1115
1116 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1117 }
1118
45719127
AT		 1119 /* sync on channel control descriptors for output ports */
1120 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA_OUT);
1121 if (d_q_data->fmt->coplanar)
1122 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA_OUT);
1123
585e6f01
AT		 1124 if (ctx->deinterlacing)
1125 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1126
45719127
AT		 1127 enable_irqs(ctx);
1128
1129 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1130 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list);
1131}
1132
585e6f01
AT		 1133static void dei_error(struct vpe_ctx *ctx)
1134{
1135 dev_warn(ctx->dev->v4l2_dev.dev,
1136 "received DEI error interrupt\n");
1137}
1138
45719127
AT		 1139static void ds1_uv_error(struct vpe_ctx *ctx)
1140{
1141 dev_warn(ctx->dev->v4l2_dev.dev,
1142 "received downsampler error interrupt\n");
1143}
1144
1145static irqreturn_t vpe_irq(int irq_vpe, void *data)
1146{
1147 struct vpe_dev *dev = (struct vpe_dev *)data;
1148 struct vpe_ctx *ctx;
585e6f01 1149 struct vpe_q_data *d_q_data;
45719127
AT		 1150 struct vb2_buffer *s_vb, *d_vb;
1151 struct v4l2_buffer *s_buf, *d_buf;
1152 unsigned long flags;
1153 u32 irqst0, irqst1;
1154
1155 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1156 if (irqst0) {
1157 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1158 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1159 }
1160
1161 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1162 if (irqst1) {
1163 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1164 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1165 }
1166
1167 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1168 if (!ctx) {
1169 vpe_err(dev, "instance released before end of transaction\n");
1170 goto handled;
1171 }
1172
585e6f01
AT		 1173 if (irqst1) {
1174 if (irqst1 & VPE_DEI_ERROR_INT) {
1175 irqst1 &= ~VPE_DEI_ERROR_INT;
1176 dei_error(ctx);
1177 }
1178 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1179 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1180 ds1_uv_error(ctx);
1181 }
45719127
AT		 1182 }
1183
1184 if (irqst0) {
1185 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1186 vpdma_clear_list_stat(ctx->dev->vpdma);
1187
1188 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1189 }
1190
1191 if (irqst0 | irqst1) {
1192 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: "
1193 "INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1194 irqst0, irqst1);
1195 }
1196
1197 disable_irqs(ctx);
1198
1199 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1200 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1201
1202 vpdma_reset_desc_list(&ctx->desc_list);
1203
585e6f01
AT		 1204 /* the previous dst mv buffer becomes the next src mv buffer */
1205 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1206
45719127
AT		 1207 if (ctx->aborting)
1208 goto finished;
1209
585e6f01 1210 s_vb = ctx->src_vbs[0];
45719127
AT		 1211 d_vb = ctx->dst_vb;
1212 s_buf = &s_vb->v4l2_buf;
1213 d_buf = &d_vb->v4l2_buf;
1214
1215 d_buf->timestamp = s_buf->timestamp;
1216 if (s_buf->flags & V4L2_BUF_FLAG_TIMECODE) {
1217 d_buf->flags |= V4L2_BUF_FLAG_TIMECODE;
1218 d_buf->timecode = s_buf->timecode;
1219 }
45719127 1220 d_buf->sequence = ctx->sequence;
585e6f01
AT		 1221 d_buf->field = ctx->field;
1222
1223 d_q_data = &ctx->q_data[Q_DATA_DST];
1224 if (d_q_data->flags & Q_DATA_INTERLACED) {
1225 if (ctx->field == V4L2_FIELD_BOTTOM) {
1226 ctx->sequence++;
1227 ctx->field = V4L2_FIELD_TOP;
1228 } else {
1229 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1230 ctx->field = V4L2_FIELD_BOTTOM;
1231 }
1232 } else {
1233 ctx->sequence++;
1234 }
45719127 1235
585e6f01
AT		 1236 if (ctx->deinterlacing)
1237 s_vb = ctx->src_vbs[2];
45719127
AT		 1238
1239 spin_lock_irqsave(&dev->lock, flags);
1240 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1241 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1242 spin_unlock_irqrestore(&dev->lock, flags);
1243
585e6f01
AT		 1244 if (ctx->deinterlacing) {
1245 ctx->src_vbs[2] = ctx->src_vbs[1];
1246 ctx->src_vbs[1] = ctx->src_vbs[0];
1247 }
1248
45719127
AT		 1249 ctx->bufs_completed++;
1250 if (ctx->bufs_completed < ctx->bufs_per_job) {
1251 device_run(ctx);
1252 goto handled;
1253 }
1254
1255finished:
1256 vpe_dbg(ctx->dev, "finishing transaction\n");
1257 ctx->bufs_completed = 0;
1258 v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
1259handled:
1260 return IRQ_HANDLED;
1261}
1262
1263/*
1264 * video ioctls
1265 */
1266static int vpe_querycap(struct file *file, void *priv,
1267 struct v4l2_capability *cap)
1268{
1269 strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
1270 strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
1271 strlcpy(cap->bus_info, VPE_MODULE_NAME, sizeof(cap->bus_info));
1272 cap->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
1273 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1274 return 0;
1275}
1276
1277static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1278{
1279 int i, index;
1280 struct vpe_fmt *fmt = NULL;
1281
1282 index = 0;
1283 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1284 if (vpe_formats[i].types & type) {
1285 if (index == f->index) {
1286 fmt = &vpe_formats[i];
1287 break;
1288 }
1289 index++;
1290 }
1291 }
1292
1293 if (!fmt)
1294 return -EINVAL;
1295
1296 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
1297 f->pixelformat = fmt->fourcc;
1298 return 0;
1299}
1300
1301static int vpe_enum_fmt(struct file *file, void *priv,
1302 struct v4l2_fmtdesc *f)
1303{
1304 if (V4L2_TYPE_IS_OUTPUT(f->type))
1305 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1306
1307 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1308}
1309
1310static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1311{
1312 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1313 struct vpe_ctx *ctx = file2ctx(file);
1314 struct vb2_queue *vq;
1315 struct vpe_q_data *q_data;
1316 int i;
1317
1318 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1319 if (!vq)
1320 return -EINVAL;
1321
1322 q_data = get_q_data(ctx, f->type);
1323
1324 pix->width = q_data->width;
1325 pix->height = q_data->height;
1326 pix->pixelformat = q_data->fmt->fourcc;
585e6f01 1327 pix->field = q_data->field;
45719127
AT		 1328
1329 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1330 pix->colorspace = q_data->colorspace;
1331 } else {
1332 struct vpe_q_data *s_q_data;
1333
1334 /* get colorspace from the source queue */
1335 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1336
1337 pix->colorspace = s_q_data->colorspace;
1338 }
1339
1340 pix->num_planes = q_data->fmt->coplanar ? 2 : 1;
1341
1342 for (i = 0; i < pix->num_planes; i++) {
1343 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1344 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1345 }
1346
1347 return 0;
1348}
1349
1350static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1351 struct vpe_fmt *fmt, int type)
1352{
1353 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1354 struct v4l2_plane_pix_format *plane_fmt;
1355 int i;
1356
1357 if (!fmt || !(fmt->types & type)) {
1358 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1359 pix->pixelformat);
1360 return -EINVAL;
1361 }
1362
585e6f01
AT		 1363 if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE)
1364 pix->field = V4L2_FIELD_NONE;
45719127
AT		 1365
1366 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, W_ALIGN,
1367 &pix->height, MIN_H, MAX_H, H_ALIGN,
1368 S_ALIGN);
1369
1370 pix->num_planes = fmt->coplanar ? 2 : 1;
1371 pix->pixelformat = fmt->fourcc;
1372
1373 if (type == VPE_FMT_TYPE_CAPTURE) {
1374 struct vpe_q_data *s_q_data;
1375
1376 /* get colorspace from the source queue */
1377 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1378
1379 pix->colorspace = s_q_data->colorspace;
1380 } else {
1381 if (!pix->colorspace)
1382 pix->colorspace = V4L2_COLORSPACE_SMPTE240M;
1383 }
1384
1385 for (i = 0; i < pix->num_planes; i++) {
1386 int depth;
1387
1388 plane_fmt = &pix->plane_fmt[i];
1389 depth = fmt->vpdma_fmt[i]->depth;
1390
1391 if (i == VPE_LUMA)
1392 plane_fmt->bytesperline =
1393 round_up((pix->width * depth) >> 3,
1394 1 << L_ALIGN);
1395 else
1396 plane_fmt->bytesperline = pix->width;
1397
1398 plane_fmt->sizeimage =
1399 (pix->height * pix->width * depth) >> 3;
1400 }
1401
1402 return 0;
1403}
1404
1405static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1406{
1407 struct vpe_ctx *ctx = file2ctx(file);
1408 struct vpe_fmt *fmt = find_format(f);
1409
1410 if (V4L2_TYPE_IS_OUTPUT(f->type))
1411 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1412 else
1413 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1414}
1415
1416static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1417{
1418 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1419 struct v4l2_plane_pix_format *plane_fmt;
1420 struct vpe_q_data *q_data;
1421 struct vb2_queue *vq;
1422 int i;
1423
1424 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1425 if (!vq)
1426 return -EINVAL;
1427
1428 if (vb2_is_busy(vq)) {
1429 vpe_err(ctx->dev, "queue busy\n");
1430 return -EBUSY;
1431 }
1432
1433 q_data = get_q_data(ctx, f->type);
1434 if (!q_data)
1435 return -EINVAL;
1436
1437 q_data->fmt = find_format(f);
1438 q_data->width = pix->width;
1439 q_data->height = pix->height;
1440 q_data->colorspace = pix->colorspace;
585e6f01 1441 q_data->field = pix->field;
45719127
AT		 1442
1443 for (i = 0; i < pix->num_planes; i++) {
1444 plane_fmt = &pix->plane_fmt[i];
1445
1446 q_data->bytesperline[i] = plane_fmt->bytesperline;
1447 q_data->sizeimage[i] = plane_fmt->sizeimage;
1448 }
1449
1450 q_data->c_rect.left = 0;
1451 q_data->c_rect.top = 0;
1452 q_data->c_rect.width = q_data->width;
1453 q_data->c_rect.height = q_data->height;
1454
585e6f01
AT		 1455 if (q_data->field == V4L2_FIELD_ALTERNATE)
1456 q_data->flags |= Q_DATA_INTERLACED;
1457 else
1458 q_data->flags &= ~Q_DATA_INTERLACED;
1459
45719127
AT		 1460 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1461 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1462 q_data->bytesperline[VPE_LUMA]);
1463 if (q_data->fmt->coplanar)
1464 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1465 q_data->bytesperline[VPE_CHROMA]);
1466
1467 return 0;
1468}
1469
1470static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1471{
1472 int ret;
1473 struct vpe_ctx *ctx = file2ctx(file);
1474
1475 ret = vpe_try_fmt(file, priv, f);
1476 if (ret)
1477 return ret;
1478
1479 ret = __vpe_s_fmt(ctx, f);
1480 if (ret)
1481 return ret;
1482
1483 if (V4L2_TYPE_IS_OUTPUT(f->type))
1484 set_src_registers(ctx);
1485 else
1486 set_dst_registers(ctx);
1487
1488 return set_srcdst_params(ctx);
1489}
1490
1491static int vpe_reqbufs(struct file *file, void *priv,
1492 struct v4l2_requestbuffers *reqbufs)
1493{
1494 struct vpe_ctx *ctx = file2ctx(file);
1495
1496 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1497}
1498
1499static int vpe_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1500{
1501 struct vpe_ctx *ctx = file2ctx(file);
1502
1503 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1504}
1505
1506static int vpe_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1507{
1508 struct vpe_ctx *ctx = file2ctx(file);
1509
1510 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1511}
1512
1513static int vpe_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
1514{
1515 struct vpe_ctx *ctx = file2ctx(file);
1516
1517 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1518}
1519
1520static int vpe_streamon(struct file *file, void *priv, enum v4l2_buf_type type)
1521{
1522 struct vpe_ctx *ctx = file2ctx(file);
1523
1524 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1525}
1526
1527static int vpe_streamoff(struct file *file, void *priv, enum v4l2_buf_type type)
1528{
1529 struct vpe_ctx *ctx = file2ctx(file);
1530
1531 vpe_dump_regs(ctx->dev);
1532 vpdma_dump_regs(ctx->dev->vpdma);
1533
1534 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1535}
1536
1537/*
1538 * defines number of buffers/frames a context can process with VPE before
1539 * switching to a different context. default value is 1 buffer per context
1540 */
1541#define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1542
1543static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1544{
1545 struct vpe_ctx *ctx =
1546 container_of(ctrl->handler, struct vpe_ctx, hdl);
1547
1548 switch (ctrl->id) {
1549 case V4L2_CID_VPE_BUFS_PER_JOB:
1550 ctx->bufs_per_job = ctrl->val;
1551 break;
1552
1553 default:
1554 vpe_err(ctx->dev, "Invalid control\n");
1555 return -EINVAL;
1556 }
1557
1558 return 0;
1559}
1560
1561static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1562 .s_ctrl = vpe_s_ctrl,
1563};
1564
1565static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1566 .vidioc_querycap = vpe_querycap,
1567
1568 .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
1569 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
1570 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
1571 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
1572
1573 .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
1574 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
1575 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
1576 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
1577
1578 .vidioc_reqbufs = vpe_reqbufs,
1579 .vidioc_querybuf = vpe_querybuf,
1580
1581 .vidioc_qbuf = vpe_qbuf,
1582 .vidioc_dqbuf = vpe_dqbuf,
1583
1584 .vidioc_streamon = vpe_streamon,
1585 .vidioc_streamoff = vpe_streamoff,
1586 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1587 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1588};
1589
1590/*
1591 * Queue operations
1592 */
1593static int vpe_queue_setup(struct vb2_queue *vq,
1594 const struct v4l2_format *fmt,
1595 unsigned int *nbuffers, unsigned int *nplanes,
1596 unsigned int sizes[], void *alloc_ctxs[])
1597{
1598 int i;
1599 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
1600 struct vpe_q_data *q_data;
1601
1602 q_data = get_q_data(ctx, vq->type);
1603
1604 *nplanes = q_data->fmt->coplanar ? 2 : 1;
1605
1606 for (i = 0; i < *nplanes; i++) {
1607 sizes[i] = q_data->sizeimage[i];
1608 alloc_ctxs[i] = ctx->dev->alloc_ctx;
1609 }
1610
1611 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
1612 sizes[VPE_LUMA]);
1613 if (q_data->fmt->coplanar)
1614 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
1615
1616 return 0;
1617}
1618
1619static int vpe_buf_prepare(struct vb2_buffer *vb)
1620{
1621 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1622 struct vpe_q_data *q_data;
1623 int i, num_planes;
1624
1625 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1626
1627 q_data = get_q_data(ctx, vb->vb2_queue->type);
1628 num_planes = q_data->fmt->coplanar ? 2 : 1;
1629
1630 for (i = 0; i < num_planes; i++) {
1631 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
1632 vpe_err(ctx->dev,
1633 "data will not fit into plane (%lu < %lu)\n",
1634 vb2_plane_size(vb, i),
1635 (long) q_data->sizeimage[i]);
1636 return -EINVAL;
1637 }
1638 }
1639
1640 for (i = 0; i < num_planes; i++)
1641 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
1642
1643 return 0;
1644}
1645
1646static void vpe_buf_queue(struct vb2_buffer *vb)
1647{
1648 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1649 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
1650}
1651
1652static void vpe_wait_prepare(struct vb2_queue *q)
1653{
1654 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
1655 vpe_unlock(ctx);
1656}
1657
1658static void vpe_wait_finish(struct vb2_queue *q)
1659{
1660 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
1661 vpe_lock(ctx);
1662}
1663
1664static struct vb2_ops vpe_qops = {
1665 .queue_setup = vpe_queue_setup,
1666 .buf_prepare = vpe_buf_prepare,
1667 .buf_queue = vpe_buf_queue,
1668 .wait_prepare = vpe_wait_prepare,
1669 .wait_finish = vpe_wait_finish,
1670};
1671
1672static int queue_init(void *priv, struct vb2_queue *src_vq,
1673 struct vb2_queue *dst_vq)
1674{
1675 struct vpe_ctx *ctx = priv;
1676 int ret;
1677
1678 memset(src_vq, 0, sizeof(*src_vq));
1679 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1680 src_vq->io_modes = VB2_MMAP;
1681 src_vq->drv_priv = ctx;
1682 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1683 src_vq->ops = &vpe_qops;
1684 src_vq->mem_ops = &vb2_dma_contig_memops;
1685 src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1686
1687 ret = vb2_queue_init(src_vq);
1688 if (ret)
1689 return ret;
1690
1691 memset(dst_vq, 0, sizeof(*dst_vq));
1692 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1693 dst_vq->io_modes = VB2_MMAP;
1694 dst_vq->drv_priv = ctx;
1695 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1696 dst_vq->ops = &vpe_qops;
1697 dst_vq->mem_ops = &vb2_dma_contig_memops;
1698 dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1699
1700 return vb2_queue_init(dst_vq);
1701}
1702
1703static const struct v4l2_ctrl_config vpe_bufs_per_job = {
1704 .ops = &vpe_ctrl_ops,
1705 .id = V4L2_CID_VPE_BUFS_PER_JOB,
1706 .name = "Buffers Per Transaction",
1707 .type = V4L2_CTRL_TYPE_INTEGER,
1708 .def = VPE_DEF_BUFS_PER_JOB,
1709 .min = 1,
1710 .max = VIDEO_MAX_FRAME,
1711 .step = 1,
1712};
1713
1714/*
1715 * File operations
1716 */
1717static int vpe_open(struct file *file)
1718{
1719 struct vpe_dev *dev = video_drvdata(file);
1720 struct vpe_ctx *ctx = NULL;
1721 struct vpe_q_data *s_q_data;
1722 struct v4l2_ctrl_handler *hdl;
1723 int ret;
1724
1725 vpe_dbg(dev, "vpe_open\n");
1726
1727 if (!dev->vpdma->ready) {
1728 vpe_err(dev, "vpdma firmware not loaded\n");
1729 return -ENODEV;
1730 }
1731
1732 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1733 if (!ctx)
1734 return -ENOMEM;
1735
1736 ctx->dev = dev;
1737
1738 if (mutex_lock_interruptible(&dev->dev_mutex)) {
1739 ret = -ERESTARTSYS;
1740 goto free_ctx;
1741 }
1742
1743 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
1744 VPDMA_LIST_TYPE_NORMAL);
1745 if (ret != 0)
1746 goto unlock;
1747
1748 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
1749 if (ret != 0)
1750 goto free_desc_list;
1751
1752 init_adb_hdrs(ctx);
1753
1754 v4l2_fh_init(&ctx->fh, video_devdata(file));
1755 file->private_data = &ctx->fh;
1756
1757 hdl = &ctx->hdl;
1758 v4l2_ctrl_handler_init(hdl, 1);
1759 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
1760 if (hdl->error) {
1761 ret = hdl->error;
1762 goto exit_fh;
1763 }
1764 ctx->fh.ctrl_handler = hdl;
1765 v4l2_ctrl_handler_setup(hdl);
1766
1767 s_q_data = &ctx->q_data[Q_DATA_SRC];
1768 s_q_data->fmt = &vpe_formats[2];
1769 s_q_data->width = 1920;
1770 s_q_data->height = 1080;
1771 s_q_data->sizeimage[VPE_LUMA] = (s_q_data->width * s_q_data->height *
1772 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
1773 s_q_data->colorspace = V4L2_COLORSPACE_SMPTE240M;
585e6f01 1774 s_q_data->field = V4L2_FIELD_NONE;
45719127
AT		 1775 s_q_data->c_rect.left = 0;
1776 s_q_data->c_rect.top = 0;
1777 s_q_data->c_rect.width = s_q_data->width;
1778 s_q_data->c_rect.height = s_q_data->height;
1779 s_q_data->flags = 0;
1780
1781 ctx->q_data[Q_DATA_DST] = *s_q_data;
1782
585e6f01 1783 set_dei_shadow_registers(ctx);
45719127
AT		 1784 set_src_registers(ctx);
1785 set_dst_registers(ctx);
1786 ret = set_srcdst_params(ctx);
1787 if (ret)
1788 goto exit_fh;
1789
1790 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
1791
1792 if (IS_ERR(ctx->m2m_ctx)) {
1793 ret = PTR_ERR(ctx->m2m_ctx);
1794 goto exit_fh;
1795 }
1796
1797 v4l2_fh_add(&ctx->fh);
1798
1799 /*
1800 * for now, just report the creation of the first instance, we can later
1801 * optimize the driver to enable or disable clocks when the first
1802 * instance is created or the last instance released
1803 */
1804 if (atomic_inc_return(&dev->num_instances) == 1)
1805 vpe_dbg(dev, "first instance created\n");
1806
1807 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
1808
1809 ctx->load_mmrs = true;
1810
1811 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
1812 ctx, ctx->m2m_ctx);
1813
1814 mutex_unlock(&dev->dev_mutex);
1815
1816 return 0;
1817exit_fh:
1818 v4l2_ctrl_handler_free(hdl);
1819 v4l2_fh_exit(&ctx->fh);
1820 vpdma_free_desc_buf(&ctx->mmr_adb);
1821free_desc_list:
1822 vpdma_free_desc_list(&ctx->desc_list);
1823unlock:
1824 mutex_unlock(&dev->dev_mutex);
1825free_ctx:
1826 kfree(ctx);
1827 return ret;
1828}
1829
1830static int vpe_release(struct file *file)
1831{
1832 struct vpe_dev *dev = video_drvdata(file);
1833 struct vpe_ctx *ctx = file2ctx(file);
1834
1835 vpe_dbg(dev, "releasing instance %p\n", ctx);
1836
1837 mutex_lock(&dev->dev_mutex);
585e6f01
AT		 1838 free_vbs(ctx);
1839 free_mv_buffers(ctx);
45719127
AT		 1840 vpdma_free_desc_list(&ctx->desc_list);
1841 vpdma_free_desc_buf(&ctx->mmr_adb);
1842
1843 v4l2_fh_del(&ctx->fh);
1844 v4l2_fh_exit(&ctx->fh);
1845 v4l2_ctrl_handler_free(&ctx->hdl);
1846 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1847
1848 kfree(ctx);
1849
1850 /*
1851 * for now, just report the release of the last instance, we can later
1852 * optimize the driver to enable or disable clocks when the first
1853 * instance is created or the last instance released
1854 */
1855 if (atomic_dec_return(&dev->num_instances) == 0)
1856 vpe_dbg(dev, "last instance released\n");
1857
1858 mutex_unlock(&dev->dev_mutex);
1859
1860 return 0;
1861}
1862
1863static unsigned int vpe_poll(struct file *file,
1864 struct poll_table_struct *wait)
1865{
1866 struct vpe_ctx *ctx = file2ctx(file);
1867 struct vpe_dev *dev = ctx->dev;
1868 int ret;
1869
1870 mutex_lock(&dev->dev_mutex);
1871 ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1872 mutex_unlock(&dev->dev_mutex);
1873 return ret;
1874}
1875
1876static int vpe_mmap(struct file *file, struct vm_area_struct *vma)
1877{
1878 struct vpe_ctx *ctx = file2ctx(file);
1879 struct vpe_dev *dev = ctx->dev;
1880 int ret;
1881
1882 if (mutex_lock_interruptible(&dev->dev_mutex))
1883 return -ERESTARTSYS;
1884 ret = v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1885 mutex_unlock(&dev->dev_mutex);
1886 return ret;
1887}
1888
1889static const struct v4l2_file_operations vpe_fops = {
1890 .owner = THIS_MODULE,
1891 .open = vpe_open,
1892 .release = vpe_release,
1893 .poll = vpe_poll,
1894 .unlocked_ioctl = video_ioctl2,
1895 .mmap = vpe_mmap,
1896};
1897
1898static struct video_device vpe_videodev = {
1899 .name = VPE_MODULE_NAME,
1900 .fops = &vpe_fops,
1901 .ioctl_ops = &vpe_ioctl_ops,
1902 .minor = -1,
1903 .release = video_device_release,
1904 .vfl_dir = VFL_DIR_M2M,
1905};
1906
1907static struct v4l2_m2m_ops m2m_ops = {
1908 .device_run = device_run,
1909 .job_ready = job_ready,
1910 .job_abort = job_abort,
1911 .lock = vpe_lock,
1912 .unlock = vpe_unlock,
1913};
1914
1915static int vpe_runtime_get(struct platform_device *pdev)
1916{
1917 int r;
1918
1919 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
1920
1921 r = pm_runtime_get_sync(&pdev->dev);
1922 WARN_ON(r < 0);
1923 return r < 0 ? r : 0;
1924}
1925
1926static void vpe_runtime_put(struct platform_device *pdev)
1927{
1928
1929 int r;
1930
1931 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
1932
1933 r = pm_runtime_put_sync(&pdev->dev);
1934 WARN_ON(r < 0 && r != -ENOSYS);
1935}
1936
1937static int vpe_probe(struct platform_device *pdev)
1938{
1939 struct vpe_dev *dev;
1940 struct video_device *vfd;
1941 struct resource *res;
1942 int ret, irq, func;
1943
1944 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1945 if (IS_ERR(dev))
1946 return PTR_ERR(dev);
1947
1948 spin_lock_init(&dev->lock);
1949
1950 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1951 if (ret)
1952 return ret;
1953
1954 atomic_set(&dev->num_instances, 0);
1955 mutex_init(&dev->dev_mutex);
1956
1957 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpe_top");
1958 /*
1959 * HACK: we get resource info from device tree in the form of a list of
1960 * VPE sub blocks, the driver currently uses only the base of vpe_top
1961 * for register access, the driver should be changed later to access
1962 * registers based on the sub block base addresses
1963 */
1964 dev->base = devm_ioremap(&pdev->dev, res->start, SZ_32K);
1965 if (IS_ERR(dev->base)) {
1966 ret = PTR_ERR(dev->base);
1967 goto v4l2_dev_unreg;
1968 }
1969
1970 irq = platform_get_irq(pdev, 0);
1971 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
1972 dev);
1973 if (ret)
1974 goto v4l2_dev_unreg;
1975
1976 platform_set_drvdata(pdev, dev);
1977
1978 dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1979 if (IS_ERR(dev->alloc_ctx)) {
1980 vpe_err(dev, "Failed to alloc vb2 context\n");
1981 ret = PTR_ERR(dev->alloc_ctx);
1982 goto v4l2_dev_unreg;
1983 }
1984
1985 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
1986 if (IS_ERR(dev->m2m_dev)) {
1987 vpe_err(dev, "Failed to init mem2mem device\n");
1988 ret = PTR_ERR(dev->m2m_dev);
1989 goto rel_ctx;
1990 }
1991
1992 pm_runtime_enable(&pdev->dev);
1993
1994 ret = vpe_runtime_get(pdev);
1995 if (ret)
1996 goto rel_m2m;
1997
1998 /* Perform clk enable followed by reset */
1999 vpe_set_clock_enable(dev, 1);
2000
2001 vpe_top_reset(dev);
2002
2003 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2004 VPE_PID_FUNC_SHIFT);
2005 vpe_dbg(dev, "VPE PID function %x\n", func);
2006
2007 vpe_top_vpdma_reset(dev);
2008
2009 dev->vpdma = vpdma_create(pdev);
2010 if (IS_ERR(dev->vpdma))
2011 goto runtime_put;
2012
2013 vfd = &dev->vfd;
2014 *vfd = vpe_videodev;
2015 vfd->lock = &dev->dev_mutex;
2016 vfd->v4l2_dev = &dev->v4l2_dev;
2017
2018 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2019 if (ret) {
2020 vpe_err(dev, "Failed to register video device\n");
2021 goto runtime_put;
2022 }
2023
2024 video_set_drvdata(vfd, dev);
2025 snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name);
2026 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2027 vfd->num);
2028
2029 return 0;
2030
2031runtime_put:
2032 vpe_runtime_put(pdev);
2033rel_m2m:
2034 pm_runtime_disable(&pdev->dev);
2035 v4l2_m2m_release(dev->m2m_dev);
2036rel_ctx:
2037 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2038v4l2_dev_unreg:
2039 v4l2_device_unregister(&dev->v4l2_dev);
2040
2041 return ret;
2042}
2043
2044static int vpe_remove(struct platform_device *pdev)
2045{
2046 struct vpe_dev *dev =
2047 (struct vpe_dev *) platform_get_drvdata(pdev);
2048
2049 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2050
2051 v4l2_m2m_release(dev->m2m_dev);
2052 video_unregister_device(&dev->vfd);
2053 v4l2_device_unregister(&dev->v4l2_dev);
2054 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2055
2056 vpe_set_clock_enable(dev, 0);
2057 vpe_runtime_put(pdev);
2058 pm_runtime_disable(&pdev->dev);
2059
2060 return 0;
2061}
2062
2063#if defined(CONFIG_OF)
2064static const struct of_device_id vpe_of_match[] = {
2065 {
2066 .compatible = "ti,vpe",
2067 },
2068 {},
2069};
2070#else
2071#define vpe_of_match NULL
2072#endif
2073
2074static struct platform_driver vpe_pdrv = {
2075 .probe = vpe_probe,
2076 .remove = vpe_remove,
2077 .driver = {
2078 .name = VPE_MODULE_NAME,
2079 .owner = THIS_MODULE,
2080 .of_match_table = vpe_of_match,
2081 },
2082};
2083
2084static void __exit vpe_exit(void)
2085{
2086 platform_driver_unregister(&vpe_pdrv);
2087}
2088
2089static int __init vpe_init(void)
2090{
2091 return platform_driver_register(&vpe_pdrv);
2092}
2093
2094module_init(vpe_init);
2095module_exit(vpe_exit);
2096
2097MODULE_DESCRIPTION("TI VPE driver");
2098MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2099MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)