Commit | Line | Data |
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45719127 AT |
1 | /* |
2 | * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver | |
3 | * | |
4 | * Copyright (c) 2013 Texas Instruments Inc. | |
5 | * David Griego, <dagriego@biglakesoftware.com> | |
6 | * Dale Farnsworth, <dale@farnsworth.org> | |
7 | * Archit Taneja, <archit@ti.com> | |
8 | * | |
9 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | |
10 | * Pawel Osciak, <pawel@osciak.com> | |
11 | * Marek Szyprowski, <m.szyprowski@samsung.com> | |
12 | * | |
13 | * Based on the virtual v4l2-mem2mem example device | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License version 2 as published by | |
17 | * the Free Software Foundation | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/ioctl.h> | |
27 | #include <linux/module.h> | |
47e604c5 | 28 | #include <linux/of.h> |
45719127 AT |
29 | #include <linux/platform_device.h> |
30 | #include <linux/pm_runtime.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/videodev2.h> | |
a51cd8f5 | 34 | #include <linux/log2.h> |
f3334180 | 35 | #include <linux/sizes.h> |
45719127 AT |
36 | |
37 | #include <media/v4l2-common.h> | |
38 | #include <media/v4l2-ctrls.h> | |
39 | #include <media/v4l2-device.h> | |
40 | #include <media/v4l2-event.h> | |
41 | #include <media/v4l2-ioctl.h> | |
42 | #include <media/v4l2-mem2mem.h> | |
c139990e | 43 | #include <media/videobuf2-v4l2.h> |
45719127 AT |
44 | #include <media/videobuf2-dma-contig.h> |
45 | ||
46 | #include "vpdma.h" | |
634271f8 | 47 | #include "vpdma_priv.h" |
45719127 | 48 | #include "vpe_regs.h" |
44687b2e | 49 | #include "sc.h" |
6948082d | 50 | #include "csc.h" |
45719127 AT |
51 | |
52 | #define VPE_MODULE_NAME "vpe" | |
53 | ||
54 | /* minimum and maximum frame sizes */ | |
ce392fd7 AT |
55 | #define MIN_W 32 |
56 | #define MIN_H 32 | |
8028bfed HB |
57 | #define MAX_W 2048 |
58 | #define MAX_H 1184 | |
45719127 AT |
59 | |
60 | /* required alignments */ | |
61 | #define S_ALIGN 0 /* multiple of 1 */ | |
62 | #define H_ALIGN 1 /* multiple of 2 */ | |
45719127 AT |
63 | |
64 | /* flags that indicate a format can be used for capture/output */ | |
65 | #define VPE_FMT_TYPE_CAPTURE (1 << 0) | |
66 | #define VPE_FMT_TYPE_OUTPUT (1 << 1) | |
67 | ||
68 | /* used as plane indices */ | |
69 | #define VPE_MAX_PLANES 2 | |
70 | #define VPE_LUMA 0 | |
71 | #define VPE_CHROMA 1 | |
72 | ||
73 | /* per m2m context info */ | |
585e6f01 AT |
74 | #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */ |
75 | ||
45719127 AT |
76 | #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */ |
77 | ||
78 | /* | |
47e604c5 | 79 | * each VPE context can need up to 3 config descriptors, 7 input descriptors, |
45719127 AT |
80 | * 3 output descriptors, and 10 control descriptors |
81 | */ | |
82 | #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \ | |
83 | 13 * VPDMA_CFD_CTD_DESC_SIZE) | |
84 | ||
85 | #define vpe_dbg(vpedev, fmt, arg...) \ | |
86 | dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg) | |
87 | #define vpe_err(vpedev, fmt, arg...) \ | |
88 | dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg) | |
89 | ||
90 | struct vpe_us_coeffs { | |
91 | unsigned short anchor_fid0_c0; | |
92 | unsigned short anchor_fid0_c1; | |
93 | unsigned short anchor_fid0_c2; | |
94 | unsigned short anchor_fid0_c3; | |
95 | unsigned short interp_fid0_c0; | |
96 | unsigned short interp_fid0_c1; | |
97 | unsigned short interp_fid0_c2; | |
98 | unsigned short interp_fid0_c3; | |
99 | unsigned short anchor_fid1_c0; | |
100 | unsigned short anchor_fid1_c1; | |
101 | unsigned short anchor_fid1_c2; | |
102 | unsigned short anchor_fid1_c3; | |
103 | unsigned short interp_fid1_c0; | |
104 | unsigned short interp_fid1_c1; | |
105 | unsigned short interp_fid1_c2; | |
106 | unsigned short interp_fid1_c3; | |
107 | }; | |
108 | ||
109 | /* | |
110 | * Default upsampler coefficients | |
111 | */ | |
112 | static const struct vpe_us_coeffs us_coeffs[] = { | |
113 | { | |
114 | /* Coefficients for progressive input */ | |
115 | 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8, | |
116 | 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8, | |
117 | }, | |
585e6f01 AT |
118 | { |
119 | /* Coefficients for Top Field Interlaced input */ | |
120 | 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3, | |
121 | /* Coefficients for Bottom Field Interlaced input */ | |
122 | 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9, | |
123 | }, | |
124 | }; | |
125 | ||
126 | /* | |
127 | * the following registers are for configuring some of the parameters of the | |
128 | * motion and edge detection blocks inside DEI, these generally remain the same, | |
129 | * these could be passed later via userspace if some one needs to tweak these. | |
130 | */ | |
131 | struct vpe_dei_regs { | |
132 | unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */ | |
133 | unsigned long edi_config_reg; /* VPE_DEI_REG3 */ | |
134 | unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */ | |
135 | unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */ | |
136 | unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */ | |
137 | unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */ | |
138 | }; | |
139 | ||
140 | /* | |
141 | * default expert DEI register values, unlikely to be modified. | |
142 | */ | |
143 | static const struct vpe_dei_regs dei_regs = { | |
1148f6fd | 144 | .mdt_spacial_freq_thr_reg = 0x020C0804u, |
15f632e6 | 145 | .edi_config_reg = 0x0118100Cu, |
1148f6fd JL |
146 | .edi_lut_reg0 = 0x08040200u, |
147 | .edi_lut_reg1 = 0x1010100Cu, | |
148 | .edi_lut_reg2 = 0x10101010u, | |
149 | .edi_lut_reg3 = 0x10101010u, | |
45719127 AT |
150 | }; |
151 | ||
152 | /* | |
153 | * The port_data structure contains per-port data. | |
154 | */ | |
155 | struct vpe_port_data { | |
156 | enum vpdma_channel channel; /* VPDMA channel */ | |
585e6f01 | 157 | u8 vb_index; /* input frame f, f-1, f-2 index */ |
45719127 AT |
158 | u8 vb_part; /* plane index for co-panar formats */ |
159 | }; | |
160 | ||
161 | /* | |
162 | * Define indices into the port_data tables | |
163 | */ | |
164 | #define VPE_PORT_LUMA1_IN 0 | |
165 | #define VPE_PORT_CHROMA1_IN 1 | |
585e6f01 AT |
166 | #define VPE_PORT_LUMA2_IN 2 |
167 | #define VPE_PORT_CHROMA2_IN 3 | |
168 | #define VPE_PORT_LUMA3_IN 4 | |
169 | #define VPE_PORT_CHROMA3_IN 5 | |
170 | #define VPE_PORT_MV_IN 6 | |
171 | #define VPE_PORT_MV_OUT 7 | |
45719127 AT |
172 | #define VPE_PORT_LUMA_OUT 8 |
173 | #define VPE_PORT_CHROMA_OUT 9 | |
174 | #define VPE_PORT_RGB_OUT 10 | |
175 | ||
176 | static const struct vpe_port_data port_data[11] = { | |
177 | [VPE_PORT_LUMA1_IN] = { | |
178 | .channel = VPE_CHAN_LUMA1_IN, | |
585e6f01 | 179 | .vb_index = 0, |
45719127 AT |
180 | .vb_part = VPE_LUMA, |
181 | }, | |
182 | [VPE_PORT_CHROMA1_IN] = { | |
183 | .channel = VPE_CHAN_CHROMA1_IN, | |
585e6f01 AT |
184 | .vb_index = 0, |
185 | .vb_part = VPE_CHROMA, | |
186 | }, | |
187 | [VPE_PORT_LUMA2_IN] = { | |
188 | .channel = VPE_CHAN_LUMA2_IN, | |
189 | .vb_index = 1, | |
190 | .vb_part = VPE_LUMA, | |
191 | }, | |
192 | [VPE_PORT_CHROMA2_IN] = { | |
193 | .channel = VPE_CHAN_CHROMA2_IN, | |
194 | .vb_index = 1, | |
195 | .vb_part = VPE_CHROMA, | |
196 | }, | |
197 | [VPE_PORT_LUMA3_IN] = { | |
198 | .channel = VPE_CHAN_LUMA3_IN, | |
199 | .vb_index = 2, | |
200 | .vb_part = VPE_LUMA, | |
201 | }, | |
202 | [VPE_PORT_CHROMA3_IN] = { | |
203 | .channel = VPE_CHAN_CHROMA3_IN, | |
204 | .vb_index = 2, | |
45719127 AT |
205 | .vb_part = VPE_CHROMA, |
206 | }, | |
585e6f01 AT |
207 | [VPE_PORT_MV_IN] = { |
208 | .channel = VPE_CHAN_MV_IN, | |
209 | }, | |
210 | [VPE_PORT_MV_OUT] = { | |
211 | .channel = VPE_CHAN_MV_OUT, | |
212 | }, | |
45719127 AT |
213 | [VPE_PORT_LUMA_OUT] = { |
214 | .channel = VPE_CHAN_LUMA_OUT, | |
215 | .vb_part = VPE_LUMA, | |
216 | }, | |
217 | [VPE_PORT_CHROMA_OUT] = { | |
218 | .channel = VPE_CHAN_CHROMA_OUT, | |
219 | .vb_part = VPE_CHROMA, | |
220 | }, | |
221 | [VPE_PORT_RGB_OUT] = { | |
222 | .channel = VPE_CHAN_RGB_OUT, | |
223 | .vb_part = VPE_LUMA, | |
224 | }, | |
225 | }; | |
226 | ||
227 | ||
228 | /* driver info for each of the supported video formats */ | |
229 | struct vpe_fmt { | |
230 | char *name; /* human-readable name */ | |
231 | u32 fourcc; /* standard format identifier */ | |
232 | u8 types; /* CAPTURE and/or OUTPUT */ | |
233 | u8 coplanar; /* set for unpacked Luma and Chroma */ | |
234 | /* vpdma format info for each plane */ | |
235 | struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES]; | |
236 | }; | |
237 | ||
238 | static struct vpe_fmt vpe_formats[] = { | |
239 | { | |
eaa6808d | 240 | .name = "NV16 YUV 422 co-planar", |
45719127 AT |
241 | .fourcc = V4L2_PIX_FMT_NV16, |
242 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
243 | .coplanar = 1, | |
244 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444], | |
245 | &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444], | |
246 | }, | |
247 | }, | |
248 | { | |
eaa6808d | 249 | .name = "NV12 YUV 420 co-planar", |
45719127 AT |
250 | .fourcc = V4L2_PIX_FMT_NV12, |
251 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
252 | .coplanar = 1, | |
253 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420], | |
254 | &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420], | |
255 | }, | |
256 | }, | |
257 | { | |
258 | .name = "YUYV 422 packed", | |
259 | .fourcc = V4L2_PIX_FMT_YUYV, | |
260 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
261 | .coplanar = 0, | |
eaa6808d | 262 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422], |
45719127 AT |
263 | }, |
264 | }, | |
265 | { | |
266 | .name = "UYVY 422 packed", | |
267 | .fourcc = V4L2_PIX_FMT_UYVY, | |
268 | .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT, | |
269 | .coplanar = 0, | |
eaa6808d | 270 | .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422], |
45719127 AT |
271 | }, |
272 | }, | |
30496799 AT |
273 | { |
274 | .name = "RGB888 packed", | |
275 | .fourcc = V4L2_PIX_FMT_RGB24, | |
276 | .types = VPE_FMT_TYPE_CAPTURE, | |
277 | .coplanar = 0, | |
278 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24], | |
279 | }, | |
280 | }, | |
281 | { | |
282 | .name = "ARGB32", | |
283 | .fourcc = V4L2_PIX_FMT_RGB32, | |
284 | .types = VPE_FMT_TYPE_CAPTURE, | |
285 | .coplanar = 0, | |
286 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32], | |
287 | }, | |
288 | }, | |
289 | { | |
290 | .name = "BGR888 packed", | |
291 | .fourcc = V4L2_PIX_FMT_BGR24, | |
292 | .types = VPE_FMT_TYPE_CAPTURE, | |
293 | .coplanar = 0, | |
294 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24], | |
295 | }, | |
296 | }, | |
297 | { | |
298 | .name = "ABGR32", | |
299 | .fourcc = V4L2_PIX_FMT_BGR32, | |
300 | .types = VPE_FMT_TYPE_CAPTURE, | |
301 | .coplanar = 0, | |
302 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32], | |
303 | }, | |
304 | }, | |
b28b8f1d ND |
305 | { |
306 | .name = "RGB565", | |
307 | .fourcc = V4L2_PIX_FMT_RGB565, | |
308 | .types = VPE_FMT_TYPE_CAPTURE, | |
309 | .coplanar = 0, | |
310 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565], | |
311 | }, | |
312 | }, | |
313 | { | |
314 | .name = "RGB5551", | |
315 | .fourcc = V4L2_PIX_FMT_RGB555, | |
316 | .types = VPE_FMT_TYPE_CAPTURE, | |
317 | .coplanar = 0, | |
318 | .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551], | |
319 | }, | |
320 | }, | |
45719127 AT |
321 | }; |
322 | ||
323 | /* | |
324 | * per-queue, driver-specific private data. | |
325 | * there is one source queue and one destination queue for each m2m context. | |
326 | */ | |
327 | struct vpe_q_data { | |
328 | unsigned int width; /* frame width */ | |
329 | unsigned int height; /* frame height */ | |
ed1f47cc | 330 | unsigned int nplanes; /* Current number of planes */ |
45719127 AT |
331 | unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */ |
332 | enum v4l2_colorspace colorspace; | |
585e6f01 | 333 | enum v4l2_field field; /* supported field value */ |
45719127 AT |
334 | unsigned int flags; |
335 | unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */ | |
336 | struct v4l2_rect c_rect; /* crop/compose rectangle */ | |
337 | struct vpe_fmt *fmt; /* format info */ | |
338 | }; | |
339 | ||
340 | /* vpe_q_data flag bits */ | |
823f4208 ND |
341 | #define Q_DATA_FRAME_1D BIT(0) |
342 | #define Q_DATA_MODE_TILED BIT(1) | |
343 | #define Q_DATA_INTERLACED_ALTERNATE BIT(2) | |
344 | #define Q_DATA_INTERLACED_SEQ_TB BIT(3) | |
345 | ||
346 | #define Q_IS_INTERLACED (Q_DATA_INTERLACED_ALTERNATE | \ | |
347 | Q_DATA_INTERLACED_SEQ_TB) | |
45719127 AT |
348 | |
349 | enum { | |
350 | Q_DATA_SRC = 0, | |
351 | Q_DATA_DST = 1, | |
352 | }; | |
353 | ||
354 | /* find our format description corresponding to the passed v4l2_format */ | |
355 | static struct vpe_fmt *find_format(struct v4l2_format *f) | |
356 | { | |
357 | struct vpe_fmt *fmt; | |
358 | unsigned int k; | |
359 | ||
360 | for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) { | |
361 | fmt = &vpe_formats[k]; | |
362 | if (fmt->fourcc == f->fmt.pix.pixelformat) | |
363 | return fmt; | |
364 | } | |
365 | ||
366 | return NULL; | |
367 | } | |
368 | ||
369 | /* | |
370 | * there is one vpe_dev structure in the driver, it is shared by | |
371 | * all instances. | |
372 | */ | |
373 | struct vpe_dev { | |
374 | struct v4l2_device v4l2_dev; | |
375 | struct video_device vfd; | |
376 | struct v4l2_m2m_dev *m2m_dev; | |
377 | ||
378 | atomic_t num_instances; /* count of driver instances */ | |
379 | dma_addr_t loaded_mmrs; /* shadow mmrs in device */ | |
380 | struct mutex dev_mutex; | |
381 | spinlock_t lock; | |
382 | ||
383 | int irq; | |
384 | void __iomem *base; | |
44687b2e | 385 | struct resource *res; |
45719127 | 386 | |
c786595b | 387 | struct vpdma_data vpdma_data; |
45719127 | 388 | struct vpdma_data *vpdma; /* vpdma data handle */ |
44687b2e | 389 | struct sc_data *sc; /* scaler data handle */ |
6948082d | 390 | struct csc_data *csc; /* csc data handle */ |
45719127 AT |
391 | }; |
392 | ||
393 | /* | |
394 | * There is one vpe_ctx structure for each m2m context. | |
395 | */ | |
396 | struct vpe_ctx { | |
397 | struct v4l2_fh fh; | |
398 | struct vpe_dev *dev; | |
45719127 AT |
399 | struct v4l2_ctrl_handler hdl; |
400 | ||
585e6f01 | 401 | unsigned int field; /* current field */ |
45719127 AT |
402 | unsigned int sequence; /* current frame/field seq */ |
403 | unsigned int aborting; /* abort after next irq */ | |
404 | ||
405 | unsigned int bufs_per_job; /* input buffers per batch */ | |
406 | unsigned int bufs_completed; /* bufs done in this batch */ | |
407 | ||
408 | struct vpe_q_data q_data[2]; /* src & dst queue data */ | |
2d700715 JS |
409 | struct vb2_v4l2_buffer *src_vbs[VPE_MAX_SRC_BUFS]; |
410 | struct vb2_v4l2_buffer *dst_vb; | |
45719127 | 411 | |
585e6f01 AT |
412 | dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */ |
413 | void *mv_buf[2]; /* virtual addrs of motion vector bufs */ | |
414 | size_t mv_buf_size; /* current motion vector buffer size */ | |
45719127 | 415 | struct vpdma_buf mmr_adb; /* shadow reg addr/data block */ |
773f0657 AT |
416 | struct vpdma_buf sc_coeff_h; /* h coeff buffer */ |
417 | struct vpdma_buf sc_coeff_v; /* v coeff buffer */ | |
45719127 AT |
418 | struct vpdma_desc_list desc_list; /* DMA descriptor list */ |
419 | ||
585e6f01 | 420 | bool deinterlacing; /* using de-interlacer */ |
45719127 | 421 | bool load_mmrs; /* have new shadow reg values */ |
585e6f01 AT |
422 | |
423 | unsigned int src_mv_buf_selector; | |
45719127 AT |
424 | }; |
425 | ||
426 | ||
427 | /* | |
428 | * M2M devices get 2 queues. | |
429 | * Return the queue given the type. | |
430 | */ | |
431 | static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx, | |
432 | enum v4l2_buf_type type) | |
433 | { | |
434 | switch (type) { | |
435 | case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: | |
2ef114f6 | 436 | case V4L2_BUF_TYPE_VIDEO_OUTPUT: |
45719127 AT |
437 | return &ctx->q_data[Q_DATA_SRC]; |
438 | case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: | |
2ef114f6 | 439 | case V4L2_BUF_TYPE_VIDEO_CAPTURE: |
45719127 AT |
440 | return &ctx->q_data[Q_DATA_DST]; |
441 | default: | |
072915b5 | 442 | return NULL; |
45719127 AT |
443 | } |
444 | return NULL; | |
445 | } | |
446 | ||
447 | static u32 read_reg(struct vpe_dev *dev, int offset) | |
448 | { | |
449 | return ioread32(dev->base + offset); | |
450 | } | |
451 | ||
452 | static void write_reg(struct vpe_dev *dev, int offset, u32 value) | |
453 | { | |
454 | iowrite32(value, dev->base + offset); | |
455 | } | |
456 | ||
457 | /* register field read/write helpers */ | |
458 | static int get_field(u32 value, u32 mask, int shift) | |
459 | { | |
460 | return (value & (mask << shift)) >> shift; | |
461 | } | |
462 | ||
463 | static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift) | |
464 | { | |
465 | return get_field(read_reg(dev, offset), mask, shift); | |
466 | } | |
467 | ||
468 | static void write_field(u32 *valp, u32 field, u32 mask, int shift) | |
469 | { | |
470 | u32 val = *valp; | |
471 | ||
472 | val &= ~(mask << shift); | |
473 | val |= (field & mask) << shift; | |
474 | *valp = val; | |
475 | } | |
476 | ||
477 | static void write_field_reg(struct vpe_dev *dev, int offset, u32 field, | |
478 | u32 mask, int shift) | |
479 | { | |
480 | u32 val = read_reg(dev, offset); | |
481 | ||
482 | write_field(&val, field, mask, shift); | |
483 | ||
484 | write_reg(dev, offset, val); | |
485 | } | |
486 | ||
487 | /* | |
488 | * DMA address/data block for the shadow registers | |
489 | */ | |
490 | struct vpe_mmr_adb { | |
491 | struct vpdma_adb_hdr out_fmt_hdr; | |
492 | u32 out_fmt_reg[1]; | |
493 | u32 out_fmt_pad[3]; | |
494 | struct vpdma_adb_hdr us1_hdr; | |
495 | u32 us1_regs[8]; | |
496 | struct vpdma_adb_hdr us2_hdr; | |
497 | u32 us2_regs[8]; | |
498 | struct vpdma_adb_hdr us3_hdr; | |
499 | u32 us3_regs[8]; | |
500 | struct vpdma_adb_hdr dei_hdr; | |
585e6f01 | 501 | u32 dei_regs[8]; |
bbee8b39 AT |
502 | struct vpdma_adb_hdr sc_hdr0; |
503 | u32 sc_regs0[7]; | |
504 | u32 sc_pad0[1]; | |
505 | struct vpdma_adb_hdr sc_hdr8; | |
506 | u32 sc_regs8[6]; | |
507 | u32 sc_pad8[2]; | |
508 | struct vpdma_adb_hdr sc_hdr17; | |
509 | u32 sc_regs17[9]; | |
510 | u32 sc_pad17[3]; | |
45719127 AT |
511 | struct vpdma_adb_hdr csc_hdr; |
512 | u32 csc_regs[6]; | |
513 | u32 csc_pad[2]; | |
514 | }; | |
515 | ||
44687b2e AT |
516 | #define GET_OFFSET_TOP(ctx, obj, reg) \ |
517 | ((obj)->res->start - ctx->dev->res->start + reg) | |
518 | ||
45719127 AT |
519 | #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \ |
520 | VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a) | |
521 | /* | |
522 | * Set the headers for all of the address/data block structures. | |
523 | */ | |
524 | static void init_adb_hdrs(struct vpe_ctx *ctx) | |
525 | { | |
526 | VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT); | |
527 | VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0); | |
528 | VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0); | |
529 | VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0); | |
530 | VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE); | |
bbee8b39 | 531 | VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0, |
44687b2e | 532 | GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0)); |
bbee8b39 AT |
533 | VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8, |
534 | GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8)); | |
535 | VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17, | |
536 | GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17)); | |
6948082d AT |
537 | VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs, |
538 | GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00)); | |
45719127 AT |
539 | }; |
540 | ||
585e6f01 AT |
541 | /* |
542 | * Allocate or re-allocate the motion vector DMA buffers | |
543 | * There are two buffers, one for input and one for output. | |
544 | * However, the roles are reversed after each field is processed. | |
545 | * In other words, after each field is processed, the previous | |
546 | * output (dst) MV buffer becomes the new input (src) MV buffer. | |
547 | */ | |
548 | static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size) | |
549 | { | |
550 | struct device *dev = ctx->dev->v4l2_dev.dev; | |
551 | ||
552 | if (ctx->mv_buf_size == size) | |
553 | return 0; | |
554 | ||
555 | if (ctx->mv_buf[0]) | |
556 | dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0], | |
557 | ctx->mv_buf_dma[0]); | |
558 | ||
559 | if (ctx->mv_buf[1]) | |
560 | dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1], | |
561 | ctx->mv_buf_dma[1]); | |
562 | ||
563 | if (size == 0) | |
564 | return 0; | |
565 | ||
566 | ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0], | |
567 | GFP_KERNEL); | |
568 | if (!ctx->mv_buf[0]) { | |
569 | vpe_err(ctx->dev, "failed to allocate motion vector buffer\n"); | |
570 | return -ENOMEM; | |
571 | } | |
572 | ||
573 | ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1], | |
574 | GFP_KERNEL); | |
575 | if (!ctx->mv_buf[1]) { | |
576 | vpe_err(ctx->dev, "failed to allocate motion vector buffer\n"); | |
577 | dma_free_coherent(dev, size, ctx->mv_buf[0], | |
578 | ctx->mv_buf_dma[0]); | |
579 | ||
580 | return -ENOMEM; | |
581 | } | |
582 | ||
583 | ctx->mv_buf_size = size; | |
584 | ctx->src_mv_buf_selector = 0; | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | static void free_mv_buffers(struct vpe_ctx *ctx) | |
590 | { | |
591 | realloc_mv_buffers(ctx, 0); | |
592 | } | |
593 | ||
594 | /* | |
595 | * While de-interlacing, we keep the two most recent input buffers | |
596 | * around. This function frees those two buffers when we have | |
597 | * finished processing the current stream. | |
598 | */ | |
599 | static void free_vbs(struct vpe_ctx *ctx) | |
600 | { | |
601 | struct vpe_dev *dev = ctx->dev; | |
602 | unsigned long flags; | |
603 | ||
604 | if (ctx->src_vbs[2] == NULL) | |
605 | return; | |
606 | ||
607 | spin_lock_irqsave(&dev->lock, flags); | |
608 | if (ctx->src_vbs[2]) { | |
609 | v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE); | |
dfe1349d BP |
610 | if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2])) |
611 | v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE); | |
612 | ctx->src_vbs[2] = NULL; | |
613 | ctx->src_vbs[1] = NULL; | |
585e6f01 AT |
614 | } |
615 | spin_unlock_irqrestore(&dev->lock, flags); | |
616 | } | |
617 | ||
45719127 AT |
618 | /* |
619 | * Enable or disable the VPE clocks | |
620 | */ | |
621 | static void vpe_set_clock_enable(struct vpe_dev *dev, bool on) | |
622 | { | |
623 | u32 val = 0; | |
624 | ||
625 | if (on) | |
626 | val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE; | |
627 | write_reg(dev, VPE_CLK_ENABLE, val); | |
628 | } | |
629 | ||
630 | static void vpe_top_reset(struct vpe_dev *dev) | |
631 | { | |
632 | ||
633 | write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK, | |
634 | VPE_DATA_PATH_CLK_RESET_SHIFT); | |
635 | ||
636 | usleep_range(100, 150); | |
637 | ||
638 | write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK, | |
639 | VPE_DATA_PATH_CLK_RESET_SHIFT); | |
640 | } | |
641 | ||
642 | static void vpe_top_vpdma_reset(struct vpe_dev *dev) | |
643 | { | |
644 | write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK, | |
645 | VPE_VPDMA_CLK_RESET_SHIFT); | |
646 | ||
647 | usleep_range(100, 150); | |
648 | ||
649 | write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK, | |
650 | VPE_VPDMA_CLK_RESET_SHIFT); | |
651 | } | |
652 | ||
653 | /* | |
654 | * Load the correct of upsampler coefficients into the shadow MMRs | |
655 | */ | |
656 | static void set_us_coefficients(struct vpe_ctx *ctx) | |
657 | { | |
658 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
585e6f01 | 659 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; |
45719127 AT |
660 | u32 *us1_reg = &mmr_adb->us1_regs[0]; |
661 | u32 *us2_reg = &mmr_adb->us2_regs[0]; | |
662 | u32 *us3_reg = &mmr_adb->us3_regs[0]; | |
663 | const unsigned short *cp, *end_cp; | |
664 | ||
665 | cp = &us_coeffs[0].anchor_fid0_c0; | |
666 | ||
823f4208 | 667 | if (s_q_data->flags & Q_IS_INTERLACED) /* interlaced */ |
585e6f01 AT |
668 | cp += sizeof(us_coeffs[0]) / sizeof(*cp); |
669 | ||
45719127 AT |
670 | end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp); |
671 | ||
672 | while (cp < end_cp) { | |
673 | write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT); | |
674 | write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT); | |
675 | *us2_reg++ = *us1_reg; | |
676 | *us3_reg++ = *us1_reg++; | |
677 | } | |
678 | ctx->load_mmrs = true; | |
679 | } | |
680 | ||
681 | /* | |
682 | * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs. | |
683 | */ | |
655e4656 | 684 | static void set_cfg_modes(struct vpe_ctx *ctx) |
45719127 AT |
685 | { |
686 | struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt; | |
687 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
688 | u32 *us1_reg0 = &mmr_adb->us1_regs[0]; | |
689 | u32 *us2_reg0 = &mmr_adb->us2_regs[0]; | |
690 | u32 *us3_reg0 = &mmr_adb->us3_regs[0]; | |
45719127 AT |
691 | int cfg_mode = 1; |
692 | ||
693 | /* | |
694 | * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing. | |
695 | * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing. | |
696 | */ | |
697 | ||
655e4656 | 698 | if (fmt->fourcc == V4L2_PIX_FMT_NV12) |
45719127 | 699 | cfg_mode = 0; |
45719127 AT |
700 | |
701 | write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT); | |
702 | write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT); | |
703 | write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT); | |
704 | ||
655e4656 ND |
705 | ctx->load_mmrs = true; |
706 | } | |
707 | ||
708 | static void set_line_modes(struct vpe_ctx *ctx) | |
709 | { | |
710 | struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt; | |
711 | int line_mode = 1; | |
712 | ||
713 | if (fmt->fourcc == V4L2_PIX_FMT_NV12) | |
714 | line_mode = 0; /* double lines to line buffer */ | |
715 | ||
45719127 AT |
716 | /* regs for now */ |
717 | vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN); | |
585e6f01 AT |
718 | vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN); |
719 | vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN); | |
45719127 AT |
720 | |
721 | /* frame start for input luma */ | |
722 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
723 | VPE_CHAN_LUMA1_IN); | |
585e6f01 AT |
724 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, |
725 | VPE_CHAN_LUMA2_IN); | |
726 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
727 | VPE_CHAN_LUMA3_IN); | |
45719127 AT |
728 | |
729 | /* frame start for input chroma */ | |
730 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
731 | VPE_CHAN_CHROMA1_IN); | |
585e6f01 AT |
732 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, |
733 | VPE_CHAN_CHROMA2_IN); | |
734 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
735 | VPE_CHAN_CHROMA3_IN); | |
736 | ||
737 | /* frame start for MV in client */ | |
738 | vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE, | |
739 | VPE_CHAN_MV_IN); | |
45719127 AT |
740 | } |
741 | ||
742 | /* | |
743 | * Set the shadow registers that are modified when the source | |
744 | * format changes. | |
745 | */ | |
746 | static void set_src_registers(struct vpe_ctx *ctx) | |
747 | { | |
748 | set_us_coefficients(ctx); | |
749 | } | |
750 | ||
751 | /* | |
752 | * Set the shadow registers that are modified when the destination | |
753 | * format changes. | |
754 | */ | |
755 | static void set_dst_registers(struct vpe_ctx *ctx) | |
756 | { | |
757 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
30496799 | 758 | enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace; |
45719127 AT |
759 | struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt; |
760 | u32 val = 0; | |
761 | ||
b28b8f1d | 762 | if (clrspc == V4L2_COLORSPACE_SRGB) { |
30496799 | 763 | val |= VPE_RGB_OUT_SELECT; |
b28b8f1d ND |
764 | vpdma_set_bg_color(ctx->dev->vpdma, |
765 | (struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff); | |
766 | } else if (fmt->fourcc == V4L2_PIX_FMT_NV16) | |
45719127 AT |
767 | val |= VPE_COLOR_SEPARATE_422; |
768 | ||
30496799 AT |
769 | /* |
770 | * the source of CHR_DS and CSC is always the scaler, irrespective of | |
771 | * whether it's used or not | |
772 | */ | |
773 | val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER; | |
45719127 AT |
774 | |
775 | if (fmt->fourcc != V4L2_PIX_FMT_NV12) | |
776 | val |= VPE_DS_BYPASS; | |
777 | ||
778 | mmr_adb->out_fmt_reg[0] = val; | |
779 | ||
780 | ctx->load_mmrs = true; | |
781 | } | |
782 | ||
783 | /* | |
784 | * Set the de-interlacer shadow register values | |
785 | */ | |
585e6f01 | 786 | static void set_dei_regs(struct vpe_ctx *ctx) |
45719127 AT |
787 | { |
788 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
789 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; | |
790 | unsigned int src_h = s_q_data->c_rect.height; | |
791 | unsigned int src_w = s_q_data->c_rect.width; | |
792 | u32 *dei_mmr0 = &mmr_adb->dei_regs[0]; | |
585e6f01 | 793 | bool deinterlace = true; |
45719127 AT |
794 | u32 val = 0; |
795 | ||
796 | /* | |
797 | * according to TRM, we should set DEI in progressive bypass mode when | |
798 | * the input content is progressive, however, DEI is bypassed correctly | |
799 | * for both progressive and interlace content in interlace bypass mode. | |
800 | * It has been recommended not to use progressive bypass mode. | |
801 | */ | |
823f4208 | 802 | if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) { |
585e6f01 AT |
803 | deinterlace = false; |
804 | val = VPE_DEI_INTERLACE_BYPASS; | |
805 | } | |
806 | ||
807 | src_h = deinterlace ? src_h * 2 : src_h; | |
45719127 AT |
808 | |
809 | val |= (src_h << VPE_DEI_HEIGHT_SHIFT) | | |
810 | (src_w << VPE_DEI_WIDTH_SHIFT) | | |
811 | VPE_DEI_FIELD_FLUSH; | |
812 | ||
813 | *dei_mmr0 = val; | |
814 | ||
815 | ctx->load_mmrs = true; | |
816 | } | |
817 | ||
585e6f01 AT |
818 | static void set_dei_shadow_registers(struct vpe_ctx *ctx) |
819 | { | |
820 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
821 | u32 *dei_mmr = &mmr_adb->dei_regs[0]; | |
822 | const struct vpe_dei_regs *cur = &dei_regs; | |
823 | ||
824 | dei_mmr[2] = cur->mdt_spacial_freq_thr_reg; | |
825 | dei_mmr[3] = cur->edi_config_reg; | |
826 | dei_mmr[4] = cur->edi_lut_reg0; | |
827 | dei_mmr[5] = cur->edi_lut_reg1; | |
828 | dei_mmr[6] = cur->edi_lut_reg2; | |
829 | dei_mmr[7] = cur->edi_lut_reg3; | |
830 | ||
831 | ctx->load_mmrs = true; | |
832 | } | |
833 | ||
15f632e6 AT |
834 | static void config_edi_input_mode(struct vpe_ctx *ctx, int mode) |
835 | { | |
836 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; | |
837 | u32 *edi_config_reg = &mmr_adb->dei_regs[3]; | |
838 | ||
839 | if (mode & 0x2) | |
840 | write_field(edi_config_reg, 1, 1, 2); /* EDI_ENABLE_3D */ | |
841 | ||
842 | if (mode & 0x3) | |
843 | write_field(edi_config_reg, 1, 1, 3); /* EDI_CHROMA_3D */ | |
844 | ||
845 | write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK, | |
846 | VPE_EDI_INP_MODE_SHIFT); | |
847 | ||
848 | ctx->load_mmrs = true; | |
849 | } | |
850 | ||
45719127 AT |
851 | /* |
852 | * Set the shadow registers whose values are modified when either the | |
853 | * source or destination format is changed. | |
854 | */ | |
855 | static int set_srcdst_params(struct vpe_ctx *ctx) | |
856 | { | |
585e6f01 AT |
857 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; |
858 | struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST]; | |
44687b2e | 859 | struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr; |
773f0657 AT |
860 | unsigned int src_w = s_q_data->c_rect.width; |
861 | unsigned int src_h = s_q_data->c_rect.height; | |
862 | unsigned int dst_w = d_q_data->c_rect.width; | |
863 | unsigned int dst_h = d_q_data->c_rect.height; | |
585e6f01 AT |
864 | size_t mv_buf_size; |
865 | int ret; | |
866 | ||
45719127 | 867 | ctx->sequence = 0; |
585e6f01 AT |
868 | ctx->field = V4L2_FIELD_TOP; |
869 | ||
823f4208 ND |
870 | if ((s_q_data->flags & Q_IS_INTERLACED) && |
871 | !(d_q_data->flags & Q_IS_INTERLACED)) { | |
a51cd8f5 | 872 | int bytes_per_line; |
585e6f01 AT |
873 | const struct vpdma_data_format *mv = |
874 | &vpdma_misc_fmts[VPDMA_DATA_FMT_MV]; | |
875 | ||
a51cd8f5 AT |
876 | /* |
877 | * we make sure that the source image has a 16 byte aligned | |
878 | * stride, we need to do the same for the motion vector buffer | |
8b72c18d | 879 | * by aligning it's stride to the next 16 byte boundary. this |
a51cd8f5 AT |
880 | * extra space will not be used by the de-interlacer, but will |
881 | * ensure that vpdma operates correctly | |
882 | */ | |
883 | bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3, | |
884 | VPDMA_STRIDE_ALIGN); | |
885 | mv_buf_size = bytes_per_line * s_q_data->height; | |
773f0657 | 886 | |
68bbbd79 | 887 | ctx->deinterlacing = true; |
773f0657 | 888 | src_h <<= 1; |
585e6f01 | 889 | } else { |
68bbbd79 | 890 | ctx->deinterlacing = false; |
585e6f01 AT |
891 | mv_buf_size = 0; |
892 | } | |
893 | ||
894 | free_vbs(ctx); | |
0f469c1a | 895 | ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL; |
585e6f01 AT |
896 | |
897 | ret = realloc_mv_buffers(ctx, mv_buf_size); | |
898 | if (ret) | |
899 | return ret; | |
45719127 | 900 | |
655e4656 | 901 | set_cfg_modes(ctx); |
585e6f01 | 902 | set_dei_regs(ctx); |
6948082d | 903 | |
30496799 AT |
904 | csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0], |
905 | s_q_data->colorspace, d_q_data->colorspace); | |
bbee8b39 | 906 | |
773f0657 AT |
907 | sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w); |
908 | sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h); | |
bbee8b39 AT |
909 | |
910 | sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0], | |
911 | &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0], | |
912 | src_w, src_h, dst_w, dst_h); | |
45719127 AT |
913 | |
914 | return 0; | |
915 | } | |
916 | ||
917 | /* | |
918 | * Return the vpe_ctx structure for a given struct file | |
919 | */ | |
920 | static struct vpe_ctx *file2ctx(struct file *file) | |
921 | { | |
922 | return container_of(file->private_data, struct vpe_ctx, fh); | |
923 | } | |
924 | ||
925 | /* | |
926 | * mem2mem callbacks | |
927 | */ | |
928 | ||
cba862dc | 929 | /* |
45719127 AT |
930 | * job_ready() - check whether an instance is ready to be scheduled to run |
931 | */ | |
932 | static int job_ready(void *priv) | |
933 | { | |
934 | struct vpe_ctx *ctx = priv; | |
45719127 | 935 | |
5dc07f20 ND |
936 | /* |
937 | * This check is needed as this might be called directly from driver | |
938 | * When called by m2m framework, this will always satisfy, but when | |
939 | * called from vpe_irq, this might fail. (src stream with zero buffers) | |
940 | */ | |
941 | if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 || | |
942 | v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0) | |
db476163 AT |
943 | return 0; |
944 | ||
45719127 AT |
945 | return 1; |
946 | } | |
947 | ||
948 | static void job_abort(void *priv) | |
949 | { | |
950 | struct vpe_ctx *ctx = priv; | |
951 | ||
952 | /* Will cancel the transaction in the next interrupt handler */ | |
953 | ctx->aborting = 1; | |
954 | } | |
955 | ||
45719127 AT |
956 | static void vpe_dump_regs(struct vpe_dev *dev) |
957 | { | |
958 | #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r)) | |
959 | ||
960 | vpe_dbg(dev, "VPE Registers:\n"); | |
961 | ||
962 | DUMPREG(PID); | |
963 | DUMPREG(SYSCONFIG); | |
964 | DUMPREG(INT0_STATUS0_RAW); | |
965 | DUMPREG(INT0_STATUS0); | |
966 | DUMPREG(INT0_ENABLE0); | |
967 | DUMPREG(INT0_STATUS1_RAW); | |
968 | DUMPREG(INT0_STATUS1); | |
969 | DUMPREG(INT0_ENABLE1); | |
970 | DUMPREG(CLK_ENABLE); | |
971 | DUMPREG(CLK_RESET); | |
972 | DUMPREG(CLK_FORMAT_SELECT); | |
973 | DUMPREG(CLK_RANGE_MAP); | |
974 | DUMPREG(US1_R0); | |
975 | DUMPREG(US1_R1); | |
976 | DUMPREG(US1_R2); | |
977 | DUMPREG(US1_R3); | |
978 | DUMPREG(US1_R4); | |
979 | DUMPREG(US1_R5); | |
980 | DUMPREG(US1_R6); | |
981 | DUMPREG(US1_R7); | |
982 | DUMPREG(US2_R0); | |
983 | DUMPREG(US2_R1); | |
984 | DUMPREG(US2_R2); | |
985 | DUMPREG(US2_R3); | |
986 | DUMPREG(US2_R4); | |
987 | DUMPREG(US2_R5); | |
988 | DUMPREG(US2_R6); | |
989 | DUMPREG(US2_R7); | |
990 | DUMPREG(US3_R0); | |
991 | DUMPREG(US3_R1); | |
992 | DUMPREG(US3_R2); | |
993 | DUMPREG(US3_R3); | |
994 | DUMPREG(US3_R4); | |
995 | DUMPREG(US3_R5); | |
996 | DUMPREG(US3_R6); | |
997 | DUMPREG(US3_R7); | |
998 | DUMPREG(DEI_FRAME_SIZE); | |
999 | DUMPREG(MDT_BYPASS); | |
1000 | DUMPREG(MDT_SF_THRESHOLD); | |
1001 | DUMPREG(EDI_CONFIG); | |
1002 | DUMPREG(DEI_EDI_LUT_R0); | |
1003 | DUMPREG(DEI_EDI_LUT_R1); | |
1004 | DUMPREG(DEI_EDI_LUT_R2); | |
1005 | DUMPREG(DEI_EDI_LUT_R3); | |
1006 | DUMPREG(DEI_FMD_WINDOW_R0); | |
1007 | DUMPREG(DEI_FMD_WINDOW_R1); | |
1008 | DUMPREG(DEI_FMD_CONTROL_R0); | |
1009 | DUMPREG(DEI_FMD_CONTROL_R1); | |
1010 | DUMPREG(DEI_FMD_STATUS_R0); | |
1011 | DUMPREG(DEI_FMD_STATUS_R1); | |
1012 | DUMPREG(DEI_FMD_STATUS_R2); | |
45719127 | 1013 | #undef DUMPREG |
44687b2e AT |
1014 | |
1015 | sc_dump_regs(dev->sc); | |
6948082d | 1016 | csc_dump_regs(dev->csc); |
45719127 AT |
1017 | } |
1018 | ||
1019 | static void add_out_dtd(struct vpe_ctx *ctx, int port) | |
1020 | { | |
1021 | struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST]; | |
1022 | const struct vpe_port_data *p_data = &port_data[port]; | |
2d700715 | 1023 | struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf; |
45719127 AT |
1024 | struct vpe_fmt *fmt = q_data->fmt; |
1025 | const struct vpdma_data_format *vpdma_fmt; | |
585e6f01 | 1026 | int mv_buf_selector = !ctx->src_mv_buf_selector; |
45719127 AT |
1027 | dma_addr_t dma_addr; |
1028 | u32 flags = 0; | |
ed1f47cc | 1029 | u32 offset = 0; |
45719127 | 1030 | |
585e6f01 AT |
1031 | if (port == VPE_PORT_MV_OUT) { |
1032 | vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV]; | |
1033 | dma_addr = ctx->mv_buf_dma[mv_buf_selector]; | |
00db9699 | 1034 | q_data = &ctx->q_data[Q_DATA_SRC]; |
585e6f01 AT |
1035 | } else { |
1036 | /* to incorporate interleaved formats */ | |
1037 | int plane = fmt->coplanar ? p_data->vb_part : 0; | |
1038 | ||
1039 | vpdma_fmt = fmt->vpdma_fmt[plane]; | |
ed1f47cc BP |
1040 | /* |
1041 | * If we are using a single plane buffer and | |
1042 | * we need to set a separate vpdma chroma channel. | |
1043 | */ | |
1044 | if (q_data->nplanes == 1 && plane) { | |
1045 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); | |
1046 | /* Compute required offset */ | |
1047 | offset = q_data->bytesperline[0] * q_data->height; | |
1048 | } else { | |
1049 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane); | |
1050 | /* Use address as is, no offset */ | |
1051 | offset = 0; | |
1052 | } | |
585e6f01 AT |
1053 | if (!dma_addr) { |
1054 | vpe_err(ctx->dev, | |
1055 | "acquiring output buffer(%d) dma_addr failed\n", | |
1056 | port); | |
1057 | return; | |
1058 | } | |
ed1f47cc BP |
1059 | /* Apply the offset */ |
1060 | dma_addr += offset; | |
45719127 AT |
1061 | } |
1062 | ||
1063 | if (q_data->flags & Q_DATA_FRAME_1D) | |
1064 | flags |= VPDMA_DATA_FRAME_1D; | |
1065 | if (q_data->flags & Q_DATA_MODE_TILED) | |
1066 | flags |= VPDMA_DATA_MODE_TILED; | |
1067 | ||
634271f8 ND |
1068 | vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1, |
1069 | MAX_W, MAX_H); | |
1070 | ||
da4414ea BP |
1071 | vpdma_add_out_dtd(&ctx->desc_list, q_data->width, |
1072 | q_data->bytesperline[VPE_LUMA], &q_data->c_rect, | |
634271f8 ND |
1073 | vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1, |
1074 | MAX_OUT_HEIGHT_REG1, p_data->channel, flags); | |
45719127 AT |
1075 | } |
1076 | ||
1077 | static void add_in_dtd(struct vpe_ctx *ctx, int port) | |
1078 | { | |
1079 | struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC]; | |
1080 | const struct vpe_port_data *p_data = &port_data[port]; | |
2d700715 JS |
1081 | struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf; |
1082 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); | |
45719127 AT |
1083 | struct vpe_fmt *fmt = q_data->fmt; |
1084 | const struct vpdma_data_format *vpdma_fmt; | |
585e6f01 | 1085 | int mv_buf_selector = ctx->src_mv_buf_selector; |
2d700715 | 1086 | int field = vbuf->field == V4L2_FIELD_BOTTOM; |
928bf2ba | 1087 | int frame_width, frame_height; |
45719127 AT |
1088 | dma_addr_t dma_addr; |
1089 | u32 flags = 0; | |
ed1f47cc | 1090 | u32 offset = 0; |
45719127 | 1091 | |
585e6f01 AT |
1092 | if (port == VPE_PORT_MV_IN) { |
1093 | vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV]; | |
1094 | dma_addr = ctx->mv_buf_dma[mv_buf_selector]; | |
1095 | } else { | |
1096 | /* to incorporate interleaved formats */ | |
1097 | int plane = fmt->coplanar ? p_data->vb_part : 0; | |
45719127 | 1098 | |
585e6f01 | 1099 | vpdma_fmt = fmt->vpdma_fmt[plane]; |
ed1f47cc BP |
1100 | /* |
1101 | * If we are using a single plane buffer and | |
1102 | * we need to set a separate vpdma chroma channel. | |
1103 | */ | |
1104 | if (q_data->nplanes == 1 && plane) { | |
1105 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); | |
1106 | /* Compute required offset */ | |
1107 | offset = q_data->bytesperline[0] * q_data->height; | |
1108 | } else { | |
1109 | dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane); | |
1110 | /* Use address as is, no offset */ | |
1111 | offset = 0; | |
1112 | } | |
585e6f01 AT |
1113 | if (!dma_addr) { |
1114 | vpe_err(ctx->dev, | |
ed1f47cc | 1115 | "acquiring output buffer(%d) dma_addr failed\n", |
585e6f01 AT |
1116 | port); |
1117 | return; | |
1118 | } | |
ed1f47cc BP |
1119 | /* Apply the offset */ |
1120 | dma_addr += offset; | |
823f4208 ND |
1121 | |
1122 | if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) { | |
1123 | /* | |
1124 | * Use top or bottom field from same vb alternately | |
1125 | * f,f-1,f-2 = TBT when seq is even | |
1126 | * f,f-1,f-2 = BTB when seq is odd | |
1127 | */ | |
1128 | field = (p_data->vb_index + (ctx->sequence % 2)) % 2; | |
1129 | ||
1130 | if (field) { | |
1131 | /* | |
1132 | * bottom field of a SEQ_TB buffer | |
1133 | * Skip the top field data by | |
1134 | */ | |
1135 | int height = q_data->height / 2; | |
1136 | int bpp = fmt->fourcc == V4L2_PIX_FMT_NV12 ? | |
1137 | 1 : (vpdma_fmt->depth >> 3); | |
1138 | if (plane) | |
1139 | height /= 2; | |
1140 | dma_addr += q_data->width * height * bpp; | |
1141 | } | |
1142 | } | |
45719127 AT |
1143 | } |
1144 | ||
1145 | if (q_data->flags & Q_DATA_FRAME_1D) | |
1146 | flags |= VPDMA_DATA_FRAME_1D; | |
1147 | if (q_data->flags & Q_DATA_MODE_TILED) | |
1148 | flags |= VPDMA_DATA_MODE_TILED; | |
1149 | ||
928bf2ba AT |
1150 | frame_width = q_data->c_rect.width; |
1151 | frame_height = q_data->c_rect.height; | |
1152 | ||
1153 | if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12) | |
1154 | frame_height /= 2; | |
1155 | ||
da4414ea BP |
1156 | vpdma_add_in_dtd(&ctx->desc_list, q_data->width, |
1157 | q_data->bytesperline[VPE_LUMA], &q_data->c_rect, | |
928bf2ba AT |
1158 | vpdma_fmt, dma_addr, p_data->channel, field, flags, frame_width, |
1159 | frame_height, 0, 0); | |
45719127 AT |
1160 | } |
1161 | ||
1162 | /* | |
1163 | * Enable the expected IRQ sources | |
1164 | */ | |
1165 | static void enable_irqs(struct vpe_ctx *ctx) | |
1166 | { | |
1167 | write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE); | |
585e6f01 AT |
1168 | write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT | |
1169 | VPE_DS1_UV_ERROR_INT); | |
45719127 | 1170 | |
2f88703a | 1171 | vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true); |
45719127 AT |
1172 | } |
1173 | ||
1174 | static void disable_irqs(struct vpe_ctx *ctx) | |
1175 | { | |
1176 | write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff); | |
1177 | write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff); | |
1178 | ||
2f88703a | 1179 | vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false); |
45719127 AT |
1180 | } |
1181 | ||
1182 | /* device_run() - prepares and starts the device | |
1183 | * | |
1184 | * This function is only called when both the source and destination | |
1185 | * buffers are in place. | |
1186 | */ | |
1187 | static void device_run(void *priv) | |
1188 | { | |
1189 | struct vpe_ctx *ctx = priv; | |
773f0657 | 1190 | struct sc_data *sc = ctx->dev->sc; |
45719127 | 1191 | struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST]; |
823f4208 ND |
1192 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; |
1193 | ||
1194 | if (ctx->deinterlacing && s_q_data->flags & Q_DATA_INTERLACED_SEQ_TB && | |
1195 | ctx->sequence % 2 == 0) { | |
1196 | /* When using SEQ_TB buffers, When using it first time, | |
1197 | * No need to remove the buffer as the next field is present | |
1198 | * in the same buffer. (so that job_ready won't fail) | |
1199 | * It will be removed when using bottom field | |
1200 | */ | |
1201 | ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); | |
1202 | WARN_ON(ctx->src_vbs[0] == NULL); | |
1203 | } else { | |
1204 | ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); | |
1205 | WARN_ON(ctx->src_vbs[0] == NULL); | |
1206 | } | |
45719127 | 1207 | |
47e604c5 | 1208 | ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); |
45719127 AT |
1209 | WARN_ON(ctx->dst_vb == NULL); |
1210 | ||
15f632e6 | 1211 | if (ctx->deinterlacing) { |
5dc07f20 ND |
1212 | |
1213 | if (ctx->src_vbs[2] == NULL) { | |
1214 | ctx->src_vbs[2] = ctx->src_vbs[0]; | |
1215 | WARN_ON(ctx->src_vbs[2] == NULL); | |
1216 | ctx->src_vbs[1] = ctx->src_vbs[0]; | |
1217 | WARN_ON(ctx->src_vbs[1] == NULL); | |
1218 | } | |
1219 | ||
15f632e6 AT |
1220 | /* |
1221 | * we have output the first 2 frames through line average, we | |
1222 | * now switch to EDI de-interlacer | |
1223 | */ | |
1224 | if (ctx->sequence == 2) | |
1225 | config_edi_input_mode(ctx, 0x3); /* EDI (Y + UV) */ | |
1226 | } | |
1227 | ||
45719127 AT |
1228 | /* config descriptors */ |
1229 | if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) { | |
1230 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb); | |
1231 | vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb); | |
655e4656 ND |
1232 | |
1233 | set_line_modes(ctx); | |
1234 | ||
45719127 AT |
1235 | ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr; |
1236 | ctx->load_mmrs = false; | |
1237 | } | |
1238 | ||
773f0657 AT |
1239 | if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr || |
1240 | sc->load_coeff_h) { | |
1241 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h); | |
1242 | vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT, | |
1243 | &ctx->sc_coeff_h, 0); | |
1244 | ||
1245 | sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr; | |
1246 | sc->load_coeff_h = false; | |
1247 | } | |
1248 | ||
1249 | if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr || | |
1250 | sc->load_coeff_v) { | |
1251 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v); | |
1252 | vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT, | |
1253 | &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4); | |
1254 | ||
1255 | sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr; | |
1256 | sc->load_coeff_v = false; | |
1257 | } | |
1258 | ||
585e6f01 AT |
1259 | /* output data descriptors */ |
1260 | if (ctx->deinterlacing) | |
1261 | add_out_dtd(ctx, VPE_PORT_MV_OUT); | |
1262 | ||
30496799 AT |
1263 | if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) { |
1264 | add_out_dtd(ctx, VPE_PORT_RGB_OUT); | |
1265 | } else { | |
1266 | add_out_dtd(ctx, VPE_PORT_LUMA_OUT); | |
1267 | if (d_q_data->fmt->coplanar) | |
1268 | add_out_dtd(ctx, VPE_PORT_CHROMA_OUT); | |
1269 | } | |
45719127 | 1270 | |
585e6f01 AT |
1271 | /* input data descriptors */ |
1272 | if (ctx->deinterlacing) { | |
1273 | add_in_dtd(ctx, VPE_PORT_LUMA3_IN); | |
1274 | add_in_dtd(ctx, VPE_PORT_CHROMA3_IN); | |
1275 | ||
1276 | add_in_dtd(ctx, VPE_PORT_LUMA2_IN); | |
1277 | add_in_dtd(ctx, VPE_PORT_CHROMA2_IN); | |
1278 | } | |
1279 | ||
45719127 AT |
1280 | add_in_dtd(ctx, VPE_PORT_LUMA1_IN); |
1281 | add_in_dtd(ctx, VPE_PORT_CHROMA1_IN); | |
1282 | ||
585e6f01 AT |
1283 | if (ctx->deinterlacing) |
1284 | add_in_dtd(ctx, VPE_PORT_MV_IN); | |
1285 | ||
45719127 AT |
1286 | /* sync on channel control descriptors for input ports */ |
1287 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN); | |
1288 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN); | |
1289 | ||
585e6f01 AT |
1290 | if (ctx->deinterlacing) { |
1291 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1292 | VPE_CHAN_LUMA2_IN); | |
1293 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1294 | VPE_CHAN_CHROMA2_IN); | |
1295 | ||
1296 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1297 | VPE_CHAN_LUMA3_IN); | |
1298 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1299 | VPE_CHAN_CHROMA3_IN); | |
1300 | ||
1301 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN); | |
1302 | } | |
1303 | ||
45719127 | 1304 | /* sync on channel control descriptors for output ports */ |
30496799 AT |
1305 | if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) { |
1306 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1307 | VPE_CHAN_RGB_OUT); | |
1308 | } else { | |
1309 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1310 | VPE_CHAN_LUMA_OUT); | |
1311 | if (d_q_data->fmt->coplanar) | |
1312 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, | |
1313 | VPE_CHAN_CHROMA_OUT); | |
1314 | } | |
45719127 | 1315 | |
585e6f01 AT |
1316 | if (ctx->deinterlacing) |
1317 | vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT); | |
1318 | ||
45719127 AT |
1319 | enable_irqs(ctx); |
1320 | ||
1321 | vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf); | |
2f88703a | 1322 | vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0); |
45719127 AT |
1323 | } |
1324 | ||
585e6f01 AT |
1325 | static void dei_error(struct vpe_ctx *ctx) |
1326 | { | |
1327 | dev_warn(ctx->dev->v4l2_dev.dev, | |
1328 | "received DEI error interrupt\n"); | |
1329 | } | |
1330 | ||
45719127 AT |
1331 | static void ds1_uv_error(struct vpe_ctx *ctx) |
1332 | { | |
1333 | dev_warn(ctx->dev->v4l2_dev.dev, | |
1334 | "received downsampler error interrupt\n"); | |
1335 | } | |
1336 | ||
1337 | static irqreturn_t vpe_irq(int irq_vpe, void *data) | |
1338 | { | |
1339 | struct vpe_dev *dev = (struct vpe_dev *)data; | |
1340 | struct vpe_ctx *ctx; | |
585e6f01 | 1341 | struct vpe_q_data *d_q_data; |
2d700715 | 1342 | struct vb2_v4l2_buffer *s_vb, *d_vb; |
45719127 AT |
1343 | unsigned long flags; |
1344 | u32 irqst0, irqst1; | |
5b617957 | 1345 | bool list_complete = false; |
45719127 AT |
1346 | |
1347 | irqst0 = read_reg(dev, VPE_INT0_STATUS0); | |
1348 | if (irqst0) { | |
1349 | write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0); | |
1350 | vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0); | |
1351 | } | |
1352 | ||
1353 | irqst1 = read_reg(dev, VPE_INT0_STATUS1); | |
1354 | if (irqst1) { | |
1355 | write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1); | |
1356 | vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1); | |
1357 | } | |
1358 | ||
1359 | ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev); | |
1360 | if (!ctx) { | |
1361 | vpe_err(dev, "instance released before end of transaction\n"); | |
1362 | goto handled; | |
1363 | } | |
1364 | ||
585e6f01 AT |
1365 | if (irqst1) { |
1366 | if (irqst1 & VPE_DEI_ERROR_INT) { | |
1367 | irqst1 &= ~VPE_DEI_ERROR_INT; | |
1368 | dei_error(ctx); | |
1369 | } | |
1370 | if (irqst1 & VPE_DS1_UV_ERROR_INT) { | |
1371 | irqst1 &= ~VPE_DS1_UV_ERROR_INT; | |
1372 | ds1_uv_error(ctx); | |
1373 | } | |
45719127 AT |
1374 | } |
1375 | ||
1376 | if (irqst0) { | |
1377 | if (irqst0 & VPE_INT0_LIST0_COMPLETE) | |
afbc0ae9 | 1378 | vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0); |
45719127 AT |
1379 | |
1380 | irqst0 &= ~(VPE_INT0_LIST0_COMPLETE); | |
5b617957 | 1381 | list_complete = true; |
45719127 AT |
1382 | } |
1383 | ||
1384 | if (irqst0 | irqst1) { | |
637d5ac5 | 1385 | dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n", |
45719127 AT |
1386 | irqst0, irqst1); |
1387 | } | |
1388 | ||
5b617957 ND |
1389 | /* |
1390 | * Setup next operation only when list complete IRQ occurs | |
1391 | * otherwise, skip the following code | |
1392 | */ | |
1393 | if (!list_complete) | |
1394 | goto handled; | |
1395 | ||
45719127 AT |
1396 | disable_irqs(ctx); |
1397 | ||
1398 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf); | |
1399 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb); | |
773f0657 AT |
1400 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h); |
1401 | vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v); | |
45719127 AT |
1402 | |
1403 | vpdma_reset_desc_list(&ctx->desc_list); | |
1404 | ||
585e6f01 AT |
1405 | /* the previous dst mv buffer becomes the next src mv buffer */ |
1406 | ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector; | |
1407 | ||
45719127 AT |
1408 | if (ctx->aborting) |
1409 | goto finished; | |
1410 | ||
585e6f01 | 1411 | s_vb = ctx->src_vbs[0]; |
45719127 | 1412 | d_vb = ctx->dst_vb; |
45719127 | 1413 | |
2d700715 | 1414 | d_vb->flags = s_vb->flags; |
d6dd645e | 1415 | d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp; |
bbe24c67 | 1416 | |
2d700715 JS |
1417 | if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE) |
1418 | d_vb->timecode = s_vb->timecode; | |
bbe24c67 | 1419 | |
2d700715 | 1420 | d_vb->sequence = ctx->sequence; |
585e6f01 AT |
1421 | |
1422 | d_q_data = &ctx->q_data[Q_DATA_DST]; | |
823f4208 | 1423 | if (d_q_data->flags & Q_IS_INTERLACED) { |
2d700715 | 1424 | d_vb->field = ctx->field; |
585e6f01 AT |
1425 | if (ctx->field == V4L2_FIELD_BOTTOM) { |
1426 | ctx->sequence++; | |
1427 | ctx->field = V4L2_FIELD_TOP; | |
1428 | } else { | |
1429 | WARN_ON(ctx->field != V4L2_FIELD_TOP); | |
1430 | ctx->field = V4L2_FIELD_BOTTOM; | |
1431 | } | |
1432 | } else { | |
2d700715 | 1433 | d_vb->field = V4L2_FIELD_NONE; |
585e6f01 AT |
1434 | ctx->sequence++; |
1435 | } | |
45719127 | 1436 | |
823f4208 ND |
1437 | if (ctx->deinterlacing) { |
1438 | /* | |
1439 | * Allow source buffer to be dequeued only if it won't be used | |
1440 | * in the next iteration. All vbs are initialized to first | |
1441 | * buffer and we are shifting buffers every iteration, for the | |
1442 | * first two iterations, no buffer will be dequeued. | |
1443 | * This ensures that driver will keep (n-2)th (n-1)th and (n)th | |
1444 | * field when deinterlacing is enabled | |
1445 | */ | |
1446 | if (ctx->src_vbs[2] != ctx->src_vbs[1]) | |
1447 | s_vb = ctx->src_vbs[2]; | |
1448 | else | |
1449 | s_vb = NULL; | |
1450 | } | |
45719127 AT |
1451 | |
1452 | spin_lock_irqsave(&dev->lock, flags); | |
823f4208 ND |
1453 | |
1454 | if (s_vb) | |
1455 | v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE); | |
1456 | ||
45719127 | 1457 | v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE); |
823f4208 | 1458 | |
45719127 AT |
1459 | spin_unlock_irqrestore(&dev->lock, flags); |
1460 | ||
585e6f01 AT |
1461 | if (ctx->deinterlacing) { |
1462 | ctx->src_vbs[2] = ctx->src_vbs[1]; | |
1463 | ctx->src_vbs[1] = ctx->src_vbs[0]; | |
1464 | } | |
1465 | ||
dfe1349d BP |
1466 | /* |
1467 | * Since the vb2_buf_done has already been called fir therse | |
1468 | * buffer we can now NULL them out so that we won't try | |
1469 | * to clean out stray pointer later on. | |
1470 | */ | |
1471 | ctx->src_vbs[0] = NULL; | |
1472 | ctx->dst_vb = NULL; | |
1473 | ||
45719127 | 1474 | ctx->bufs_completed++; |
5dc07f20 | 1475 | if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) { |
45719127 AT |
1476 | device_run(ctx); |
1477 | goto handled; | |
1478 | } | |
1479 | ||
1480 | finished: | |
1481 | vpe_dbg(ctx->dev, "finishing transaction\n"); | |
1482 | ctx->bufs_completed = 0; | |
47e604c5 | 1483 | v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx); |
45719127 AT |
1484 | handled: |
1485 | return IRQ_HANDLED; | |
1486 | } | |
1487 | ||
1488 | /* | |
1489 | * video ioctls | |
1490 | */ | |
1491 | static int vpe_querycap(struct file *file, void *priv, | |
1492 | struct v4l2_capability *cap) | |
1493 | { | |
85709cbf MCC |
1494 | strscpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver)); |
1495 | strscpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card)); | |
b20902b9 AT |
1496 | snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", |
1497 | VPE_MODULE_NAME); | |
45719127 AT |
1498 | return 0; |
1499 | } | |
1500 | ||
1501 | static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type) | |
1502 | { | |
1503 | int i, index; | |
1504 | struct vpe_fmt *fmt = NULL; | |
1505 | ||
1506 | index = 0; | |
1507 | for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) { | |
1508 | if (vpe_formats[i].types & type) { | |
1509 | if (index == f->index) { | |
1510 | fmt = &vpe_formats[i]; | |
1511 | break; | |
1512 | } | |
1513 | index++; | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | if (!fmt) | |
1518 | return -EINVAL; | |
1519 | ||
85709cbf | 1520 | strscpy(f->description, fmt->name, sizeof(f->description)); |
45719127 AT |
1521 | f->pixelformat = fmt->fourcc; |
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | static int vpe_enum_fmt(struct file *file, void *priv, | |
1526 | struct v4l2_fmtdesc *f) | |
1527 | { | |
1528 | if (V4L2_TYPE_IS_OUTPUT(f->type)) | |
1529 | return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT); | |
1530 | ||
1531 | return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE); | |
1532 | } | |
1533 | ||
1534 | static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f) | |
1535 | { | |
1536 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; | |
1537 | struct vpe_ctx *ctx = file2ctx(file); | |
1538 | struct vb2_queue *vq; | |
1539 | struct vpe_q_data *q_data; | |
1540 | int i; | |
1541 | ||
47e604c5 | 1542 | vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); |
45719127 AT |
1543 | if (!vq) |
1544 | return -EINVAL; | |
1545 | ||
1546 | q_data = get_q_data(ctx, f->type); | |
1547 | ||
1548 | pix->width = q_data->width; | |
1549 | pix->height = q_data->height; | |
1550 | pix->pixelformat = q_data->fmt->fourcc; | |
585e6f01 | 1551 | pix->field = q_data->field; |
45719127 AT |
1552 | |
1553 | if (V4L2_TYPE_IS_OUTPUT(f->type)) { | |
1554 | pix->colorspace = q_data->colorspace; | |
1555 | } else { | |
1556 | struct vpe_q_data *s_q_data; | |
1557 | ||
1558 | /* get colorspace from the source queue */ | |
1559 | s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); | |
1560 | ||
1561 | pix->colorspace = s_q_data->colorspace; | |
1562 | } | |
1563 | ||
ed1f47cc | 1564 | pix->num_planes = q_data->nplanes; |
45719127 AT |
1565 | |
1566 | for (i = 0; i < pix->num_planes; i++) { | |
1567 | pix->plane_fmt[i].bytesperline = q_data->bytesperline[i]; | |
1568 | pix->plane_fmt[i].sizeimage = q_data->sizeimage[i]; | |
1569 | } | |
1570 | ||
1571 | return 0; | |
1572 | } | |
1573 | ||
1574 | static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f, | |
1575 | struct vpe_fmt *fmt, int type) | |
1576 | { | |
1577 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; | |
1578 | struct v4l2_plane_pix_format *plane_fmt; | |
a51cd8f5 | 1579 | unsigned int w_align; |
823f4208 | 1580 | int i, depth, depth_bytes, height; |
3dc2046c | 1581 | unsigned int stride = 0; |
45719127 AT |
1582 | |
1583 | if (!fmt || !(fmt->types & type)) { | |
1584 | vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n", | |
1585 | pix->pixelformat); | |
1586 | return -EINVAL; | |
1587 | } | |
1588 | ||
823f4208 ND |
1589 | if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE |
1590 | && pix->field != V4L2_FIELD_SEQ_TB) | |
585e6f01 | 1591 | pix->field = V4L2_FIELD_NONE; |
45719127 | 1592 | |
a51cd8f5 AT |
1593 | depth = fmt->vpdma_fmt[VPE_LUMA]->depth; |
1594 | ||
1595 | /* | |
1596 | * the line stride should 16 byte aligned for VPDMA to work, based on | |
1597 | * the bytes per pixel, figure out how much the width should be aligned | |
1598 | * to make sure line stride is 16 byte aligned | |
1599 | */ | |
1600 | depth_bytes = depth >> 3; | |
1601 | ||
af93189d | 1602 | if (depth_bytes == 3) { |
a51cd8f5 AT |
1603 | /* |
1604 | * if bpp is 3(as in some RGB formats), the pixel width doesn't | |
1605 | * really help in ensuring line stride is 16 byte aligned | |
1606 | */ | |
1607 | w_align = 4; | |
af93189d | 1608 | } else { |
a51cd8f5 AT |
1609 | /* |
1610 | * for the remainder bpp(4, 2 and 1), the pixel width alignment | |
1611 | * can ensure a line stride alignment of 16 bytes. For example, | |
1612 | * if bpp is 2, then the line stride can be 16 byte aligned if | |
1613 | * the width is 8 byte aligned | |
1614 | */ | |
af93189d MCC |
1615 | |
1616 | /* | |
1617 | * HACK: using order_base_2() here causes lots of asm output | |
1618 | * errors with smatch, on i386: | |
1619 | * ./arch/x86/include/asm/bitops.h:457:22: | |
1620 | * warning: asm output is not an lvalue | |
1621 | * Perhaps some gcc optimization is doing the wrong thing | |
1622 | * there. | |
1623 | * Let's get rid of them by doing the calculus on two steps | |
1624 | */ | |
1625 | w_align = roundup_pow_of_two(VPDMA_DESC_ALIGN / depth_bytes); | |
1626 | w_align = ilog2(w_align); | |
1627 | } | |
a51cd8f5 AT |
1628 | |
1629 | v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align, | |
45719127 AT |
1630 | &pix->height, MIN_H, MAX_H, H_ALIGN, |
1631 | S_ALIGN); | |
1632 | ||
ed1f47cc BP |
1633 | if (!pix->num_planes) |
1634 | pix->num_planes = fmt->coplanar ? 2 : 1; | |
1635 | else if (pix->num_planes > 1 && !fmt->coplanar) | |
1636 | pix->num_planes = 1; | |
1637 | ||
45719127 AT |
1638 | pix->pixelformat = fmt->fourcc; |
1639 | ||
823f4208 ND |
1640 | /* |
1641 | * For the actual image parameters, we need to consider the field | |
1642 | * height of the image for SEQ_TB buffers. | |
1643 | */ | |
1644 | if (pix->field == V4L2_FIELD_SEQ_TB) | |
1645 | height = pix->height / 2; | |
1646 | else | |
1647 | height = pix->height; | |
1648 | ||
30496799 AT |
1649 | if (!pix->colorspace) { |
1650 | if (fmt->fourcc == V4L2_PIX_FMT_RGB24 || | |
1651 | fmt->fourcc == V4L2_PIX_FMT_BGR24 || | |
1652 | fmt->fourcc == V4L2_PIX_FMT_RGB32 || | |
1653 | fmt->fourcc == V4L2_PIX_FMT_BGR32) { | |
1654 | pix->colorspace = V4L2_COLORSPACE_SRGB; | |
1655 | } else { | |
823f4208 | 1656 | if (height > 1280) /* HD */ |
30496799 AT |
1657 | pix->colorspace = V4L2_COLORSPACE_REC709; |
1658 | else /* SD */ | |
1659 | pix->colorspace = V4L2_COLORSPACE_SMPTE170M; | |
1660 | } | |
45719127 AT |
1661 | } |
1662 | ||
92851f1c | 1663 | memset(pix->reserved, 0, sizeof(pix->reserved)); |
45719127 | 1664 | for (i = 0; i < pix->num_planes; i++) { |
45719127 AT |
1665 | plane_fmt = &pix->plane_fmt[i]; |
1666 | depth = fmt->vpdma_fmt[i]->depth; | |
1667 | ||
3dc2046c BP |
1668 | stride = (pix->width * fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3; |
1669 | if (stride > plane_fmt->bytesperline) | |
1670 | plane_fmt->bytesperline = stride; | |
1671 | ||
1672 | plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline, | |
1673 | VPDMA_STRIDE_ALIGN); | |
45719127 | 1674 | |
3dc2046c BP |
1675 | if (i == VPE_LUMA) { |
1676 | plane_fmt->sizeimage = pix->height * | |
1677 | plane_fmt->bytesperline; | |
92851f1c | 1678 | |
3dc2046c BP |
1679 | if (pix->num_planes == 1 && fmt->coplanar) |
1680 | plane_fmt->sizeimage += pix->height * | |
1681 | plane_fmt->bytesperline * | |
1682 | fmt->vpdma_fmt[VPE_CHROMA]->depth >> 3; | |
1683 | ||
1684 | } else { /* i == VIP_CHROMA */ | |
1685 | plane_fmt->sizeimage = (pix->height * | |
1686 | plane_fmt->bytesperline * | |
1687 | depth) >> 3; | |
1688 | } | |
92851f1c | 1689 | memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved)); |
45719127 AT |
1690 | } |
1691 | ||
1692 | return 0; | |
1693 | } | |
1694 | ||
1695 | static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f) | |
1696 | { | |
1697 | struct vpe_ctx *ctx = file2ctx(file); | |
1698 | struct vpe_fmt *fmt = find_format(f); | |
1699 | ||
1700 | if (V4L2_TYPE_IS_OUTPUT(f->type)) | |
1701 | return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT); | |
1702 | else | |
1703 | return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE); | |
1704 | } | |
1705 | ||
1706 | static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f) | |
1707 | { | |
1708 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; | |
1709 | struct v4l2_plane_pix_format *plane_fmt; | |
1710 | struct vpe_q_data *q_data; | |
1711 | struct vb2_queue *vq; | |
1712 | int i; | |
1713 | ||
47e604c5 | 1714 | vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); |
45719127 AT |
1715 | if (!vq) |
1716 | return -EINVAL; | |
1717 | ||
1718 | if (vb2_is_busy(vq)) { | |
1719 | vpe_err(ctx->dev, "queue busy\n"); | |
1720 | return -EBUSY; | |
1721 | } | |
1722 | ||
1723 | q_data = get_q_data(ctx, f->type); | |
1724 | if (!q_data) | |
1725 | return -EINVAL; | |
1726 | ||
1727 | q_data->fmt = find_format(f); | |
1728 | q_data->width = pix->width; | |
1729 | q_data->height = pix->height; | |
1730 | q_data->colorspace = pix->colorspace; | |
585e6f01 | 1731 | q_data->field = pix->field; |
ed1f47cc | 1732 | q_data->nplanes = pix->num_planes; |
45719127 AT |
1733 | |
1734 | for (i = 0; i < pix->num_planes; i++) { | |
1735 | plane_fmt = &pix->plane_fmt[i]; | |
1736 | ||
1737 | q_data->bytesperline[i] = plane_fmt->bytesperline; | |
1738 | q_data->sizeimage[i] = plane_fmt->sizeimage; | |
1739 | } | |
1740 | ||
1741 | q_data->c_rect.left = 0; | |
1742 | q_data->c_rect.top = 0; | |
1743 | q_data->c_rect.width = q_data->width; | |
1744 | q_data->c_rect.height = q_data->height; | |
1745 | ||
585e6f01 | 1746 | if (q_data->field == V4L2_FIELD_ALTERNATE) |
823f4208 ND |
1747 | q_data->flags |= Q_DATA_INTERLACED_ALTERNATE; |
1748 | else if (q_data->field == V4L2_FIELD_SEQ_TB) | |
1749 | q_data->flags |= Q_DATA_INTERLACED_SEQ_TB; | |
585e6f01 | 1750 | else |
823f4208 ND |
1751 | q_data->flags &= ~Q_IS_INTERLACED; |
1752 | ||
1753 | /* the crop height is halved for the case of SEQ_TB buffers */ | |
1754 | if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) | |
1755 | q_data->c_rect.height /= 2; | |
585e6f01 | 1756 | |
45719127 AT |
1757 | vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d", |
1758 | f->type, q_data->width, q_data->height, q_data->fmt->fourcc, | |
1759 | q_data->bytesperline[VPE_LUMA]); | |
ed1f47cc | 1760 | if (q_data->nplanes == 2) |
45719127 AT |
1761 | vpe_dbg(ctx->dev, " bpl_uv %d\n", |
1762 | q_data->bytesperline[VPE_CHROMA]); | |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f) | |
1768 | { | |
1769 | int ret; | |
1770 | struct vpe_ctx *ctx = file2ctx(file); | |
1771 | ||
1772 | ret = vpe_try_fmt(file, priv, f); | |
1773 | if (ret) | |
1774 | return ret; | |
1775 | ||
1776 | ret = __vpe_s_fmt(ctx, f); | |
1777 | if (ret) | |
1778 | return ret; | |
1779 | ||
1780 | if (V4L2_TYPE_IS_OUTPUT(f->type)) | |
1781 | set_src_registers(ctx); | |
1782 | else | |
1783 | set_dst_registers(ctx); | |
1784 | ||
1785 | return set_srcdst_params(ctx); | |
1786 | } | |
1787 | ||
2ef114f6 AT |
1788 | static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s) |
1789 | { | |
1790 | struct vpe_q_data *q_data; | |
823f4208 | 1791 | int height; |
2ef114f6 AT |
1792 | |
1793 | if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) && | |
1794 | (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)) | |
1795 | return -EINVAL; | |
1796 | ||
1797 | q_data = get_q_data(ctx, s->type); | |
1798 | if (!q_data) | |
1799 | return -EINVAL; | |
1800 | ||
1801 | switch (s->target) { | |
1802 | case V4L2_SEL_TGT_COMPOSE: | |
1803 | /* | |
1804 | * COMPOSE target is only valid for capture buffer type, return | |
1805 | * error for output buffer type | |
1806 | */ | |
1807 | if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) | |
1808 | return -EINVAL; | |
1809 | break; | |
1810 | case V4L2_SEL_TGT_CROP: | |
1811 | /* | |
1812 | * CROP target is only valid for output buffer type, return | |
1813 | * error for capture buffer type | |
1814 | */ | |
1815 | if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1816 | return -EINVAL; | |
1817 | break; | |
1818 | /* | |
1819 | * bound and default crop/compose targets are invalid targets to | |
1820 | * try/set | |
1821 | */ | |
1822 | default: | |
1823 | return -EINVAL; | |
1824 | } | |
1825 | ||
823f4208 ND |
1826 | /* |
1827 | * For SEQ_TB buffers, crop height should be less than the height of | |
1828 | * the field height, not the buffer height | |
1829 | */ | |
1830 | if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) | |
1831 | height = q_data->height / 2; | |
1832 | else | |
1833 | height = q_data->height; | |
1834 | ||
2ef114f6 AT |
1835 | if (s->r.top < 0 || s->r.left < 0) { |
1836 | vpe_err(ctx->dev, "negative values for top and left\n"); | |
1837 | s->r.top = s->r.left = 0; | |
1838 | } | |
1839 | ||
1840 | v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1, | |
823f4208 | 1841 | &s->r.height, MIN_H, height, H_ALIGN, S_ALIGN); |
2ef114f6 AT |
1842 | |
1843 | /* adjust left/top if cropping rectangle is out of bounds */ | |
1844 | if (s->r.left + s->r.width > q_data->width) | |
1845 | s->r.left = q_data->width - s->r.width; | |
1846 | if (s->r.top + s->r.height > q_data->height) | |
1847 | s->r.top = q_data->height - s->r.height; | |
1848 | ||
1849 | return 0; | |
1850 | } | |
1851 | ||
1852 | static int vpe_g_selection(struct file *file, void *fh, | |
1853 | struct v4l2_selection *s) | |
1854 | { | |
1855 | struct vpe_ctx *ctx = file2ctx(file); | |
1856 | struct vpe_q_data *q_data; | |
1857 | bool use_c_rect = false; | |
1858 | ||
1859 | if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) && | |
1860 | (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)) | |
1861 | return -EINVAL; | |
1862 | ||
1863 | q_data = get_q_data(ctx, s->type); | |
1864 | if (!q_data) | |
1865 | return -EINVAL; | |
1866 | ||
1867 | switch (s->target) { | |
1868 | case V4L2_SEL_TGT_COMPOSE_DEFAULT: | |
1869 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: | |
1870 | if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) | |
1871 | return -EINVAL; | |
1872 | break; | |
1873 | case V4L2_SEL_TGT_CROP_BOUNDS: | |
1874 | case V4L2_SEL_TGT_CROP_DEFAULT: | |
1875 | if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1876 | return -EINVAL; | |
1877 | break; | |
1878 | case V4L2_SEL_TGT_COMPOSE: | |
1879 | if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) | |
1880 | return -EINVAL; | |
1881 | use_c_rect = true; | |
1882 | break; | |
1883 | case V4L2_SEL_TGT_CROP: | |
1884 | if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1885 | return -EINVAL; | |
1886 | use_c_rect = true; | |
1887 | break; | |
1888 | default: | |
1889 | return -EINVAL; | |
1890 | } | |
1891 | ||
1892 | if (use_c_rect) { | |
1893 | /* | |
1894 | * for CROP/COMPOSE target type, return c_rect params from the | |
1895 | * respective buffer type | |
1896 | */ | |
1897 | s->r = q_data->c_rect; | |
1898 | } else { | |
1899 | /* | |
1900 | * for DEFAULT/BOUNDS target type, return width and height from | |
1901 | * S_FMT of the respective buffer type | |
1902 | */ | |
1903 | s->r.left = 0; | |
1904 | s->r.top = 0; | |
1905 | s->r.width = q_data->width; | |
1906 | s->r.height = q_data->height; | |
1907 | } | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | ||
1913 | static int vpe_s_selection(struct file *file, void *fh, | |
1914 | struct v4l2_selection *s) | |
1915 | { | |
1916 | struct vpe_ctx *ctx = file2ctx(file); | |
1917 | struct vpe_q_data *q_data; | |
1918 | struct v4l2_selection sel = *s; | |
1919 | int ret; | |
1920 | ||
1921 | ret = __vpe_try_selection(ctx, &sel); | |
1922 | if (ret) | |
1923 | return ret; | |
1924 | ||
1925 | q_data = get_q_data(ctx, sel.type); | |
1926 | if (!q_data) | |
1927 | return -EINVAL; | |
1928 | ||
1929 | if ((q_data->c_rect.left == sel.r.left) && | |
1930 | (q_data->c_rect.top == sel.r.top) && | |
1931 | (q_data->c_rect.width == sel.r.width) && | |
1932 | (q_data->c_rect.height == sel.r.height)) { | |
1933 | vpe_dbg(ctx->dev, | |
1934 | "requested crop/compose values are already set\n"); | |
1935 | return 0; | |
1936 | } | |
1937 | ||
1938 | q_data->c_rect = sel.r; | |
1939 | ||
1940 | return set_srcdst_params(ctx); | |
1941 | } | |
1942 | ||
45719127 AT |
1943 | /* |
1944 | * defines number of buffers/frames a context can process with VPE before | |
1945 | * switching to a different context. default value is 1 buffer per context | |
1946 | */ | |
1947 | #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0) | |
1948 | ||
1949 | static int vpe_s_ctrl(struct v4l2_ctrl *ctrl) | |
1950 | { | |
1951 | struct vpe_ctx *ctx = | |
1952 | container_of(ctrl->handler, struct vpe_ctx, hdl); | |
1953 | ||
1954 | switch (ctrl->id) { | |
1955 | case V4L2_CID_VPE_BUFS_PER_JOB: | |
1956 | ctx->bufs_per_job = ctrl->val; | |
1957 | break; | |
1958 | ||
1959 | default: | |
1960 | vpe_err(ctx->dev, "Invalid control\n"); | |
1961 | return -EINVAL; | |
1962 | } | |
1963 | ||
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | static const struct v4l2_ctrl_ops vpe_ctrl_ops = { | |
1968 | .s_ctrl = vpe_s_ctrl, | |
1969 | }; | |
1970 | ||
1971 | static const struct v4l2_ioctl_ops vpe_ioctl_ops = { | |
47e604c5 | 1972 | .vidioc_querycap = vpe_querycap, |
45719127 | 1973 | |
47e604c5 | 1974 | .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt, |
45719127 AT |
1975 | .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt, |
1976 | .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt, | |
1977 | .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt, | |
1978 | ||
47e604c5 | 1979 | .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt, |
45719127 AT |
1980 | .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt, |
1981 | .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt, | |
1982 | .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt, | |
1983 | ||
2ef114f6 AT |
1984 | .vidioc_g_selection = vpe_g_selection, |
1985 | .vidioc_s_selection = vpe_s_selection, | |
1986 | ||
47e604c5 PL |
1987 | .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, |
1988 | .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, | |
1989 | .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, | |
1990 | .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, | |
b8b3ac44 | 1991 | .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, |
47e604c5 PL |
1992 | .vidioc_streamon = v4l2_m2m_ioctl_streamon, |
1993 | .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, | |
45719127 | 1994 | |
47e604c5 PL |
1995 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
1996 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
45719127 AT |
1997 | }; |
1998 | ||
1999 | /* | |
2000 | * Queue operations | |
2001 | */ | |
2002 | static int vpe_queue_setup(struct vb2_queue *vq, | |
45719127 | 2003 | unsigned int *nbuffers, unsigned int *nplanes, |
36c0f8b3 | 2004 | unsigned int sizes[], struct device *alloc_devs[]) |
45719127 AT |
2005 | { |
2006 | int i; | |
2007 | struct vpe_ctx *ctx = vb2_get_drv_priv(vq); | |
2008 | struct vpe_q_data *q_data; | |
2009 | ||
2010 | q_data = get_q_data(ctx, vq->type); | |
2011 | ||
ed1f47cc | 2012 | *nplanes = q_data->nplanes; |
45719127 | 2013 | |
dce57314 | 2014 | for (i = 0; i < *nplanes; i++) |
45719127 | 2015 | sizes[i] = q_data->sizeimage[i]; |
45719127 AT |
2016 | |
2017 | vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers, | |
2018 | sizes[VPE_LUMA]); | |
ed1f47cc | 2019 | if (q_data->nplanes == 2) |
45719127 AT |
2020 | vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]); |
2021 | ||
2022 | return 0; | |
2023 | } | |
2024 | ||
2025 | static int vpe_buf_prepare(struct vb2_buffer *vb) | |
2026 | { | |
2d700715 | 2027 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
45719127 AT |
2028 | struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); |
2029 | struct vpe_q_data *q_data; | |
2030 | int i, num_planes; | |
2031 | ||
2032 | vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type); | |
2033 | ||
2034 | q_data = get_q_data(ctx, vb->vb2_queue->type); | |
ed1f47cc | 2035 | num_planes = q_data->nplanes; |
45719127 | 2036 | |
5269fef7 | 2037 | if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { |
823f4208 | 2038 | if (!(q_data->flags & Q_IS_INTERLACED)) { |
2d700715 | 2039 | vbuf->field = V4L2_FIELD_NONE; |
5269fef7 | 2040 | } else { |
2d700715 | 2041 | if (vbuf->field != V4L2_FIELD_TOP && |
823f4208 ND |
2042 | vbuf->field != V4L2_FIELD_BOTTOM && |
2043 | vbuf->field != V4L2_FIELD_SEQ_TB) | |
5269fef7 AT |
2044 | return -EINVAL; |
2045 | } | |
2046 | } | |
2047 | ||
45719127 AT |
2048 | for (i = 0; i < num_planes; i++) { |
2049 | if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) { | |
2050 | vpe_err(ctx->dev, | |
2051 | "data will not fit into plane (%lu < %lu)\n", | |
2052 | vb2_plane_size(vb, i), | |
2053 | (long) q_data->sizeimage[i]); | |
2054 | return -EINVAL; | |
2055 | } | |
2056 | } | |
2057 | ||
2058 | for (i = 0; i < num_planes; i++) | |
2059 | vb2_set_plane_payload(vb, i, q_data->sizeimage[i]); | |
2060 | ||
2061 | return 0; | |
2062 | } | |
2063 | ||
2064 | static void vpe_buf_queue(struct vb2_buffer *vb) | |
2065 | { | |
2d700715 | 2066 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
45719127 | 2067 | struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); |
47e604c5 | 2068 | |
2d700715 | 2069 | v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); |
47e604c5 PL |
2070 | } |
2071 | ||
35be6d86 | 2072 | static int check_srcdst_sizes(struct vpe_ctx *ctx) |
47e604c5 | 2073 | { |
35be6d86 BP |
2074 | struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC]; |
2075 | struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST]; | |
2076 | unsigned int src_w = s_q_data->c_rect.width; | |
2077 | unsigned int src_h = s_q_data->c_rect.height; | |
2078 | unsigned int dst_w = d_q_data->c_rect.width; | |
2079 | unsigned int dst_h = d_q_data->c_rect.height; | |
15f632e6 | 2080 | |
35be6d86 BP |
2081 | if (src_w == dst_w && src_h == dst_h) |
2082 | return 0; | |
47e604c5 | 2083 | |
35be6d86 BP |
2084 | if (src_h <= SC_MAX_PIXEL_HEIGHT && |
2085 | src_w <= SC_MAX_PIXEL_WIDTH && | |
2086 | dst_h <= SC_MAX_PIXEL_HEIGHT && | |
2087 | dst_w <= SC_MAX_PIXEL_WIDTH) | |
2088 | return 0; | |
0f469c1a | 2089 | |
35be6d86 | 2090 | return -1; |
47e604c5 PL |
2091 | } |
2092 | ||
35be6d86 BP |
2093 | static void vpe_return_all_buffers(struct vpe_ctx *ctx, struct vb2_queue *q, |
2094 | enum vb2_buffer_state state) | |
47e604c5 | 2095 | { |
dfe1349d BP |
2096 | struct vb2_v4l2_buffer *vb; |
2097 | unsigned long flags; | |
47e604c5 | 2098 | |
dfe1349d BP |
2099 | for (;;) { |
2100 | if (V4L2_TYPE_IS_OUTPUT(q->type)) | |
2101 | vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); | |
2102 | else | |
2103 | vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); | |
2104 | if (!vb) | |
2105 | break; | |
2106 | spin_lock_irqsave(&ctx->dev->lock, flags); | |
35be6d86 | 2107 | v4l2_m2m_buf_done(vb, state); |
dfe1349d BP |
2108 | spin_unlock_irqrestore(&ctx->dev->lock, flags); |
2109 | } | |
2110 | ||
2111 | /* | |
2112 | * Cleanup the in-transit vb2 buffers that have been | |
2113 | * removed from their respective queue already but for | |
2114 | * which procecessing has not been completed yet. | |
2115 | */ | |
2116 | if (V4L2_TYPE_IS_OUTPUT(q->type)) { | |
2117 | spin_lock_irqsave(&ctx->dev->lock, flags); | |
2118 | ||
2119 | if (ctx->src_vbs[2]) | |
35be6d86 | 2120 | v4l2_m2m_buf_done(ctx->src_vbs[2], state); |
dfe1349d BP |
2121 | |
2122 | if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2])) | |
35be6d86 | 2123 | v4l2_m2m_buf_done(ctx->src_vbs[1], state); |
dfe1349d BP |
2124 | |
2125 | if (ctx->src_vbs[0] && | |
2126 | (ctx->src_vbs[0] != ctx->src_vbs[1]) && | |
2127 | (ctx->src_vbs[0] != ctx->src_vbs[2])) | |
35be6d86 | 2128 | v4l2_m2m_buf_done(ctx->src_vbs[0], state); |
dfe1349d BP |
2129 | |
2130 | ctx->src_vbs[2] = NULL; | |
2131 | ctx->src_vbs[1] = NULL; | |
2132 | ctx->src_vbs[0] = NULL; | |
2133 | ||
2134 | spin_unlock_irqrestore(&ctx->dev->lock, flags); | |
2135 | } else { | |
2136 | if (ctx->dst_vb) { | |
2137 | spin_lock_irqsave(&ctx->dev->lock, flags); | |
2138 | ||
35be6d86 | 2139 | v4l2_m2m_buf_done(ctx->dst_vb, state); |
dfe1349d BP |
2140 | ctx->dst_vb = NULL; |
2141 | spin_unlock_irqrestore(&ctx->dev->lock, flags); | |
2142 | } | |
2143 | } | |
45719127 AT |
2144 | } |
2145 | ||
35be6d86 BP |
2146 | static int vpe_start_streaming(struct vb2_queue *q, unsigned int count) |
2147 | { | |
2148 | struct vpe_ctx *ctx = vb2_get_drv_priv(q); | |
2149 | ||
2150 | /* Check any of the size exceed maximum scaling sizes */ | |
2151 | if (check_srcdst_sizes(ctx)) { | |
2152 | vpe_err(ctx->dev, | |
2153 | "Conversion setup failed, check source and destination parameters\n" | |
2154 | ); | |
2155 | vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_QUEUED); | |
2156 | return -EINVAL; | |
2157 | } | |
2158 | ||
2159 | if (ctx->deinterlacing) | |
2160 | config_edi_input_mode(ctx, 0x0); | |
2161 | ||
2162 | if (ctx->sequence != 0) | |
2163 | set_srcdst_params(ctx); | |
2164 | ||
2165 | return 0; | |
2166 | } | |
2167 | ||
2168 | static void vpe_stop_streaming(struct vb2_queue *q) | |
2169 | { | |
2170 | struct vpe_ctx *ctx = vb2_get_drv_priv(q); | |
2171 | ||
2172 | vpe_dump_regs(ctx->dev); | |
2173 | vpdma_dump_regs(ctx->dev->vpdma); | |
2174 | ||
2175 | vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_ERROR); | |
2176 | } | |
2177 | ||
b7b361f0 | 2178 | static const struct vb2_ops vpe_qops = { |
45719127 AT |
2179 | .queue_setup = vpe_queue_setup, |
2180 | .buf_prepare = vpe_buf_prepare, | |
2181 | .buf_queue = vpe_buf_queue, | |
3d0aed38 PL |
2182 | .wait_prepare = vb2_ops_wait_prepare, |
2183 | .wait_finish = vb2_ops_wait_finish, | |
47e604c5 PL |
2184 | .start_streaming = vpe_start_streaming, |
2185 | .stop_streaming = vpe_stop_streaming, | |
45719127 AT |
2186 | }; |
2187 | ||
2188 | static int queue_init(void *priv, struct vb2_queue *src_vq, | |
2189 | struct vb2_queue *dst_vq) | |
2190 | { | |
2191 | struct vpe_ctx *ctx = priv; | |
3d0aed38 | 2192 | struct vpe_dev *dev = ctx->dev; |
45719127 AT |
2193 | int ret; |
2194 | ||
2195 | memset(src_vq, 0, sizeof(*src_vq)); | |
2196 | src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; | |
668f91d4 | 2197 | src_vq->io_modes = VB2_MMAP | VB2_DMABUF; |
45719127 AT |
2198 | src_vq->drv_priv = ctx; |
2199 | src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); | |
2200 | src_vq->ops = &vpe_qops; | |
2201 | src_vq->mem_ops = &vb2_dma_contig_memops; | |
ade48681 | 2202 | src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
3d0aed38 | 2203 | src_vq->lock = &dev->dev_mutex; |
dce57314 | 2204 | src_vq->dev = dev->v4l2_dev.dev; |
45719127 AT |
2205 | |
2206 | ret = vb2_queue_init(src_vq); | |
2207 | if (ret) | |
2208 | return ret; | |
2209 | ||
2210 | memset(dst_vq, 0, sizeof(*dst_vq)); | |
2211 | dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; | |
668f91d4 | 2212 | dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; |
45719127 AT |
2213 | dst_vq->drv_priv = ctx; |
2214 | dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); | |
2215 | dst_vq->ops = &vpe_qops; | |
2216 | dst_vq->mem_ops = &vb2_dma_contig_memops; | |
ade48681 | 2217 | dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
3d0aed38 | 2218 | dst_vq->lock = &dev->dev_mutex; |
dce57314 | 2219 | dst_vq->dev = dev->v4l2_dev.dev; |
45719127 AT |
2220 | |
2221 | return vb2_queue_init(dst_vq); | |
2222 | } | |
2223 | ||
2224 | static const struct v4l2_ctrl_config vpe_bufs_per_job = { | |
2225 | .ops = &vpe_ctrl_ops, | |
2226 | .id = V4L2_CID_VPE_BUFS_PER_JOB, | |
2227 | .name = "Buffers Per Transaction", | |
2228 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2229 | .def = VPE_DEF_BUFS_PER_JOB, | |
2230 | .min = 1, | |
2231 | .max = VIDEO_MAX_FRAME, | |
2232 | .step = 1, | |
2233 | }; | |
2234 | ||
2235 | /* | |
2236 | * File operations | |
2237 | */ | |
2238 | static int vpe_open(struct file *file) | |
2239 | { | |
2240 | struct vpe_dev *dev = video_drvdata(file); | |
45719127 AT |
2241 | struct vpe_q_data *s_q_data; |
2242 | struct v4l2_ctrl_handler *hdl; | |
47e604c5 | 2243 | struct vpe_ctx *ctx; |
45719127 AT |
2244 | int ret; |
2245 | ||
2246 | vpe_dbg(dev, "vpe_open\n"); | |
2247 | ||
45719127 AT |
2248 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
2249 | if (!ctx) | |
2250 | return -ENOMEM; | |
2251 | ||
2252 | ctx->dev = dev; | |
2253 | ||
2254 | if (mutex_lock_interruptible(&dev->dev_mutex)) { | |
2255 | ret = -ERESTARTSYS; | |
2256 | goto free_ctx; | |
2257 | } | |
2258 | ||
2259 | ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE, | |
2260 | VPDMA_LIST_TYPE_NORMAL); | |
2261 | if (ret != 0) | |
2262 | goto unlock; | |
2263 | ||
2264 | ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb)); | |
2265 | if (ret != 0) | |
2266 | goto free_desc_list; | |
2267 | ||
773f0657 AT |
2268 | ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE); |
2269 | if (ret != 0) | |
2270 | goto free_mmr_adb; | |
2271 | ||
2272 | ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE); | |
2273 | if (ret != 0) | |
2274 | goto free_sc_h; | |
2275 | ||
45719127 AT |
2276 | init_adb_hdrs(ctx); |
2277 | ||
2278 | v4l2_fh_init(&ctx->fh, video_devdata(file)); | |
2279 | file->private_data = &ctx->fh; | |
2280 | ||
2281 | hdl = &ctx->hdl; | |
2282 | v4l2_ctrl_handler_init(hdl, 1); | |
2283 | v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL); | |
2284 | if (hdl->error) { | |
2285 | ret = hdl->error; | |
2286 | goto exit_fh; | |
2287 | } | |
2288 | ctx->fh.ctrl_handler = hdl; | |
2289 | v4l2_ctrl_handler_setup(hdl); | |
2290 | ||
2291 | s_q_data = &ctx->q_data[Q_DATA_SRC]; | |
2292 | s_q_data->fmt = &vpe_formats[2]; | |
2293 | s_q_data->width = 1920; | |
2294 | s_q_data->height = 1080; | |
ed1f47cc | 2295 | s_q_data->nplanes = 1; |
67fb87ee | 2296 | s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width * |
45719127 | 2297 | s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3; |
67fb87ee AT |
2298 | s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] * |
2299 | s_q_data->height); | |
2300 | s_q_data->colorspace = V4L2_COLORSPACE_REC709; | |
585e6f01 | 2301 | s_q_data->field = V4L2_FIELD_NONE; |
45719127 AT |
2302 | s_q_data->c_rect.left = 0; |
2303 | s_q_data->c_rect.top = 0; | |
2304 | s_q_data->c_rect.width = s_q_data->width; | |
2305 | s_q_data->c_rect.height = s_q_data->height; | |
2306 | s_q_data->flags = 0; | |
2307 | ||
2308 | ctx->q_data[Q_DATA_DST] = *s_q_data; | |
2309 | ||
585e6f01 | 2310 | set_dei_shadow_registers(ctx); |
45719127 AT |
2311 | set_src_registers(ctx); |
2312 | set_dst_registers(ctx); | |
2313 | ret = set_srcdst_params(ctx); | |
2314 | if (ret) | |
2315 | goto exit_fh; | |
2316 | ||
47e604c5 | 2317 | ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init); |
45719127 | 2318 | |
47e604c5 PL |
2319 | if (IS_ERR(ctx->fh.m2m_ctx)) { |
2320 | ret = PTR_ERR(ctx->fh.m2m_ctx); | |
45719127 AT |
2321 | goto exit_fh; |
2322 | } | |
2323 | ||
2324 | v4l2_fh_add(&ctx->fh); | |
2325 | ||
2326 | /* | |
2327 | * for now, just report the creation of the first instance, we can later | |
2328 | * optimize the driver to enable or disable clocks when the first | |
2329 | * instance is created or the last instance released | |
2330 | */ | |
2331 | if (atomic_inc_return(&dev->num_instances) == 1) | |
2332 | vpe_dbg(dev, "first instance created\n"); | |
2333 | ||
2334 | ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB; | |
2335 | ||
2336 | ctx->load_mmrs = true; | |
2337 | ||
2338 | vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n", | |
47e604c5 | 2339 | ctx, ctx->fh.m2m_ctx); |
45719127 AT |
2340 | |
2341 | mutex_unlock(&dev->dev_mutex); | |
2342 | ||
2343 | return 0; | |
2344 | exit_fh: | |
2345 | v4l2_ctrl_handler_free(hdl); | |
2346 | v4l2_fh_exit(&ctx->fh); | |
773f0657 AT |
2347 | vpdma_free_desc_buf(&ctx->sc_coeff_v); |
2348 | free_sc_h: | |
2349 | vpdma_free_desc_buf(&ctx->sc_coeff_h); | |
2350 | free_mmr_adb: | |
45719127 AT |
2351 | vpdma_free_desc_buf(&ctx->mmr_adb); |
2352 | free_desc_list: | |
2353 | vpdma_free_desc_list(&ctx->desc_list); | |
2354 | unlock: | |
2355 | mutex_unlock(&dev->dev_mutex); | |
2356 | free_ctx: | |
2357 | kfree(ctx); | |
2358 | return ret; | |
2359 | } | |
2360 | ||
2361 | static int vpe_release(struct file *file) | |
2362 | { | |
2363 | struct vpe_dev *dev = video_drvdata(file); | |
2364 | struct vpe_ctx *ctx = file2ctx(file); | |
2365 | ||
2366 | vpe_dbg(dev, "releasing instance %p\n", ctx); | |
2367 | ||
2368 | mutex_lock(&dev->dev_mutex); | |
585e6f01 | 2369 | free_mv_buffers(ctx); |
45719127 AT |
2370 | vpdma_free_desc_list(&ctx->desc_list); |
2371 | vpdma_free_desc_buf(&ctx->mmr_adb); | |
2372 | ||
f43aa420 HB |
2373 | vpdma_free_desc_buf(&ctx->sc_coeff_v); |
2374 | vpdma_free_desc_buf(&ctx->sc_coeff_h); | |
2375 | ||
45719127 AT |
2376 | v4l2_fh_del(&ctx->fh); |
2377 | v4l2_fh_exit(&ctx->fh); | |
2378 | v4l2_ctrl_handler_free(&ctx->hdl); | |
47e604c5 | 2379 | v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); |
45719127 AT |
2380 | |
2381 | kfree(ctx); | |
2382 | ||
2383 | /* | |
2384 | * for now, just report the release of the last instance, we can later | |
2385 | * optimize the driver to enable or disable clocks when the first | |
2386 | * instance is created or the last instance released | |
2387 | */ | |
2388 | if (atomic_dec_return(&dev->num_instances) == 0) | |
2389 | vpe_dbg(dev, "last instance released\n"); | |
2390 | ||
2391 | mutex_unlock(&dev->dev_mutex); | |
2392 | ||
2393 | return 0; | |
2394 | } | |
2395 | ||
45719127 AT |
2396 | static const struct v4l2_file_operations vpe_fops = { |
2397 | .owner = THIS_MODULE, | |
2398 | .open = vpe_open, | |
2399 | .release = vpe_release, | |
47e604c5 | 2400 | .poll = v4l2_m2m_fop_poll, |
45719127 | 2401 | .unlocked_ioctl = video_ioctl2, |
47e604c5 | 2402 | .mmap = v4l2_m2m_fop_mmap, |
45719127 AT |
2403 | }; |
2404 | ||
5303135c | 2405 | static const struct video_device vpe_videodev = { |
45719127 AT |
2406 | .name = VPE_MODULE_NAME, |
2407 | .fops = &vpe_fops, | |
2408 | .ioctl_ops = &vpe_ioctl_ops, | |
2409 | .minor = -1, | |
772a7b7a | 2410 | .release = video_device_release_empty, |
45719127 | 2411 | .vfl_dir = VFL_DIR_M2M, |
1ddc8a97 | 2412 | .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING, |
45719127 AT |
2413 | }; |
2414 | ||
42f310d3 | 2415 | static const struct v4l2_m2m_ops m2m_ops = { |
45719127 AT |
2416 | .device_run = device_run, |
2417 | .job_ready = job_ready, | |
2418 | .job_abort = job_abort, | |
45719127 AT |
2419 | }; |
2420 | ||
2421 | static int vpe_runtime_get(struct platform_device *pdev) | |
2422 | { | |
2423 | int r; | |
2424 | ||
2425 | dev_dbg(&pdev->dev, "vpe_runtime_get\n"); | |
2426 | ||
2427 | r = pm_runtime_get_sync(&pdev->dev); | |
2428 | WARN_ON(r < 0); | |
2429 | return r < 0 ? r : 0; | |
2430 | } | |
2431 | ||
2432 | static void vpe_runtime_put(struct platform_device *pdev) | |
2433 | { | |
2434 | ||
2435 | int r; | |
2436 | ||
2437 | dev_dbg(&pdev->dev, "vpe_runtime_put\n"); | |
2438 | ||
2439 | r = pm_runtime_put_sync(&pdev->dev); | |
2440 | WARN_ON(r < 0 && r != -ENOSYS); | |
2441 | } | |
2442 | ||
b2c9472f AT |
2443 | static void vpe_fw_cb(struct platform_device *pdev) |
2444 | { | |
2445 | struct vpe_dev *dev = platform_get_drvdata(pdev); | |
2446 | struct video_device *vfd; | |
2447 | int ret; | |
2448 | ||
2449 | vfd = &dev->vfd; | |
2450 | *vfd = vpe_videodev; | |
2451 | vfd->lock = &dev->dev_mutex; | |
2452 | vfd->v4l2_dev = &dev->v4l2_dev; | |
2453 | ||
2454 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); | |
2455 | if (ret) { | |
2456 | vpe_err(dev, "Failed to register video device\n"); | |
2457 | ||
2458 | vpe_set_clock_enable(dev, 0); | |
2459 | vpe_runtime_put(pdev); | |
2460 | pm_runtime_disable(&pdev->dev); | |
2461 | v4l2_m2m_release(dev->m2m_dev); | |
b2c9472f AT |
2462 | v4l2_device_unregister(&dev->v4l2_dev); |
2463 | ||
2464 | return; | |
2465 | } | |
2466 | ||
2467 | video_set_drvdata(vfd, dev); | |
b2c9472f AT |
2468 | dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n", |
2469 | vfd->num); | |
2470 | } | |
2471 | ||
45719127 AT |
2472 | static int vpe_probe(struct platform_device *pdev) |
2473 | { | |
2474 | struct vpe_dev *dev; | |
45719127 AT |
2475 | int ret, irq, func; |
2476 | ||
2477 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); | |
b68231a1 WY |
2478 | if (!dev) |
2479 | return -ENOMEM; | |
45719127 AT |
2480 | |
2481 | spin_lock_init(&dev->lock); | |
2482 | ||
2483 | ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); | |
2484 | if (ret) | |
2485 | return ret; | |
2486 | ||
2487 | atomic_set(&dev->num_instances, 0); | |
2488 | mutex_init(&dev->dev_mutex); | |
2489 | ||
44687b2e AT |
2490 | dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2491 | "vpe_top"); | |
45719127 AT |
2492 | /* |
2493 | * HACK: we get resource info from device tree in the form of a list of | |
2494 | * VPE sub blocks, the driver currently uses only the base of vpe_top | |
2495 | * for register access, the driver should be changed later to access | |
2496 | * registers based on the sub block base addresses | |
2497 | */ | |
44687b2e | 2498 | dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K); |
b68231a1 WY |
2499 | if (!dev->base) { |
2500 | ret = -ENOMEM; | |
45719127 AT |
2501 | goto v4l2_dev_unreg; |
2502 | } | |
2503 | ||
2504 | irq = platform_get_irq(pdev, 0); | |
2505 | ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME, | |
2506 | dev); | |
2507 | if (ret) | |
2508 | goto v4l2_dev_unreg; | |
2509 | ||
2510 | platform_set_drvdata(pdev, dev); | |
2511 | ||
45719127 AT |
2512 | dev->m2m_dev = v4l2_m2m_init(&m2m_ops); |
2513 | if (IS_ERR(dev->m2m_dev)) { | |
2514 | vpe_err(dev, "Failed to init mem2mem device\n"); | |
2515 | ret = PTR_ERR(dev->m2m_dev); | |
dce57314 | 2516 | goto v4l2_dev_unreg; |
45719127 AT |
2517 | } |
2518 | ||
2519 | pm_runtime_enable(&pdev->dev); | |
2520 | ||
2521 | ret = vpe_runtime_get(pdev); | |
2522 | if (ret) | |
2523 | goto rel_m2m; | |
2524 | ||
2525 | /* Perform clk enable followed by reset */ | |
2526 | vpe_set_clock_enable(dev, 1); | |
2527 | ||
2528 | vpe_top_reset(dev); | |
2529 | ||
2530 | func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK, | |
2531 | VPE_PID_FUNC_SHIFT); | |
2532 | vpe_dbg(dev, "VPE PID function %x\n", func); | |
2533 | ||
2534 | vpe_top_vpdma_reset(dev); | |
2535 | ||
1c6e8178 | 2536 | dev->sc = sc_create(pdev, "sc"); |
44687b2e AT |
2537 | if (IS_ERR(dev->sc)) { |
2538 | ret = PTR_ERR(dev->sc); | |
2539 | goto runtime_put; | |
2540 | } | |
2541 | ||
51b56c39 | 2542 | dev->csc = csc_create(pdev, "csc"); |
6948082d AT |
2543 | if (IS_ERR(dev->csc)) { |
2544 | ret = PTR_ERR(dev->csc); | |
2545 | goto runtime_put; | |
2546 | } | |
2547 | ||
c786595b ND |
2548 | dev->vpdma = &dev->vpdma_data; |
2549 | ret = vpdma_create(pdev, dev->vpdma, vpe_fw_cb); | |
2550 | if (ret) | |
45719127 AT |
2551 | goto runtime_put; |
2552 | ||
45719127 AT |
2553 | return 0; |
2554 | ||
2555 | runtime_put: | |
2556 | vpe_runtime_put(pdev); | |
2557 | rel_m2m: | |
2558 | pm_runtime_disable(&pdev->dev); | |
2559 | v4l2_m2m_release(dev->m2m_dev); | |
45719127 AT |
2560 | v4l2_dev_unreg: |
2561 | v4l2_device_unregister(&dev->v4l2_dev); | |
2562 | ||
2563 | return ret; | |
2564 | } | |
2565 | ||
2566 | static int vpe_remove(struct platform_device *pdev) | |
2567 | { | |
1eb96047 | 2568 | struct vpe_dev *dev = platform_get_drvdata(pdev); |
45719127 AT |
2569 | |
2570 | v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME); | |
2571 | ||
2572 | v4l2_m2m_release(dev->m2m_dev); | |
2573 | video_unregister_device(&dev->vfd); | |
2574 | v4l2_device_unregister(&dev->v4l2_dev); | |
45719127 AT |
2575 | |
2576 | vpe_set_clock_enable(dev, 0); | |
2577 | vpe_runtime_put(pdev); | |
2578 | pm_runtime_disable(&pdev->dev); | |
2579 | ||
2580 | return 0; | |
2581 | } | |
2582 | ||
2583 | #if defined(CONFIG_OF) | |
2584 | static const struct of_device_id vpe_of_match[] = { | |
2585 | { | |
2586 | .compatible = "ti,vpe", | |
2587 | }, | |
2588 | {}, | |
2589 | }; | |
e228467c | 2590 | MODULE_DEVICE_TABLE(of, vpe_of_match); |
45719127 AT |
2591 | #endif |
2592 | ||
2593 | static struct platform_driver vpe_pdrv = { | |
2594 | .probe = vpe_probe, | |
2595 | .remove = vpe_remove, | |
2596 | .driver = { | |
2597 | .name = VPE_MODULE_NAME, | |
47e604c5 | 2598 | .of_match_table = of_match_ptr(vpe_of_match), |
45719127 AT |
2599 | }, |
2600 | }; | |
2601 | ||
903cbb83 | 2602 | module_platform_driver(vpe_pdrv); |
45719127 AT |
2603 | |
2604 | MODULE_DESCRIPTION("TI VPE driver"); | |
2605 | MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>"); | |
2606 | MODULE_LICENSE("GPL"); |