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[media] s5p-mfc: added missing end-of-lines in debug messages
[linux-2.6-block.git] / drivers / media / platform / s5p-mfc / s5p_mfc_opr_v6.c
CommitLineData
f96f3cfa
JP		 1/*
2 * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
3 *
4 * Samsung MFC (Multi Function Codec - FIMV) driver
5 * This file contains hw related functions.
6 *
7 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
8 * http://www.samsung.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#undef DEBUG
16
17#include <linux/delay.h>
18#include <linux/mm.h>
19#include <linux/io.h>
20#include <linux/jiffies.h>
21#include <linux/firmware.h>
22#include <linux/err.h>
23#include <linux/sched.h>
24#include <linux/dma-mapping.h>
25
26#include <asm/cacheflush.h>
27
28#include "s5p_mfc_common.h"
29#include "s5p_mfc_cmd.h"
30#include "s5p_mfc_intr.h"
31#include "s5p_mfc_pm.h"
32#include "s5p_mfc_debug.h"
33#include "s5p_mfc_opr.h"
34#include "s5p_mfc_opr_v6.h"
35
36/* #define S5P_MFC_DEBUG_REGWRITE */
37#ifdef S5P_MFC_DEBUG_REGWRITE
38#undef writel
39#define writel(v, r) \
40 do { \
41 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
42 __raw_writel(v, r); \
43 } while (0)
44#endif /* S5P_MFC_DEBUG_REGWRITE */
45
46#define READL(offset) readl(dev->regs_base + (offset))
47#define WRITEL(data, offset) writel((data), dev->regs_base + (offset))
48#define OFFSETA(x) (((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET)
49#define OFFSETB(x) (((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET)
50
51/* Allocate temporary buffers for decoding */
b9571a57 52static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 53{
54 /* NOP */
55
56 return 0;
57}
58
59/* Release temproary buffers for decoding */
b9571a57 60static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 61{
62 /* NOP */
63}
64
f96f3cfa 65/* Allocate codec buffers */
b9571a57 66static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 67{
68 struct s5p_mfc_dev *dev = ctx->dev;
69 unsigned int mb_width, mb_height;
317b4ca4 70 int ret;
f96f3cfa
JP		 71
72 mb_width = MB_WIDTH(ctx->img_width);
73 mb_height = MB_HEIGHT(ctx->img_height);
74
75 if (ctx->type == MFCINST_DECODER) {
76 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
77 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
78 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
79 } else if (ctx->type == MFCINST_ENCODER) {
80 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
81 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
82 S5P_FIMV_TMV_BUFFER_ALIGN_V6);
83 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
84 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
85 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
86 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
87 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
88 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
89 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
90 ctx->img_width, ctx->img_height,
91 mb_width, mb_height),
92 S5P_FIMV_ME_BUFFER_ALIGN_V6);
93
94 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
95 ctx->luma_dpb_size, ctx->chroma_dpb_size);
96 } else {
97 return -EINVAL;
98 }
99
100 /* Codecs have different memory requirements */
101 switch (ctx->codec_mode) {
102 case S5P_MFC_CODEC_H264_DEC:
103 case S5P_MFC_CODEC_H264_MVC_DEC:
104 ctx->scratch_buf_size =
105 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
106 mb_width,
107 mb_height);
108 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
109 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
317b4ca4 110 ctx->bank1.size =
f96f3cfa
JP		 111 ctx->scratch_buf_size +
112 (ctx->mv_count * ctx->mv_size);
113 break;
114 case S5P_MFC_CODEC_MPEG4_DEC:
115 ctx->scratch_buf_size =
116 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
117 mb_width,
118 mb_height);
119 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
120 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
317b4ca4 121 ctx->bank1.size = ctx->scratch_buf_size;
f96f3cfa
JP		 122 break;
123 case S5P_MFC_CODEC_VC1RCV_DEC:
124 case S5P_MFC_CODEC_VC1_DEC:
125 ctx->scratch_buf_size =
126 S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
127 mb_width,
128 mb_height);
129 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
130 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
317b4ca4 131 ctx->bank1.size = ctx->scratch_buf_size;
f96f3cfa
JP		 132 break;
133 case S5P_MFC_CODEC_MPEG2_DEC:
317b4ca4
KD		 134 ctx->bank1.size = 0;
135 ctx->bank2.size = 0;
f96f3cfa
JP		 136 break;
137 case S5P_MFC_CODEC_H263_DEC:
138 ctx->scratch_buf_size =
139 S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
140 mb_width,
141 mb_height);
142 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
143 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
317b4ca4 144 ctx->bank1.size = ctx->scratch_buf_size;
f96f3cfa
JP		 145 break;
146 case S5P_MFC_CODEC_VP8_DEC:
147 ctx->scratch_buf_size =
148 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
149 mb_width,
150 mb_height);
151 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
152 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
317b4ca4 153 ctx->bank1.size = ctx->scratch_buf_size;
f96f3cfa
JP		 154 break;
155 case S5P_MFC_CODEC_H264_ENC:
156 ctx->scratch_buf_size =
157 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
158 mb_width,
159 mb_height);
160 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
161 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
317b4ca4 162 ctx->bank1.size =
f96f3cfa 163 ctx->scratch_buf_size + ctx->tmv_buffer_size +
e9d98ddc 164 (ctx->pb_count * (ctx->luma_dpb_size +
f96f3cfa 165 ctx->chroma_dpb_size + ctx->me_buffer_size));
317b4ca4 166 ctx->bank2.size = 0;
f96f3cfa
JP		 167 break;
168 case S5P_MFC_CODEC_MPEG4_ENC:
169 case S5P_MFC_CODEC_H263_ENC:
170 ctx->scratch_buf_size =
171 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
172 mb_width,
173 mb_height);
174 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
175 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
317b4ca4 176 ctx->bank1.size =
f96f3cfa 177 ctx->scratch_buf_size + ctx->tmv_buffer_size +
e9d98ddc 178 (ctx->pb_count * (ctx->luma_dpb_size +
f96f3cfa 179 ctx->chroma_dpb_size + ctx->me_buffer_size));
317b4ca4 180 ctx->bank2.size = 0;
f96f3cfa
JP		 181 break;
182 default:
183 break;
184 }
185
186 /* Allocate only if memory from bank 1 is necessary */
317b4ca4
KD		 187 if (ctx->bank1.size > 0) {
188 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1);
189 if (ret) {
190 mfc_err("Failed to allocate Bank1 memory\n");
191 return ret;
f96f3cfa 192 }
317b4ca4 193 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
f96f3cfa 194 }
f96f3cfa
JP		 195 return 0;
196}
197
198/* Release buffers allocated for codec */
b9571a57 199static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa 200{
317b4ca4 201 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
f96f3cfa
JP		 202}
203
204/* Allocate memory for instance data buffer */
b9571a57 205static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 206{
207 struct s5p_mfc_dev *dev = ctx->dev;
208 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
317b4ca4 209 int ret;
f96f3cfa
JP		 210
211 mfc_debug_enter();
212
213 switch (ctx->codec_mode) {
214 case S5P_MFC_CODEC_H264_DEC:
215 case S5P_MFC_CODEC_H264_MVC_DEC:
216 ctx->ctx.size = buf_size->h264_dec_ctx;
217 break;
218 case S5P_MFC_CODEC_MPEG4_DEC:
219 case S5P_MFC_CODEC_H263_DEC:
220 case S5P_MFC_CODEC_VC1RCV_DEC:
221 case S5P_MFC_CODEC_VC1_DEC:
222 case S5P_MFC_CODEC_MPEG2_DEC:
223 case S5P_MFC_CODEC_VP8_DEC:
224 ctx->ctx.size = buf_size->other_dec_ctx;
225 break;
226 case S5P_MFC_CODEC_H264_ENC:
227 ctx->ctx.size = buf_size->h264_enc_ctx;
228 break;
229 case S5P_MFC_CODEC_MPEG4_ENC:
230 case S5P_MFC_CODEC_H263_ENC:
231 ctx->ctx.size = buf_size->other_enc_ctx;
232 break;
233 default:
234 ctx->ctx.size = 0;
235 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
236 break;
237 }
238
317b4ca4
KD		 239 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx);
240 if (ret) {
241 mfc_err("Failed to allocate instance buffer\n");
242 return ret;
f96f3cfa
JP		 243 }
244
245 memset(ctx->ctx.virt, 0, ctx->ctx.size);
246 wmb();
247
248 mfc_debug_leave();
249
250 return 0;
251}
252
253/* Release instance buffer */
b9571a57 254static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa 255{
317b4ca4 256 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
f96f3cfa
JP		 257}
258
259/* Allocate context buffers for SYS_INIT */
b9571a57 260static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 261{
262 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
317b4ca4 263 int ret;
f96f3cfa
JP		 264
265 mfc_debug_enter();
266
317b4ca4
KD		 267 dev->ctx_buf.size = buf_size->dev_ctx;
268 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
269 if (ret) {
270 mfc_err("Failed to allocate device context buffer\n");
271 return ret;
f96f3cfa
JP		 272 }
273
274 memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
275 wmb();
276
277 mfc_debug_leave();
278
279 return 0;
280}
281
282/* Release context buffers for SYS_INIT */
b9571a57 283static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
f96f3cfa 284{
317b4ca4 285 s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
f96f3cfa
JP		 286}
287
288static int calc_plane(int width, int height)
289{
290 int mbX, mbY;
291
292 mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
293 mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
294
295 if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
296 mbY = (mbY + 1) / 2 * 2;
297
298 return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
299 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
300}
301
b9571a57 302static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 303{
304 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
305 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
306 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
307 "buffer dimensions: %dx%d\n", ctx->img_width,
308 ctx->img_height, ctx->buf_width, ctx->buf_height);
309
310 ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
311 ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
312 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
313 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
314 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
315 ctx->img_height);
316 ctx->mv_size = ALIGN(ctx->mv_size, 16);
317 } else {
318 ctx->mv_size = 0;
319 }
320}
321
b9571a57 322static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 323{
324 unsigned int mb_width, mb_height;
325
326 mb_width = MB_WIDTH(ctx->img_width);
327 mb_height = MB_HEIGHT(ctx->img_height);
328
329 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
330 ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
331 ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
332}
333
334/* Set registers for decoding stream buffer */
b9571a57
SK		 335static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
336 int buf_addr, unsigned int start_num_byte,
337 unsigned int strm_size)
f96f3cfa
JP		 338{
339 struct s5p_mfc_dev *dev = ctx->dev;
340 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
341
342 mfc_debug_enter();
343 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
344 "buf_size: 0x%08x (%d)\n",
345 ctx->inst_no, buf_addr, strm_size, strm_size);
346 WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
347 WRITEL(buf_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
348 WRITEL(buf_size->cpb, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
349 WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
350
351 mfc_debug_leave();
352 return 0;
353}
354
355/* Set decoding frame buffer */
b9571a57 356static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 357{
358 unsigned int frame_size, i;
359 unsigned int frame_size_ch, frame_size_mv;
360 struct s5p_mfc_dev *dev = ctx->dev;
361 size_t buf_addr1;
362 int buf_size1;
363 int align_gap;
364
317b4ca4
KD		 365 buf_addr1 = ctx->bank1.dma;
366 buf_size1 = ctx->bank1.size;
f96f3cfa
JP		 367
368 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
369 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
370 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
371
372 WRITEL(ctx->total_dpb_count, S5P_FIMV_D_NUM_DPB_V6);
373 WRITEL(ctx->luma_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
374 WRITEL(ctx->chroma_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
375
376 WRITEL(buf_addr1, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
377 WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
378 buf_addr1 += ctx->scratch_buf_size;
379 buf_size1 -= ctx->scratch_buf_size;
380
381 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
382 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
383 WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
384 WRITEL(ctx->mv_count, S5P_FIMV_D_NUM_MV_V6);
385 }
386
387 frame_size = ctx->luma_size;
388 frame_size_ch = ctx->chroma_size;
389 frame_size_mv = ctx->mv_size;
390 mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
391 frame_size, frame_size_ch, frame_size_mv);
392
393 for (i = 0; i < ctx->total_dpb_count; i++) {
394 /* Bank2 */
395 mfc_debug(2, "Luma %d: %x\n", i,
396 ctx->dst_bufs[i].cookie.raw.luma);
397 WRITEL(ctx->dst_bufs[i].cookie.raw.luma,
398 S5P_FIMV_D_LUMA_DPB_V6 + i * 4);
399 mfc_debug(2, "\tChroma %d: %x\n", i,
400 ctx->dst_bufs[i].cookie.raw.chroma);
401 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma,
402 S5P_FIMV_D_CHROMA_DPB_V6 + i * 4);
403 }
404 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
405 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
406 for (i = 0; i < ctx->mv_count; i++) {
407 /* To test alignment */
408 align_gap = buf_addr1;
409 buf_addr1 = ALIGN(buf_addr1, 16);
410 align_gap = buf_addr1 - align_gap;
411 buf_size1 -= align_gap;
412
413 mfc_debug(2, "\tBuf1: %x, size: %d\n",
414 buf_addr1, buf_size1);
415 WRITEL(buf_addr1, S5P_FIMV_D_MV_BUFFER_V6 + i * 4);
416 buf_addr1 += frame_size_mv;
417 buf_size1 -= frame_size_mv;
418 }
419 }
420
421 mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n",
422 buf_addr1, buf_size1, ctx->total_dpb_count);
423 if (buf_size1 < 0) {
424 mfc_debug(2, "Not enough memory has been allocated.\n");
425 return -ENOMEM;
426 }
427
428 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
429 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
430 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
431
432 mfc_debug(2, "After setting buffers.\n");
433 return 0;
434}
435
436/* Set registers for encoding stream buffer */
b9571a57 437static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
f96f3cfa
JP		 438 unsigned long addr, unsigned int size)
439{
440 struct s5p_mfc_dev *dev = ctx->dev;
441
442 WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6); /* 16B align */
443 WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
444
4130eabc
AH		 445 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n",
446 addr, size);
f96f3cfa
JP		 447
448 return 0;
449}
450
b9571a57 451static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
f96f3cfa
JP		 452 unsigned long y_addr, unsigned long c_addr)
453{
454 struct s5p_mfc_dev *dev = ctx->dev;
455
456 WRITEL(y_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6); /* 256B align */
457 WRITEL(c_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
458
4130eabc
AH		 459 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
460 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
f96f3cfa
JP		 461}
462
b9571a57 463static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
f96f3cfa
JP		 464 unsigned long *y_addr, unsigned long *c_addr)
465{
466 struct s5p_mfc_dev *dev = ctx->dev;
467 unsigned long enc_recon_y_addr, enc_recon_c_addr;
468
469 *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
470 *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
471
472 enc_recon_y_addr = READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
473 enc_recon_c_addr = READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
474
4130eabc
AH		 475 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr);
476 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
f96f3cfa
JP		 477}
478
479/* Set encoding ref & codec buffer */
b9571a57 480static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 481{
482 struct s5p_mfc_dev *dev = ctx->dev;
4a9c85aa
SK		 483 size_t buf_addr1;
484 int i, buf_size1;
f96f3cfa
JP		 485
486 mfc_debug_enter();
487
317b4ca4
KD		 488 buf_addr1 = ctx->bank1.dma;
489 buf_size1 = ctx->bank1.size;
f96f3cfa
JP		 490
491 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
492
e9d98ddc 493 for (i = 0; i < ctx->pb_count; i++) {
f96f3cfa
JP		 494 WRITEL(buf_addr1, S5P_FIMV_E_LUMA_DPB_V6 + (4 * i));
495 buf_addr1 += ctx->luma_dpb_size;
496 WRITEL(buf_addr1, S5P_FIMV_E_CHROMA_DPB_V6 + (4 * i));
497 buf_addr1 += ctx->chroma_dpb_size;
498 WRITEL(buf_addr1, S5P_FIMV_E_ME_BUFFER_V6 + (4 * i));
499 buf_addr1 += ctx->me_buffer_size;
500 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
501 ctx->me_buffer_size);
502 }
503
504 WRITEL(buf_addr1, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
505 WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
506 buf_addr1 += ctx->scratch_buf_size;
507 buf_size1 -= ctx->scratch_buf_size;
508
509 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER0_V6);
510 buf_addr1 += ctx->tmv_buffer_size >> 1;
511 WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER1_V6);
512 buf_addr1 += ctx->tmv_buffer_size >> 1;
513 buf_size1 -= ctx->tmv_buffer_size;
514
515 mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n",
e9d98ddc 516 buf_addr1, buf_size1, ctx->pb_count);
f96f3cfa
JP		 517 if (buf_size1 < 0) {
518 mfc_debug(2, "Not enough memory has been allocated.\n");
519 return -ENOMEM;
520 }
521
522 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
523 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
524 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
525
526 mfc_debug_leave();
527
528 return 0;
529}
530
531static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
532{
533 struct s5p_mfc_dev *dev = ctx->dev;
534
535 /* multi-slice control */
536 /* multi-slice MB number or bit size */
537 WRITEL(ctx->slice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
538 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
539 WRITEL(ctx->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
540 } else if (ctx->slice_mode ==
541 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
542 WRITEL(ctx->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
543 } else {
544 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
545 WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
546 }
547
548 return 0;
549}
550
551static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
552{
553 struct s5p_mfc_dev *dev = ctx->dev;
554 struct s5p_mfc_enc_params *p = &ctx->enc_params;
555 unsigned int reg = 0;
556
557 mfc_debug_enter();
558
559 /* width */
560 WRITEL(ctx->img_width, S5P_FIMV_E_FRAME_WIDTH_V6); /* 16 align */
561 /* height */
562 WRITEL(ctx->img_height, S5P_FIMV_E_FRAME_HEIGHT_V6); /* 16 align */
563
564 /* cropped width */
565 WRITEL(ctx->img_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
566 /* cropped height */
567 WRITEL(ctx->img_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
568 /* cropped offset */
569 WRITEL(0x0, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
570
571 /* pictype : IDR period */
572 reg = 0;
573 reg |= p->gop_size & 0xFFFF;
574 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
575
576 /* multi-slice control */
577 /* multi-slice MB number or bit size */
578 ctx->slice_mode = p->slice_mode;
579 reg = 0;
580 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
581 reg |= (0x1 << 3);
582 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
583 ctx->slice_size.mb = p->slice_mb;
584 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
585 reg |= (0x1 << 3);
586 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
587 ctx->slice_size.bits = p->slice_bit;
588 } else {
589 reg &= ~(0x1 << 3);
590 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
591 }
592
593 s5p_mfc_set_slice_mode(ctx);
594
595 /* cyclic intra refresh */
596 WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE_V6);
597 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
598 if (p->intra_refresh_mb == 0)
599 reg &= ~(0x1 << 4);
600 else
601 reg |= (0x1 << 4);
602 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
603
604 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
605 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
606 reg &= ~(0x1 << 9);
607 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
608
609 /* memory structure cur. frame */
610 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
611 /* 0: Linear, 1: 2D tiled*/
612 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
613 reg &= ~(0x1 << 7);
614 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
615 /* 0: NV12(CbCr), 1: NV21(CrCb) */
616 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
617 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
618 /* 0: Linear, 1: 2D tiled*/
619 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
620 reg &= ~(0x1 << 7);
621 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
622 /* 0: NV12(CbCr), 1: NV21(CrCb) */
623 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
624 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
625 /* 0: Linear, 1: 2D tiled*/
626 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
627 reg |= (0x1 << 7);
628 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
629 /* 0: NV12(CbCr), 1: NV21(CrCb) */
630 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
631 }
632
633 /* memory structure recon. frame */
634 /* 0: Linear, 1: 2D tiled */
635 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
636 reg |= (0x1 << 8);
637 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
638
639 /* padding control & value */
640 WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL_V6);
641 if (p->pad) {
642 reg = 0;
643 /** enable */
644 reg |= (1 << 31);
645 /** cr value */
646 reg |= ((p->pad_cr & 0xFF) << 16);
647 /** cb value */
648 reg |= ((p->pad_cb & 0xFF) << 8);
649 /** y value */
650 reg |= p->pad_luma & 0xFF;
651 WRITEL(reg, S5P_FIMV_E_PADDING_CTRL_V6);
652 }
653
654 /* rate control config. */
655 reg = 0;
656 /* frame-level rate control */
657 reg |= ((p->rc_frame & 0x1) << 9);
658 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
659
660 /* bit rate */
661 if (p->rc_frame)
662 WRITEL(p->rc_bitrate,
663 S5P_FIMV_E_RC_BIT_RATE_V6);
664 else
665 WRITEL(1, S5P_FIMV_E_RC_BIT_RATE_V6);
666
667 /* reaction coefficient */
668 if (p->rc_frame) {
669 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
670 WRITEL(1, S5P_FIMV_E_RC_RPARAM_V6);
671 else /* loose CBR */
672 WRITEL(2, S5P_FIMV_E_RC_RPARAM_V6);
673 }
674
675 /* seq header ctrl */
676 reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6);
677 reg &= ~(0x1 << 2);
678 reg |= ((p->seq_hdr_mode & 0x1) << 2);
679
680 /* frame skip mode */
681 reg &= ~(0x3);
682 reg |= (p->frame_skip_mode & 0x3);
683 WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6);
684
685 /* 'DROP_CONTROL_ENABLE', disable */
686 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
687 reg &= ~(0x1 << 10);
688 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
689
690 /* setting for MV range [16, 256] */
691 reg = 0;
692 reg &= ~(0x3FFF);
693 reg = 256;
694 WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6);
695
696 reg = 0;
697 reg &= ~(0x3FFF);
698 reg = 256;
699 WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6);
700
701 WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6);
702 WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
703 WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE_V6);
704 WRITEL(0x0, S5P_FIMV_E_RC_ROI_CTRL_V6);
705 WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG_V6);
706
707 WRITEL(0x0, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
708 WRITEL(0x0, S5P_FIMV_E_MAX_BIT_COUNT_V6);
709 WRITEL(0x0, S5P_FIMV_E_MIN_BIT_COUNT_V6);
710
711 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
712 WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
713
714 mfc_debug_leave();
715
716 return 0;
717}
718
719static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
720{
721 struct s5p_mfc_dev *dev = ctx->dev;
722 struct s5p_mfc_enc_params *p = &ctx->enc_params;
723 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
724 unsigned int reg = 0;
725 int i;
726
727 mfc_debug_enter();
728
729 s5p_mfc_set_enc_params(ctx);
730
731 /* pictype : number of B */
732 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
733 reg &= ~(0x3 << 16);
734 reg |= ((p->num_b_frame & 0x3) << 16);
735 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
736
737 /* profile & level */
738 reg = 0;
739 /** level */
740 reg |= ((p_h264->level & 0xFF) << 8);
741 /** profile - 0 ~ 3 */
742 reg |= p_h264->profile & 0x3F;
743 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
744
745 /* rate control config. */
746 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
747 /** macroblock level rate control */
748 reg &= ~(0x1 << 8);
749 reg |= ((p->rc_mb & 0x1) << 8);
750 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
751 /** frame QP */
752 reg &= ~(0x3F);
753 reg |= p_h264->rc_frame_qp & 0x3F;
754 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
755
756 /* max & min value of QP */
757 reg = 0;
758 /** max QP */
759 reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
760 /** min QP */
761 reg |= p_h264->rc_min_qp & 0x3F;
762 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
763
764 /* other QPs */
765 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
766 if (!p->rc_frame && !p->rc_mb) {
767 reg = 0;
768 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
769 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
770 reg |= p_h264->rc_frame_qp & 0x3F;
771 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
772 }
773
774 /* frame rate */
775 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
776 reg = 0;
777 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
778 reg |= p->rc_framerate_denom & 0xFFFF;
779 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
780 }
781
782 /* vbv buffer size */
783 if (p->frame_skip_mode ==
784 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
785 WRITEL(p_h264->cpb_size & 0xFFFF,
786 S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
787
788 if (p->rc_frame)
789 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
790 }
791
792 /* interlace */
793 reg = 0;
794 reg |= ((p_h264->interlace & 0x1) << 3);
795 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
796
797 /* height */
798 if (p_h264->interlace) {
799 WRITEL(ctx->img_height >> 1,
800 S5P_FIMV_E_FRAME_HEIGHT_V6); /* 32 align */
801 /* cropped height */
802 WRITEL(ctx->img_height >> 1,
803 S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
804 }
805
806 /* loop filter ctrl */
807 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
808 reg &= ~(0x3 << 1);
809 reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
810 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
811
812 /* loopfilter alpha offset */
813 if (p_h264->loop_filter_alpha < 0) {
814 reg = 0x10;
815 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
816 } else {
817 reg = 0x00;
818 reg |= (p_h264->loop_filter_alpha & 0xF);
819 }
820 WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
821
822 /* loopfilter beta offset */
823 if (p_h264->loop_filter_beta < 0) {
824 reg = 0x10;
825 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
826 } else {
827 reg = 0x00;
828 reg |= (p_h264->loop_filter_beta & 0xF);
829 }
830 WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
831
832 /* entropy coding mode */
833 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
834 reg &= ~(0x1);
835 reg |= p_h264->entropy_mode & 0x1;
836 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
837
838 /* number of ref. picture */
839 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
840 reg &= ~(0x1 << 7);
841 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
842 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
843
844 /* 8x8 transform enable */
845 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
846 reg &= ~(0x3 << 12);
847 reg |= ((p_h264->_8x8_transform & 0x3) << 12);
848 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
849
850 /* macroblock adaptive scaling features */
851 WRITEL(0x0, S5P_FIMV_E_MB_RC_CONFIG_V6);
852 if (p->rc_mb) {
853 reg = 0;
854 /** dark region */
855 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
856 /** smooth region */
857 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
858 /** static region */
859 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
860 /** high activity region */
861 reg |= p_h264->rc_mb_activity & 0x1;
862 WRITEL(reg, S5P_FIMV_E_MB_RC_CONFIG_V6);
863 }
864
865 /* aspect ratio VUI */
866 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
867 reg &= ~(0x1 << 5);
868 reg |= ((p_h264->vui_sar & 0x1) << 5);
869 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
870
871 WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO_V6);
872 WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR_V6);
873 if (p_h264->vui_sar) {
874 /* aspect ration IDC */
875 reg = 0;
876 reg |= p_h264->vui_sar_idc & 0xFF;
877 WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO_V6);
878 if (p_h264->vui_sar_idc == 0xFF) {
879 /* extended SAR */
880 reg = 0;
881 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
882 reg |= p_h264->vui_ext_sar_height & 0xFFFF;
883 WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR_V6);
884 }
885 }
886
887 /* intra picture period for H.264 open GOP */
888 /* control */
889 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
890 reg &= ~(0x1 << 4);
891 reg |= ((p_h264->open_gop & 0x1) << 4);
892 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
893 /* value */
894 WRITEL(0x0, S5P_FIMV_E_H264_I_PERIOD_V6);
895 if (p_h264->open_gop) {
896 reg = 0;
897 reg |= p_h264->open_gop_size & 0xFFFF;
898 WRITEL(reg, S5P_FIMV_E_H264_I_PERIOD_V6);
899 }
900
901 /* 'WEIGHTED_BI_PREDICTION' for B is disable */
902 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
903 reg &= ~(0x3 << 9);
904 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
905
906 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
907 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
908 reg &= ~(0x1 << 14);
909 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
910
911 /* ASO */
912 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
913 reg &= ~(0x1 << 6);
914 reg |= ((p_h264->aso & 0x1) << 6);
915 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
916
917 /* hier qp enable */
918 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
919 reg &= ~(0x1 << 8);
920 reg |= ((p_h264->open_gop & 0x1) << 8);
921 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
922 reg = 0;
923 if (p_h264->hier_qp && p_h264->hier_qp_layer) {
924 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
925 reg |= p_h264->hier_qp_layer & 0x7;
926 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
927 /* QP value for each layer */
928 for (i = 0; i < (p_h264->hier_qp_layer & 0x7); i++)
929 WRITEL(p_h264->hier_qp_layer_qp[i],
930 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 +
931 i * 4);
932 }
933 /* number of coding layer should be zero when hierarchical is disable */
934 WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
935
936 /* frame packing SEI generation */
937 reg = READL(S5P_FIMV_E_H264_OPTIONS_V6);
938 reg &= ~(0x1 << 25);
939 reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
940 WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6);
941 if (p_h264->sei_frame_packing) {
942 reg = 0;
943 /** current frame0 flag */
944 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
945 /** arrangement type */
946 reg |= p_h264->sei_fp_arrangement_type & 0x3;
947 WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
948 }
949
950 if (p_h264->fmo) {
951 switch (p_h264->fmo_map_type) {
952 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
953 if (p_h264->fmo_slice_grp > 4)
954 p_h264->fmo_slice_grp = 4;
955 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
956 WRITEL(p_h264->fmo_run_len[i] - 1,
957 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 +
958 i * 4);
959 break;
960 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
961 if (p_h264->fmo_slice_grp > 4)
962 p_h264->fmo_slice_grp = 4;
963 break;
964 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
965 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
966 if (p_h264->fmo_slice_grp > 2)
967 p_h264->fmo_slice_grp = 2;
968 WRITEL(p_h264->fmo_chg_dir & 0x1,
969 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
970 /* the valid range is 0 ~ number of macroblocks -1 */
971 WRITEL(p_h264->fmo_chg_rate,
972 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
973 break;
974 default:
975 mfc_err("Unsupported map type for FMO: %d\n",
976 p_h264->fmo_map_type);
977 p_h264->fmo_map_type = 0;
978 p_h264->fmo_slice_grp = 1;
979 break;
980 }
981
982 WRITEL(p_h264->fmo_map_type,
983 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
984 WRITEL(p_h264->fmo_slice_grp - 1,
985 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
986 } else {
987 WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
988 }
989
990 mfc_debug_leave();
991
992 return 0;
993}
994
995static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
996{
997 struct s5p_mfc_dev *dev = ctx->dev;
998 struct s5p_mfc_enc_params *p = &ctx->enc_params;
999 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1000 unsigned int reg = 0;
1001
1002 mfc_debug_enter();
1003
1004 s5p_mfc_set_enc_params(ctx);
1005
1006 /* pictype : number of B */
1007 reg = READL(S5P_FIMV_E_GOP_CONFIG_V6);
1008 reg &= ~(0x3 << 16);
1009 reg |= ((p->num_b_frame & 0x3) << 16);
1010 WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6);
1011
1012 /* profile & level */
1013 reg = 0;
1014 /** level */
1015 reg |= ((p_mpeg4->level & 0xFF) << 8);
1016 /** profile - 0 ~ 1 */
1017 reg |= p_mpeg4->profile & 0x3F;
1018 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1019
1020 /* rate control config. */
1021 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1022 /** macroblock level rate control */
1023 reg &= ~(0x1 << 8);
1024 reg |= ((p->rc_mb & 0x1) << 8);
1025 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1026 /** frame QP */
1027 reg &= ~(0x3F);
1028 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1029 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1030
1031 /* max & min value of QP */
1032 reg = 0;
1033 /** max QP */
1034 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1035 /** min QP */
1036 reg |= p_mpeg4->rc_min_qp & 0x3F;
1037 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1038
1039 /* other QPs */
1040 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1041 if (!p->rc_frame && !p->rc_mb) {
1042 reg = 0;
1043 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1044 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1045 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1046 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1047 }
1048
1049 /* frame rate */
1050 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1051 reg = 0;
1052 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1053 reg |= p->rc_framerate_denom & 0xFFFF;
1054 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1055 }
1056
1057 /* vbv buffer size */
1058 if (p->frame_skip_mode ==
1059 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1060 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1061
1062 if (p->rc_frame)
1063 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1064 }
1065
1066 /* Disable HEC */
1067 WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS_V6);
1068 WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
1069
1070 mfc_debug_leave();
1071
1072 return 0;
1073}
1074
1075static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1076{
1077 struct s5p_mfc_dev *dev = ctx->dev;
1078 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1079 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1080 unsigned int reg = 0;
1081
1082 mfc_debug_enter();
1083
1084 s5p_mfc_set_enc_params(ctx);
1085
1086 /* profile & level */
1087 reg = 0;
1088 /** profile */
1089 reg |= (0x1 << 4);
1090 WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6);
1091
1092 /* rate control config. */
1093 reg = READL(S5P_FIMV_E_RC_CONFIG_V6);
1094 /** macroblock level rate control */
1095 reg &= ~(0x1 << 8);
1096 reg |= ((p->rc_mb & 0x1) << 8);
1097 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1098 /** frame QP */
1099 reg &= ~(0x3F);
1100 reg |= p_h263->rc_frame_qp & 0x3F;
1101 WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6);
1102
1103 /* max & min value of QP */
1104 reg = 0;
1105 /** max QP */
1106 reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1107 /** min QP */
1108 reg |= p_h263->rc_min_qp & 0x3F;
1109 WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6);
1110
1111 /* other QPs */
1112 WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1113 if (!p->rc_frame && !p->rc_mb) {
1114 reg = 0;
1115 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1116 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1117 reg |= p_h263->rc_frame_qp & 0x3F;
1118 WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
1119 }
1120
1121 /* frame rate */
1122 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1123 reg = 0;
1124 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1125 reg |= p->rc_framerate_denom & 0xFFFF;
1126 WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6);
1127 }
1128
1129 /* vbv buffer size */
1130 if (p->frame_skip_mode ==
1131 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1132 WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
1133
1134 if (p->rc_frame)
1135 WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
1136 }
1137
1138 mfc_debug_leave();
1139
1140 return 0;
1141}
1142
1143/* Initialize decoding */
b9571a57 1144static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1145{
1146 struct s5p_mfc_dev *dev = ctx->dev;
1147 unsigned int reg = 0;
1148 int fmo_aso_ctrl = 0;
1149
1150 mfc_debug_enter();
1151 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1152 S5P_FIMV_CH_SEQ_HEADER_V6);
1153 mfc_debug(2, "BUFs: %08x %08x %08x\n",
1154 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1155 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6),
1156 READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6));
1157
1158 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1159 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1160
1161 /* When user sets desplay_delay to 0,
1162 * It works as "display_delay enable" and delay set to 0.
1163 * If user wants display_delay disable, It should be
1164 * set to negative value. */
1165 if (ctx->display_delay >= 0) {
1166 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1167 WRITEL(ctx->display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
1168 }
1169 /* Setup loop filter, for decoding this is only valid for MPEG4 */
1170 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1171 mfc_debug(2, "Set loop filter to: %d\n",
1172 ctx->loop_filter_mpeg4);
1173 reg |= (ctx->loop_filter_mpeg4 <<
1174 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1175 }
1176 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1177 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1178
1179 WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6);
1180
1181 /* 0: NV12(CbCr), 1: NV21(CrCb) */
1182 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1183 WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6);
1184 else
1185 WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6);
1186
1187 /* sei parse */
1188 WRITEL(ctx->sei_fp_parse & 0x1, S5P_FIMV_D_SEI_ENABLE_V6);
1189
1190 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1191 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1192 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1193
1194 mfc_debug_leave();
1195 return 0;
1196}
1197
1198static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1199{
1200 struct s5p_mfc_dev *dev = ctx->dev;
8f23cc02
AK		 1201
1202 if (flush) {
1203 dev->curr_ctx = ctx->num;
1204 s5p_mfc_clean_ctx_int_flags(ctx);
1205 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1206 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1207 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1208 }
f96f3cfa
JP		 1209}
1210
1211/* Decode a single frame */
b9571a57 1212static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
f96f3cfa
JP		 1213 enum s5p_mfc_decode_arg last_frame)
1214{
1215 struct s5p_mfc_dev *dev = ctx->dev;
1216
1217 WRITEL(ctx->dec_dst_flag, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
1218 WRITEL(ctx->slice_interface & 0x1, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
1219
1220 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1221 /* Issue different commands to instance basing on whether it
1222 * is the last frame or not. */
1223 switch (last_frame) {
1224 case 0:
1225 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1226 S5P_FIMV_CH_FRAME_START_V6, NULL);
1227 break;
1228 case 1:
1229 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1230 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1231 break;
1232 default:
1233 mfc_err("Unsupported last frame arg.\n");
1234 return -EINVAL;
1235 }
1236
1237 mfc_debug(2, "Decoding a usual frame.\n");
1238 return 0;
1239}
1240
b9571a57 1241static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1242{
1243 struct s5p_mfc_dev *dev = ctx->dev;
1244
1245 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1246 s5p_mfc_set_enc_params_h264(ctx);
1247 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1248 s5p_mfc_set_enc_params_mpeg4(ctx);
1249 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1250 s5p_mfc_set_enc_params_h263(ctx);
1251 else {
1252 mfc_err("Unknown codec for encoding (%x).\n",
1253 ctx->codec_mode);
1254 return -EINVAL;
1255 }
1256
1257 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1258 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1259 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1260
1261 return 0;
1262}
1263
b9571a57 1264static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1265{
1266 struct s5p_mfc_dev *dev = ctx->dev;
1267 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1268 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1269 int i;
1270
1271 if (p_h264->aso) {
1272 for (i = 0; i < 8; i++)
1273 WRITEL(p_h264->aso_slice_order[i],
1274 S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 + i * 4);
1275 }
1276 return 0;
1277}
1278
1279/* Encode a single frame */
b9571a57 1280static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1281{
1282 struct s5p_mfc_dev *dev = ctx->dev;
1283
1284 mfc_debug(2, "++\n");
1285
1286 /* memory structure cur. frame */
1287
1288 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1289 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1290
1291 s5p_mfc_set_slice_mode(ctx);
1292
1293 WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
1294 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1295 S5P_FIMV_CH_FRAME_START_V6, NULL);
1296
1297 mfc_debug(2, "--\n");
1298
1299 return 0;
1300}
1301
1302static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1303{
1304 unsigned long flags;
1305 int new_ctx;
1306 int cnt;
1307
1308 spin_lock_irqsave(&dev->condlock, flags);
1309 mfc_debug(2, "Previos context: %d (bits %08lx)\n", dev->curr_ctx,
1310 dev->ctx_work_bits);
1311 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1312 cnt = 0;
1313 while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1314 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1315 cnt++;
1316 if (cnt > MFC_NUM_CONTEXTS) {
1317 /* No contexts to run */
1318 spin_unlock_irqrestore(&dev->condlock, flags);
1319 return -EAGAIN;
1320 }
1321 }
1322 spin_unlock_irqrestore(&dev->condlock, flags);
1323 return new_ctx;
1324}
1325
1326static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1327{
1328 struct s5p_mfc_dev *dev = ctx->dev;
1329 struct s5p_mfc_buf *temp_vb;
1330 unsigned long flags;
1331
1332 spin_lock_irqsave(&dev->irqlock, flags);
1333
1334 /* Frames are being decoded */
1335 if (list_empty(&ctx->src_queue)) {
1336 mfc_debug(2, "No src buffers.\n");
1337 spin_unlock_irqrestore(&dev->irqlock, flags);
1338 return;
1339 }
1340 /* Get the next source buffer */
1341 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1342 temp_vb->flags |= MFC_BUF_FLAG_USED;
1343 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1344 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0);
1345 spin_unlock_irqrestore(&dev->irqlock, flags);
1346
1347 dev->curr_ctx = ctx->num;
1348 s5p_mfc_clean_ctx_int_flags(ctx);
1349 s5p_mfc_decode_one_frame_v6(ctx, 1);
1350}
1351
1352static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1353{
1354 struct s5p_mfc_dev *dev = ctx->dev;
1355 struct s5p_mfc_buf *temp_vb;
1356 unsigned long flags;
1357 int last_frame = 0;
f96f3cfa 1358
a34026e7
KD		 1359 if (ctx->state == MFCINST_FINISHING) {
1360 last_frame = MFC_DEC_LAST_FRAME;
1361 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1362 dev->curr_ctx = ctx->num;
1363 s5p_mfc_clean_ctx_int_flags(ctx);
1364 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1365 return 0;
1366 }
f96f3cfa 1367
a34026e7 1368 spin_lock_irqsave(&dev->irqlock, flags);
f96f3cfa
JP		 1369 /* Frames are being decoded */
1370 if (list_empty(&ctx->src_queue)) {
1371 mfc_debug(2, "No src buffers.\n");
1372 spin_unlock_irqrestore(&dev->irqlock, flags);
1373 return -EAGAIN;
1374 }
1375 /* Get the next source buffer */
1376 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1377 temp_vb->flags |= MFC_BUF_FLAG_USED;
1378 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1379 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1380 ctx->consumed_stream,
1381 temp_vb->b->v4l2_planes[0].bytesused);
1382 spin_unlock_irqrestore(&dev->irqlock, flags);
1383
f96f3cfa
JP		 1384 dev->curr_ctx = ctx->num;
1385 s5p_mfc_clean_ctx_int_flags(ctx);
1386 if (temp_vb->b->v4l2_planes[0].bytesused == 0) {
1387 last_frame = 1;
1388 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1389 ctx->state = MFCINST_FINISHING;
1390 }
1391 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1392
1393 return 0;
1394}
1395
1396static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1397{
1398 struct s5p_mfc_dev *dev = ctx->dev;
1399 unsigned long flags;
1400 struct s5p_mfc_buf *dst_mb;
1401 struct s5p_mfc_buf *src_mb;
1402 unsigned long src_y_addr, src_c_addr, dst_addr;
1403 /*
1404 unsigned int src_y_size, src_c_size;
1405 */
1406 unsigned int dst_size;
f96f3cfa
JP		 1407
1408 spin_lock_irqsave(&dev->irqlock, flags);
1409
1410 if (list_empty(&ctx->src_queue)) {
1411 mfc_debug(2, "no src buffers.\n");
1412 spin_unlock_irqrestore(&dev->irqlock, flags);
1413 return -EAGAIN;
1414 }
1415
1416 if (list_empty(&ctx->dst_queue)) {
1417 mfc_debug(2, "no dst buffers.\n");
1418 spin_unlock_irqrestore(&dev->irqlock, flags);
1419 return -EAGAIN;
1420 }
1421
1422 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1423 src_mb->flags |= MFC_BUF_FLAG_USED;
1424 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
1425 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
1426
4130eabc
AH		 1427 mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1428 mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
f96f3cfa
JP		 1429
1430 s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1431
1432 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1433 dst_mb->flags |= MFC_BUF_FLAG_USED;
1434 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1435 dst_size = vb2_plane_size(dst_mb->b, 0);
1436
1437 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1438
1439 spin_unlock_irqrestore(&dev->irqlock, flags);
1440
f96f3cfa
JP		 1441 dev->curr_ctx = ctx->num;
1442 s5p_mfc_clean_ctx_int_flags(ctx);
1443 s5p_mfc_encode_one_frame_v6(ctx);
1444
1445 return 0;
1446}
1447
1448static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1449{
1450 struct s5p_mfc_dev *dev = ctx->dev;
1451 unsigned long flags;
1452 struct s5p_mfc_buf *temp_vb;
1453
1454 /* Initializing decoding - parsing header */
1455 spin_lock_irqsave(&dev->irqlock, flags);
1456 mfc_debug(2, "Preparing to init decoding.\n");
1457 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1458 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1459 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1460 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0,
1461 temp_vb->b->v4l2_planes[0].bytesused);
1462 spin_unlock_irqrestore(&dev->irqlock, flags);
1463 dev->curr_ctx = ctx->num;
1464 s5p_mfc_clean_ctx_int_flags(ctx);
1465 s5p_mfc_init_decode_v6(ctx);
1466}
1467
1468static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1469{
1470 struct s5p_mfc_dev *dev = ctx->dev;
1471 unsigned long flags;
1472 struct s5p_mfc_buf *dst_mb;
1473 unsigned long dst_addr;
1474 unsigned int dst_size;
1475
1476 spin_lock_irqsave(&dev->irqlock, flags);
1477
1478 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1479 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1480 dst_size = vb2_plane_size(dst_mb->b, 0);
1481 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1482 spin_unlock_irqrestore(&dev->irqlock, flags);
1483 dev->curr_ctx = ctx->num;
1484 s5p_mfc_clean_ctx_int_flags(ctx);
1485 s5p_mfc_init_encode_v6(ctx);
1486}
1487
1488static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1489{
1490 struct s5p_mfc_dev *dev = ctx->dev;
1491 int ret;
1492 /* Header was parsed now start processing
1493 * First set the output frame buffers
1494 * s5p_mfc_alloc_dec_buffers(ctx); */
1495
1496 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1497 mfc_err("It seems that not all destionation buffers were\n"
1498 "mmaped.MFC requires that all destination are mmaped\n"
1499 "before starting processing.\n");
1500 return -EAGAIN;
1501 }
1502
1503 dev->curr_ctx = ctx->num;
1504 s5p_mfc_clean_ctx_int_flags(ctx);
1505 ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1506 if (ret) {
1507 mfc_err("Failed to alloc frame mem.\n");
1508 ctx->state = MFCINST_ERROR;
1509 }
1510 return ret;
1511}
1512
1513static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1514{
1515 struct s5p_mfc_dev *dev = ctx->dev;
1516 int ret;
1517
f96f3cfa
JP		 1518 dev->curr_ctx = ctx->num;
1519 s5p_mfc_clean_ctx_int_flags(ctx);
1520 ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1521 if (ret) {
1522 mfc_err("Failed to alloc frame mem.\n");
1523 ctx->state = MFCINST_ERROR;
1524 }
1525 return ret;
1526}
1527
1528/* Try running an operation on hardware */
b9571a57 1529static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1530{
1531 struct s5p_mfc_ctx *ctx;
1532 int new_ctx;
1533 unsigned int ret = 0;
1534
1535 mfc_debug(1, "Try run dev: %p\n", dev);
1536
1537 /* Check whether hardware is not running */
1538 if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1539 /* This is perfectly ok, the scheduled ctx should wait */
1540 mfc_debug(1, "Couldn't lock HW.\n");
1541 return;
1542 }
1543
1544 /* Choose the context to run */
1545 new_ctx = s5p_mfc_get_new_ctx(dev);
1546 if (new_ctx < 0) {
1547 /* No contexts to run */
1548 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1549 mfc_err("Failed to unlock hardware.\n");
1550 return;
1551 }
1552
1553 mfc_debug(1, "No ctx is scheduled to be run.\n");
1554 return;
1555 }
1556
1557 mfc_debug(1, "New context: %d\n", new_ctx);
1558 ctx = dev->ctx[new_ctx];
1559 mfc_debug(1, "Seting new context to %p\n", ctx);
1560 /* Got context to run in ctx */
1561 mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
e9d98ddc 1562 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
f96f3cfa
JP		 1563 mfc_debug(1, "ctx->state=%d\n", ctx->state);
1564 /* Last frame has already been sent to MFC
1565 * Now obtaining frames from MFC buffer */
1566
1567 s5p_mfc_clock_on();
1568 if (ctx->type == MFCINST_DECODER) {
1569 switch (ctx->state) {
1570 case MFCINST_FINISHING:
1571 s5p_mfc_run_dec_last_frames(ctx);
1572 break;
1573 case MFCINST_RUNNING:
1574 ret = s5p_mfc_run_dec_frame(ctx);
1575 break;
1576 case MFCINST_INIT:
1577 s5p_mfc_clean_ctx_int_flags(ctx);
1578 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1579 ctx);
1580 break;
1581 case MFCINST_RETURN_INST:
1582 s5p_mfc_clean_ctx_int_flags(ctx);
1583 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1584 ctx);
1585 break;
1586 case MFCINST_GOT_INST:
1587 s5p_mfc_run_init_dec(ctx);
1588 break;
1589 case MFCINST_HEAD_PARSED:
1590 ret = s5p_mfc_run_init_dec_buffers(ctx);
1591 break;
8f23cc02
AK		 1592 case MFCINST_FLUSH:
1593 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1594 break;
f96f3cfa
JP		 1595 case MFCINST_RES_CHANGE_INIT:
1596 s5p_mfc_run_dec_last_frames(ctx);
1597 break;
1598 case MFCINST_RES_CHANGE_FLUSH:
1599 s5p_mfc_run_dec_last_frames(ctx);
1600 break;
1601 case MFCINST_RES_CHANGE_END:
1602 mfc_debug(2, "Finished remaining frames after resolution change.\n");
1603 ctx->capture_state = QUEUE_FREE;
1604 mfc_debug(2, "Will re-init the codec`.\n");
1605 s5p_mfc_run_init_dec(ctx);
1606 break;
1607 default:
1608 ret = -EAGAIN;
1609 }
1610 } else if (ctx->type == MFCINST_ENCODER) {
1611 switch (ctx->state) {
1612 case MFCINST_FINISHING:
1613 case MFCINST_RUNNING:
1614 ret = s5p_mfc_run_enc_frame(ctx);
1615 break;
1616 case MFCINST_INIT:
1617 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1618 ctx);
1619 break;
1620 case MFCINST_RETURN_INST:
1621 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1622 ctx);
1623 break;
1624 case MFCINST_GOT_INST:
1625 s5p_mfc_run_init_enc(ctx);
1626 break;
e9d98ddc 1627 case MFCINST_HEAD_PRODUCED:
f96f3cfa
JP		 1628 ret = s5p_mfc_run_init_enc_buffers(ctx);
1629 break;
1630 default:
1631 ret = -EAGAIN;
1632 }
1633 } else {
1634 mfc_err("invalid context type: %d\n", ctx->type);
1635 ret = -EAGAIN;
1636 }
1637
1638 if (ret) {
1639 /* Free hardware lock */
1640 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1641 mfc_err("Failed to unlock hardware.\n");
1642
1643 /* This is in deed imporant, as no operation has been
1644 * scheduled, reduce the clock count as no one will
1645 * ever do this, because no interrupt related to this try_run
1646 * will ever come from hardware. */
1647 s5p_mfc_clock_off();
1648 }
1649}
1650
1651
b9571a57 1652static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
f96f3cfa
JP		 1653{
1654 struct s5p_mfc_buf *b;
1655 int i;
1656
1657 while (!list_empty(lh)) {
1658 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1659 for (i = 0; i < b->b->num_planes; i++)
1660 vb2_set_plane_payload(b->b, i, 0);
1661 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR);
1662 list_del(&b->list);
1663 }
1664}
1665
b9571a57 1666static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1667{
1668 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
1669 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_INT_V6);
1670}
1671
b9571a57 1672static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
f96f3cfa
JP		 1673 unsigned int ofs)
1674{
1675 struct s5p_mfc_dev *dev = ctx->dev;
1676
1677 s5p_mfc_clock_on();
1678 WRITEL(data, ofs);
1679 s5p_mfc_clock_off();
1680}
1681
b9571a57
SK		 1682static unsigned int
1683s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
f96f3cfa
JP		 1684{
1685 struct s5p_mfc_dev *dev = ctx->dev;
1686 int ret;
1687
1688 s5p_mfc_clock_on();
1689 ret = READL(ofs);
1690 s5p_mfc_clock_off();
1691
1692 return ret;
1693}
1694
b9571a57 1695static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1696{
1697 return mfc_read(dev, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
1698}
1699
b9571a57 1700static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
f96f3cfa 1701{
d9acbe1a 1702 return mfc_read(dev, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
f96f3cfa
JP		 1703}
1704
b9571a57 1705static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1706{
1707 return mfc_read(dev, S5P_FIMV_D_DISPLAY_STATUS_V6);
1708}
1709
644469ae 1710static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1711{
1712 return mfc_read(dev, S5P_FIMV_D_DECODED_STATUS_V6);
1713}
1714
b9571a57 1715static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1716{
1717 return mfc_read(dev, S5P_FIMV_D_DECODED_FRAME_TYPE_V6) &
1718 S5P_FIMV_DECODE_FRAME_MASK_V6;
1719}
1720
b9571a57 1721static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1722{
1723 return mfc_read(ctx->dev, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6) &
1724 S5P_FIMV_DECODE_FRAME_MASK_V6;
1725}
1726
b9571a57 1727static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1728{
1729 return mfc_read(dev, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
1730}
1731
b9571a57 1732static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1733{
1734 return mfc_read(dev, S5P_FIMV_RISC2HOST_CMD_V6) &
1735 S5P_FIMV_RISC2HOST_CMD_MASK;
1736}
1737
b9571a57 1738static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1739{
1740 return mfc_read(dev, S5P_FIMV_ERROR_CODE_V6);
1741}
1742
b9571a57 1743static int s5p_mfc_err_dec_v6(unsigned int err)
f96f3cfa
JP		 1744{
1745 return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
1746}
1747
b9571a57 1748static int s5p_mfc_err_dspl_v6(unsigned int err)
f96f3cfa
JP		 1749{
1750 return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6;
1751}
1752
b9571a57 1753static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1754{
1755 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
1756}
1757
b9571a57 1758static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1759{
1760 return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
1761}
1762
b9571a57 1763static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1764{
1765 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_DPB_V6);
1766}
1767
b9571a57 1768static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1769{
1770 return mfc_read(dev, S5P_FIMV_D_MIN_NUM_MV_V6);
1771}
1772
b9571a57 1773static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1774{
1775 return mfc_read(dev, S5P_FIMV_RET_INSTANCE_ID_V6);
1776}
1777
b9571a57 1778static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1779{
1780 return mfc_read(dev, S5P_FIMV_E_NUM_DPB_V6);
1781}
1782
b9571a57 1783static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1784{
1785 return mfc_read(dev, S5P_FIMV_E_STREAM_SIZE_V6);
1786}
1787
b9571a57 1788static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1789{
1790 return mfc_read(dev, S5P_FIMV_E_SLICE_TYPE_V6);
1791}
1792
b9571a57 1793static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1794{
1795 return mfc_read(dev, S5P_FIMV_E_PICTURE_COUNT_V6);
1796}
1797
b9571a57 1798static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1799{
1800 return mfc_read(ctx->dev, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
1801}
1802
b9571a57 1803static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1804{
1805 return mfc_read(dev, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
1806}
1807
b9571a57 1808static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
f96f3cfa
JP		 1809{
1810 return mfc_read(dev, S5P_FIMV_D_MVC_VIEW_ID_V6);
1811}
1812
b9571a57 1813static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1814{
1815 return s5p_mfc_read_info_v6(ctx, PIC_TIME_TOP_V6);
1816}
1817
b9571a57 1818static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1819{
1820 return s5p_mfc_read_info_v6(ctx, PIC_TIME_BOT_V6);
1821}
1822
b9571a57 1823static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1824{
1825 return s5p_mfc_read_info_v6(ctx, CROP_INFO_H_V6);
1826}
1827
b9571a57 1828static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
f96f3cfa
JP		 1829{
1830 return s5p_mfc_read_info_v6(ctx, CROP_INFO_V_V6);
1831}
1832
1833/* Initialize opr function pointers for MFC v6 */
1834static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
1835 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
1836 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
1837 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
1838 .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
1839 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
1840 .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
1841 .alloc_dev_context_buffer =
1842 s5p_mfc_alloc_dev_context_buffer_v6,
1843 .release_dev_context_buffer =
1844 s5p_mfc_release_dev_context_buffer_v6,
1845 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
1846 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
1847 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6,
1848 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6,
1849 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
1850 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
1851 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
1852 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6,
1853 .init_decode = s5p_mfc_init_decode_v6,
1854 .init_encode = s5p_mfc_init_encode_v6,
1855 .encode_one_frame = s5p_mfc_encode_one_frame_v6,
1856 .try_run = s5p_mfc_try_run_v6,
1857 .cleanup_queue = s5p_mfc_cleanup_queue_v6,
1858 .clear_int_flags = s5p_mfc_clear_int_flags_v6,
1859 .write_info = s5p_mfc_write_info_v6,
1860 .read_info = s5p_mfc_read_info_v6,
1861 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
1862 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
1863 .get_dspl_status = s5p_mfc_get_dspl_status_v6,
1864 .get_dec_status = s5p_mfc_get_dec_status_v6,
1865 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
1866 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
1867 .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
1868 .get_int_reason = s5p_mfc_get_int_reason_v6,
1869 .get_int_err = s5p_mfc_get_int_err_v6,
1870 .err_dec = s5p_mfc_err_dec_v6,
1871 .err_dspl = s5p_mfc_err_dspl_v6,
1872 .get_img_width = s5p_mfc_get_img_width_v6,
1873 .get_img_height = s5p_mfc_get_img_height_v6,
1874 .get_dpb_count = s5p_mfc_get_dpb_count_v6,
1875 .get_mv_count = s5p_mfc_get_mv_count_v6,
1876 .get_inst_no = s5p_mfc_get_inst_no_v6,
1877 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
1878 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
1879 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
1880 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6,
1881 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6,
1882 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6,
1883 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6,
1884 .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
1885 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
1886 .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
1887 .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
1888};
1889
1890struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
1891{
1892 return &s5p_mfc_ops_v6;
1893}
Linux 6.x block layer and io_uring tree(s)