Commit | Line | Data |
---|---|---|
af935746 | 1 | /* |
43a1ea1f | 2 | * drivers/media/platform/samsung/mfc5/s5p_mfc_opr_v5.c |
af935746 KD |
3 | * |
4 | * Samsung MFC (Multi Function Codec - FIMV) driver | |
5 | * This file contains hw related functions. | |
6 | * | |
7 | * Kamil Debski, Copyright (c) 2011 Samsung Electronics | |
8 | * http://www.samsung.com/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
af935746 | 15 | #include "s5p_mfc_common.h" |
43a1ea1f | 16 | #include "s5p_mfc_cmd.h" |
af935746 KD |
17 | #include "s5p_mfc_ctrl.h" |
18 | #include "s5p_mfc_debug.h" | |
19 | #include "s5p_mfc_intr.h" | |
af935746 | 20 | #include "s5p_mfc_pm.h" |
43a1ea1f AK |
21 | #include "s5p_mfc_opr.h" |
22 | #include "s5p_mfc_opr_v5.h" | |
af935746 KD |
23 | #include <asm/cacheflush.h> |
24 | #include <linux/delay.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/firmware.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/jiffies.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/sched.h> | |
32 | ||
33 | #define OFFSETA(x) (((x) - dev->bank1) >> MFC_OFFSET_SHIFT) | |
34 | #define OFFSETB(x) (((x) - dev->bank2) >> MFC_OFFSET_SHIFT) | |
35 | ||
36 | /* Allocate temporary buffers for decoding */ | |
3c75a2e1 | 37 | static int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx) |
af935746 | 38 | { |
af935746 | 39 | struct s5p_mfc_dev *dev = ctx->dev; |
8f532a7f | 40 | struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; |
317b4ca4 | 41 | int ret; |
af935746 | 42 | |
317b4ca4 | 43 | ctx->dsc.size = buf_size->dsc; |
1af21985 | 44 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, &ctx->dsc); |
317b4ca4 KD |
45 | if (ret) { |
46 | mfc_err("Failed to allocate temporary buffer\n"); | |
47 | return ret; | |
af935746 | 48 | } |
317b4ca4 | 49 | |
8f532a7f | 50 | BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); |
317b4ca4 | 51 | memset(ctx->dsc.virt, 0, ctx->dsc.size); |
af935746 KD |
52 | wmb(); |
53 | return 0; | |
54 | } | |
55 | ||
317b4ca4 | 56 | |
af935746 | 57 | /* Release temporary buffers for decoding */ |
3c75a2e1 | 58 | static void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx) |
af935746 | 59 | { |
317b4ca4 | 60 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->dsc); |
af935746 KD |
61 | } |
62 | ||
63 | /* Allocate codec buffers */ | |
3c75a2e1 | 64 | static int s5p_mfc_alloc_codec_buffers_v5(struct s5p_mfc_ctx *ctx) |
af935746 KD |
65 | { |
66 | struct s5p_mfc_dev *dev = ctx->dev; | |
67 | unsigned int enc_ref_y_size = 0; | |
68 | unsigned int enc_ref_c_size = 0; | |
69 | unsigned int guard_width, guard_height; | |
317b4ca4 | 70 | int ret; |
af935746 KD |
71 | |
72 | if (ctx->type == MFCINST_DECODER) { | |
73 | mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", | |
74 | ctx->luma_size, ctx->chroma_size, ctx->mv_size); | |
75 | mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); | |
76 | } else if (ctx->type == MFCINST_ENCODER) { | |
77 | enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) | |
78 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); | |
79 | enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); | |
80 | ||
43a1ea1f | 81 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { |
af935746 KD |
82 | enc_ref_c_size = ALIGN(ctx->img_width, |
83 | S5P_FIMV_NV12MT_HALIGN) | |
84 | * ALIGN(ctx->img_height >> 1, | |
85 | S5P_FIMV_NV12MT_VALIGN); | |
86 | enc_ref_c_size = ALIGN(enc_ref_c_size, | |
87 | S5P_FIMV_NV12MT_SALIGN); | |
88 | } else { | |
89 | guard_width = ALIGN(ctx->img_width + 16, | |
90 | S5P_FIMV_NV12MT_HALIGN); | |
91 | guard_height = ALIGN((ctx->img_height >> 1) + 4, | |
92 | S5P_FIMV_NV12MT_VALIGN); | |
93 | enc_ref_c_size = ALIGN(guard_width * guard_height, | |
94 | S5P_FIMV_NV12MT_SALIGN); | |
95 | } | |
96 | mfc_debug(2, "recon luma size: %d chroma size: %d\n", | |
97 | enc_ref_y_size, enc_ref_c_size); | |
98 | } else { | |
99 | return -EINVAL; | |
100 | } | |
101 | /* Codecs have different memory requirements */ | |
102 | switch (ctx->codec_mode) { | |
43a1ea1f | 103 | case S5P_MFC_CODEC_H264_DEC: |
317b4ca4 | 104 | ctx->bank1.size = |
af935746 KD |
105 | ALIGN(S5P_FIMV_DEC_NB_IP_SIZE + |
106 | S5P_FIMV_DEC_VERT_NB_MV_SIZE, | |
107 | S5P_FIMV_DEC_BUF_ALIGN); | |
317b4ca4 | 108 | ctx->bank2.size = ctx->total_dpb_count * ctx->mv_size; |
af935746 | 109 | break; |
43a1ea1f | 110 | case S5P_MFC_CODEC_MPEG4_DEC: |
317b4ca4 | 111 | ctx->bank1.size = |
af935746 KD |
112 | ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE + |
113 | S5P_FIMV_DEC_UPNB_MV_SIZE + | |
114 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + | |
115 | S5P_FIMV_DEC_STX_PARSER_SIZE + | |
116 | S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE, | |
117 | S5P_FIMV_DEC_BUF_ALIGN); | |
317b4ca4 | 118 | ctx->bank2.size = 0; |
af935746 | 119 | break; |
43a1ea1f AK |
120 | case S5P_MFC_CODEC_VC1RCV_DEC: |
121 | case S5P_MFC_CODEC_VC1_DEC: | |
317b4ca4 | 122 | ctx->bank1.size = |
af935746 KD |
123 | ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + |
124 | S5P_FIMV_DEC_UPNB_MV_SIZE + | |
125 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + | |
126 | S5P_FIMV_DEC_NB_DCAC_SIZE + | |
127 | 3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE, | |
128 | S5P_FIMV_DEC_BUF_ALIGN); | |
317b4ca4 | 129 | ctx->bank2.size = 0; |
af935746 | 130 | break; |
43a1ea1f | 131 | case S5P_MFC_CODEC_MPEG2_DEC: |
317b4ca4 KD |
132 | ctx->bank1.size = 0; |
133 | ctx->bank2.size = 0; | |
af935746 | 134 | break; |
43a1ea1f | 135 | case S5P_MFC_CODEC_H263_DEC: |
317b4ca4 | 136 | ctx->bank1.size = |
af935746 KD |
137 | ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + |
138 | S5P_FIMV_DEC_UPNB_MV_SIZE + | |
139 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + | |
140 | S5P_FIMV_DEC_NB_DCAC_SIZE, | |
141 | S5P_FIMV_DEC_BUF_ALIGN); | |
317b4ca4 | 142 | ctx->bank2.size = 0; |
af935746 | 143 | break; |
43a1ea1f | 144 | case S5P_MFC_CODEC_H264_ENC: |
317b4ca4 | 145 | ctx->bank1.size = (enc_ref_y_size * 2) + |
af935746 KD |
146 | S5P_FIMV_ENC_UPMV_SIZE + |
147 | S5P_FIMV_ENC_COLFLG_SIZE + | |
148 | S5P_FIMV_ENC_INTRAMD_SIZE + | |
149 | S5P_FIMV_ENC_NBORINFO_SIZE; | |
317b4ca4 | 150 | ctx->bank2.size = (enc_ref_y_size * 2) + |
af935746 KD |
151 | (enc_ref_c_size * 4) + |
152 | S5P_FIMV_ENC_INTRAPRED_SIZE; | |
153 | break; | |
43a1ea1f | 154 | case S5P_MFC_CODEC_MPEG4_ENC: |
317b4ca4 | 155 | ctx->bank1.size = (enc_ref_y_size * 2) + |
af935746 KD |
156 | S5P_FIMV_ENC_UPMV_SIZE + |
157 | S5P_FIMV_ENC_COLFLG_SIZE + | |
158 | S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
317b4ca4 | 159 | ctx->bank2.size = (enc_ref_y_size * 2) + |
af935746 KD |
160 | (enc_ref_c_size * 4); |
161 | break; | |
43a1ea1f | 162 | case S5P_MFC_CODEC_H263_ENC: |
317b4ca4 | 163 | ctx->bank1.size = (enc_ref_y_size * 2) + |
af935746 KD |
164 | S5P_FIMV_ENC_UPMV_SIZE + |
165 | S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
317b4ca4 | 166 | ctx->bank2.size = (enc_ref_y_size * 2) + |
af935746 KD |
167 | (enc_ref_c_size * 4); |
168 | break; | |
169 | default: | |
170 | break; | |
171 | } | |
172 | /* Allocate only if memory from bank 1 is necessary */ | |
317b4ca4 KD |
173 | if (ctx->bank1.size > 0) { |
174 | ||
1af21985 MS |
175 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, |
176 | &ctx->bank1); | |
317b4ca4 KD |
177 | if (ret) { |
178 | mfc_err("Failed to allocate Bank1 temporary buffer\n"); | |
179 | return ret; | |
af935746 | 180 | } |
317b4ca4 | 181 | BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); |
af935746 KD |
182 | } |
183 | /* Allocate only if memory from bank 2 is necessary */ | |
317b4ca4 | 184 | if (ctx->bank2.size > 0) { |
1af21985 MS |
185 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_r, dev->bank2, |
186 | &ctx->bank2); | |
317b4ca4 KD |
187 | if (ret) { |
188 | mfc_err("Failed to allocate Bank2 temporary buffer\n"); | |
69148bcd | 189 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); |
317b4ca4 | 190 | return ret; |
af935746 | 191 | } |
317b4ca4 | 192 | BUG_ON(ctx->bank2.dma & ((1 << MFC_BANK2_ALIGN_ORDER) - 1)); |
af935746 KD |
193 | } |
194 | return 0; | |
195 | } | |
196 | ||
197 | /* Release buffers allocated for codec */ | |
3c75a2e1 | 198 | static void s5p_mfc_release_codec_buffers_v5(struct s5p_mfc_ctx *ctx) |
af935746 | 199 | { |
317b4ca4 KD |
200 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); |
201 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_r, &ctx->bank2); | |
af935746 KD |
202 | } |
203 | ||
204 | /* Allocate memory for instance data buffer */ | |
3c75a2e1 | 205 | static int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx) |
af935746 | 206 | { |
af935746 | 207 | struct s5p_mfc_dev *dev = ctx->dev; |
8f532a7f | 208 | struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; |
317b4ca4 | 209 | int ret; |
af935746 | 210 | |
8f532a7f AK |
211 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || |
212 | ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) | |
213 | ctx->ctx.size = buf_size->h264_ctx; | |
af935746 | 214 | else |
8f532a7f | 215 | ctx->ctx.size = buf_size->non_h264_ctx; |
317b4ca4 | 216 | |
1af21985 | 217 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, &ctx->ctx); |
317b4ca4 KD |
218 | if (ret) { |
219 | mfc_err("Failed to allocate instance buffer\n"); | |
220 | return ret; | |
af935746 | 221 | } |
8f532a7f | 222 | ctx->ctx.ofs = OFFSETA(ctx->ctx.dma); |
317b4ca4 | 223 | |
af935746 | 224 | /* Zero content of the allocated memory */ |
8f532a7f | 225 | memset(ctx->ctx.virt, 0, ctx->ctx.size); |
af935746 | 226 | wmb(); |
77a788fc AK |
227 | |
228 | /* Initialize shared memory */ | |
317b4ca4 | 229 | ctx->shm.size = buf_size->shm; |
1af21985 | 230 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, &ctx->shm); |
317b4ca4 KD |
231 | if (ret) { |
232 | mfc_err("Failed to allocate shared memory buffer\n"); | |
6c5c680b | 233 | s5p_mfc_release_priv_buf(dev->mem_dev_l, &ctx->ctx); |
317b4ca4 | 234 | return ret; |
77a788fc | 235 | } |
317b4ca4 | 236 | |
77a788fc | 237 | /* shared memory offset only keeps the offset from base (port a) */ |
317b4ca4 | 238 | ctx->shm.ofs = ctx->shm.dma - dev->bank1; |
8f532a7f | 239 | BUG_ON(ctx->shm.ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); |
77a788fc | 240 | |
317b4ca4 | 241 | memset(ctx->shm.virt, 0, buf_size->shm); |
77a788fc | 242 | wmb(); |
af935746 KD |
243 | return 0; |
244 | } | |
245 | ||
246 | /* Release instance buffer */ | |
3c75a2e1 | 247 | static void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx) |
af935746 | 248 | { |
317b4ca4 KD |
249 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx); |
250 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->shm); | |
af935746 KD |
251 | } |
252 | ||
3c75a2e1 | 253 | static int s5p_mfc_alloc_dev_context_buffer_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
254 | { |
255 | /* NOP */ | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
3c75a2e1 | 260 | static void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
261 | { |
262 | /* NOP */ | |
263 | } | |
264 | ||
265 | static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data, | |
77a788fc AK |
266 | unsigned int ofs) |
267 | { | |
1d03deff | 268 | *(u32 *)(ctx->shm.virt + ofs) = data; |
77a788fc AK |
269 | wmb(); |
270 | } | |
271 | ||
43a1ea1f | 272 | static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx, |
6c9fe765 | 273 | unsigned long ofs) |
77a788fc AK |
274 | { |
275 | rmb(); | |
1d03deff | 276 | return *(u32 *)(ctx->shm.virt + ofs); |
77a788fc AK |
277 | } |
278 | ||
3c75a2e1 | 279 | static void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f | 280 | { |
8f532a7f AK |
281 | unsigned int guard_width, guard_height; |
282 | ||
283 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); | |
284 | ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); | |
285 | mfc_debug(2, | |
286 | "SEQ Done: Movie dimensions %dx%d, buffer dimensions: %dx%d\n", | |
287 | ctx->img_width, ctx->img_height, ctx->buf_width, | |
288 | ctx->buf_height); | |
289 | ||
290 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { | |
291 | ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height, | |
292 | S5P_FIMV_DEC_BUF_ALIGN); | |
293 | ctx->chroma_size = ALIGN(ctx->buf_width * | |
294 | ALIGN((ctx->img_height >> 1), | |
295 | S5P_FIMV_NV12MT_VALIGN), | |
296 | S5P_FIMV_DEC_BUF_ALIGN); | |
297 | ctx->mv_size = ALIGN(ctx->buf_width * | |
298 | ALIGN((ctx->buf_height >> 2), | |
299 | S5P_FIMV_NV12MT_VALIGN), | |
300 | S5P_FIMV_DEC_BUF_ALIGN); | |
301 | } else { | |
302 | guard_width = | |
303 | ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN); | |
304 | guard_height = | |
305 | ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN); | |
306 | ctx->luma_size = ALIGN(guard_width * guard_height, | |
307 | S5P_FIMV_DEC_BUF_ALIGN); | |
308 | ||
309 | guard_width = | |
310 | ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN); | |
311 | guard_height = | |
312 | ALIGN((ctx->img_height >> 1) + 4, | |
313 | S5P_FIMV_NV12MT_VALIGN); | |
314 | ctx->chroma_size = ALIGN(guard_width * guard_height, | |
315 | S5P_FIMV_DEC_BUF_ALIGN); | |
316 | ||
317 | ctx->mv_size = 0; | |
318 | } | |
43a1ea1f AK |
319 | } |
320 | ||
3c75a2e1 | 321 | static void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f | 322 | { |
8f532a7f AK |
323 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { |
324 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN); | |
325 | ||
326 | ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) | |
327 | * ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN); | |
328 | ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) | |
329 | * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN); | |
330 | ||
331 | ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN); | |
332 | ctx->chroma_size = | |
333 | ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN); | |
334 | } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) { | |
335 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); | |
336 | ||
337 | ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) | |
338 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); | |
339 | ctx->chroma_size = | |
340 | ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) | |
341 | * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); | |
342 | ||
343 | ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN); | |
344 | ctx->chroma_size = | |
345 | ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN); | |
346 | } | |
43a1ea1f AK |
347 | } |
348 | ||
af935746 | 349 | /* Set registers for decoding temporary buffers */ |
43a1ea1f | 350 | static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx) |
af935746 KD |
351 | { |
352 | struct s5p_mfc_dev *dev = ctx->dev; | |
8f532a7f | 353 | struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; |
af935746 | 354 | |
8f532a7f AK |
355 | mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); |
356 | mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); | |
af935746 KD |
357 | } |
358 | ||
359 | /* Set registers for shared buffer */ | |
a13bba4f | 360 | static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx) |
af935746 KD |
361 | { |
362 | struct s5p_mfc_dev *dev = ctx->dev; | |
8f532a7f | 363 | mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR); |
af935746 KD |
364 | } |
365 | ||
366 | /* Set registers for decoding stream buffer */ | |
3c75a2e1 SK |
367 | static int s5p_mfc_set_dec_stream_buffer_v5(struct s5p_mfc_ctx *ctx, |
368 | int buf_addr, unsigned int start_num_byte, | |
369 | unsigned int buf_size) | |
af935746 KD |
370 | { |
371 | struct s5p_mfc_dev *dev = ctx->dev; | |
372 | ||
373 | mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR); | |
374 | mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE); | |
375 | mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE); | |
77a788fc | 376 | s5p_mfc_write_info_v5(ctx, start_num_byte, START_BYTE_NUM); |
af935746 KD |
377 | return 0; |
378 | } | |
379 | ||
380 | /* Set decoding frame buffer */ | |
3c75a2e1 | 381 | static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx) |
af935746 | 382 | { |
9aee8b80 | 383 | unsigned int frame_size_lu, i; |
af935746 KD |
384 | unsigned int frame_size_ch, frame_size_mv; |
385 | struct s5p_mfc_dev *dev = ctx->dev; | |
386 | unsigned int dpb; | |
387 | size_t buf_addr1, buf_addr2; | |
388 | int buf_size1, buf_size2; | |
389 | ||
317b4ca4 KD |
390 | buf_addr1 = ctx->bank1.dma; |
391 | buf_size1 = ctx->bank1.size; | |
392 | buf_addr2 = ctx->bank2.dma; | |
393 | buf_size2 = ctx->bank2.size; | |
af935746 KD |
394 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & |
395 | ~S5P_FIMV_DPB_COUNT_MASK; | |
396 | mfc_write(dev, ctx->total_dpb_count | dpb, | |
397 | S5P_FIMV_SI_CH0_DPB_CONF_CTRL); | |
398 | s5p_mfc_set_shared_buffer(ctx); | |
399 | switch (ctx->codec_mode) { | |
43a1ea1f | 400 | case S5P_MFC_CODEC_H264_DEC: |
af935746 KD |
401 | mfc_write(dev, OFFSETA(buf_addr1), |
402 | S5P_FIMV_H264_VERT_NB_MV_ADR); | |
403 | buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE; | |
404 | buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE; | |
405 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR); | |
406 | buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE; | |
407 | buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE; | |
408 | break; | |
43a1ea1f | 409 | case S5P_MFC_CODEC_MPEG4_DEC: |
af935746 KD |
410 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR); |
411 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; | |
412 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; | |
413 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR); | |
414 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; | |
415 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; | |
416 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR); | |
417 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
418 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
419 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR); | |
420 | buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE; | |
421 | buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE; | |
422 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR); | |
423 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
424 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
425 | break; | |
43a1ea1f | 426 | case S5P_MFC_CODEC_H263_DEC: |
af935746 KD |
427 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR); |
428 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
429 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
430 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR); | |
431 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; | |
432 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; | |
433 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR); | |
434 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
435 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
436 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR); | |
437 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; | |
438 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; | |
439 | break; | |
43a1ea1f AK |
440 | case S5P_MFC_CODEC_VC1_DEC: |
441 | case S5P_MFC_CODEC_VC1RCV_DEC: | |
af935746 KD |
442 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR); |
443 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; | |
444 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; | |
445 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR); | |
446 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
447 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
448 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR); | |
449 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; | |
450 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; | |
451 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR); | |
452 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
453 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
454 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR); | |
455 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
456 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
457 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR); | |
458 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
459 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
460 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR); | |
461 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
462 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
463 | break; | |
43a1ea1f | 464 | case S5P_MFC_CODEC_MPEG2_DEC: |
af935746 KD |
465 | break; |
466 | default: | |
467 | mfc_err("Unknown codec for decoding (%x)\n", | |
468 | ctx->codec_mode); | |
469 | return -EINVAL; | |
af935746 | 470 | } |
9aee8b80 | 471 | frame_size_lu = ctx->luma_size; |
af935746 KD |
472 | frame_size_ch = ctx->chroma_size; |
473 | frame_size_mv = ctx->mv_size; | |
9aee8b80 | 474 | mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size_lu, frame_size_ch, |
af935746 KD |
475 | frame_size_mv); |
476 | for (i = 0; i < ctx->total_dpb_count; i++) { | |
477 | /* Bank2 */ | |
e13f7d5a | 478 | mfc_debug(2, "Luma %d: %zx\n", i, |
af935746 KD |
479 | ctx->dst_bufs[i].cookie.raw.luma); |
480 | mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma), | |
481 | S5P_FIMV_DEC_LUMA_ADR + i * 4); | |
e13f7d5a | 482 | mfc_debug(2, "\tChroma %d: %zx\n", i, |
af935746 KD |
483 | ctx->dst_bufs[i].cookie.raw.chroma); |
484 | mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma), | |
485 | S5P_FIMV_DEC_CHROMA_ADR + i * 4); | |
43a1ea1f | 486 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { |
e13f7d5a | 487 | mfc_debug(2, "\tBuf2: %zx, size: %d\n", |
af935746 KD |
488 | buf_addr2, buf_size2); |
489 | mfc_write(dev, OFFSETB(buf_addr2), | |
490 | S5P_FIMV_H264_MV_ADR + i * 4); | |
491 | buf_addr2 += frame_size_mv; | |
492 | buf_size2 -= frame_size_mv; | |
493 | } | |
494 | } | |
e13f7d5a | 495 | mfc_debug(2, "Buf1: %zu, buf_size1: %d\n", buf_addr1, buf_size1); |
af935746 KD |
496 | mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n", |
497 | buf_size1, buf_size2, ctx->total_dpb_count); | |
498 | if (buf_size1 < 0 || buf_size2 < 0) { | |
499 | mfc_debug(2, "Not enough memory has been allocated\n"); | |
500 | return -ENOMEM; | |
501 | } | |
9aee8b80 | 502 | s5p_mfc_write_info_v5(ctx, frame_size_lu, ALLOC_LUMA_DPB_SIZE); |
77a788fc | 503 | s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE); |
43a1ea1f | 504 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) |
77a788fc | 505 | s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE); |
af935746 KD |
506 | mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK) |
507 | << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), | |
508 | S5P_FIMV_SI_CH0_INST_ID); | |
509 | return 0; | |
510 | } | |
511 | ||
512 | /* Set registers for encoding stream buffer */ | |
3c75a2e1 | 513 | static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx, |
af935746 KD |
514 | unsigned long addr, unsigned int size) |
515 | { | |
516 | struct s5p_mfc_dev *dev = ctx->dev; | |
517 | ||
518 | mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR); | |
519 | mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE); | |
520 | return 0; | |
521 | } | |
522 | ||
3c75a2e1 | 523 | static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, |
af935746 KD |
524 | unsigned long y_addr, unsigned long c_addr) |
525 | { | |
526 | struct s5p_mfc_dev *dev = ctx->dev; | |
527 | ||
528 | mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR); | |
529 | mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR); | |
530 | } | |
531 | ||
3c75a2e1 | 532 | static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, |
af935746 KD |
533 | unsigned long *y_addr, unsigned long *c_addr) |
534 | { | |
535 | struct s5p_mfc_dev *dev = ctx->dev; | |
536 | ||
537 | *y_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR) | |
538 | << MFC_OFFSET_SHIFT); | |
539 | *c_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR) | |
540 | << MFC_OFFSET_SHIFT); | |
541 | } | |
542 | ||
543 | /* Set encoding ref & codec buffer */ | |
3c75a2e1 | 544 | static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) |
af935746 KD |
545 | { |
546 | struct s5p_mfc_dev *dev = ctx->dev; | |
547 | size_t buf_addr1, buf_addr2; | |
548 | size_t buf_size1, buf_size2; | |
549 | unsigned int enc_ref_y_size, enc_ref_c_size; | |
550 | unsigned int guard_width, guard_height; | |
551 | int i; | |
552 | ||
317b4ca4 KD |
553 | buf_addr1 = ctx->bank1.dma; |
554 | buf_size1 = ctx->bank1.size; | |
555 | buf_addr2 = ctx->bank2.dma; | |
556 | buf_size2 = ctx->bank2.size; | |
af935746 KD |
557 | enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) |
558 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); | |
559 | enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); | |
43a1ea1f | 560 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { |
af935746 KD |
561 | enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) |
562 | * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); | |
563 | enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN); | |
564 | } else { | |
565 | guard_width = ALIGN(ctx->img_width + 16, | |
566 | S5P_FIMV_NV12MT_HALIGN); | |
567 | guard_height = ALIGN((ctx->img_height >> 1) + 4, | |
568 | S5P_FIMV_NV12MT_VALIGN); | |
569 | enc_ref_c_size = ALIGN(guard_width * guard_height, | |
570 | S5P_FIMV_NV12MT_SALIGN); | |
571 | } | |
03ce7816 | 572 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2); |
af935746 | 573 | switch (ctx->codec_mode) { |
43a1ea1f | 574 | case S5P_MFC_CODEC_H264_ENC: |
af935746 KD |
575 | for (i = 0; i < 2; i++) { |
576 | mfc_write(dev, OFFSETA(buf_addr1), | |
577 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); | |
578 | buf_addr1 += enc_ref_y_size; | |
579 | buf_size1 -= enc_ref_y_size; | |
580 | ||
581 | mfc_write(dev, OFFSETB(buf_addr2), | |
582 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); | |
583 | buf_addr2 += enc_ref_y_size; | |
584 | buf_size2 -= enc_ref_y_size; | |
585 | } | |
586 | for (i = 0; i < 4; i++) { | |
587 | mfc_write(dev, OFFSETB(buf_addr2), | |
588 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); | |
589 | buf_addr2 += enc_ref_c_size; | |
590 | buf_size2 -= enc_ref_c_size; | |
591 | } | |
592 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR); | |
593 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; | |
594 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; | |
595 | mfc_write(dev, OFFSETA(buf_addr1), | |
596 | S5P_FIMV_H264_COZERO_FLAG_ADR); | |
597 | buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; | |
598 | buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; | |
599 | mfc_write(dev, OFFSETA(buf_addr1), | |
600 | S5P_FIMV_H264_UP_INTRA_MD_ADR); | |
601 | buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE; | |
602 | buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE; | |
603 | mfc_write(dev, OFFSETB(buf_addr2), | |
604 | S5P_FIMV_H264_UP_INTRA_PRED_ADR); | |
605 | buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE; | |
606 | buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE; | |
607 | mfc_write(dev, OFFSETA(buf_addr1), | |
608 | S5P_FIMV_H264_NBOR_INFO_ADR); | |
609 | buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE; | |
610 | buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE; | |
03ce7816 | 611 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", |
af935746 KD |
612 | buf_size1, buf_size2); |
613 | break; | |
43a1ea1f | 614 | case S5P_MFC_CODEC_MPEG4_ENC: |
af935746 KD |
615 | for (i = 0; i < 2; i++) { |
616 | mfc_write(dev, OFFSETA(buf_addr1), | |
617 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); | |
618 | buf_addr1 += enc_ref_y_size; | |
619 | buf_size1 -= enc_ref_y_size; | |
620 | mfc_write(dev, OFFSETB(buf_addr2), | |
621 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); | |
622 | buf_addr2 += enc_ref_y_size; | |
623 | buf_size2 -= enc_ref_y_size; | |
624 | } | |
625 | for (i = 0; i < 4; i++) { | |
626 | mfc_write(dev, OFFSETB(buf_addr2), | |
627 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); | |
628 | buf_addr2 += enc_ref_c_size; | |
629 | buf_size2 -= enc_ref_c_size; | |
630 | } | |
631 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR); | |
632 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; | |
633 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; | |
634 | mfc_write(dev, OFFSETA(buf_addr1), | |
635 | S5P_FIMV_MPEG4_COZERO_FLAG_ADR); | |
636 | buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; | |
637 | buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; | |
638 | mfc_write(dev, OFFSETA(buf_addr1), | |
639 | S5P_FIMV_MPEG4_ACDC_COEF_ADR); | |
640 | buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
641 | buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
03ce7816 | 642 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", |
af935746 KD |
643 | buf_size1, buf_size2); |
644 | break; | |
43a1ea1f | 645 | case S5P_MFC_CODEC_H263_ENC: |
af935746 KD |
646 | for (i = 0; i < 2; i++) { |
647 | mfc_write(dev, OFFSETA(buf_addr1), | |
648 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); | |
649 | buf_addr1 += enc_ref_y_size; | |
650 | buf_size1 -= enc_ref_y_size; | |
651 | mfc_write(dev, OFFSETB(buf_addr2), | |
652 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); | |
653 | buf_addr2 += enc_ref_y_size; | |
654 | buf_size2 -= enc_ref_y_size; | |
655 | } | |
656 | for (i = 0; i < 4; i++) { | |
657 | mfc_write(dev, OFFSETB(buf_addr2), | |
658 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); | |
659 | buf_addr2 += enc_ref_c_size; | |
660 | buf_size2 -= enc_ref_c_size; | |
661 | } | |
662 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR); | |
663 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; | |
664 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; | |
665 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR); | |
666 | buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
667 | buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
03ce7816 | 668 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", |
af935746 KD |
669 | buf_size1, buf_size2); |
670 | break; | |
671 | default: | |
672 | mfc_err("Unknown codec set for encoding: %d\n", | |
673 | ctx->codec_mode); | |
674 | return -EINVAL; | |
675 | } | |
676 | return 0; | |
677 | } | |
678 | ||
679 | static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) | |
680 | { | |
681 | struct s5p_mfc_dev *dev = ctx->dev; | |
682 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
683 | unsigned int reg; | |
684 | unsigned int shm; | |
685 | ||
686 | /* width */ | |
687 | mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX); | |
688 | /* height */ | |
689 | mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX); | |
690 | /* pictype : enable, IDR period */ | |
691 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
692 | reg |= (1 << 18); | |
693 | reg &= ~(0xFFFF); | |
694 | reg |= p->gop_size; | |
695 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
696 | mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON); | |
697 | /* multi-slice control */ | |
698 | /* multi-slice MB number or bit size */ | |
699 | mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL); | |
700 | if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { | |
701 | mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB); | |
702 | } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { | |
703 | mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT); | |
704 | } else { | |
705 | mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB); | |
706 | mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT); | |
707 | } | |
708 | /* cyclic intra refresh */ | |
709 | mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL); | |
710 | /* memory structure cur. frame */ | |
711 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) | |
712 | mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); | |
713 | else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) | |
714 | mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); | |
715 | /* padding control & value */ | |
716 | reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL); | |
717 | if (p->pad) { | |
718 | /** enable */ | |
719 | reg |= (1 << 31); | |
720 | /** cr value */ | |
721 | reg &= ~(0xFF << 16); | |
722 | reg |= (p->pad_cr << 16); | |
723 | /** cb value */ | |
724 | reg &= ~(0xFF << 8); | |
725 | reg |= (p->pad_cb << 8); | |
726 | /** y value */ | |
727 | reg &= ~(0xFF); | |
728 | reg |= (p->pad_luma); | |
729 | } else { | |
730 | /** disable & all value clear */ | |
731 | reg = 0; | |
732 | } | |
733 | mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL); | |
734 | /* rate control config. */ | |
735 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
736 | /** frame-level rate control */ | |
737 | reg &= ~(0x1 << 9); | |
738 | reg |= (p->rc_frame << 9); | |
739 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
740 | /* bit rate */ | |
741 | if (p->rc_frame) | |
742 | mfc_write(dev, p->rc_bitrate, | |
743 | S5P_FIMV_ENC_RC_BIT_RATE); | |
744 | else | |
745 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE); | |
746 | /* reaction coefficient */ | |
747 | if (p->rc_frame) | |
748 | mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA); | |
77a788fc | 749 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
af935746 KD |
750 | /* seq header ctrl */ |
751 | shm &= ~(0x1 << 3); | |
752 | shm |= (p->seq_hdr_mode << 3); | |
753 | /* frame skip mode */ | |
754 | shm &= ~(0x3 << 1); | |
755 | shm |= (p->frame_skip_mode << 1); | |
77a788fc | 756 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
af935746 | 757 | /* fixed target bit */ |
77a788fc | 758 | s5p_mfc_write_info_v5(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG); |
af935746 KD |
759 | return 0; |
760 | } | |
761 | ||
762 | static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) | |
763 | { | |
764 | struct s5p_mfc_dev *dev = ctx->dev; | |
765 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
766 | struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264; | |
767 | unsigned int reg; | |
768 | unsigned int shm; | |
769 | ||
770 | s5p_mfc_set_enc_params(ctx); | |
771 | /* pictype : number of B */ | |
772 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
773 | /* num_b_frame - 0 ~ 2 */ | |
774 | reg &= ~(0x3 << 16); | |
775 | reg |= (p->num_b_frame << 16); | |
776 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
777 | /* profile & level */ | |
778 | reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); | |
779 | /* level */ | |
780 | reg &= ~(0xFF << 8); | |
781 | reg |= (p_264->level << 8); | |
782 | /* profile - 0 ~ 2 */ | |
783 | reg &= ~(0x3F); | |
784 | reg |= p_264->profile; | |
785 | mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); | |
786 | /* interlace */ | |
8f532a7f | 787 | mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT); |
af935746 | 788 | /* height */ |
8f532a7f | 789 | if (p_264->interlace) |
af935746 KD |
790 | mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX); |
791 | /* loopfilter ctrl */ | |
792 | mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL); | |
793 | /* loopfilter alpha offset */ | |
794 | if (p_264->loop_filter_alpha < 0) { | |
795 | reg = 0x10; | |
796 | reg |= (0xFF - p_264->loop_filter_alpha) + 1; | |
797 | } else { | |
798 | reg = 0x00; | |
799 | reg |= (p_264->loop_filter_alpha & 0xF); | |
800 | } | |
801 | mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF); | |
802 | /* loopfilter beta offset */ | |
803 | if (p_264->loop_filter_beta < 0) { | |
804 | reg = 0x10; | |
805 | reg |= (0xFF - p_264->loop_filter_beta) + 1; | |
806 | } else { | |
807 | reg = 0x00; | |
808 | reg |= (p_264->loop_filter_beta & 0xF); | |
809 | } | |
810 | mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF); | |
811 | /* entropy coding mode */ | |
812 | if (p_264->entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) | |
813 | mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE); | |
814 | else | |
815 | mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE); | |
816 | /* number of ref. picture */ | |
817 | reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF); | |
818 | /* num of ref. pictures of P */ | |
819 | reg &= ~(0x3 << 5); | |
820 | reg |= (p_264->num_ref_pic_4p << 5); | |
821 | /* max number of ref. pictures */ | |
822 | reg &= ~(0x1F); | |
823 | reg |= p_264->max_ref_pic; | |
824 | mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF); | |
825 | /* 8x8 transform enable */ | |
826 | mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG); | |
827 | /* rate control config. */ | |
828 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
829 | /* macroblock level rate control */ | |
830 | reg &= ~(0x1 << 8); | |
8f532a7f | 831 | reg |= (p->rc_mb << 8); |
af935746 KD |
832 | /* frame QP */ |
833 | reg &= ~(0x3F); | |
834 | reg |= p_264->rc_frame_qp; | |
835 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
836 | /* frame rate */ | |
837 | if (p->rc_frame && p->rc_framerate_denom) | |
838 | mfc_write(dev, p->rc_framerate_num * 1000 | |
839 | / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); | |
840 | else | |
841 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); | |
842 | /* max & min value of QP */ | |
843 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); | |
844 | /* max QP */ | |
845 | reg &= ~(0x3F << 8); | |
846 | reg |= (p_264->rc_max_qp << 8); | |
847 | /* min QP */ | |
848 | reg &= ~(0x3F); | |
849 | reg |= p_264->rc_min_qp; | |
850 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); | |
851 | /* macroblock adaptive scaling features */ | |
8f532a7f | 852 | if (p->rc_mb) { |
af935746 KD |
853 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL); |
854 | /* dark region */ | |
855 | reg &= ~(0x1 << 3); | |
856 | reg |= (p_264->rc_mb_dark << 3); | |
857 | /* smooth region */ | |
858 | reg &= ~(0x1 << 2); | |
859 | reg |= (p_264->rc_mb_smooth << 2); | |
860 | /* static region */ | |
861 | reg &= ~(0x1 << 1); | |
862 | reg |= (p_264->rc_mb_static << 1); | |
863 | /* high activity region */ | |
864 | reg &= ~(0x1); | |
865 | reg |= p_264->rc_mb_activity; | |
866 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL); | |
867 | } | |
8f532a7f | 868 | if (!p->rc_frame && !p->rc_mb) { |
77a788fc | 869 | shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); |
af935746 KD |
870 | shm &= ~(0xFFF); |
871 | shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6); | |
872 | shm |= (p_264->rc_p_frame_qp & 0x3F); | |
77a788fc | 873 | s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); |
af935746 KD |
874 | } |
875 | /* extended encoder ctrl */ | |
77a788fc | 876 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
af935746 KD |
877 | /* AR VUI control */ |
878 | shm &= ~(0x1 << 15); | |
879 | shm |= (p_264->vui_sar << 1); | |
77a788fc | 880 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
af935746 KD |
881 | if (p_264->vui_sar) { |
882 | /* aspect ration IDC */ | |
77a788fc | 883 | shm = s5p_mfc_read_info_v5(ctx, SAMPLE_ASPECT_RATIO_IDC); |
af935746 KD |
884 | shm &= ~(0xFF); |
885 | shm |= p_264->vui_sar_idc; | |
77a788fc | 886 | s5p_mfc_write_info_v5(ctx, shm, SAMPLE_ASPECT_RATIO_IDC); |
af935746 KD |
887 | if (p_264->vui_sar_idc == 0xFF) { |
888 | /* sample AR info */ | |
77a788fc | 889 | shm = s5p_mfc_read_info_v5(ctx, EXTENDED_SAR); |
af935746 KD |
890 | shm &= ~(0xFFFFFFFF); |
891 | shm |= p_264->vui_ext_sar_width << 16; | |
892 | shm |= p_264->vui_ext_sar_height; | |
77a788fc | 893 | s5p_mfc_write_info_v5(ctx, shm, EXTENDED_SAR); |
af935746 KD |
894 | } |
895 | } | |
896 | /* intra picture period for H.264 */ | |
77a788fc | 897 | shm = s5p_mfc_read_info_v5(ctx, H264_I_PERIOD); |
af935746 KD |
898 | /* control */ |
899 | shm &= ~(0x1 << 16); | |
900 | shm |= (p_264->open_gop << 16); | |
901 | /* value */ | |
902 | if (p_264->open_gop) { | |
903 | shm &= ~(0xFFFF); | |
904 | shm |= p_264->open_gop_size; | |
905 | } | |
77a788fc | 906 | s5p_mfc_write_info_v5(ctx, shm, H264_I_PERIOD); |
af935746 | 907 | /* extended encoder ctrl */ |
77a788fc | 908 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
af935746 KD |
909 | /* vbv buffer size */ |
910 | if (p->frame_skip_mode == | |
911 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
912 | shm &= ~(0xFFFF << 16); | |
913 | shm |= (p_264->cpb_size << 16); | |
914 | } | |
77a788fc | 915 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
af935746 KD |
916 | return 0; |
917 | } | |
918 | ||
919 | static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) | |
920 | { | |
921 | struct s5p_mfc_dev *dev = ctx->dev; | |
922 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
923 | struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; | |
924 | unsigned int reg; | |
925 | unsigned int shm; | |
926 | unsigned int framerate; | |
927 | ||
928 | s5p_mfc_set_enc_params(ctx); | |
929 | /* pictype : number of B */ | |
930 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
931 | /* num_b_frame - 0 ~ 2 */ | |
932 | reg &= ~(0x3 << 16); | |
933 | reg |= (p->num_b_frame << 16); | |
934 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
935 | /* profile & level */ | |
936 | reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); | |
937 | /* level */ | |
938 | reg &= ~(0xFF << 8); | |
939 | reg |= (p_mpeg4->level << 8); | |
940 | /* profile - 0 ~ 2 */ | |
941 | reg &= ~(0x3F); | |
942 | reg |= p_mpeg4->profile; | |
943 | mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); | |
944 | /* quarter_pixel */ | |
945 | mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL); | |
946 | /* qp */ | |
947 | if (!p->rc_frame) { | |
77a788fc | 948 | shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); |
af935746 KD |
949 | shm &= ~(0xFFF); |
950 | shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6); | |
951 | shm |= (p_mpeg4->rc_p_frame_qp & 0x3F); | |
77a788fc | 952 | s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); |
af935746 KD |
953 | } |
954 | /* frame rate */ | |
955 | if (p->rc_frame) { | |
956 | if (p->rc_framerate_denom > 0) { | |
957 | framerate = p->rc_framerate_num * 1000 / | |
958 | p->rc_framerate_denom; | |
959 | mfc_write(dev, framerate, | |
960 | S5P_FIMV_ENC_RC_FRAME_RATE); | |
77a788fc | 961 | shm = s5p_mfc_read_info_v5(ctx, RC_VOP_TIMING); |
af935746 KD |
962 | shm &= ~(0xFFFFFFFF); |
963 | shm |= (1 << 31); | |
964 | shm |= ((p->rc_framerate_num & 0x7FFF) << 16); | |
965 | shm |= (p->rc_framerate_denom & 0xFFFF); | |
77a788fc | 966 | s5p_mfc_write_info_v5(ctx, shm, RC_VOP_TIMING); |
af935746 KD |
967 | } |
968 | } else { | |
969 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); | |
970 | } | |
971 | /* rate control config. */ | |
972 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
973 | /* frame QP */ | |
974 | reg &= ~(0x3F); | |
975 | reg |= p_mpeg4->rc_frame_qp; | |
976 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
977 | /* max & min value of QP */ | |
978 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); | |
979 | /* max QP */ | |
980 | reg &= ~(0x3F << 8); | |
981 | reg |= (p_mpeg4->rc_max_qp << 8); | |
982 | /* min QP */ | |
983 | reg &= ~(0x3F); | |
984 | reg |= p_mpeg4->rc_min_qp; | |
985 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); | |
986 | /* extended encoder ctrl */ | |
77a788fc | 987 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
af935746 KD |
988 | /* vbv buffer size */ |
989 | if (p->frame_skip_mode == | |
990 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
991 | shm &= ~(0xFFFF << 16); | |
992 | shm |= (p->vbv_size << 16); | |
993 | } | |
77a788fc | 994 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
af935746 KD |
995 | return 0; |
996 | } | |
997 | ||
998 | static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) | |
999 | { | |
1000 | struct s5p_mfc_dev *dev = ctx->dev; | |
1001 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
1002 | struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; | |
1003 | unsigned int reg; | |
1004 | unsigned int shm; | |
1005 | ||
1006 | s5p_mfc_set_enc_params(ctx); | |
1007 | /* qp */ | |
1008 | if (!p->rc_frame) { | |
77a788fc | 1009 | shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); |
af935746 KD |
1010 | shm &= ~(0xFFF); |
1011 | shm |= (p_h263->rc_p_frame_qp & 0x3F); | |
77a788fc | 1012 | s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); |
af935746 KD |
1013 | } |
1014 | /* frame rate */ | |
1015 | if (p->rc_frame && p->rc_framerate_denom) | |
1016 | mfc_write(dev, p->rc_framerate_num * 1000 | |
1017 | / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); | |
1018 | else | |
1019 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); | |
1020 | /* rate control config. */ | |
1021 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
1022 | /* frame QP */ | |
1023 | reg &= ~(0x3F); | |
1024 | reg |= p_h263->rc_frame_qp; | |
1025 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
1026 | /* max & min value of QP */ | |
1027 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); | |
1028 | /* max QP */ | |
1029 | reg &= ~(0x3F << 8); | |
1030 | reg |= (p_h263->rc_max_qp << 8); | |
1031 | /* min QP */ | |
1032 | reg &= ~(0x3F); | |
1033 | reg |= p_h263->rc_min_qp; | |
1034 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); | |
1035 | /* extended encoder ctrl */ | |
77a788fc | 1036 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
af935746 KD |
1037 | /* vbv buffer size */ |
1038 | if (p->frame_skip_mode == | |
1039 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
1040 | shm &= ~(0xFFFF << 16); | |
1041 | shm |= (p->vbv_size << 16); | |
1042 | } | |
77a788fc | 1043 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
af935746 KD |
1044 | return 0; |
1045 | } | |
1046 | ||
1047 | /* Initialize decoding */ | |
3c75a2e1 | 1048 | static int s5p_mfc_init_decode_v5(struct s5p_mfc_ctx *ctx) |
af935746 KD |
1049 | { |
1050 | struct s5p_mfc_dev *dev = ctx->dev; | |
1051 | ||
1052 | s5p_mfc_set_shared_buffer(ctx); | |
1053 | /* Setup loop filter, for decoding this is only valid for MPEG4 */ | |
43a1ea1f | 1054 | if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) |
af935746 KD |
1055 | mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL); |
1056 | else | |
1057 | mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL); | |
1058 | mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) << | |
1059 | S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable << | |
1060 | S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay & | |
1061 | S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT), | |
1062 | S5P_FIMV_SI_CH0_DPB_CONF_CTRL); | |
1063 | mfc_write(dev, | |
1064 | ((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | |
1065 | | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) | |
1070 | { | |
1071 | struct s5p_mfc_dev *dev = ctx->dev; | |
1072 | unsigned int dpb; | |
1073 | ||
1074 | if (flush) | |
1075 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | ( | |
1076 | S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); | |
1077 | else | |
1078 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & | |
1079 | ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); | |
1080 | mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL); | |
1081 | } | |
1082 | ||
1083 | /* Decode a single frame */ | |
3c75a2e1 | 1084 | static int s5p_mfc_decode_one_frame_v5(struct s5p_mfc_ctx *ctx, |
af935746 KD |
1085 | enum s5p_mfc_decode_arg last_frame) |
1086 | { | |
1087 | struct s5p_mfc_dev *dev = ctx->dev; | |
1088 | ||
1089 | mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF); | |
1090 | s5p_mfc_set_shared_buffer(ctx); | |
1091 | s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag); | |
1092 | /* Issue different commands to instance basing on whether it | |
1093 | * is the last frame or not. */ | |
1094 | switch (last_frame) { | |
1095 | case MFC_DEC_FRAME: | |
1096 | mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) << | |
1097 | S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1098 | break; | |
1099 | case MFC_DEC_LAST_FRAME: | |
1100 | mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) << | |
1101 | S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1102 | break; | |
1103 | case MFC_DEC_RES_CHANGE: | |
1104 | mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC & | |
1105 | S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), | |
1106 | S5P_FIMV_SI_CH0_INST_ID); | |
1107 | break; | |
1108 | } | |
1109 | mfc_debug(2, "Decoding a usual frame\n"); | |
1110 | return 0; | |
1111 | } | |
1112 | ||
3c75a2e1 | 1113 | static int s5p_mfc_init_encode_v5(struct s5p_mfc_ctx *ctx) |
af935746 KD |
1114 | { |
1115 | struct s5p_mfc_dev *dev = ctx->dev; | |
1116 | ||
43a1ea1f | 1117 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) |
af935746 | 1118 | s5p_mfc_set_enc_params_h264(ctx); |
43a1ea1f | 1119 | else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC) |
af935746 | 1120 | s5p_mfc_set_enc_params_mpeg4(ctx); |
43a1ea1f | 1121 | else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC) |
af935746 KD |
1122 | s5p_mfc_set_enc_params_h263(ctx); |
1123 | else { | |
1124 | mfc_err("Unknown codec for encoding (%x)\n", | |
1125 | ctx->codec_mode); | |
1126 | return -EINVAL; | |
1127 | } | |
1128 | s5p_mfc_set_shared_buffer(ctx); | |
1129 | mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) | | |
1130 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1131 | return 0; | |
1132 | } | |
1133 | ||
1134 | /* Encode a single frame */ | |
3c75a2e1 | 1135 | static int s5p_mfc_encode_one_frame_v5(struct s5p_mfc_ctx *ctx) |
af935746 KD |
1136 | { |
1137 | struct s5p_mfc_dev *dev = ctx->dev; | |
f9f715a9 | 1138 | int cmd; |
af935746 KD |
1139 | /* memory structure cur. frame */ |
1140 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) | |
1141 | mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); | |
1142 | else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) | |
1143 | mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); | |
1144 | s5p_mfc_set_shared_buffer(ctx); | |
f9f715a9 AH |
1145 | |
1146 | if (ctx->state == MFCINST_FINISHING) | |
1147 | cmd = S5P_FIMV_CH_LAST_FRAME; | |
1148 | else | |
1149 | cmd = S5P_FIMV_CH_FRAME_START; | |
1150 | mfc_write(dev, ((cmd & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | |
1151 | | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1152 | ||
af935746 KD |
1153 | return 0; |
1154 | } | |
1155 | ||
1156 | static int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) | |
1157 | { | |
1158 | unsigned long flags; | |
1159 | int new_ctx; | |
1160 | int cnt; | |
1161 | ||
1162 | spin_lock_irqsave(&dev->condlock, flags); | |
1163 | new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS; | |
1164 | cnt = 0; | |
1165 | while (!test_bit(new_ctx, &dev->ctx_work_bits)) { | |
1166 | new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS; | |
1167 | if (++cnt > MFC_NUM_CONTEXTS) { | |
1168 | /* No contexts to run */ | |
1169 | spin_unlock_irqrestore(&dev->condlock, flags); | |
1170 | return -EAGAIN; | |
1171 | } | |
1172 | } | |
1173 | spin_unlock_irqrestore(&dev->condlock, flags); | |
1174 | return new_ctx; | |
1175 | } | |
1176 | ||
1177 | static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx) | |
1178 | { | |
1179 | struct s5p_mfc_dev *dev = ctx->dev; | |
1180 | ||
43a1ea1f | 1181 | s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); |
af935746 | 1182 | dev->curr_ctx = ctx->num; |
43a1ea1f | 1183 | s5p_mfc_decode_one_frame_v5(ctx, MFC_DEC_RES_CHANGE); |
af935746 KD |
1184 | } |
1185 | ||
1186 | static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame) | |
1187 | { | |
1188 | struct s5p_mfc_dev *dev = ctx->dev; | |
1189 | struct s5p_mfc_buf *temp_vb; | |
1190 | unsigned long flags; | |
af935746 | 1191 | |
a34026e7 KD |
1192 | if (ctx->state == MFCINST_FINISHING) { |
1193 | last_frame = MFC_DEC_LAST_FRAME; | |
1194 | s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); | |
1195 | dev->curr_ctx = ctx->num; | |
a34026e7 KD |
1196 | s5p_mfc_decode_one_frame_v5(ctx, last_frame); |
1197 | return 0; | |
1198 | } | |
1199 | ||
af935746 KD |
1200 | spin_lock_irqsave(&dev->irqlock, flags); |
1201 | /* Frames are being decoded */ | |
1202 | if (list_empty(&ctx->src_queue)) { | |
1203 | mfc_debug(2, "No src buffers\n"); | |
1204 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1205 | return -EAGAIN; | |
1206 | } | |
1207 | /* Get the next source buffer */ | |
1208 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
f9f715a9 | 1209 | temp_vb->flags |= MFC_BUF_FLAG_USED; |
43a1ea1f | 1210 | s5p_mfc_set_dec_stream_buffer_v5(ctx, |
2d700715 JS |
1211 | vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), |
1212 | ctx->consumed_stream, temp_vb->b->vb2_buf.planes[0].bytesused); | |
af935746 | 1213 | spin_unlock_irqrestore(&dev->irqlock, flags); |
af935746 | 1214 | dev->curr_ctx = ctx->num; |
2d700715 | 1215 | if (temp_vb->b->vb2_buf.planes[0].bytesused == 0) { |
af935746 KD |
1216 | last_frame = MFC_DEC_LAST_FRAME; |
1217 | mfc_debug(2, "Setting ctx->state to FINISHING\n"); | |
1218 | ctx->state = MFCINST_FINISHING; | |
1219 | } | |
43a1ea1f | 1220 | s5p_mfc_decode_one_frame_v5(ctx, last_frame); |
af935746 KD |
1221 | return 0; |
1222 | } | |
1223 | ||
1224 | static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) | |
1225 | { | |
1226 | struct s5p_mfc_dev *dev = ctx->dev; | |
1227 | unsigned long flags; | |
1228 | struct s5p_mfc_buf *dst_mb; | |
1229 | struct s5p_mfc_buf *src_mb; | |
1230 | unsigned long src_y_addr, src_c_addr, dst_addr; | |
1231 | unsigned int dst_size; | |
1232 | ||
1233 | spin_lock_irqsave(&dev->irqlock, flags); | |
f9f715a9 | 1234 | if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) { |
af935746 KD |
1235 | mfc_debug(2, "no src buffers\n"); |
1236 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1237 | return -EAGAIN; | |
1238 | } | |
1239 | if (list_empty(&ctx->dst_queue)) { | |
1240 | mfc_debug(2, "no dst buffers\n"); | |
1241 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1242 | return -EAGAIN; | |
1243 | } | |
f9f715a9 AH |
1244 | if (list_empty(&ctx->src_queue)) { |
1245 | /* send null frame */ | |
43a1ea1f | 1246 | s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, dev->bank2); |
f9f715a9 AH |
1247 | src_mb = NULL; |
1248 | } else { | |
1249 | src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, | |
1250 | list); | |
1251 | src_mb->flags |= MFC_BUF_FLAG_USED; | |
2d700715 | 1252 | if (src_mb->b->vb2_buf.planes[0].bytesused == 0) { |
f9f715a9 | 1253 | /* send null frame */ |
43a1ea1f | 1254 | s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, |
f9f715a9 AH |
1255 | dev->bank2); |
1256 | ctx->state = MFCINST_FINISHING; | |
1257 | } else { | |
2d700715 JS |
1258 | src_y_addr = vb2_dma_contig_plane_dma_addr( |
1259 | &src_mb->b->vb2_buf, 0); | |
1260 | src_c_addr = vb2_dma_contig_plane_dma_addr( | |
1261 | &src_mb->b->vb2_buf, 1); | |
43a1ea1f | 1262 | s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr, |
f9f715a9 AH |
1263 | src_c_addr); |
1264 | if (src_mb->flags & MFC_BUF_FLAG_EOS) | |
1265 | ctx->state = MFCINST_FINISHING; | |
1266 | } | |
1267 | } | |
af935746 | 1268 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); |
f9f715a9 | 1269 | dst_mb->flags |= MFC_BUF_FLAG_USED; |
2d700715 JS |
1270 | dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0); |
1271 | dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0); | |
43a1ea1f | 1272 | s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); |
af935746 KD |
1273 | spin_unlock_irqrestore(&dev->irqlock, flags); |
1274 | dev->curr_ctx = ctx->num; | |
4130eabc | 1275 | mfc_debug(2, "encoding buffer with index=%d state=%d\n", |
2d700715 | 1276 | src_mb ? src_mb->b->vb2_buf.index : -1, ctx->state); |
43a1ea1f | 1277 | s5p_mfc_encode_one_frame_v5(ctx); |
af935746 KD |
1278 | return 0; |
1279 | } | |
1280 | ||
1281 | static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx) | |
1282 | { | |
1283 | struct s5p_mfc_dev *dev = ctx->dev; | |
1284 | unsigned long flags; | |
1285 | struct s5p_mfc_buf *temp_vb; | |
1286 | ||
1287 | /* Initializing decoding - parsing header */ | |
1288 | spin_lock_irqsave(&dev->irqlock, flags); | |
1289 | mfc_debug(2, "Preparing to init decoding\n"); | |
1290 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1291 | s5p_mfc_set_dec_desc_buffer(ctx); | |
2d700715 JS |
1292 | mfc_debug(2, "Header size: %d\n", |
1293 | temp_vb->b->vb2_buf.planes[0].bytesused); | |
43a1ea1f | 1294 | s5p_mfc_set_dec_stream_buffer_v5(ctx, |
2d700715 JS |
1295 | vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), |
1296 | 0, temp_vb->b->vb2_buf.planes[0].bytesused); | |
af935746 KD |
1297 | spin_unlock_irqrestore(&dev->irqlock, flags); |
1298 | dev->curr_ctx = ctx->num; | |
43a1ea1f | 1299 | s5p_mfc_init_decode_v5(ctx); |
af935746 KD |
1300 | } |
1301 | ||
1302 | static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx) | |
1303 | { | |
1304 | struct s5p_mfc_dev *dev = ctx->dev; | |
1305 | unsigned long flags; | |
1306 | struct s5p_mfc_buf *dst_mb; | |
1307 | unsigned long dst_addr; | |
1308 | unsigned int dst_size; | |
1309 | ||
43a1ea1f | 1310 | s5p_mfc_set_enc_ref_buffer_v5(ctx); |
af935746 KD |
1311 | spin_lock_irqsave(&dev->irqlock, flags); |
1312 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); | |
2d700715 JS |
1313 | dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0); |
1314 | dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0); | |
43a1ea1f | 1315 | s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); |
af935746 KD |
1316 | spin_unlock_irqrestore(&dev->irqlock, flags); |
1317 | dev->curr_ctx = ctx->num; | |
43a1ea1f | 1318 | s5p_mfc_init_encode_v5(ctx); |
af935746 KD |
1319 | } |
1320 | ||
1321 | static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx) | |
1322 | { | |
1323 | struct s5p_mfc_dev *dev = ctx->dev; | |
1324 | unsigned long flags; | |
1325 | struct s5p_mfc_buf *temp_vb; | |
1326 | int ret; | |
1327 | ||
1328 | /* | |
1329 | * Header was parsed now starting processing | |
1330 | * First set the output frame buffers | |
1331 | */ | |
1332 | if (ctx->capture_state != QUEUE_BUFS_MMAPED) { | |
1333 | mfc_err("It seems that not all destionation buffers were " | |
1334 | "mmaped\nMFC requires that all destination are mmaped " | |
1335 | "before starting processing\n"); | |
1336 | return -EAGAIN; | |
1337 | } | |
1338 | spin_lock_irqsave(&dev->irqlock, flags); | |
1339 | if (list_empty(&ctx->src_queue)) { | |
1340 | mfc_err("Header has been deallocated in the middle of" | |
1341 | " initialization\n"); | |
1342 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1343 | return -EIO; | |
1344 | } | |
1345 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
2d700715 JS |
1346 | mfc_debug(2, "Header size: %d\n", |
1347 | temp_vb->b->vb2_buf.planes[0].bytesused); | |
43a1ea1f | 1348 | s5p_mfc_set_dec_stream_buffer_v5(ctx, |
2d700715 JS |
1349 | vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), |
1350 | 0, temp_vb->b->vb2_buf.planes[0].bytesused); | |
af935746 KD |
1351 | spin_unlock_irqrestore(&dev->irqlock, flags); |
1352 | dev->curr_ctx = ctx->num; | |
43a1ea1f | 1353 | ret = s5p_mfc_set_dec_frame_buffer_v5(ctx); |
af935746 KD |
1354 | if (ret) { |
1355 | mfc_err("Failed to alloc frame mem\n"); | |
1356 | ctx->state = MFCINST_ERROR; | |
1357 | } | |
1358 | return ret; | |
1359 | } | |
1360 | ||
1361 | /* Try running an operation on hardware */ | |
3c75a2e1 | 1362 | static void s5p_mfc_try_run_v5(struct s5p_mfc_dev *dev) |
af935746 KD |
1363 | { |
1364 | struct s5p_mfc_ctx *ctx; | |
1365 | int new_ctx; | |
1366 | unsigned int ret = 0; | |
1367 | ||
1368 | if (test_bit(0, &dev->enter_suspend)) { | |
1369 | mfc_debug(1, "Entering suspend so do not schedule any jobs\n"); | |
1370 | return; | |
1371 | } | |
1372 | /* Check whether hardware is not running */ | |
1373 | if (test_and_set_bit(0, &dev->hw_lock) != 0) { | |
1374 | /* This is perfectly ok, the scheduled ctx should wait */ | |
1375 | mfc_debug(1, "Couldn't lock HW\n"); | |
1376 | return; | |
1377 | } | |
1378 | /* Choose the context to run */ | |
1379 | new_ctx = s5p_mfc_get_new_ctx(dev); | |
1380 | if (new_ctx < 0) { | |
1381 | /* No contexts to run */ | |
1382 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) { | |
1383 | mfc_err("Failed to unlock hardware\n"); | |
1384 | return; | |
1385 | } | |
1386 | mfc_debug(1, "No ctx is scheduled to be run\n"); | |
1387 | return; | |
1388 | } | |
1389 | ctx = dev->ctx[new_ctx]; | |
1390 | /* Got context to run in ctx */ | |
1391 | /* | |
1392 | * Last frame has already been sent to MFC. | |
1393 | * Now obtaining frames from MFC buffer | |
1394 | */ | |
1395 | s5p_mfc_clock_on(); | |
f2035364 PO |
1396 | s5p_mfc_clean_ctx_int_flags(ctx); |
1397 | ||
af935746 KD |
1398 | if (ctx->type == MFCINST_DECODER) { |
1399 | s5p_mfc_set_dec_desc_buffer(ctx); | |
1400 | switch (ctx->state) { | |
1401 | case MFCINST_FINISHING: | |
1402 | s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME); | |
1403 | break; | |
1404 | case MFCINST_RUNNING: | |
1405 | ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); | |
1406 | break; | |
1407 | case MFCINST_INIT: | |
43a1ea1f AK |
1408 | ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, |
1409 | ctx); | |
af935746 KD |
1410 | break; |
1411 | case MFCINST_RETURN_INST: | |
43a1ea1f AK |
1412 | ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, |
1413 | ctx); | |
af935746 KD |
1414 | break; |
1415 | case MFCINST_GOT_INST: | |
1416 | s5p_mfc_run_init_dec(ctx); | |
1417 | break; | |
1418 | case MFCINST_HEAD_PARSED: | |
1419 | ret = s5p_mfc_run_init_dec_buffers(ctx); | |
1420 | mfc_debug(1, "head parsed\n"); | |
1421 | break; | |
1422 | case MFCINST_RES_CHANGE_INIT: | |
1423 | s5p_mfc_run_res_change(ctx); | |
1424 | break; | |
1425 | case MFCINST_RES_CHANGE_FLUSH: | |
1426 | s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); | |
1427 | break; | |
1428 | case MFCINST_RES_CHANGE_END: | |
1429 | mfc_debug(2, "Finished remaining frames after resolution change\n"); | |
1430 | ctx->capture_state = QUEUE_FREE; | |
1431 | mfc_debug(2, "Will re-init the codec\n"); | |
1432 | s5p_mfc_run_init_dec(ctx); | |
1433 | break; | |
1434 | default: | |
1435 | ret = -EAGAIN; | |
1436 | } | |
1437 | } else if (ctx->type == MFCINST_ENCODER) { | |
1438 | switch (ctx->state) { | |
1439 | case MFCINST_FINISHING: | |
1440 | case MFCINST_RUNNING: | |
1441 | ret = s5p_mfc_run_enc_frame(ctx); | |
1442 | break; | |
1443 | case MFCINST_INIT: | |
43a1ea1f AK |
1444 | ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, |
1445 | ctx); | |
af935746 KD |
1446 | break; |
1447 | case MFCINST_RETURN_INST: | |
43a1ea1f AK |
1448 | ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, |
1449 | ctx); | |
af935746 KD |
1450 | break; |
1451 | case MFCINST_GOT_INST: | |
1452 | s5p_mfc_run_init_enc(ctx); | |
1453 | break; | |
1454 | default: | |
1455 | ret = -EAGAIN; | |
1456 | } | |
1457 | } else { | |
1458 | mfc_err("Invalid context type: %d\n", ctx->type); | |
1459 | ret = -EAGAIN; | |
1460 | } | |
1461 | ||
1462 | if (ret) { | |
1463 | /* Free hardware lock */ | |
1464 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
1465 | mfc_err("Failed to unlock hardware\n"); | |
1466 | ||
1467 | /* This is in deed imporant, as no operation has been | |
1468 | * scheduled, reduce the clock count as no one will | |
1469 | * ever do this, because no interrupt related to this try_run | |
1470 | * will ever come from hardware. */ | |
1471 | s5p_mfc_clock_off(); | |
1472 | } | |
1473 | } | |
1474 | ||
1475 | ||
3c75a2e1 | 1476 | static void s5p_mfc_cleanup_queue_v5(struct list_head *lh, struct vb2_queue *vq) |
af935746 KD |
1477 | { |
1478 | struct s5p_mfc_buf *b; | |
1479 | int i; | |
1480 | ||
1481 | while (!list_empty(lh)) { | |
1482 | b = list_entry(lh->next, struct s5p_mfc_buf, list); | |
2d700715 JS |
1483 | for (i = 0; i < b->b->vb2_buf.num_planes; i++) |
1484 | vb2_set_plane_payload(&b->b->vb2_buf, i, 0); | |
1485 | vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR); | |
af935746 KD |
1486 | list_del(&b->list); |
1487 | } | |
1488 | } | |
1489 | ||
3c75a2e1 | 1490 | static void s5p_mfc_clear_int_flags_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1491 | { |
1492 | mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); | |
1493 | mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); | |
1494 | mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); | |
1495 | } | |
1496 | ||
3c75a2e1 | 1497 | static int s5p_mfc_get_dspl_y_adr_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1498 | { |
1499 | return mfc_read(dev, S5P_FIMV_SI_DISPLAY_Y_ADR) << MFC_OFFSET_SHIFT; | |
1500 | } | |
1501 | ||
3c75a2e1 | 1502 | static int s5p_mfc_get_dec_y_adr_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1503 | { |
1504 | return mfc_read(dev, S5P_FIMV_SI_DECODE_Y_ADR) << MFC_OFFSET_SHIFT; | |
1505 | } | |
1506 | ||
3c75a2e1 | 1507 | static int s5p_mfc_get_dspl_status_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1508 | { |
1509 | return mfc_read(dev, S5P_FIMV_SI_DISPLAY_STATUS); | |
1510 | } | |
1511 | ||
3c75a2e1 | 1512 | static int s5p_mfc_get_dec_status_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1513 | { |
1514 | return mfc_read(dev, S5P_FIMV_SI_DECODE_STATUS); | |
1515 | } | |
1516 | ||
3c75a2e1 | 1517 | static int s5p_mfc_get_dec_frame_type_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1518 | { |
1519 | return mfc_read(dev, S5P_FIMV_DECODE_FRAME_TYPE) & | |
1520 | S5P_FIMV_DECODE_FRAME_MASK; | |
1521 | } | |
1522 | ||
3c75a2e1 | 1523 | static int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f | 1524 | { |
8f532a7f AK |
1525 | return (s5p_mfc_read_info_v5(ctx, DISP_PIC_FRAME_TYPE) >> |
1526 | S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) & | |
1527 | S5P_FIMV_DECODE_FRAME_MASK; | |
43a1ea1f AK |
1528 | } |
1529 | ||
3c75a2e1 | 1530 | static int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1531 | { |
1532 | return mfc_read(dev, S5P_FIMV_SI_CONSUMED_BYTES); | |
1533 | } | |
1534 | ||
3c75a2e1 | 1535 | static int s5p_mfc_get_int_reason_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1536 | { |
1537 | int reason; | |
1538 | reason = mfc_read(dev, S5P_FIMV_RISC2HOST_CMD) & | |
1539 | S5P_FIMV_RISC2HOST_CMD_MASK; | |
1540 | switch (reason) { | |
1541 | case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET: | |
1542 | reason = S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET; | |
1543 | break; | |
1544 | case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET: | |
1545 | reason = S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET; | |
1546 | break; | |
1547 | case S5P_FIMV_R2H_CMD_SEQ_DONE_RET: | |
1548 | reason = S5P_MFC_R2H_CMD_SEQ_DONE_RET; | |
1549 | break; | |
1550 | case S5P_FIMV_R2H_CMD_FRAME_DONE_RET: | |
1551 | reason = S5P_MFC_R2H_CMD_FRAME_DONE_RET; | |
1552 | break; | |
1553 | case S5P_FIMV_R2H_CMD_SLICE_DONE_RET: | |
1554 | reason = S5P_MFC_R2H_CMD_SLICE_DONE_RET; | |
1555 | break; | |
1556 | case S5P_FIMV_R2H_CMD_SYS_INIT_RET: | |
1557 | reason = S5P_MFC_R2H_CMD_SYS_INIT_RET; | |
1558 | break; | |
1559 | case S5P_FIMV_R2H_CMD_FW_STATUS_RET: | |
1560 | reason = S5P_MFC_R2H_CMD_FW_STATUS_RET; | |
1561 | break; | |
1562 | case S5P_FIMV_R2H_CMD_SLEEP_RET: | |
1563 | reason = S5P_MFC_R2H_CMD_SLEEP_RET; | |
1564 | break; | |
1565 | case S5P_FIMV_R2H_CMD_WAKEUP_RET: | |
1566 | reason = S5P_MFC_R2H_CMD_WAKEUP_RET; | |
1567 | break; | |
1568 | case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET: | |
1569 | reason = S5P_MFC_R2H_CMD_INIT_BUFFERS_RET; | |
1570 | break; | |
1571 | case S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET: | |
1572 | reason = S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET; | |
1573 | break; | |
1574 | case S5P_FIMV_R2H_CMD_ERR_RET: | |
1575 | reason = S5P_MFC_R2H_CMD_ERR_RET; | |
1576 | break; | |
1577 | default: | |
1578 | reason = S5P_MFC_R2H_CMD_EMPTY; | |
2028c71d | 1579 | } |
43a1ea1f AK |
1580 | return reason; |
1581 | } | |
1582 | ||
3c75a2e1 | 1583 | static int s5p_mfc_get_int_err_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1584 | { |
1585 | return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG2); | |
1586 | } | |
1587 | ||
3c75a2e1 | 1588 | static int s5p_mfc_err_dec_v5(unsigned int err) |
43a1ea1f AK |
1589 | { |
1590 | return (err & S5P_FIMV_ERR_DEC_MASK) >> S5P_FIMV_ERR_DEC_SHIFT; | |
1591 | } | |
1592 | ||
3c75a2e1 | 1593 | static int s5p_mfc_err_dspl_v5(unsigned int err) |
43a1ea1f AK |
1594 | { |
1595 | return (err & S5P_FIMV_ERR_DSPL_MASK) >> S5P_FIMV_ERR_DSPL_SHIFT; | |
1596 | } | |
1597 | ||
3c75a2e1 | 1598 | static int s5p_mfc_get_img_width_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1599 | { |
1600 | return mfc_read(dev, S5P_FIMV_SI_HRESOL); | |
1601 | } | |
1602 | ||
3c75a2e1 | 1603 | static int s5p_mfc_get_img_height_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1604 | { |
1605 | return mfc_read(dev, S5P_FIMV_SI_VRESOL); | |
1606 | } | |
1607 | ||
3c75a2e1 | 1608 | static int s5p_mfc_get_dpb_count_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1609 | { |
1610 | return mfc_read(dev, S5P_FIMV_SI_BUF_NUMBER); | |
1611 | } | |
1612 | ||
3c75a2e1 | 1613 | static int s5p_mfc_get_mv_count_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1614 | { |
1615 | /* NOP */ | |
1616 | return -1; | |
1617 | } | |
1618 | ||
3c75a2e1 | 1619 | static int s5p_mfc_get_inst_no_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1620 | { |
1621 | return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG1); | |
1622 | } | |
1623 | ||
3c75a2e1 | 1624 | static int s5p_mfc_get_enc_strm_size_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1625 | { |
1626 | return mfc_read(dev, S5P_FIMV_ENC_SI_STRM_SIZE); | |
1627 | } | |
1628 | ||
3c75a2e1 | 1629 | static int s5p_mfc_get_enc_slice_type_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1630 | { |
1631 | return mfc_read(dev, S5P_FIMV_ENC_SI_SLICE_TYPE); | |
1632 | } | |
1633 | ||
3c75a2e1 | 1634 | static int s5p_mfc_get_enc_dpb_count_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1635 | { |
1636 | return -1; | |
1637 | } | |
1638 | ||
3c75a2e1 | 1639 | static int s5p_mfc_get_enc_pic_count_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1640 | { |
1641 | return mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT); | |
1642 | } | |
1643 | ||
3c75a2e1 | 1644 | static int s5p_mfc_get_sei_avail_status_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f AK |
1645 | { |
1646 | return s5p_mfc_read_info_v5(ctx, FRAME_PACK_SEI_AVAIL); | |
1647 | } | |
1648 | ||
3c75a2e1 | 1649 | static int s5p_mfc_get_mvc_num_views_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1650 | { |
1651 | return -1; | |
1652 | } | |
1653 | ||
3c75a2e1 | 1654 | static int s5p_mfc_get_mvc_view_id_v5(struct s5p_mfc_dev *dev) |
43a1ea1f AK |
1655 | { |
1656 | return -1; | |
1657 | } | |
1658 | ||
3c75a2e1 | 1659 | static unsigned int s5p_mfc_get_pic_type_top_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f AK |
1660 | { |
1661 | return s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP); | |
1662 | } | |
1663 | ||
3c75a2e1 | 1664 | static unsigned int s5p_mfc_get_pic_type_bot_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f AK |
1665 | { |
1666 | return s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT); | |
1667 | } | |
1668 | ||
3c75a2e1 | 1669 | static unsigned int s5p_mfc_get_crop_info_h_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f AK |
1670 | { |
1671 | return s5p_mfc_read_info_v5(ctx, CROP_INFO_H); | |
1672 | } | |
1673 | ||
3c75a2e1 | 1674 | static unsigned int s5p_mfc_get_crop_info_v_v5(struct s5p_mfc_ctx *ctx) |
43a1ea1f AK |
1675 | { |
1676 | return s5p_mfc_read_info_v5(ctx, CROP_INFO_V); | |
1677 | } | |
1678 | ||
1679 | /* Initialize opr function pointers for MFC v5 */ | |
1680 | static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = { | |
1681 | .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v5, | |
1682 | .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v5, | |
1683 | .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v5, | |
1684 | .release_codec_buffers = s5p_mfc_release_codec_buffers_v5, | |
1685 | .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v5, | |
1686 | .release_instance_buffer = s5p_mfc_release_instance_buffer_v5, | |
1687 | .alloc_dev_context_buffer = s5p_mfc_alloc_dev_context_buffer_v5, | |
1688 | .release_dev_context_buffer = s5p_mfc_release_dev_context_buffer_v5, | |
1689 | .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v5, | |
1690 | .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v5, | |
1691 | .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v5, | |
1692 | .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v5, | |
1693 | .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v5, | |
1694 | .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v5, | |
1695 | .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v5, | |
1696 | .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v5, | |
1697 | .init_decode = s5p_mfc_init_decode_v5, | |
1698 | .init_encode = s5p_mfc_init_encode_v5, | |
1699 | .encode_one_frame = s5p_mfc_encode_one_frame_v5, | |
1700 | .try_run = s5p_mfc_try_run_v5, | |
1701 | .cleanup_queue = s5p_mfc_cleanup_queue_v5, | |
1702 | .clear_int_flags = s5p_mfc_clear_int_flags_v5, | |
1703 | .write_info = s5p_mfc_write_info_v5, | |
1704 | .read_info = s5p_mfc_read_info_v5, | |
1705 | .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v5, | |
1706 | .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v5, | |
1707 | .get_dspl_status = s5p_mfc_get_dspl_status_v5, | |
1708 | .get_dec_status = s5p_mfc_get_dec_status_v5, | |
1709 | .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v5, | |
1710 | .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v5, | |
1711 | .get_consumed_stream = s5p_mfc_get_consumed_stream_v5, | |
1712 | .get_int_reason = s5p_mfc_get_int_reason_v5, | |
1713 | .get_int_err = s5p_mfc_get_int_err_v5, | |
1714 | .err_dec = s5p_mfc_err_dec_v5, | |
1715 | .err_dspl = s5p_mfc_err_dspl_v5, | |
1716 | .get_img_width = s5p_mfc_get_img_width_v5, | |
1717 | .get_img_height = s5p_mfc_get_img_height_v5, | |
1718 | .get_dpb_count = s5p_mfc_get_dpb_count_v5, | |
1719 | .get_mv_count = s5p_mfc_get_mv_count_v5, | |
1720 | .get_inst_no = s5p_mfc_get_inst_no_v5, | |
1721 | .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v5, | |
1722 | .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v5, | |
1723 | .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v5, | |
1724 | .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v5, | |
1725 | .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v5, | |
1726 | .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v5, | |
1727 | .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v5, | |
1728 | .get_pic_type_top = s5p_mfc_get_pic_type_top_v5, | |
1729 | .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v5, | |
1730 | .get_crop_info_h = s5p_mfc_get_crop_info_h_v5, | |
1731 | .get_crop_info_v = s5p_mfc_get_crop_info_v_v5, | |
1732 | }; | |
1733 | ||
1734 | struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void) | |
1735 | { | |
1736 | return &s5p_mfc_ops_v5; | |
1737 | } |