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[media] V4L: Add VP8 encoder controls
[linux-2.6-block.git] / drivers / media / platform / s5p-mfc / s5p_mfc_common.h
CommitLineData
af935746
KD		 1/*
2 * Samsung S5P Multi Format Codec v 5.0
3 *
4 * This file contains definitions of enums and structs used by the codec
5 * driver.
6 *
7 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
8 * Kamil Debski, <k.debski@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version
14 */
15
16#ifndef S5P_MFC_COMMON_H_
17#define S5P_MFC_COMMON_H_
18
af935746
KD		 19#include <linux/platform_device.h>
20#include <linux/videodev2.h>
21#include <media/v4l2-ctrls.h>
22#include <media/v4l2-device.h>
23#include <media/v4l2-ioctl.h>
24#include <media/videobuf2-core.h>
f96f3cfa
JP		 25#include "regs-mfc.h"
26#include "regs-mfc-v6.h"
5441e9da 27#include "regs-mfc-v7.h"
af935746
KD		 28
29/* Definitions related to MFC memory */
30
31/* Offset base used to differentiate between CAPTURE and OUTPUT
32* while mmaping */
33#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
34
af935746
KD		 35#define MFC_BANK1_ALLOC_CTX 0
36#define MFC_BANK2_ALLOC_CTX 1
37
38#define MFC_BANK1_ALIGN_ORDER 13
39#define MFC_BANK2_ALIGN_ORDER 13
40#define MFC_BASE_ALIGN_ORDER 17
41
42#include <media/videobuf2-dma-contig.h>
43
44static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
45{
46 /* Same functionality as the vb2_dma_contig_plane_paddr */
47 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
48
49 return *paddr;
50}
51
52/* MFC definitions */
53#define MFC_MAX_EXTRA_DPB 5
54#define MFC_MAX_BUFFERS 32
55#define MFC_NUM_CONTEXTS 4
56/* Interrupt timeout */
57#define MFC_INT_TIMEOUT 2000
58/* Busy wait timeout */
59#define MFC_BW_TIMEOUT 500
60/* Watchdog interval */
61#define MFC_WATCHDOG_INTERVAL 1000
62/* After how many executions watchdog should assume lock up */
63#define MFC_WATCHDOG_CNT 10
64#define MFC_NO_INSTANCE_SET -1
65#define MFC_ENC_CAP_PLANE_COUNT 1
66#define MFC_ENC_OUT_PLANE_COUNT 2
67#define STUFF_BYTE 4
43a1ea1f
AK		 68#define MFC_MAX_CTRLS 70
69
70#define S5P_MFC_CODEC_NONE -1
71#define S5P_MFC_CODEC_H264_DEC 0
72#define S5P_MFC_CODEC_H264_MVC_DEC 1
73#define S5P_MFC_CODEC_VC1_DEC 2
74#define S5P_MFC_CODEC_MPEG4_DEC 3
75#define S5P_MFC_CODEC_MPEG2_DEC 4
76#define S5P_MFC_CODEC_H263_DEC 5
77#define S5P_MFC_CODEC_VC1RCV_DEC 6
78#define S5P_MFC_CODEC_VP8_DEC 7
79
80#define S5P_MFC_CODEC_H264_ENC 20
81#define S5P_MFC_CODEC_H264_MVC_ENC 21
82#define S5P_MFC_CODEC_MPEG4_ENC 22
83#define S5P_MFC_CODEC_H263_ENC 23
84
85#define S5P_MFC_R2H_CMD_EMPTY 0
86#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
87#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
88#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
89#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
90#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
91#define S5P_MFC_R2H_CMD_SLEEP_RET 7
92#define S5P_MFC_R2H_CMD_WAKEUP_RET 8
93#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
94#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
95#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
96#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
97#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
98#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
99#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
100#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
101#define S5P_MFC_R2H_CMD_ERR_RET 32
af935746
KD		 102
103#define mfc_read(dev, offset) readl(dev->regs_base + (offset))
104#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
105 (offset))
106
107/**
108 * enum s5p_mfc_fmt_type - type of the pixelformat
109 */
110enum s5p_mfc_fmt_type {
111 MFC_FMT_DEC,
112 MFC_FMT_ENC,
113 MFC_FMT_RAW,
114};
115
116/**
117 * enum s5p_mfc_node_type - The type of an MFC device node.
118 */
119enum s5p_mfc_node_type {
120 MFCNODE_INVALID = -1,
121 MFCNODE_DECODER = 0,
122 MFCNODE_ENCODER = 1,
123};
124
125/**
126 * enum s5p_mfc_inst_type - The type of an MFC instance.
127 */
128enum s5p_mfc_inst_type {
129 MFCINST_INVALID,
130 MFCINST_DECODER,
131 MFCINST_ENCODER,
132};
133
134/**
135 * enum s5p_mfc_inst_state - The state of an MFC instance.
136 */
137enum s5p_mfc_inst_state {
138 MFCINST_FREE = 0,
139 MFCINST_INIT = 100,
140 MFCINST_GOT_INST,
141 MFCINST_HEAD_PARSED,
e9d98ddc 142 MFCINST_HEAD_PRODUCED,
af935746
KD		 143 MFCINST_BUFS_SET,
144 MFCINST_RUNNING,
145 MFCINST_FINISHING,
146 MFCINST_FINISHED,
147 MFCINST_RETURN_INST,
148 MFCINST_ERROR,
149 MFCINST_ABORT,
8f23cc02 150 MFCINST_FLUSH,
af935746
KD		 151 MFCINST_RES_CHANGE_INIT,
152 MFCINST_RES_CHANGE_FLUSH,
153 MFCINST_RES_CHANGE_END,
154};
155
156/**
157 * enum s5p_mfc_queue_state - The state of buffer queue.
158 */
159enum s5p_mfc_queue_state {
160 QUEUE_FREE,
161 QUEUE_BUFS_REQUESTED,
162 QUEUE_BUFS_QUERIED,
163 QUEUE_BUFS_MMAPED,
164};
165
166/**
167 * enum s5p_mfc_decode_arg - type of frame decoding
168 */
169enum s5p_mfc_decode_arg {
170 MFC_DEC_FRAME,
171 MFC_DEC_LAST_FRAME,
172 MFC_DEC_RES_CHANGE,
173};
174
f9f715a9
AH		 175#define MFC_BUF_FLAG_USED (1 << 0)
176#define MFC_BUF_FLAG_EOS (1 << 1)
177
af935746
KD		 178struct s5p_mfc_ctx;
179
180/**
181 * struct s5p_mfc_buf - MFC buffer
182 */
183struct s5p_mfc_buf {
184 struct list_head list;
185 struct vb2_buffer *b;
186 union {
187 struct {
188 size_t luma;
189 size_t chroma;
190 } raw;
191 size_t stream;
192 } cookie;
f9f715a9 193 int flags;
af935746
KD		 194};
195
196/**
197 * struct s5p_mfc_pm - power management data structure
198 */
199struct s5p_mfc_pm {
200 struct clk *clock;
201 struct clk *clock_gate;
202 atomic_t power;
203 struct device *device;
204};
205
8f532a7f
AK		 206struct s5p_mfc_buf_size_v5 {
207 unsigned int h264_ctx;
208 unsigned int non_h264_ctx;
209 unsigned int dsc;
210 unsigned int shm;
211};
212
f96f3cfa
JP		 213struct s5p_mfc_buf_size_v6 {
214 unsigned int dev_ctx;
215 unsigned int h264_dec_ctx;
216 unsigned int other_dec_ctx;
217 unsigned int h264_enc_ctx;
218 unsigned int other_enc_ctx;
219};
220
8f532a7f
AK		 221struct s5p_mfc_buf_size {
222 unsigned int fw;
223 unsigned int cpb;
224 void *priv;
225};
226
227struct s5p_mfc_buf_align {
228 unsigned int base;
229};
230
231struct s5p_mfc_variant {
232 unsigned int version;
233 unsigned int port_num;
234 struct s5p_mfc_buf_size *buf_size;
235 struct s5p_mfc_buf_align *buf_align;
f96f3cfa 236 char *fw_name;
8f532a7f
AK		 237};
238
239/**
240 * struct s5p_mfc_priv_buf - represents internal used buffer
241 * @alloc: allocation-specific context for each buffer
242 * (videobuf2 allocator)
243 * @ofs: offset of each buffer, will be used for MFC
244 * @virt: kernel virtual address, only valid when the
245 * buffer accessed by driver
246 * @dma: DMA address, only valid when kernel DMA API used
247 * @size: size of the buffer
248 */
249struct s5p_mfc_priv_buf {
250 void *alloc;
251 unsigned long ofs;
252 void *virt;
253 dma_addr_t dma;
254 size_t size;
255};
256
af935746
KD		 257/**
258 * struct s5p_mfc_dev - The struct containing driver internal parameters.
259 *
260 * @v4l2_dev: v4l2_device
261 * @vfd_dec: video device for decoding
262 * @vfd_enc: video device for encoding
263 * @plat_dev: platform device
264 * @mem_dev_l: child device of the left memory bank (0)
265 * @mem_dev_r: child device of the right memory bank (1)
266 * @regs_base: base address of the MFC hw registers
267 * @irq: irq resource
af935746
KD		 268 * @dec_ctrl_handler: control framework handler for decoding
269 * @enc_ctrl_handler: control framework handler for encoding
270 * @pm: power management control
8f532a7f 271 * @variant: MFC hardware variant information
af935746
KD		 272 * @num_inst: couter of active MFC instances
273 * @irqlock: lock for operations on videobuf2 queues
274 * @condlock: lock for changing/checking if a context is ready to be
275 * processed
276 * @mfc_mutex: lock for video_device
277 * @int_cond: variable used by the waitqueue
278 * @int_type: type of last interrupt
279 * @int_err: error number for last interrupt
280 * @queue: waitqueue for waiting for completion of device commands
281 * @fw_size: size of firmware
2e731e44
KD		 282 * @fw_virt_addr: virtual firmware address
283 * @bank1: address of the beginning of bank 1 memory
284 * @bank2: address of the beginning of bank 2 memory
af935746
KD		 285 * @hw_lock: used for hardware locking
286 * @ctx: array of driver contexts
287 * @curr_ctx: number of the currently running context
288 * @ctx_work_bits: used to mark which contexts are waiting for hardware
289 * @watchdog_cnt: counter for the watchdog
290 * @watchdog_workqueue: workqueue for the watchdog
291 * @watchdog_work: worker for the watchdog
292 * @alloc_ctx: videobuf2 allocator contexts for two memory banks
293 * @enter_suspend: flag set when entering suspend
f96f3cfa 294 * @ctx_buf: common context memory (MFCv6)
43a1ea1f
AK		 295 * @warn_start: hardware error code from which warnings start
296 * @mfc_ops: ops structure holding HW operation function pointers
297 * @mfc_cmds: cmd structure holding HW commands function pointers
af935746
KD		 298 *
299 */
300struct s5p_mfc_dev {
301 struct v4l2_device v4l2_dev;
302 struct video_device *vfd_dec;
303 struct video_device *vfd_enc;
304 struct platform_device *plat_dev;
305 struct device *mem_dev_l;
306 struct device *mem_dev_r;
307 void __iomem *regs_base;
308 int irq;
af935746
KD		 309 struct v4l2_ctrl_handler dec_ctrl_handler;
310 struct v4l2_ctrl_handler enc_ctrl_handler;
311 struct s5p_mfc_pm pm;
8f532a7f 312 struct s5p_mfc_variant *variant;
af935746
KD		 313 int num_inst;
314 spinlock_t irqlock; /* lock when operating on videobuf2 queues */
315 spinlock_t condlock; /* lock when changing/checking if a context is
316 ready to be processed */
317 struct mutex mfc_mutex; /* video_device lock */
318 int int_cond;
319 int int_type;
320 unsigned int int_err;
321 wait_queue_head_t queue;
322 size_t fw_size;
2e731e44
KD		 323 void *fw_virt_addr;
324 dma_addr_t bank1;
325 dma_addr_t bank2;
af935746
KD		 326 unsigned long hw_lock;
327 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
328 int curr_ctx;
329 unsigned long ctx_work_bits;
330 atomic_t watchdog_cnt;
331 struct timer_list watchdog_timer;
332 struct workqueue_struct *watchdog_workqueue;
333 struct work_struct watchdog_work;
334 void *alloc_ctx[2];
335 unsigned long enter_suspend;
43a1ea1f 336
f96f3cfa 337 struct s5p_mfc_priv_buf ctx_buf;
43a1ea1f
AK		 338 int warn_start;
339 struct s5p_mfc_hw_ops *mfc_ops;
340 struct s5p_mfc_hw_cmds *mfc_cmds;
af935746
KD		 341};
342
343/**
344 * struct s5p_mfc_h264_enc_params - encoding parameters for h264
345 */
346struct s5p_mfc_h264_enc_params {
347 enum v4l2_mpeg_video_h264_profile profile;
348 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
349 s8 loop_filter_alpha;
350 s8 loop_filter_beta;
351 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
352 u8 max_ref_pic;
353 u8 num_ref_pic_4p;
354 int _8x8_transform;
af935746
KD		 355 int rc_mb_dark;
356 int rc_mb_smooth;
357 int rc_mb_static;
358 int rc_mb_activity;
359 int vui_sar;
360 u8 vui_sar_idc;
361 u16 vui_ext_sar_width;
362 u16 vui_ext_sar_height;
363 int open_gop;
364 u16 open_gop_size;
365 u8 rc_frame_qp;
366 u8 rc_min_qp;
367 u8 rc_max_qp;
368 u8 rc_p_frame_qp;
369 u8 rc_b_frame_qp;
370 enum v4l2_mpeg_video_h264_level level_v4l2;
371 int level;
372 u16 cpb_size;
8f532a7f 373 int interlace;
f96f3cfa
JP		 374 u8 hier_qp;
375 u8 hier_qp_type;
376 u8 hier_qp_layer;
377 u8 hier_qp_layer_qp[7];
378 u8 sei_frame_packing;
379 u8 sei_fp_curr_frame_0;
380 u8 sei_fp_arrangement_type;
381
382 u8 fmo;
383 u8 fmo_map_type;
384 u8 fmo_slice_grp;
385 u8 fmo_chg_dir;
386 u32 fmo_chg_rate;
387 u32 fmo_run_len[4];
388 u8 aso;
389 u32 aso_slice_order[8];
af935746
KD		 390};
391
392/**
393 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
394 */
395struct s5p_mfc_mpeg4_enc_params {
396 /* MPEG4 Only */
397 enum v4l2_mpeg_video_mpeg4_profile profile;
398 int quarter_pixel;
399 /* Common for MPEG4, H263 */
400 u16 vop_time_res;
401 u16 vop_frm_delta;
402 u8 rc_frame_qp;
403 u8 rc_min_qp;
404 u8 rc_max_qp;
405 u8 rc_p_frame_qp;
406 u8 rc_b_frame_qp;
407 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
408 int level;
409};
410
411/**
412 * struct s5p_mfc_enc_params - general encoding parameters
413 */
414struct s5p_mfc_enc_params {
415 u16 width;
416 u16 height;
417
418 u16 gop_size;
419 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
420 u16 slice_mb;
421 u32 slice_bit;
422 u16 intra_refresh_mb;
423 int pad;
424 u8 pad_luma;
425 u8 pad_cb;
426 u8 pad_cr;
427 int rc_frame;
8f532a7f 428 int rc_mb;
af935746
KD		 429 u32 rc_bitrate;
430 u16 rc_reaction_coeff;
431 u16 vbv_size;
f96f3cfa 432 u32 vbv_delay;
af935746
KD		 433
434 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
435 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
436 int fixed_target_bit;
437
438 u8 num_b_frame;
439 u32 rc_framerate_num;
440 u32 rc_framerate_denom;
af935746 441
ac5f867f 442 struct {
af935746
KD		 443 struct s5p_mfc_h264_enc_params h264;
444 struct s5p_mfc_mpeg4_enc_params mpeg4;
445 } codec;
446
447};
448
449/**
450 * struct s5p_mfc_codec_ops - codec ops, used by encoding
451 */
452struct s5p_mfc_codec_ops {
453 /* initialization routines */
454 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
455 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
456 /* execution routines */
457 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
458 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
459};
460
461#define call_cop(c, op, args...) \
462 (((c)->c_ops->op) ? \
463 ((c)->c_ops->op(args)) : 0)
464
465/**
466 * struct s5p_mfc_ctx - This struct contains the instance context
467 *
468 * @dev: pointer to the s5p_mfc_dev of the device
469 * @fh: struct v4l2_fh
470 * @num: number of the context that this structure describes
471 * @int_cond: variable used by the waitqueue
472 * @int_type: type of the last interrupt
473 * @int_err: error number received from MFC hw in the interrupt
474 * @queue: waitqueue that can be used to wait for this context to
475 * finish
476 * @src_fmt: source pixelformat information
477 * @dst_fmt: destination pixelformat information
478 * @vq_src: vb2 queue for source buffers
479 * @vq_dst: vb2 queue for destination buffers
480 * @src_queue: driver internal queue for source buffers
481 * @dst_queue: driver internal queue for destination buffers
482 * @src_queue_cnt: number of buffers queued on the source internal queue
483 * @dst_queue_cnt: number of buffers queued on the dest internal queue
484 * @type: type of the instance - decoder or encoder
485 * @state: state of the context
486 * @inst_no: number of hw instance associated with the context
487 * @img_width: width of the image that is decoded or encoded
488 * @img_height: height of the image that is decoded or encoded
489 * @buf_width: width of the buffer for processed image
490 * @buf_height: height of the buffer for processed image
491 * @luma_size: size of a luma plane
492 * @chroma_size: size of a chroma plane
493 * @mv_size: size of a motion vectors buffer
494 * @consumed_stream: number of bytes that have been used so far from the
495 * decoding buffer
496 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
497 * flushed
f96f3cfa
JP		 498 * @head_processed: flag mentioning whether the header data is processed
499 * completely or not
317b4ca4 500 * @bank1: handle to memory allocated for temporary buffers from
af935746 501 * memory bank 1
317b4ca4 502 * @bank2: handle to memory allocated for temporary buffers from
af935746
KD		 503 * memory bank 2
504 * @capture_state: state of the capture buffers queue
505 * @output_state: state of the output buffers queue
506 * @src_bufs: information on allocated source buffers
507 * @dst_bufs: information on allocated destination buffers
508 * @sequence: counter for the sequence number for v4l2
509 * @dec_dst_flag: flags for buffers queued in the hardware
510 * @dec_src_buf_size: size of the buffer for source buffers in decoding
511 * @codec_mode: number of codec mode used by MFC hw
512 * @slice_interface: slice interface flag
513 * @loop_filter_mpeg4: loop filter for MPEG4 flag
514 * @display_delay: value of the display delay for H264
515 * @display_delay_enable: display delay for H264 enable flag
516 * @after_packed_pb: flag used to track buffer when stream is in
517 * Packed PB format
f96f3cfa 518 * @sei_fp_parse: enable/disable parsing of frame packing SEI information
af935746
KD		 519 * @dpb_count: count of the DPB buffers required by MFC hw
520 * @total_dpb_count: count of DPB buffers with additional buffers
521 * requested by the application
8f532a7f
AK		 522 * @ctx: context buffer information
523 * @dsc: descriptor buffer information
524 * @shm: shared memory buffer information
f96f3cfa 525 * @mv_count: number of MV buffers allocated for decoding
af935746
KD		 526 * @enc_params: encoding parameters for MFC
527 * @enc_dst_buf_size: size of the buffers for encoder output
f96f3cfa
JP		 528 * @luma_dpb_size: dpb buffer size for luma
529 * @chroma_dpb_size: dpb buffer size for chroma
530 * @me_buffer_size: size of the motion estimation buffer
531 * @tmv_buffer_size: size of temporal predictor motion vector buffer
af935746
KD		 532 * @frame_type: used to force the type of the next encoded frame
533 * @ref_queue: list of the reference buffers for encoding
534 * @ref_queue_cnt: number of the buffers in the reference list
535 * @c_ops: ops for encoding
536 * @ctrls: array of controls, used when adding controls to the
537 * v4l2 control framework
538 * @ctrl_handler: handler for v4l2 framework
539 */
540struct s5p_mfc_ctx {
541 struct s5p_mfc_dev *dev;
542 struct v4l2_fh fh;
543
544 int num;
545
546 int int_cond;
547 int int_type;
548 unsigned int int_err;
549 wait_queue_head_t queue;
550
551 struct s5p_mfc_fmt *src_fmt;
552 struct s5p_mfc_fmt *dst_fmt;
553
554 struct vb2_queue vq_src;
555 struct vb2_queue vq_dst;
556
557 struct list_head src_queue;
558 struct list_head dst_queue;
559
560 unsigned int src_queue_cnt;
561 unsigned int dst_queue_cnt;
562
563 enum s5p_mfc_inst_type type;
564 enum s5p_mfc_inst_state state;
565 int inst_no;
566
567 /* Image parameters */
568 int img_width;
569 int img_height;
570 int buf_width;
571 int buf_height;
572
573 int luma_size;
574 int chroma_size;
575 int mv_size;
576
577 unsigned long consumed_stream;
578
579 unsigned int dpb_flush_flag;
f96f3cfa 580 unsigned int head_processed;
af935746 581
317b4ca4
KD		 582 struct s5p_mfc_priv_buf bank1;
583 struct s5p_mfc_priv_buf bank2;
af935746
KD		 584
585 enum s5p_mfc_queue_state capture_state;
586 enum s5p_mfc_queue_state output_state;
587
588 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
589 int src_bufs_cnt;
590 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
591 int dst_bufs_cnt;
592
593 unsigned int sequence;
594 unsigned long dec_dst_flag;
595 size_t dec_src_buf_size;
596
597 /* Control values */
598 int codec_mode;
599 int slice_interface;
600 int loop_filter_mpeg4;
601 int display_delay;
602 int display_delay_enable;
603 int after_packed_pb;
f96f3cfa 604 int sei_fp_parse;
af935746 605
e9d98ddc 606 int pb_count;
af935746 607 int total_dpb_count;
f96f3cfa 608 int mv_count;
af935746 609 /* Buffers */
8f532a7f
AK		 610 struct s5p_mfc_priv_buf ctx;
611 struct s5p_mfc_priv_buf dsc;
612 struct s5p_mfc_priv_buf shm;
af935746
KD		 613
614 struct s5p_mfc_enc_params enc_params;
615
616 size_t enc_dst_buf_size;
f96f3cfa
JP		 617 size_t luma_dpb_size;
618 size_t chroma_dpb_size;
619 size_t me_buffer_size;
620 size_t tmv_buffer_size;
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KD		 621
622 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
623
624 struct list_head ref_queue;
625 unsigned int ref_queue_cnt;
626
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JP		 627 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
628 union {
629 unsigned int mb;
630 unsigned int bits;
631 } slice_size;
632
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KD		 633 struct s5p_mfc_codec_ops *c_ops;
634
635 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
636 struct v4l2_ctrl_handler ctrl_handler;
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JP		 637 unsigned int frame_tag;
638 size_t scratch_buf_size;
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KD		 639};
640
641/*
642 * struct s5p_mfc_fmt - structure used to store information about pixelformats
643 * used by the MFC
644 */
645struct s5p_mfc_fmt {
646 char *name;
647 u32 fourcc;
648 u32 codec_mode;
649 enum s5p_mfc_fmt_type type;
650 u32 num_planes;
651};
652
653/**
654 * struct mfc_control - structure used to store information about MFC controls
655 * it is used to initialize the control framework.
656 */
657struct mfc_control {
658 __u32 id;
659 enum v4l2_ctrl_type type;
660 __u8 name[32]; /* Whatever */
661 __s32 minimum; /* Note signedness */
662 __s32 maximum;
663 __s32 step;
664 __u32 menu_skip_mask;
665 __s32 default_value;
666 __u32 flags;
667 __u32 reserved[2];
668 __u8 is_volatile;
669};
670
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AK		 671/* Macro for making hardware specific calls */
672#define s5p_mfc_hw_call(f, op, args...) \
673 ((f && f->op) ? f->op(args) : -ENODEV)
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KD		 674
675#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
676#define ctrl_to_ctx(__ctrl) \
677 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
678
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AH		 679void clear_work_bit(struct s5p_mfc_ctx *ctx);
680void set_work_bit(struct s5p_mfc_ctx *ctx);
681void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
682void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
683
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JP		 684#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
685 (dev->variant->port_num ? 1 : 0) : 0) : 0)
686#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
722b979e 687#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
5441e9da 688#define IS_MFCV7(dev) (dev->variant->version >= 0x70 ? 1 : 0)
f96f3cfa 689
af935746 690#endif /* S5P_MFC_COMMON_H_ */
Linux 6.x block layer and io_uring tree(s)