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[media] s5p-mfc: Fix an error check
[linux-2.6-block.git] / drivers / media / platform / s5p-mfc / s5p_mfc_common.h
CommitLineData
af935746
KD		 1/*
2 * Samsung S5P Multi Format Codec v 5.0
3 *
4 * This file contains definitions of enums and structs used by the codec
5 * driver.
6 *
7 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
8 * Kamil Debski, <k.debski@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version
14 */
15
16#ifndef S5P_MFC_COMMON_H_
17#define S5P_MFC_COMMON_H_
18
af935746
KD		 19#include <linux/platform_device.h>
20#include <linux/videodev2.h>
21#include <media/v4l2-ctrls.h>
22#include <media/v4l2-device.h>
23#include <media/v4l2-ioctl.h>
24#include <media/videobuf2-core.h>
f96f3cfa
JP		 25#include "regs-mfc.h"
26#include "regs-mfc-v6.h"
af935746
KD		 27
28/* Definitions related to MFC memory */
29
30/* Offset base used to differentiate between CAPTURE and OUTPUT
31* while mmaping */
32#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
33
af935746
KD		 34#define MFC_BANK1_ALLOC_CTX 0
35#define MFC_BANK2_ALLOC_CTX 1
36
37#define MFC_BANK1_ALIGN_ORDER 13
38#define MFC_BANK2_ALIGN_ORDER 13
39#define MFC_BASE_ALIGN_ORDER 17
40
41#include <media/videobuf2-dma-contig.h>
42
43static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
44{
45 /* Same functionality as the vb2_dma_contig_plane_paddr */
46 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
47
48 return *paddr;
49}
50
51/* MFC definitions */
52#define MFC_MAX_EXTRA_DPB 5
53#define MFC_MAX_BUFFERS 32
54#define MFC_NUM_CONTEXTS 4
55/* Interrupt timeout */
56#define MFC_INT_TIMEOUT 2000
57/* Busy wait timeout */
58#define MFC_BW_TIMEOUT 500
59/* Watchdog interval */
60#define MFC_WATCHDOG_INTERVAL 1000
61/* After how many executions watchdog should assume lock up */
62#define MFC_WATCHDOG_CNT 10
63#define MFC_NO_INSTANCE_SET -1
64#define MFC_ENC_CAP_PLANE_COUNT 1
65#define MFC_ENC_OUT_PLANE_COUNT 2
66#define STUFF_BYTE 4
43a1ea1f
AK		 67#define MFC_MAX_CTRLS 70
68
69#define S5P_MFC_CODEC_NONE -1
70#define S5P_MFC_CODEC_H264_DEC 0
71#define S5P_MFC_CODEC_H264_MVC_DEC 1
72#define S5P_MFC_CODEC_VC1_DEC 2
73#define S5P_MFC_CODEC_MPEG4_DEC 3
74#define S5P_MFC_CODEC_MPEG2_DEC 4
75#define S5P_MFC_CODEC_H263_DEC 5
76#define S5P_MFC_CODEC_VC1RCV_DEC 6
77#define S5P_MFC_CODEC_VP8_DEC 7
78
79#define S5P_MFC_CODEC_H264_ENC 20
80#define S5P_MFC_CODEC_H264_MVC_ENC 21
81#define S5P_MFC_CODEC_MPEG4_ENC 22
82#define S5P_MFC_CODEC_H263_ENC 23
83
84#define S5P_MFC_R2H_CMD_EMPTY 0
85#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
86#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
87#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
88#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
89#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
90#define S5P_MFC_R2H_CMD_SLEEP_RET 7
91#define S5P_MFC_R2H_CMD_WAKEUP_RET 8
92#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
93#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
94#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
95#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
96#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
97#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
98#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
99#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
100#define S5P_MFC_R2H_CMD_ERR_RET 32
af935746
KD		 101
102#define mfc_read(dev, offset) readl(dev->regs_base + (offset))
103#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
104 (offset))
105
106/**
107 * enum s5p_mfc_fmt_type - type of the pixelformat
108 */
109enum s5p_mfc_fmt_type {
110 MFC_FMT_DEC,
111 MFC_FMT_ENC,
112 MFC_FMT_RAW,
113};
114
115/**
116 * enum s5p_mfc_node_type - The type of an MFC device node.
117 */
118enum s5p_mfc_node_type {
119 MFCNODE_INVALID = -1,
120 MFCNODE_DECODER = 0,
121 MFCNODE_ENCODER = 1,
122};
123
124/**
125 * enum s5p_mfc_inst_type - The type of an MFC instance.
126 */
127enum s5p_mfc_inst_type {
128 MFCINST_INVALID,
129 MFCINST_DECODER,
130 MFCINST_ENCODER,
131};
132
133/**
134 * enum s5p_mfc_inst_state - The state of an MFC instance.
135 */
136enum s5p_mfc_inst_state {
137 MFCINST_FREE = 0,
138 MFCINST_INIT = 100,
139 MFCINST_GOT_INST,
140 MFCINST_HEAD_PARSED,
141 MFCINST_BUFS_SET,
142 MFCINST_RUNNING,
143 MFCINST_FINISHING,
144 MFCINST_FINISHED,
145 MFCINST_RETURN_INST,
146 MFCINST_ERROR,
147 MFCINST_ABORT,
8f23cc02 148 MFCINST_FLUSH,
af935746
KD		 149 MFCINST_RES_CHANGE_INIT,
150 MFCINST_RES_CHANGE_FLUSH,
151 MFCINST_RES_CHANGE_END,
152};
153
154/**
155 * enum s5p_mfc_queue_state - The state of buffer queue.
156 */
157enum s5p_mfc_queue_state {
158 QUEUE_FREE,
159 QUEUE_BUFS_REQUESTED,
160 QUEUE_BUFS_QUERIED,
161 QUEUE_BUFS_MMAPED,
162};
163
164/**
165 * enum s5p_mfc_decode_arg - type of frame decoding
166 */
167enum s5p_mfc_decode_arg {
168 MFC_DEC_FRAME,
169 MFC_DEC_LAST_FRAME,
170 MFC_DEC_RES_CHANGE,
171};
172
f9f715a9
AH		 173#define MFC_BUF_FLAG_USED (1 << 0)
174#define MFC_BUF_FLAG_EOS (1 << 1)
175
af935746
KD		 176struct s5p_mfc_ctx;
177
178/**
179 * struct s5p_mfc_buf - MFC buffer
180 */
181struct s5p_mfc_buf {
182 struct list_head list;
183 struct vb2_buffer *b;
184 union {
185 struct {
186 size_t luma;
187 size_t chroma;
188 } raw;
189 size_t stream;
190 } cookie;
f9f715a9 191 int flags;
af935746
KD		 192};
193
194/**
195 * struct s5p_mfc_pm - power management data structure
196 */
197struct s5p_mfc_pm {
198 struct clk *clock;
199 struct clk *clock_gate;
200 atomic_t power;
201 struct device *device;
202};
203
8f532a7f
AK		 204struct s5p_mfc_buf_size_v5 {
205 unsigned int h264_ctx;
206 unsigned int non_h264_ctx;
207 unsigned int dsc;
208 unsigned int shm;
209};
210
f96f3cfa
JP		 211struct s5p_mfc_buf_size_v6 {
212 unsigned int dev_ctx;
213 unsigned int h264_dec_ctx;
214 unsigned int other_dec_ctx;
215 unsigned int h264_enc_ctx;
216 unsigned int other_enc_ctx;
217};
218
8f532a7f
AK		 219struct s5p_mfc_buf_size {
220 unsigned int fw;
221 unsigned int cpb;
222 void *priv;
223};
224
225struct s5p_mfc_buf_align {
226 unsigned int base;
227};
228
229struct s5p_mfc_variant {
230 unsigned int version;
231 unsigned int port_num;
232 struct s5p_mfc_buf_size *buf_size;
233 struct s5p_mfc_buf_align *buf_align;
f96f3cfa
JP		 234 char *mclk_name;
235 char *fw_name;
8f532a7f
AK		 236};
237
238/**
239 * struct s5p_mfc_priv_buf - represents internal used buffer
240 * @alloc: allocation-specific context for each buffer
241 * (videobuf2 allocator)
242 * @ofs: offset of each buffer, will be used for MFC
243 * @virt: kernel virtual address, only valid when the
244 * buffer accessed by driver
245 * @dma: DMA address, only valid when kernel DMA API used
246 * @size: size of the buffer
247 */
248struct s5p_mfc_priv_buf {
249 void *alloc;
250 unsigned long ofs;
251 void *virt;
252 dma_addr_t dma;
253 size_t size;
254};
255
af935746
KD		 256/**
257 * struct s5p_mfc_dev - The struct containing driver internal parameters.
258 *
259 * @v4l2_dev: v4l2_device
260 * @vfd_dec: video device for decoding
261 * @vfd_enc: video device for encoding
262 * @plat_dev: platform device
263 * @mem_dev_l: child device of the left memory bank (0)
264 * @mem_dev_r: child device of the right memory bank (1)
265 * @regs_base: base address of the MFC hw registers
266 * @irq: irq resource
af935746
KD		 267 * @dec_ctrl_handler: control framework handler for decoding
268 * @enc_ctrl_handler: control framework handler for encoding
269 * @pm: power management control
8f532a7f 270 * @variant: MFC hardware variant information
af935746
KD		 271 * @num_inst: couter of active MFC instances
272 * @irqlock: lock for operations on videobuf2 queues
273 * @condlock: lock for changing/checking if a context is ready to be
274 * processed
275 * @mfc_mutex: lock for video_device
276 * @int_cond: variable used by the waitqueue
277 * @int_type: type of last interrupt
278 * @int_err: error number for last interrupt
279 * @queue: waitqueue for waiting for completion of device commands
280 * @fw_size: size of firmware
281 * @bank1: address of the beggining of bank 1 memory
282 * @bank2: address of the beggining of bank 2 memory
283 * @hw_lock: used for hardware locking
284 * @ctx: array of driver contexts
285 * @curr_ctx: number of the currently running context
286 * @ctx_work_bits: used to mark which contexts are waiting for hardware
287 * @watchdog_cnt: counter for the watchdog
288 * @watchdog_workqueue: workqueue for the watchdog
289 * @watchdog_work: worker for the watchdog
290 * @alloc_ctx: videobuf2 allocator contexts for two memory banks
291 * @enter_suspend: flag set when entering suspend
f96f3cfa 292 * @ctx_buf: common context memory (MFCv6)
43a1ea1f
AK		 293 * @warn_start: hardware error code from which warnings start
294 * @mfc_ops: ops structure holding HW operation function pointers
295 * @mfc_cmds: cmd structure holding HW commands function pointers
af935746
KD		 296 *
297 */
298struct s5p_mfc_dev {
299 struct v4l2_device v4l2_dev;
300 struct video_device *vfd_dec;
301 struct video_device *vfd_enc;
302 struct platform_device *plat_dev;
303 struct device *mem_dev_l;
304 struct device *mem_dev_r;
305 void __iomem *regs_base;
306 int irq;
af935746
KD		 307 struct v4l2_ctrl_handler dec_ctrl_handler;
308 struct v4l2_ctrl_handler enc_ctrl_handler;
309 struct s5p_mfc_pm pm;
8f532a7f 310 struct s5p_mfc_variant *variant;
af935746
KD		 311 int num_inst;
312 spinlock_t irqlock; /* lock when operating on videobuf2 queues */
313 spinlock_t condlock; /* lock when changing/checking if a context is
314 ready to be processed */
315 struct mutex mfc_mutex; /* video_device lock */
316 int int_cond;
317 int int_type;
318 unsigned int int_err;
319 wait_queue_head_t queue;
320 size_t fw_size;
321 size_t bank1;
322 size_t bank2;
323 unsigned long hw_lock;
324 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
325 int curr_ctx;
326 unsigned long ctx_work_bits;
327 atomic_t watchdog_cnt;
328 struct timer_list watchdog_timer;
329 struct workqueue_struct *watchdog_workqueue;
330 struct work_struct watchdog_work;
331 void *alloc_ctx[2];
332 unsigned long enter_suspend;
43a1ea1f 333
f96f3cfa 334 struct s5p_mfc_priv_buf ctx_buf;
43a1ea1f
AK		 335 int warn_start;
336 struct s5p_mfc_hw_ops *mfc_ops;
337 struct s5p_mfc_hw_cmds *mfc_cmds;
af935746
KD		 338};
339
340/**
341 * struct s5p_mfc_h264_enc_params - encoding parameters for h264
342 */
343struct s5p_mfc_h264_enc_params {
344 enum v4l2_mpeg_video_h264_profile profile;
345 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
346 s8 loop_filter_alpha;
347 s8 loop_filter_beta;
348 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
349 u8 max_ref_pic;
350 u8 num_ref_pic_4p;
351 int _8x8_transform;
af935746
KD		 352 int rc_mb_dark;
353 int rc_mb_smooth;
354 int rc_mb_static;
355 int rc_mb_activity;
356 int vui_sar;
357 u8 vui_sar_idc;
358 u16 vui_ext_sar_width;
359 u16 vui_ext_sar_height;
360 int open_gop;
361 u16 open_gop_size;
362 u8 rc_frame_qp;
363 u8 rc_min_qp;
364 u8 rc_max_qp;
365 u8 rc_p_frame_qp;
366 u8 rc_b_frame_qp;
367 enum v4l2_mpeg_video_h264_level level_v4l2;
368 int level;
369 u16 cpb_size;
8f532a7f 370 int interlace;
f96f3cfa
JP		 371 u8 hier_qp;
372 u8 hier_qp_type;
373 u8 hier_qp_layer;
374 u8 hier_qp_layer_qp[7];
375 u8 sei_frame_packing;
376 u8 sei_fp_curr_frame_0;
377 u8 sei_fp_arrangement_type;
378
379 u8 fmo;
380 u8 fmo_map_type;
381 u8 fmo_slice_grp;
382 u8 fmo_chg_dir;
383 u32 fmo_chg_rate;
384 u32 fmo_run_len[4];
385 u8 aso;
386 u32 aso_slice_order[8];
af935746
KD		 387};
388
389/**
390 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
391 */
392struct s5p_mfc_mpeg4_enc_params {
393 /* MPEG4 Only */
394 enum v4l2_mpeg_video_mpeg4_profile profile;
395 int quarter_pixel;
396 /* Common for MPEG4, H263 */
397 u16 vop_time_res;
398 u16 vop_frm_delta;
399 u8 rc_frame_qp;
400 u8 rc_min_qp;
401 u8 rc_max_qp;
402 u8 rc_p_frame_qp;
403 u8 rc_b_frame_qp;
404 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
405 int level;
406};
407
408/**
409 * struct s5p_mfc_enc_params - general encoding parameters
410 */
411struct s5p_mfc_enc_params {
412 u16 width;
413 u16 height;
414
415 u16 gop_size;
416 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
417 u16 slice_mb;
418 u32 slice_bit;
419 u16 intra_refresh_mb;
420 int pad;
421 u8 pad_luma;
422 u8 pad_cb;
423 u8 pad_cr;
424 int rc_frame;
8f532a7f 425 int rc_mb;
af935746
KD		 426 u32 rc_bitrate;
427 u16 rc_reaction_coeff;
428 u16 vbv_size;
f96f3cfa 429 u32 vbv_delay;
af935746
KD		 430
431 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
432 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
433 int fixed_target_bit;
434
435 u8 num_b_frame;
436 u32 rc_framerate_num;
437 u32 rc_framerate_denom;
af935746
KD		 438
439 union {
440 struct s5p_mfc_h264_enc_params h264;
441 struct s5p_mfc_mpeg4_enc_params mpeg4;
442 } codec;
443
444};
445
446/**
447 * struct s5p_mfc_codec_ops - codec ops, used by encoding
448 */
449struct s5p_mfc_codec_ops {
450 /* initialization routines */
451 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
452 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
453 /* execution routines */
454 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
455 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
456};
457
458#define call_cop(c, op, args...) \
459 (((c)->c_ops->op) ? \
460 ((c)->c_ops->op(args)) : 0)
461
462/**
463 * struct s5p_mfc_ctx - This struct contains the instance context
464 *
465 * @dev: pointer to the s5p_mfc_dev of the device
466 * @fh: struct v4l2_fh
467 * @num: number of the context that this structure describes
468 * @int_cond: variable used by the waitqueue
469 * @int_type: type of the last interrupt
470 * @int_err: error number received from MFC hw in the interrupt
471 * @queue: waitqueue that can be used to wait for this context to
472 * finish
473 * @src_fmt: source pixelformat information
474 * @dst_fmt: destination pixelformat information
475 * @vq_src: vb2 queue for source buffers
476 * @vq_dst: vb2 queue for destination buffers
477 * @src_queue: driver internal queue for source buffers
478 * @dst_queue: driver internal queue for destination buffers
479 * @src_queue_cnt: number of buffers queued on the source internal queue
480 * @dst_queue_cnt: number of buffers queued on the dest internal queue
481 * @type: type of the instance - decoder or encoder
482 * @state: state of the context
483 * @inst_no: number of hw instance associated with the context
484 * @img_width: width of the image that is decoded or encoded
485 * @img_height: height of the image that is decoded or encoded
486 * @buf_width: width of the buffer for processed image
487 * @buf_height: height of the buffer for processed image
488 * @luma_size: size of a luma plane
489 * @chroma_size: size of a chroma plane
490 * @mv_size: size of a motion vectors buffer
491 * @consumed_stream: number of bytes that have been used so far from the
492 * decoding buffer
493 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
494 * flushed
f96f3cfa
JP		 495 * @head_processed: flag mentioning whether the header data is processed
496 * completely or not
af935746
KD		 497 * @bank1_buf: handle to memory allocated for temporary buffers from
498 * memory bank 1
499 * @bank1_phys: address of the temporary buffers from memory bank 1
500 * @bank1_size: size of the memory allocated for temporary buffers from
501 * memory bank 1
502 * @bank2_buf: handle to memory allocated for temporary buffers from
503 * memory bank 2
504 * @bank2_phys: address of the temporary buffers from memory bank 2
505 * @bank2_size: size of the memory allocated for temporary buffers from
506 * memory bank 2
507 * @capture_state: state of the capture buffers queue
508 * @output_state: state of the output buffers queue
509 * @src_bufs: information on allocated source buffers
510 * @dst_bufs: information on allocated destination buffers
511 * @sequence: counter for the sequence number for v4l2
512 * @dec_dst_flag: flags for buffers queued in the hardware
513 * @dec_src_buf_size: size of the buffer for source buffers in decoding
514 * @codec_mode: number of codec mode used by MFC hw
515 * @slice_interface: slice interface flag
516 * @loop_filter_mpeg4: loop filter for MPEG4 flag
517 * @display_delay: value of the display delay for H264
518 * @display_delay_enable: display delay for H264 enable flag
519 * @after_packed_pb: flag used to track buffer when stream is in
520 * Packed PB format
f96f3cfa 521 * @sei_fp_parse: enable/disable parsing of frame packing SEI information
af935746
KD		 522 * @dpb_count: count of the DPB buffers required by MFC hw
523 * @total_dpb_count: count of DPB buffers with additional buffers
524 * requested by the application
8f532a7f
AK		 525 * @ctx: context buffer information
526 * @dsc: descriptor buffer information
527 * @shm: shared memory buffer information
f96f3cfa 528 * @mv_count: number of MV buffers allocated for decoding
af935746
KD		 529 * @enc_params: encoding parameters for MFC
530 * @enc_dst_buf_size: size of the buffers for encoder output
f96f3cfa
JP		 531 * @luma_dpb_size: dpb buffer size for luma
532 * @chroma_dpb_size: dpb buffer size for chroma
533 * @me_buffer_size: size of the motion estimation buffer
534 * @tmv_buffer_size: size of temporal predictor motion vector buffer
af935746
KD		 535 * @frame_type: used to force the type of the next encoded frame
536 * @ref_queue: list of the reference buffers for encoding
537 * @ref_queue_cnt: number of the buffers in the reference list
538 * @c_ops: ops for encoding
539 * @ctrls: array of controls, used when adding controls to the
540 * v4l2 control framework
541 * @ctrl_handler: handler for v4l2 framework
542 */
543struct s5p_mfc_ctx {
544 struct s5p_mfc_dev *dev;
545 struct v4l2_fh fh;
546
547 int num;
548
549 int int_cond;
550 int int_type;
551 unsigned int int_err;
552 wait_queue_head_t queue;
553
554 struct s5p_mfc_fmt *src_fmt;
555 struct s5p_mfc_fmt *dst_fmt;
556
557 struct vb2_queue vq_src;
558 struct vb2_queue vq_dst;
559
560 struct list_head src_queue;
561 struct list_head dst_queue;
562
563 unsigned int src_queue_cnt;
564 unsigned int dst_queue_cnt;
565
566 enum s5p_mfc_inst_type type;
567 enum s5p_mfc_inst_state state;
568 int inst_no;
569
570 /* Image parameters */
571 int img_width;
572 int img_height;
573 int buf_width;
574 int buf_height;
575
576 int luma_size;
577 int chroma_size;
578 int mv_size;
579
580 unsigned long consumed_stream;
581
582 unsigned int dpb_flush_flag;
f96f3cfa 583 unsigned int head_processed;
af935746
KD		 584
585 /* Buffers */
586 void *bank1_buf;
587 size_t bank1_phys;
588 size_t bank1_size;
589
590 void *bank2_buf;
591 size_t bank2_phys;
592 size_t bank2_size;
593
594 enum s5p_mfc_queue_state capture_state;
595 enum s5p_mfc_queue_state output_state;
596
597 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
598 int src_bufs_cnt;
599 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
600 int dst_bufs_cnt;
601
602 unsigned int sequence;
603 unsigned long dec_dst_flag;
604 size_t dec_src_buf_size;
605
606 /* Control values */
607 int codec_mode;
608 int slice_interface;
609 int loop_filter_mpeg4;
610 int display_delay;
611 int display_delay_enable;
612 int after_packed_pb;
f96f3cfa 613 int sei_fp_parse;
af935746
KD		 614
615 int dpb_count;
616 int total_dpb_count;
f96f3cfa 617 int mv_count;
af935746 618 /* Buffers */
8f532a7f
AK		 619 struct s5p_mfc_priv_buf ctx;
620 struct s5p_mfc_priv_buf dsc;
621 struct s5p_mfc_priv_buf shm;
af935746
KD		 622
623 struct s5p_mfc_enc_params enc_params;
624
625 size_t enc_dst_buf_size;
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JP		 626 size_t luma_dpb_size;
627 size_t chroma_dpb_size;
628 size_t me_buffer_size;
629 size_t tmv_buffer_size;
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KD		 630
631 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
632
633 struct list_head ref_queue;
634 unsigned int ref_queue_cnt;
635
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JP		 636 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
637 union {
638 unsigned int mb;
639 unsigned int bits;
640 } slice_size;
641
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KD		 642 struct s5p_mfc_codec_ops *c_ops;
643
644 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
645 struct v4l2_ctrl_handler ctrl_handler;
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JP		 646 unsigned int frame_tag;
647 size_t scratch_buf_size;
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KD		 648};
649
650/*
651 * struct s5p_mfc_fmt - structure used to store information about pixelformats
652 * used by the MFC
653 */
654struct s5p_mfc_fmt {
655 char *name;
656 u32 fourcc;
657 u32 codec_mode;
658 enum s5p_mfc_fmt_type type;
659 u32 num_planes;
660};
661
662/**
663 * struct mfc_control - structure used to store information about MFC controls
664 * it is used to initialize the control framework.
665 */
666struct mfc_control {
667 __u32 id;
668 enum v4l2_ctrl_type type;
669 __u8 name[32]; /* Whatever */
670 __s32 minimum; /* Note signedness */
671 __s32 maximum;
672 __s32 step;
673 __u32 menu_skip_mask;
674 __s32 default_value;
675 __u32 flags;
676 __u32 reserved[2];
677 __u8 is_volatile;
678};
679
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AK		 680/* Macro for making hardware specific calls */
681#define s5p_mfc_hw_call(f, op, args...) \
682 ((f && f->op) ? f->op(args) : -ENODEV)
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KD		 683
684#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
685#define ctrl_to_ctx(__ctrl) \
686 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
687
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AH		 688void clear_work_bit(struct s5p_mfc_ctx *ctx);
689void set_work_bit(struct s5p_mfc_ctx *ctx);
690void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
691void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
692
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JP		 693#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
694 (dev->variant->port_num ? 1 : 0) : 0) : 0)
695#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
696#define IS_MFCV6(dev) (dev->variant->version >= 0x60 ? 1 : 0)
697
af935746 698#endif /* S5P_MFC_COMMON_H_ */
Linux 6.x block layer and io_uring tree(s)