Commit | Line | Data |
---|---|---|
af935746 KD |
1 | /* |
2 | * Samsung S5P Multi Format Codec v 5.1 | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * Kamil Debski, <k.debski@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/slab.h> | |
af935746 | 21 | #include <linux/videodev2.h> |
f9f715a9 | 22 | #include <media/v4l2-event.h> |
af935746 | 23 | #include <linux/workqueue.h> |
b27a23be | 24 | #include <linux/of.h> |
4a5ab64c | 25 | #include <linux/of_device.h> |
c79667dd | 26 | #include <linux/of_reserved_mem.h> |
c139990e | 27 | #include <media/videobuf2-v4l2.h> |
43a1ea1f | 28 | #include "s5p_mfc_common.h" |
af935746 KD |
29 | #include "s5p_mfc_ctrl.h" |
30 | #include "s5p_mfc_debug.h" | |
31 | #include "s5p_mfc_dec.h" | |
32 | #include "s5p_mfc_enc.h" | |
33 | #include "s5p_mfc_intr.h" | |
04f77673 | 34 | #include "s5p_mfc_iommu.h" |
43a1ea1f AK |
35 | #include "s5p_mfc_opr.h" |
36 | #include "s5p_mfc_cmd.h" | |
af935746 | 37 | #include "s5p_mfc_pm.h" |
af935746 | 38 | |
af935746 KD |
39 | #define S5P_MFC_DEC_NAME "s5p-mfc-dec" |
40 | #define S5P_MFC_ENC_NAME "s5p-mfc-enc" | |
41 | ||
139adba6 MCC |
42 | int mfc_debug_level; |
43 | module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR); | |
af935746 KD |
44 | MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); |
45 | ||
25e73b42 MS |
46 | static char *mfc_mem_size; |
47 | module_param_named(mem, mfc_mem_size, charp, 0644); | |
48 | MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers"); | |
49 | ||
af935746 | 50 | /* Helper functions for interrupt processing */ |
7fb89eca | 51 | |
af935746 | 52 | /* Remove from hw execution round robin */ |
7fb89eca | 53 | void clear_work_bit(struct s5p_mfc_ctx *ctx) |
af935746 KD |
54 | { |
55 | struct s5p_mfc_dev *dev = ctx->dev; | |
56 | ||
57 | spin_lock(&dev->condlock); | |
7fb89eca | 58 | __clear_bit(ctx->num, &dev->ctx_work_bits); |
af935746 KD |
59 | spin_unlock(&dev->condlock); |
60 | } | |
61 | ||
7fb89eca AH |
62 | /* Add to hw execution round robin */ |
63 | void set_work_bit(struct s5p_mfc_ctx *ctx) | |
64 | { | |
65 | struct s5p_mfc_dev *dev = ctx->dev; | |
66 | ||
67 | spin_lock(&dev->condlock); | |
68 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
69 | spin_unlock(&dev->condlock); | |
70 | } | |
71 | ||
72 | /* Remove from hw execution round robin */ | |
73 | void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
74 | { | |
75 | struct s5p_mfc_dev *dev = ctx->dev; | |
76 | unsigned long flags; | |
77 | ||
78 | spin_lock_irqsave(&dev->condlock, flags); | |
79 | __clear_bit(ctx->num, &dev->ctx_work_bits); | |
80 | spin_unlock_irqrestore(&dev->condlock, flags); | |
81 | } | |
82 | ||
83 | /* Add to hw execution round robin */ | |
84 | void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) | |
85 | { | |
86 | struct s5p_mfc_dev *dev = ctx->dev; | |
87 | unsigned long flags; | |
88 | ||
89 | spin_lock_irqsave(&dev->condlock, flags); | |
90 | __set_bit(ctx->num, &dev->ctx_work_bits); | |
91 | spin_unlock_irqrestore(&dev->condlock, flags); | |
92 | } | |
93 | ||
05d1d0f0 AH |
94 | int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) |
95 | { | |
96 | unsigned long flags; | |
97 | int ctx; | |
98 | ||
99 | spin_lock_irqsave(&dev->condlock, flags); | |
100 | ctx = dev->curr_ctx; | |
101 | do { | |
102 | ctx = (ctx + 1) % MFC_NUM_CONTEXTS; | |
103 | if (ctx == dev->curr_ctx) { | |
104 | if (!test_bit(ctx, &dev->ctx_work_bits)) | |
105 | ctx = -EAGAIN; | |
106 | break; | |
107 | } | |
108 | } while (!test_bit(ctx, &dev->ctx_work_bits)); | |
109 | spin_unlock_irqrestore(&dev->condlock, flags); | |
110 | ||
111 | return ctx; | |
112 | } | |
113 | ||
af935746 KD |
114 | /* Wake up context wait_queue */ |
115 | static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, | |
116 | unsigned int err) | |
117 | { | |
118 | ctx->int_cond = 1; | |
119 | ctx->int_type = reason; | |
120 | ctx->int_err = err; | |
121 | wake_up(&ctx->queue); | |
122 | } | |
123 | ||
124 | /* Wake up device wait_queue */ | |
125 | static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, | |
126 | unsigned int err) | |
127 | { | |
128 | dev->int_cond = 1; | |
129 | dev->int_type = reason; | |
130 | dev->int_err = err; | |
131 | wake_up(&dev->queue); | |
132 | } | |
133 | ||
62bbd72b AH |
134 | void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq) |
135 | { | |
136 | struct s5p_mfc_buf *b; | |
137 | int i; | |
138 | ||
139 | while (!list_empty(lh)) { | |
140 | b = list_entry(lh->next, struct s5p_mfc_buf, list); | |
141 | for (i = 0; i < b->b->vb2_buf.num_planes; i++) | |
142 | vb2_set_plane_payload(&b->b->vb2_buf, i, 0); | |
143 | vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR); | |
144 | list_del(&b->list); | |
145 | } | |
146 | } | |
147 | ||
e99e88a9 | 148 | static void s5p_mfc_watchdog(struct timer_list *t) |
af935746 | 149 | { |
e99e88a9 | 150 | struct s5p_mfc_dev *dev = from_timer(dev, t, watchdog_timer); |
af935746 KD |
151 | |
152 | if (test_bit(0, &dev->hw_lock)) | |
153 | atomic_inc(&dev->watchdog_cnt); | |
154 | if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { | |
155 | /* This means that hw is busy and no interrupts were | |
156 | * generated by hw for the Nth time of running this | |
157 | * watchdog timer. This usually means a serious hw | |
158 | * error. Now it is time to kill all instances and | |
159 | * reset the MFC. */ | |
160 | mfc_err("Time out during waiting for HW\n"); | |
ed90013e | 161 | schedule_work(&dev->watchdog_work); |
af935746 KD |
162 | } |
163 | dev->watchdog_timer.expires = jiffies + | |
164 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
165 | add_timer(&dev->watchdog_timer); | |
166 | } | |
167 | ||
168 | static void s5p_mfc_watchdog_worker(struct work_struct *work) | |
169 | { | |
170 | struct s5p_mfc_dev *dev; | |
171 | struct s5p_mfc_ctx *ctx; | |
172 | unsigned long flags; | |
173 | int mutex_locked; | |
174 | int i, ret; | |
175 | ||
176 | dev = container_of(work, struct s5p_mfc_dev, watchdog_work); | |
177 | ||
178 | mfc_err("Driver timeout error handling\n"); | |
179 | /* Lock the mutex that protects open and release. | |
180 | * This is necessary as they may load and unload firmware. */ | |
181 | mutex_locked = mutex_trylock(&dev->mfc_mutex); | |
182 | if (!mutex_locked) | |
183 | mfc_err("Error: some instance may be closing/opening\n"); | |
184 | spin_lock_irqsave(&dev->irqlock, flags); | |
185 | ||
186 | s5p_mfc_clock_off(); | |
187 | ||
188 | for (i = 0; i < MFC_NUM_CONTEXTS; i++) { | |
189 | ctx = dev->ctx[i]; | |
190 | if (!ctx) | |
191 | continue; | |
192 | ctx->state = MFCINST_ERROR; | |
62bbd72b AH |
193 | s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst); |
194 | s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src); | |
af935746 | 195 | clear_work_bit(ctx); |
43a1ea1f | 196 | wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); |
af935746 KD |
197 | } |
198 | clear_bit(0, &dev->hw_lock); | |
199 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
b16e6448 AM |
200 | |
201 | /* De-init MFC */ | |
202 | s5p_mfc_deinit_hw(dev); | |
203 | ||
af935746 KD |
204 | /* Double check if there is at least one instance running. |
205 | * If no instance is in memory than no firmware should be present */ | |
206 | if (dev->num_inst > 0) { | |
46075006 | 207 | ret = s5p_mfc_load_firmware(dev); |
af935746 KD |
208 | if (ret) { |
209 | mfc_err("Failed to reload FW\n"); | |
210 | goto unlock; | |
211 | } | |
212 | s5p_mfc_clock_on(); | |
213 | ret = s5p_mfc_init_hw(dev); | |
a5cb00eb | 214 | s5p_mfc_clock_off(); |
af935746 KD |
215 | if (ret) |
216 | mfc_err("Failed to reinit FW\n"); | |
217 | } | |
218 | unlock: | |
219 | if (mutex_locked) | |
220 | mutex_unlock(&dev->mfc_mutex); | |
221 | } | |
222 | ||
af935746 KD |
223 | static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) |
224 | { | |
225 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f | 226 | struct s5p_mfc_dev *dev = ctx->dev; |
af935746 KD |
227 | |
228 | ctx->state = MFCINST_FINISHED; | |
229 | ctx->sequence++; | |
230 | while (!list_empty(&ctx->dst_queue)) { | |
231 | dst_buf = list_entry(ctx->dst_queue.next, | |
232 | struct s5p_mfc_buf, list); | |
233 | mfc_debug(2, "Cleaning up buffer: %d\n", | |
2d700715 JS |
234 | dst_buf->b->vb2_buf.index); |
235 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0); | |
236 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0); | |
af935746 | 237 | list_del(&dst_buf->list); |
4d0b0ed6 | 238 | dst_buf->flags |= MFC_BUF_FLAG_EOS; |
af935746 | 239 | ctx->dst_queue_cnt--; |
2d700715 | 240 | dst_buf->b->sequence = (ctx->sequence++); |
af935746 | 241 | |
43a1ea1f AK |
242 | if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == |
243 | s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) | |
2d700715 | 244 | dst_buf->b->field = V4L2_FIELD_NONE; |
af935746 | 245 | else |
2d700715 JS |
246 | dst_buf->b->field = V4L2_FIELD_INTERLACED; |
247 | dst_buf->b->flags |= V4L2_BUF_FLAG_LAST; | |
af935746 | 248 | |
2d700715 JS |
249 | ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index); |
250 | vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE); | |
af935746 KD |
251 | } |
252 | } | |
253 | ||
254 | static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) | |
255 | { | |
256 | struct s5p_mfc_dev *dev = ctx->dev; | |
257 | struct s5p_mfc_buf *dst_buf, *src_buf; | |
43a1ea1f AK |
258 | size_t dec_y_addr; |
259 | unsigned int frame_type; | |
260 | ||
bb21c54a | 261 | /* Make sure we actually have a new frame before continuing. */ |
43a1ea1f | 262 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); |
bb21c54a IF |
263 | if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) |
264 | return; | |
265 | dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); | |
af935746 KD |
266 | |
267 | /* Copy timestamp / timecode from decoded src to dst and set | |
bb21c54a | 268 | appropriate flags. */ |
af935746 KD |
269 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); |
270 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
2d700715 JS |
271 | if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0) |
272 | == dec_y_addr) { | |
273 | dst_buf->b->timecode = | |
274 | src_buf->b->timecode; | |
d6dd645e JS |
275 | dst_buf->b->vb2_buf.timestamp = |
276 | src_buf->b->vb2_buf.timestamp; | |
2d700715 | 277 | dst_buf->b->flags &= |
309f4d62 | 278 | ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; |
2d700715 JS |
279 | dst_buf->b->flags |= |
280 | src_buf->b->flags | |
309f4d62 | 281 | & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; |
af935746 KD |
282 | switch (frame_type) { |
283 | case S5P_FIMV_DECODE_FRAME_I_FRAME: | |
2d700715 | 284 | dst_buf->b->flags |= |
af935746 KD |
285 | V4L2_BUF_FLAG_KEYFRAME; |
286 | break; | |
287 | case S5P_FIMV_DECODE_FRAME_P_FRAME: | |
2d700715 | 288 | dst_buf->b->flags |= |
af935746 KD |
289 | V4L2_BUF_FLAG_PFRAME; |
290 | break; | |
291 | case S5P_FIMV_DECODE_FRAME_B_FRAME: | |
2d700715 | 292 | dst_buf->b->flags |= |
af935746 KD |
293 | V4L2_BUF_FLAG_BFRAME; |
294 | break; | |
bb21c54a IF |
295 | default: |
296 | /* Don't know how to handle | |
297 | S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */ | |
298 | mfc_debug(2, "Unexpected frame type: %d\n", | |
299 | frame_type); | |
af935746 KD |
300 | } |
301 | break; | |
302 | } | |
303 | } | |
304 | } | |
305 | ||
306 | static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) | |
307 | { | |
308 | struct s5p_mfc_dev *dev = ctx->dev; | |
309 | struct s5p_mfc_buf *dst_buf; | |
43a1ea1f AK |
310 | size_t dspl_y_addr; |
311 | unsigned int frame_type; | |
af935746 | 312 | |
43a1ea1f | 313 | dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); |
7c672812 SS |
314 | if (IS_MFCV6_PLUS(dev)) |
315 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, | |
316 | get_disp_frame_type, ctx); | |
317 | else | |
318 | frame_type = s5p_mfc_hw_call(dev->mfc_ops, | |
319 | get_dec_frame_type, dev); | |
43a1ea1f | 320 | |
af935746 KD |
321 | /* If frame is same as previous then skip and do not dequeue */ |
322 | if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { | |
323 | if (!ctx->after_packed_pb) | |
324 | ctx->sequence++; | |
325 | ctx->after_packed_pb = 0; | |
326 | return; | |
327 | } | |
328 | ctx->sequence++; | |
329 | /* The MFC returns address of the buffer, now we have to | |
330 | * check which videobuf does it correspond to */ | |
331 | list_for_each_entry(dst_buf, &ctx->dst_queue, list) { | |
332 | /* Check if this is the buffer we're looking for */ | |
2d700715 JS |
333 | if (vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0) |
334 | == dspl_y_addr) { | |
af935746 KD |
335 | list_del(&dst_buf->list); |
336 | ctx->dst_queue_cnt--; | |
2d700715 | 337 | dst_buf->b->sequence = ctx->sequence; |
43a1ea1f AK |
338 | if (s5p_mfc_hw_call(dev->mfc_ops, |
339 | get_pic_type_top, ctx) == | |
340 | s5p_mfc_hw_call(dev->mfc_ops, | |
341 | get_pic_type_bot, ctx)) | |
2d700715 | 342 | dst_buf->b->field = V4L2_FIELD_NONE; |
af935746 | 343 | else |
2d700715 | 344 | dst_buf->b->field = |
af935746 | 345 | V4L2_FIELD_INTERLACED; |
2d700715 JS |
346 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, |
347 | ctx->luma_size); | |
348 | vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, | |
349 | ctx->chroma_size); | |
350 | clear_bit(dst_buf->b->vb2_buf.index, | |
af935746 KD |
351 | &ctx->dec_dst_flag); |
352 | ||
2d700715 JS |
353 | vb2_buffer_done(&dst_buf->b->vb2_buf, err ? |
354 | VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); | |
af935746 | 355 | |
af935746 KD |
356 | break; |
357 | } | |
358 | } | |
359 | } | |
360 | ||
361 | /* Handle frame decoding interrupt */ | |
362 | static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, | |
363 | unsigned int reason, unsigned int err) | |
364 | { | |
365 | struct s5p_mfc_dev *dev = ctx->dev; | |
366 | unsigned int dst_frame_status; | |
a0517f5d | 367 | unsigned int dec_frame_status; |
af935746 | 368 | struct s5p_mfc_buf *src_buf; |
af935746 KD |
369 | unsigned int res_change; |
370 | ||
43a1ea1f | 371 | dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
af935746 | 372 | & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; |
a0517f5d PO |
373 | dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev) |
374 | & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; | |
f96f3cfa JP |
375 | res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) |
376 | & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) | |
377 | >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; | |
af935746 KD |
378 | mfc_debug(2, "Frame Status: %x\n", dst_frame_status); |
379 | if (ctx->state == MFCINST_RES_CHANGE_INIT) | |
380 | ctx->state = MFCINST_RES_CHANGE_FLUSH; | |
f96f3cfa JP |
381 | if (res_change == S5P_FIMV_RES_INCREASE || |
382 | res_change == S5P_FIMV_RES_DECREASE) { | |
af935746 | 383 | ctx->state = MFCINST_RES_CHANGE_INIT; |
fdd1d4b0 | 384 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 385 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 386 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 387 | s5p_mfc_clock_off(); |
fdd1d4b0 | 388 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
389 | return; |
390 | } | |
391 | if (ctx->dpb_flush_flag) | |
392 | ctx->dpb_flush_flag = 0; | |
393 | ||
af935746 KD |
394 | /* All frames remaining in the buffer have been extracted */ |
395 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { | |
396 | if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { | |
0520e4cc PO |
397 | static const struct v4l2_event ev_src_ch = { |
398 | .type = V4L2_EVENT_SOURCE_CHANGE, | |
399 | .u.src_change.changes = | |
400 | V4L2_EVENT_SRC_CH_RESOLUTION, | |
401 | }; | |
402 | ||
af935746 KD |
403 | s5p_mfc_handle_frame_all_extracted(ctx); |
404 | ctx->state = MFCINST_RES_CHANGE_END; | |
0520e4cc PO |
405 | v4l2_event_queue_fh(&ctx->fh, &ev_src_ch); |
406 | ||
af935746 KD |
407 | goto leave_handle_frame; |
408 | } else { | |
409 | s5p_mfc_handle_frame_all_extracted(ctx); | |
410 | } | |
411 | } | |
412 | ||
a0517f5d | 413 | if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) |
af935746 KD |
414 | s5p_mfc_handle_frame_copy_time(ctx); |
415 | ||
416 | /* A frame has been decoded and is in the buffer */ | |
417 | if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || | |
418 | dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { | |
419 | s5p_mfc_handle_frame_new(ctx, err); | |
420 | } else { | |
421 | mfc_debug(2, "No frame decode\n"); | |
422 | } | |
423 | /* Mark source buffer as complete */ | |
424 | if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY | |
425 | && !list_empty(&ctx->src_queue)) { | |
426 | src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, | |
427 | list); | |
43a1ea1f AK |
428 | ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, |
429 | get_consumed_stream, dev); | |
430 | if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && | |
f49f3ed5 | 431 | ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC && |
d2a0db1e | 432 | ctx->consumed_stream + STUFF_BYTE < |
2d700715 | 433 | src_buf->b->vb2_buf.planes[0].bytesused) { |
af935746 KD |
434 | /* Run MFC again on the same buffer */ |
435 | mfc_debug(2, "Running again the same buffer\n"); | |
436 | ctx->after_packed_pb = 1; | |
437 | } else { | |
af935746 KD |
438 | mfc_debug(2, "MFC needs next buffer\n"); |
439 | ctx->consumed_stream = 0; | |
a34026e7 KD |
440 | if (src_buf->flags & MFC_BUF_FLAG_EOS) |
441 | ctx->state = MFCINST_FINISHING; | |
af935746 KD |
442 | list_del(&src_buf->list); |
443 | ctx->src_queue_cnt--; | |
43a1ea1f | 444 | if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) |
2d700715 JS |
445 | vb2_buffer_done(&src_buf->b->vb2_buf, |
446 | VB2_BUF_STATE_ERROR); | |
af935746 | 447 | else |
2d700715 JS |
448 | vb2_buffer_done(&src_buf->b->vb2_buf, |
449 | VB2_BUF_STATE_DONE); | |
af935746 KD |
450 | } |
451 | } | |
452 | leave_handle_frame: | |
af935746 | 453 | if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) |
e9d98ddc | 454 | || ctx->dst_queue_cnt < ctx->pb_count) |
af935746 | 455 | clear_work_bit(ctx); |
fdd1d4b0 | 456 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 457 | wake_up_ctx(ctx, reason, err); |
9a7bc6b0 | 458 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 459 | s5p_mfc_clock_off(); |
76a4ddbd P |
460 | /* if suspending, wake up device and do not try_run again*/ |
461 | if (test_bit(0, &dev->enter_suspend)) | |
462 | wake_up_dev(dev, reason, err); | |
463 | else | |
fdd1d4b0 | 464 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
465 | } |
466 | ||
467 | /* Error handling for interrupt */ | |
7296e25f KD |
468 | static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, |
469 | struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) | |
af935746 | 470 | { |
af935746 | 471 | mfc_err("Interrupt Error: %08x\n", err); |
af935746 | 472 | |
4449dd0a | 473 | if (ctx) { |
7296e25f KD |
474 | /* Error recovery is dependent on the state of context */ |
475 | switch (ctx->state) { | |
476 | case MFCINST_RES_CHANGE_INIT: | |
477 | case MFCINST_RES_CHANGE_FLUSH: | |
478 | case MFCINST_RES_CHANGE_END: | |
479 | case MFCINST_FINISHING: | |
480 | case MFCINST_FINISHED: | |
481 | case MFCINST_RUNNING: | |
39c1cb2b | 482 | /* It is highly probable that an error occurred |
7296e25f KD |
483 | * while decoding a frame */ |
484 | clear_work_bit(ctx); | |
485 | ctx->state = MFCINST_ERROR; | |
486 | /* Mark all dst buffers as having an error */ | |
62bbd72b | 487 | s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst); |
7296e25f | 488 | /* Mark all src buffers as having an error */ |
62bbd72b | 489 | s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src); |
7296e25f KD |
490 | wake_up_ctx(ctx, reason, err); |
491 | break; | |
492 | default: | |
493 | clear_work_bit(ctx); | |
494 | ctx->state = MFCINST_ERROR; | |
495 | wake_up_ctx(ctx, reason, err); | |
496 | break; | |
497 | } | |
af935746 | 498 | } |
9a7bc6b0 | 499 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
fdd1d4b0 | 500 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
7296e25f KD |
501 | s5p_mfc_clock_off(); |
502 | wake_up_dev(dev, reason, err); | |
af935746 KD |
503 | } |
504 | ||
505 | /* Header parsing interrupt handling */ | |
506 | static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, | |
507 | unsigned int reason, unsigned int err) | |
508 | { | |
509 | struct s5p_mfc_dev *dev; | |
af935746 | 510 | |
4449dd0a | 511 | if (!ctx) |
af935746 KD |
512 | return; |
513 | dev = ctx->dev; | |
514 | if (ctx->c_ops->post_seq_start) { | |
515 | if (ctx->c_ops->post_seq_start(ctx)) | |
516 | mfc_err("post_seq_start() failed\n"); | |
517 | } else { | |
43a1ea1f AK |
518 | ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, |
519 | dev); | |
520 | ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, | |
521 | dev); | |
af935746 | 522 | |
fdd1d4b0 | 523 | s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); |
8f532a7f | 524 | |
e9d98ddc | 525 | ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, |
43a1ea1f | 526 | dev); |
f96f3cfa JP |
527 | ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, |
528 | dev); | |
bb869368 | 529 | if (ctx->img_width == 0 || ctx->img_height == 0) |
af935746 KD |
530 | ctx->state = MFCINST_ERROR; |
531 | else | |
532 | ctx->state = MFCINST_HEAD_PARSED; | |
f96f3cfa JP |
533 | |
534 | if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || | |
535 | ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && | |
536 | !list_empty(&ctx->src_queue)) { | |
537 | struct s5p_mfc_buf *src_buf; | |
538 | src_buf = list_entry(ctx->src_queue.next, | |
539 | struct s5p_mfc_buf, list); | |
540 | if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, | |
541 | dev) < | |
2d700715 | 542 | src_buf->b->vb2_buf.planes[0].bytesused) |
f96f3cfa JP |
543 | ctx->head_processed = 0; |
544 | else | |
545 | ctx->head_processed = 1; | |
546 | } else { | |
547 | ctx->head_processed = 1; | |
548 | } | |
af935746 | 549 | } |
fdd1d4b0 | 550 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 551 | clear_work_bit(ctx); |
9a7bc6b0 | 552 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 553 | s5p_mfc_clock_off(); |
fdd1d4b0 | 554 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
555 | wake_up_ctx(ctx, reason, err); |
556 | } | |
557 | ||
558 | /* Header parsing interrupt handling */ | |
559 | static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, | |
560 | unsigned int reason, unsigned int err) | |
561 | { | |
562 | struct s5p_mfc_buf *src_buf; | |
563 | struct s5p_mfc_dev *dev; | |
af935746 | 564 | |
4449dd0a | 565 | if (!ctx) |
af935746 KD |
566 | return; |
567 | dev = ctx->dev; | |
fdd1d4b0 | 568 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
569 | ctx->int_type = reason; |
570 | ctx->int_err = err; | |
571 | ctx->int_cond = 1; | |
7fb89eca | 572 | clear_work_bit(ctx); |
af935746 KD |
573 | if (err == 0) { |
574 | ctx->state = MFCINST_RUNNING; | |
f96f3cfa | 575 | if (!ctx->dpb_flush_flag && ctx->head_processed) { |
af935746 KD |
576 | if (!list_empty(&ctx->src_queue)) { |
577 | src_buf = list_entry(ctx->src_queue.next, | |
578 | struct s5p_mfc_buf, list); | |
579 | list_del(&src_buf->list); | |
580 | ctx->src_queue_cnt--; | |
2d700715 | 581 | vb2_buffer_done(&src_buf->b->vb2_buf, |
af935746 KD |
582 | VB2_BUF_STATE_DONE); |
583 | } | |
af935746 KD |
584 | } else { |
585 | ctx->dpb_flush_flag = 0; | |
586 | } | |
9a7bc6b0 | 587 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 KD |
588 | |
589 | s5p_mfc_clock_off(); | |
590 | ||
591 | wake_up(&ctx->queue); | |
fdd1d4b0 | 592 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 | 593 | } else { |
9a7bc6b0 | 594 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 KD |
595 | |
596 | s5p_mfc_clock_off(); | |
597 | ||
598 | wake_up(&ctx->queue); | |
599 | } | |
600 | } | |
601 | ||
96c57776 | 602 | static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx) |
f9f715a9 AH |
603 | { |
604 | struct s5p_mfc_dev *dev = ctx->dev; | |
605 | struct s5p_mfc_buf *mb_entry; | |
606 | ||
4130eabc | 607 | mfc_debug(2, "Stream completed\n"); |
f9f715a9 | 608 | |
f9f715a9 AH |
609 | ctx->state = MFCINST_FINISHED; |
610 | ||
f9f715a9 AH |
611 | if (!list_empty(&ctx->dst_queue)) { |
612 | mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, | |
613 | list); | |
614 | list_del(&mb_entry->list); | |
615 | ctx->dst_queue_cnt--; | |
2d700715 JS |
616 | vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0); |
617 | vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE); | |
f9f715a9 | 618 | } |
f9f715a9 AH |
619 | |
620 | clear_work_bit(ctx); | |
621 | ||
e8256447 | 622 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
f9f715a9 AH |
623 | |
624 | s5p_mfc_clock_off(); | |
625 | wake_up(&ctx->queue); | |
fdd1d4b0 | 626 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
f9f715a9 AH |
627 | } |
628 | ||
af935746 KD |
629 | /* Interrupt processing */ |
630 | static irqreturn_t s5p_mfc_irq(int irq, void *priv) | |
631 | { | |
632 | struct s5p_mfc_dev *dev = priv; | |
633 | struct s5p_mfc_ctx *ctx; | |
634 | unsigned int reason; | |
635 | unsigned int err; | |
636 | ||
637 | mfc_debug_enter(); | |
638 | /* Reset the timeout watchdog */ | |
639 | atomic_set(&dev->watchdog_cnt, 0); | |
7969b125 | 640 | spin_lock(&dev->irqlock); |
af935746 KD |
641 | ctx = dev->ctx[dev->curr_ctx]; |
642 | /* Get the reason of interrupt and the error code */ | |
43a1ea1f AK |
643 | reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); |
644 | err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); | |
af935746 KD |
645 | mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); |
646 | switch (reason) { | |
43a1ea1f | 647 | case S5P_MFC_R2H_CMD_ERR_RET: |
39c1cb2b | 648 | /* An error has occurred */ |
af935746 | 649 | if (ctx->state == MFCINST_RUNNING && |
5d1ec731 DL |
650 | (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= |
651 | dev->warn_start || | |
652 | err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR || | |
653 | err == S5P_FIMV_ERR_INCOMPLETE_FRAME || | |
654 | err == S5P_FIMV_ERR_TIMEOUT)) | |
af935746 KD |
655 | s5p_mfc_handle_frame(ctx, reason, err); |
656 | else | |
7296e25f | 657 | s5p_mfc_handle_error(dev, ctx, reason, err); |
af935746 KD |
658 | clear_bit(0, &dev->enter_suspend); |
659 | break; | |
660 | ||
43a1ea1f AK |
661 | case S5P_MFC_R2H_CMD_SLICE_DONE_RET: |
662 | case S5P_MFC_R2H_CMD_FIELD_DONE_RET: | |
663 | case S5P_MFC_R2H_CMD_FRAME_DONE_RET: | |
af935746 KD |
664 | if (ctx->c_ops->post_frame_start) { |
665 | if (ctx->c_ops->post_frame_start(ctx)) | |
666 | mfc_err("post_frame_start() failed\n"); | |
96c57776 AH |
667 | |
668 | if (ctx->state == MFCINST_FINISHING && | |
669 | list_empty(&ctx->ref_queue)) { | |
fdd1d4b0 | 670 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
96c57776 AH |
671 | s5p_mfc_handle_stream_complete(ctx); |
672 | break; | |
673 | } | |
fdd1d4b0 | 674 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
9a7bc6b0 | 675 | WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); |
af935746 | 676 | s5p_mfc_clock_off(); |
0c32b8ec | 677 | wake_up_ctx(ctx, reason, err); |
fdd1d4b0 | 678 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
af935746 KD |
679 | } else { |
680 | s5p_mfc_handle_frame(ctx, reason, err); | |
681 | } | |
682 | break; | |
683 | ||
43a1ea1f | 684 | case S5P_MFC_R2H_CMD_SEQ_DONE_RET: |
af935746 KD |
685 | s5p_mfc_handle_seq_done(ctx, reason, err); |
686 | break; | |
687 | ||
43a1ea1f AK |
688 | case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: |
689 | ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); | |
af935746 | 690 | ctx->state = MFCINST_GOT_INST; |
af935746 KD |
691 | goto irq_cleanup_hw; |
692 | ||
43a1ea1f | 693 | case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: |
9d87e837 | 694 | ctx->inst_no = MFC_NO_INSTANCE_SET; |
af935746 | 695 | ctx->state = MFCINST_FREE; |
af935746 KD |
696 | goto irq_cleanup_hw; |
697 | ||
43a1ea1f AK |
698 | case S5P_MFC_R2H_CMD_SYS_INIT_RET: |
699 | case S5P_MFC_R2H_CMD_FW_STATUS_RET: | |
700 | case S5P_MFC_R2H_CMD_SLEEP_RET: | |
701 | case S5P_MFC_R2H_CMD_WAKEUP_RET: | |
af935746 KD |
702 | if (ctx) |
703 | clear_work_bit(ctx); | |
fdd1d4b0 | 704 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
705 | clear_bit(0, &dev->hw_lock); |
706 | clear_bit(0, &dev->enter_suspend); | |
0c32b8ec | 707 | wake_up_dev(dev, reason, err); |
af935746 KD |
708 | break; |
709 | ||
43a1ea1f | 710 | case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: |
af935746 KD |
711 | s5p_mfc_handle_init_buffers(ctx, reason, err); |
712 | break; | |
f9f715a9 | 713 | |
43a1ea1f | 714 | case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: |
fdd1d4b0 | 715 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
96c57776 AH |
716 | ctx->int_type = reason; |
717 | ctx->int_err = err; | |
718 | s5p_mfc_handle_stream_complete(ctx); | |
f9f715a9 AH |
719 | break; |
720 | ||
8f23cc02 | 721 | case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: |
8f23cc02 | 722 | ctx->state = MFCINST_RUNNING; |
8f23cc02 AK |
723 | goto irq_cleanup_hw; |
724 | ||
af935746 KD |
725 | default: |
726 | mfc_debug(2, "Unknown int reason\n"); | |
fdd1d4b0 | 727 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 | 728 | } |
7969b125 | 729 | spin_unlock(&dev->irqlock); |
af935746 KD |
730 | mfc_debug_leave(); |
731 | return IRQ_HANDLED; | |
732 | irq_cleanup_hw: | |
fdd1d4b0 | 733 | s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); |
af935746 KD |
734 | ctx->int_type = reason; |
735 | ctx->int_err = err; | |
736 | ctx->int_cond = 1; | |
737 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
738 | mfc_err("Failed to unlock hw\n"); | |
739 | ||
740 | s5p_mfc_clock_off(); | |
0c32b8ec MS |
741 | clear_work_bit(ctx); |
742 | wake_up(&ctx->queue); | |
af935746 | 743 | |
fdd1d4b0 | 744 | s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); |
7969b125 | 745 | spin_unlock(&dev->irqlock); |
af935746 KD |
746 | mfc_debug(2, "Exit via irq_cleanup_hw\n"); |
747 | return IRQ_HANDLED; | |
748 | } | |
749 | ||
750 | /* Open an MFC node */ | |
751 | static int s5p_mfc_open(struct file *file) | |
752 | { | |
b80cb8dc | 753 | struct video_device *vdev = video_devdata(file); |
af935746 KD |
754 | struct s5p_mfc_dev *dev = video_drvdata(file); |
755 | struct s5p_mfc_ctx *ctx = NULL; | |
756 | struct vb2_queue *q; | |
af935746 KD |
757 | int ret = 0; |
758 | ||
759 | mfc_debug_enter(); | |
bc738301 HV |
760 | if (mutex_lock_interruptible(&dev->mfc_mutex)) |
761 | return -ERESTARTSYS; | |
af935746 KD |
762 | dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ |
763 | /* Allocate memory for context */ | |
bae061b4 | 764 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
af935746 | 765 | if (!ctx) { |
af935746 KD |
766 | ret = -ENOMEM; |
767 | goto err_alloc; | |
768 | } | |
7c96f59e | 769 | init_waitqueue_head(&ctx->queue); |
55647a99 | 770 | v4l2_fh_init(&ctx->fh, vdev); |
af935746 KD |
771 | file->private_data = &ctx->fh; |
772 | v4l2_fh_add(&ctx->fh); | |
773 | ctx->dev = dev; | |
774 | INIT_LIST_HEAD(&ctx->src_queue); | |
775 | INIT_LIST_HEAD(&ctx->dst_queue); | |
776 | ctx->src_queue_cnt = 0; | |
777 | ctx->dst_queue_cnt = 0; | |
778 | /* Get context number */ | |
779 | ctx->num = 0; | |
780 | while (dev->ctx[ctx->num]) { | |
781 | ctx->num++; | |
782 | if (ctx->num >= MFC_NUM_CONTEXTS) { | |
06f0a57f | 783 | mfc_debug(2, "Too many open contexts\n"); |
af935746 KD |
784 | ret = -EBUSY; |
785 | goto err_no_ctx; | |
786 | } | |
787 | } | |
788 | /* Mark context as idle */ | |
7fb89eca | 789 | clear_work_bit_irqsave(ctx); |
af935746 | 790 | dev->ctx[ctx->num] = ctx; |
b80cb8dc | 791 | if (vdev == dev->vfd_dec) { |
af935746 KD |
792 | ctx->type = MFCINST_DECODER; |
793 | ctx->c_ops = get_dec_codec_ops(); | |
43a1ea1f | 794 | s5p_mfc_dec_init(ctx); |
af935746 KD |
795 | /* Setup ctrl handler */ |
796 | ret = s5p_mfc_dec_ctrls_setup(ctx); | |
797 | if (ret) { | |
798 | mfc_err("Failed to setup mfc controls\n"); | |
799 | goto err_ctrls_setup; | |
800 | } | |
b80cb8dc | 801 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
802 | ctx->type = MFCINST_ENCODER; |
803 | ctx->c_ops = get_enc_codec_ops(); | |
804 | /* only for encoder */ | |
805 | INIT_LIST_HEAD(&ctx->ref_queue); | |
806 | ctx->ref_queue_cnt = 0; | |
43a1ea1f | 807 | s5p_mfc_enc_init(ctx); |
af935746 KD |
808 | /* Setup ctrl handler */ |
809 | ret = s5p_mfc_enc_ctrls_setup(ctx); | |
810 | if (ret) { | |
811 | mfc_err("Failed to setup mfc controls\n"); | |
812 | goto err_ctrls_setup; | |
813 | } | |
814 | } else { | |
815 | ret = -ENOENT; | |
816 | goto err_bad_node; | |
817 | } | |
818 | ctx->fh.ctrl_handler = &ctx->ctrl_handler; | |
9d87e837 | 819 | ctx->inst_no = MFC_NO_INSTANCE_SET; |
af935746 KD |
820 | /* Load firmware if this is the first instance */ |
821 | if (dev->num_inst == 1) { | |
822 | dev->watchdog_timer.expires = jiffies + | |
823 | msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); | |
824 | add_timer(&dev->watchdog_timer); | |
825 | ret = s5p_mfc_power_on(); | |
826 | if (ret < 0) { | |
827 | mfc_err("power on failed\n"); | |
828 | goto err_pwr_enable; | |
829 | } | |
830 | s5p_mfc_clock_on(); | |
2e731e44 KD |
831 | ret = s5p_mfc_load_firmware(dev); |
832 | if (ret) { | |
833 | s5p_mfc_clock_off(); | |
834 | goto err_load_fw; | |
835 | } | |
af935746 KD |
836 | /* Init the FW */ |
837 | ret = s5p_mfc_init_hw(dev); | |
2e731e44 | 838 | s5p_mfc_clock_off(); |
af935746 KD |
839 | if (ret) |
840 | goto err_init_hw; | |
af935746 KD |
841 | } |
842 | /* Init videobuf2 queue for CAPTURE */ | |
843 | q = &ctx->vq_dst; | |
844 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; | |
845 | q->drv_priv = &ctx->fh; | |
654a731b | 846 | q->lock = &dev->mfc_mutex; |
b80cb8dc | 847 | if (vdev == dev->vfd_dec) { |
af935746 KD |
848 | q->io_modes = VB2_MMAP; |
849 | q->ops = get_dec_queue_ops(); | |
b80cb8dc | 850 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
851 | q->io_modes = VB2_MMAP | VB2_USERPTR; |
852 | q->ops = get_enc_queue_ops(); | |
853 | } else { | |
854 | ret = -ENOENT; | |
855 | goto err_queue_init; | |
856 | } | |
3605163d DA |
857 | /* |
858 | * We'll do mostly sequential access, so sacrifice TLB efficiency for | |
859 | * faster allocation. | |
860 | */ | |
861 | q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES; | |
749ae716 | 862 | q->mem_ops = &vb2_dma_contig_memops; |
ade48681 | 863 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
864 | ret = vb2_queue_init(q); |
865 | if (ret) { | |
866 | mfc_err("Failed to initialize videobuf2 queue(capture)\n"); | |
867 | goto err_queue_init; | |
868 | } | |
869 | /* Init videobuf2 queue for OUTPUT */ | |
870 | q = &ctx->vq_src; | |
871 | q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; | |
af935746 | 872 | q->drv_priv = &ctx->fh; |
41f03a00 | 873 | q->lock = &dev->mfc_mutex; |
b80cb8dc | 874 | if (vdev == dev->vfd_dec) { |
af935746 KD |
875 | q->io_modes = VB2_MMAP; |
876 | q->ops = get_dec_queue_ops(); | |
b80cb8dc | 877 | } else if (vdev == dev->vfd_enc) { |
af935746 KD |
878 | q->io_modes = VB2_MMAP | VB2_USERPTR; |
879 | q->ops = get_enc_queue_ops(); | |
880 | } else { | |
881 | ret = -ENOENT; | |
882 | goto err_queue_init; | |
883 | } | |
e6c9dec3 KD |
884 | /* One way to indicate end-of-stream for MFC is to set the |
885 | * bytesused == 0. However by default videobuf2 handles bytesused | |
886 | * equal to 0 as a special case and changes its value to the size | |
887 | * of the buffer. Set the allow_zero_bytesused flag so that videobuf2 | |
888 | * will keep the value of bytesused intact. | |
889 | */ | |
890 | q->allow_zero_bytesused = 1; | |
3605163d DA |
891 | |
892 | /* | |
893 | * We'll do mostly sequential access, so sacrifice TLB efficiency for | |
894 | * faster allocation. | |
895 | */ | |
896 | q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES; | |
749ae716 | 897 | q->mem_ops = &vb2_dma_contig_memops; |
ade48681 | 898 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; |
af935746 KD |
899 | ret = vb2_queue_init(q); |
900 | if (ret) { | |
901 | mfc_err("Failed to initialize videobuf2 queue(output)\n"); | |
902 | goto err_queue_init; | |
903 | } | |
bc738301 | 904 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
905 | mfc_debug_leave(); |
906 | return ret; | |
39c1cb2b | 907 | /* Deinit when failure occurred */ |
af935746 | 908 | err_queue_init: |
2e731e44 KD |
909 | if (dev->num_inst == 1) |
910 | s5p_mfc_deinit_hw(dev); | |
af935746 | 911 | err_init_hw: |
2e731e44 | 912 | err_load_fw: |
af935746 KD |
913 | err_pwr_enable: |
914 | if (dev->num_inst == 1) { | |
915 | if (s5p_mfc_power_off() < 0) | |
916 | mfc_err("power off failed\n"); | |
1b73ba0b | 917 | del_timer_sync(&dev->watchdog_timer); |
af935746 KD |
918 | } |
919 | err_ctrls_setup: | |
920 | s5p_mfc_dec_ctrls_delete(ctx); | |
921 | err_bad_node: | |
1b73ba0b | 922 | dev->ctx[ctx->num] = NULL; |
af935746 KD |
923 | err_no_ctx: |
924 | v4l2_fh_del(&ctx->fh); | |
925 | v4l2_fh_exit(&ctx->fh); | |
926 | kfree(ctx); | |
927 | err_alloc: | |
928 | dev->num_inst--; | |
bc738301 | 929 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
930 | mfc_debug_leave(); |
931 | return ret; | |
932 | } | |
933 | ||
934 | /* Release MFC context */ | |
935 | static int s5p_mfc_release(struct file *file) | |
936 | { | |
937 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
938 | struct s5p_mfc_dev *dev = ctx->dev; | |
af935746 | 939 | |
d695c12c | 940 | /* if dev is null, do cleanup that doesn't need dev */ |
af935746 | 941 | mfc_debug_enter(); |
d695c12c SK |
942 | if (dev) |
943 | mutex_lock(&dev->mfc_mutex); | |
af935746 KD |
944 | vb2_queue_release(&ctx->vq_src); |
945 | vb2_queue_release(&ctx->vq_dst); | |
d695c12c | 946 | if (dev) { |
c0026c7b MS |
947 | s5p_mfc_clock_on(); |
948 | ||
d695c12c SK |
949 | /* Mark context as idle */ |
950 | clear_work_bit_irqsave(ctx); | |
951 | /* | |
952 | * If instance was initialised and not yet freed, | |
953 | * return instance and free resources | |
954 | */ | |
955 | if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) { | |
956 | mfc_debug(2, "Has to free instance\n"); | |
957 | s5p_mfc_close_mfc_inst(dev, ctx); | |
958 | } | |
959 | /* hardware locking scheme */ | |
960 | if (dev->curr_ctx == ctx->num) | |
961 | clear_bit(0, &dev->hw_lock); | |
962 | dev->num_inst--; | |
963 | if (dev->num_inst == 0) { | |
964 | mfc_debug(2, "Last instance\n"); | |
965 | s5p_mfc_deinit_hw(dev); | |
966 | del_timer_sync(&dev->watchdog_timer); | |
8accb8fd | 967 | s5p_mfc_clock_off(); |
d695c12c SK |
968 | if (s5p_mfc_power_off() < 0) |
969 | mfc_err("Power off failed\n"); | |
8accb8fd MS |
970 | } else { |
971 | mfc_debug(2, "Shutting down clock\n"); | |
972 | s5p_mfc_clock_off(); | |
d695c12c | 973 | } |
af935746 | 974 | } |
d695c12c SK |
975 | if (dev) |
976 | dev->ctx[ctx->num] = NULL; | |
af935746 KD |
977 | s5p_mfc_dec_ctrls_delete(ctx); |
978 | v4l2_fh_del(&ctx->fh); | |
d695c12c SK |
979 | /* vdev is gone if dev is null */ |
980 | if (dev) | |
981 | v4l2_fh_exit(&ctx->fh); | |
af935746 KD |
982 | kfree(ctx); |
983 | mfc_debug_leave(); | |
d695c12c SK |
984 | if (dev) |
985 | mutex_unlock(&dev->mfc_mutex); | |
986 | ||
af935746 KD |
987 | return 0; |
988 | } | |
989 | ||
990 | /* Poll */ | |
991 | static unsigned int s5p_mfc_poll(struct file *file, | |
992 | struct poll_table_struct *wait) | |
993 | { | |
994 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
995 | struct s5p_mfc_dev *dev = ctx->dev; | |
996 | struct vb2_queue *src_q, *dst_q; | |
997 | struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; | |
998 | unsigned int rc = 0; | |
999 | unsigned long flags; | |
1000 | ||
bc738301 | 1001 | mutex_lock(&dev->mfc_mutex); |
af935746 KD |
1002 | src_q = &ctx->vq_src; |
1003 | dst_q = &ctx->vq_dst; | |
1004 | /* | |
1005 | * There has to be at least one buffer queued on each queued_list, which | |
1006 | * means either in driver already or waiting for driver to claim it | |
1007 | * and start processing. | |
1008 | */ | |
1009 | if ((!src_q->streaming || list_empty(&src_q->queued_list)) | |
1010 | && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { | |
1011 | rc = POLLERR; | |
1012 | goto end; | |
1013 | } | |
1014 | mutex_unlock(&dev->mfc_mutex); | |
f9f715a9 | 1015 | poll_wait(file, &ctx->fh.wait, wait); |
af935746 KD |
1016 | poll_wait(file, &src_q->done_wq, wait); |
1017 | poll_wait(file, &dst_q->done_wq, wait); | |
1018 | mutex_lock(&dev->mfc_mutex); | |
f9f715a9 AH |
1019 | if (v4l2_event_pending(&ctx->fh)) |
1020 | rc |= POLLPRI; | |
af935746 KD |
1021 | spin_lock_irqsave(&src_q->done_lock, flags); |
1022 | if (!list_empty(&src_q->done_list)) | |
1023 | src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, | |
1024 | done_entry); | |
1025 | if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE | |
1026 | || src_vb->state == VB2_BUF_STATE_ERROR)) | |
1027 | rc |= POLLOUT | POLLWRNORM; | |
1028 | spin_unlock_irqrestore(&src_q->done_lock, flags); | |
1029 | spin_lock_irqsave(&dst_q->done_lock, flags); | |
1030 | if (!list_empty(&dst_q->done_list)) | |
1031 | dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, | |
1032 | done_entry); | |
1033 | if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE | |
1034 | || dst_vb->state == VB2_BUF_STATE_ERROR)) | |
1035 | rc |= POLLIN | POLLRDNORM; | |
1036 | spin_unlock_irqrestore(&dst_q->done_lock, flags); | |
1037 | end: | |
bc738301 | 1038 | mutex_unlock(&dev->mfc_mutex); |
af935746 KD |
1039 | return rc; |
1040 | } | |
1041 | ||
1042 | /* Mmap */ | |
1043 | static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) | |
1044 | { | |
1045 | struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); | |
1046 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; | |
1047 | int ret; | |
bc738301 | 1048 | |
af935746 KD |
1049 | if (offset < DST_QUEUE_OFF_BASE) { |
1050 | mfc_debug(2, "mmaping source\n"); | |
1051 | ret = vb2_mmap(&ctx->vq_src, vma); | |
1052 | } else { /* capture */ | |
1053 | mfc_debug(2, "mmaping destination\n"); | |
1054 | vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); | |
1055 | ret = vb2_mmap(&ctx->vq_dst, vma); | |
1056 | } | |
1057 | return ret; | |
1058 | } | |
1059 | ||
1060 | /* v4l2 ops */ | |
1061 | static const struct v4l2_file_operations s5p_mfc_fops = { | |
1062 | .owner = THIS_MODULE, | |
1063 | .open = s5p_mfc_open, | |
1064 | .release = s5p_mfc_release, | |
1065 | .poll = s5p_mfc_poll, | |
1066 | .unlocked_ioctl = video_ioctl2, | |
1067 | .mmap = s5p_mfc_mmap, | |
1068 | }; | |
1069 | ||
c79667dd | 1070 | /* DMA memory related helper functions */ |
6311f126 JMC |
1071 | static void s5p_mfc_memdev_release(struct device *dev) |
1072 | { | |
c79667dd | 1073 | of_reserved_mem_device_release(dev); |
6311f126 JMC |
1074 | } |
1075 | ||
c79667dd MS |
1076 | static struct device *s5p_mfc_alloc_memdev(struct device *dev, |
1077 | const char *name, unsigned int idx) | |
6e83e6e2 | 1078 | { |
c79667dd MS |
1079 | struct device *child; |
1080 | int ret; | |
6e83e6e2 | 1081 | |
d7f15bde | 1082 | child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL); |
c79667dd MS |
1083 | if (!child) |
1084 | return NULL; | |
1085 | ||
1086 | device_initialize(child); | |
1087 | dev_set_name(child, "%s:%s", dev_name(dev), name); | |
1088 | child->parent = dev; | |
1089 | child->bus = dev->bus; | |
1090 | child->coherent_dma_mask = dev->coherent_dma_mask; | |
1091 | child->dma_mask = dev->dma_mask; | |
1092 | child->release = s5p_mfc_memdev_release; | |
1093 | ||
1094 | if (device_add(child) == 0) { | |
1095 | ret = of_reserved_mem_device_init_by_idx(child, dev->of_node, | |
1096 | idx); | |
1097 | if (ret == 0) | |
1098 | return child; | |
3467c9a7 | 1099 | device_del(child); |
6e83e6e2 | 1100 | } |
29debab0 | 1101 | |
c79667dd MS |
1102 | put_device(child); |
1103 | return NULL; | |
1104 | } | |
6e83e6e2 | 1105 | |
9ce47803 | 1106 | static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev) |
c79667dd MS |
1107 | { |
1108 | struct device *dev = &mfc_dev->plat_dev->dev; | |
94eaccc0 MS |
1109 | void *bank2_virt; |
1110 | dma_addr_t bank2_dma_addr; | |
1111 | unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER; | |
94eaccc0 | 1112 | int ret; |
29debab0 | 1113 | |
c79667dd MS |
1114 | /* |
1115 | * Create and initialize virtual devices for accessing | |
1116 | * reserved memory regions. | |
1117 | */ | |
5ea289fe MS |
1118 | mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left", |
1119 | BANK_L_CTX); | |
1120 | if (!mfc_dev->mem_dev[BANK_L_CTX]) | |
c79667dd | 1121 | return -ENODEV; |
5ea289fe MS |
1122 | mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right", |
1123 | BANK_R_CTX); | |
1124 | if (!mfc_dev->mem_dev[BANK_R_CTX]) { | |
1125 | device_unregister(mfc_dev->mem_dev[BANK_L_CTX]); | |
c79667dd | 1126 | return -ENODEV; |
6e83e6e2 | 1127 | } |
c79667dd | 1128 | |
94eaccc0 MS |
1129 | /* Allocate memory for firmware and initialize both banks addresses */ |
1130 | ret = s5p_mfc_alloc_firmware(mfc_dev); | |
1131 | if (ret) { | |
5ea289fe MS |
1132 | device_unregister(mfc_dev->mem_dev[BANK_R_CTX]); |
1133 | device_unregister(mfc_dev->mem_dev[BANK_L_CTX]); | |
94eaccc0 MS |
1134 | return ret; |
1135 | } | |
1136 | ||
5ea289fe | 1137 | mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma; |
94eaccc0 | 1138 | |
5ea289fe MS |
1139 | bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX], |
1140 | align_size, &bank2_dma_addr, GFP_KERNEL); | |
94eaccc0 MS |
1141 | if (!bank2_virt) { |
1142 | mfc_err("Allocating bank2 base failed\n"); | |
1143 | s5p_mfc_release_firmware(mfc_dev); | |
5ea289fe MS |
1144 | device_unregister(mfc_dev->mem_dev[BANK_R_CTX]); |
1145 | device_unregister(mfc_dev->mem_dev[BANK_L_CTX]); | |
94eaccc0 MS |
1146 | return -ENOMEM; |
1147 | } | |
1148 | ||
1149 | /* Valid buffers passed to MFC encoder with LAST_FRAME command | |
1150 | * should not have address of bank2 - MFC will treat it as a null frame. | |
1151 | * To avoid such situation we set bank2 address below the pool address. | |
1152 | */ | |
5ea289fe | 1153 | mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size; |
94eaccc0 | 1154 | |
5ea289fe | 1155 | dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt, |
94eaccc0 MS |
1156 | bank2_dma_addr); |
1157 | ||
5ea289fe | 1158 | vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX], |
ba2e161f | 1159 | DMA_BIT_MASK(32)); |
5ea289fe | 1160 | vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX], |
ba2e161f MS |
1161 | DMA_BIT_MASK(32)); |
1162 | ||
6e83e6e2 AK |
1163 | return 0; |
1164 | } | |
1165 | ||
9ce47803 | 1166 | static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev) |
c79667dd | 1167 | { |
5ea289fe MS |
1168 | device_unregister(mfc_dev->mem_dev[BANK_L_CTX]); |
1169 | device_unregister(mfc_dev->mem_dev[BANK_R_CTX]); | |
1170 | vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]); | |
1171 | vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]); | |
9ce47803 | 1172 | } |
04f77673 | 1173 | |
9ce47803 MS |
1174 | static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev) |
1175 | { | |
1176 | struct device *dev = &mfc_dev->plat_dev->dev; | |
60641e22 | 1177 | unsigned long mem_size = SZ_4M; |
25e73b42 | 1178 | unsigned int bitmap_size; |
94eaccc0 | 1179 | |
60641e22 MS |
1180 | if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev)) |
1181 | mem_size = SZ_8M; | |
1182 | ||
25e73b42 MS |
1183 | if (mfc_mem_size) |
1184 | mem_size = memparse(mfc_mem_size, NULL); | |
1185 | ||
1186 | bitmap_size = BITS_TO_LONGS(mem_size >> PAGE_SHIFT) * sizeof(long); | |
1187 | ||
1188 | mfc_dev->mem_bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
8e409f1d | 1189 | if (!mfc_dev->mem_bitmap) |
25e73b42 | 1190 | return -ENOMEM; |
04f77673 | 1191 | |
25e73b42 MS |
1192 | mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size, |
1193 | &mfc_dev->mem_base, GFP_KERNEL); | |
1194 | if (!mfc_dev->mem_virt) { | |
1195 | kfree(mfc_dev->mem_bitmap); | |
1196 | dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n", | |
1197 | (mem_size / SZ_1M)); | |
25e73b42 MS |
1198 | return -ENOMEM; |
1199 | } | |
1200 | mfc_dev->mem_size = mem_size; | |
5ea289fe MS |
1201 | mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base; |
1202 | mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base; | |
25e73b42 | 1203 | |
8e409f1d MS |
1204 | /* |
1205 | * MFC hardware cannot handle 0 as a base address, so mark first 128K | |
1206 | * as used (to keep required base alignment) and adjust base address | |
1207 | */ | |
1208 | if (mfc_dev->mem_base == (dma_addr_t)0) { | |
1209 | unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER; | |
1210 | ||
1211 | bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT); | |
5ea289fe MS |
1212 | mfc_dev->dma_base[BANK_L_CTX] += offset; |
1213 | mfc_dev->dma_base[BANK_R_CTX] += offset; | |
8e409f1d MS |
1214 | } |
1215 | ||
25e73b42 MS |
1216 | /* Firmware allocation cannot fail in this case */ |
1217 | s5p_mfc_alloc_firmware(mfc_dev); | |
1218 | ||
5ea289fe | 1219 | mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev; |
9ce47803 MS |
1220 | vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32)); |
1221 | ||
25e73b42 MS |
1222 | dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n", |
1223 | (mem_size / SZ_1M)); | |
1224 | ||
9ce47803 MS |
1225 | return 0; |
1226 | } | |
1227 | ||
1228 | static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev) | |
1229 | { | |
1230 | struct device *dev = &mfc_dev->plat_dev->dev; | |
1231 | ||
25e73b42 MS |
1232 | dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt, |
1233 | mfc_dev->mem_base); | |
1234 | kfree(mfc_dev->mem_bitmap); | |
9ce47803 MS |
1235 | vb2_dma_contig_clear_max_seg_size(dev); |
1236 | } | |
1237 | ||
1238 | static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) | |
1239 | { | |
1240 | struct device *dev = &mfc_dev->plat_dev->dev; | |
1241 | ||
60641e22 | 1242 | if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev)) |
9ce47803 MS |
1243 | return s5p_mfc_configure_common_memory(mfc_dev); |
1244 | else | |
1245 | return s5p_mfc_configure_2port_memory(mfc_dev); | |
1246 | } | |
1247 | ||
1248 | static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev) | |
1249 | { | |
1250 | struct device *dev = &mfc_dev->plat_dev->dev; | |
1251 | ||
1252 | s5p_mfc_release_firmware(mfc_dev); | |
60641e22 | 1253 | if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev)) |
9ce47803 MS |
1254 | s5p_mfc_unconfigure_common_memory(mfc_dev); |
1255 | else | |
1256 | s5p_mfc_unconfigure_2port_memory(mfc_dev); | |
c79667dd MS |
1257 | } |
1258 | ||
af935746 | 1259 | /* MFC probe function */ |
1e393e90 | 1260 | static int s5p_mfc_probe(struct platform_device *pdev) |
af935746 KD |
1261 | { |
1262 | struct s5p_mfc_dev *dev; | |
1263 | struct video_device *vfd; | |
1264 | struct resource *res; | |
1265 | int ret; | |
1266 | ||
1267 | pr_debug("%s++\n", __func__); | |
bae061b4 | 1268 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); |
f6cd3232 | 1269 | if (!dev) |
af935746 | 1270 | return -ENOMEM; |
af935746 KD |
1271 | |
1272 | spin_lock_init(&dev->irqlock); | |
1273 | spin_lock_init(&dev->condlock); | |
1274 | dev->plat_dev = pdev; | |
1275 | if (!dev->plat_dev) { | |
1276 | dev_err(&pdev->dev, "No platform data specified\n"); | |
d310f478 | 1277 | return -ENODEV; |
af935746 KD |
1278 | } |
1279 | ||
4a5ab64c | 1280 | dev->variant = of_device_get_match_data(&pdev->dev); |
8f532a7f | 1281 | |
af935746 | 1282 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
f23999ec TR |
1283 | dev->regs_base = devm_ioremap_resource(&pdev->dev, res); |
1284 | if (IS_ERR(dev->regs_base)) | |
1285 | return PTR_ERR(dev->regs_base); | |
af935746 KD |
1286 | |
1287 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
4449dd0a | 1288 | if (!res) { |
af935746 | 1289 | dev_err(&pdev->dev, "failed to get irq resource\n"); |
e4fac74d | 1290 | return -ENOENT; |
af935746 KD |
1291 | } |
1292 | dev->irq = res->start; | |
d310f478 | 1293 | ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, |
1957f0d7 | 1294 | 0, pdev->name, dev); |
af935746 KD |
1295 | if (ret) { |
1296 | dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); | |
e4fac74d | 1297 | return ret; |
af935746 KD |
1298 | } |
1299 | ||
c79667dd MS |
1300 | ret = s5p_mfc_configure_dma_memory(dev); |
1301 | if (ret < 0) { | |
1302 | dev_err(&pdev->dev, "failed to configure DMA memory\n"); | |
1303 | return ret; | |
1304 | } | |
1305 | ||
1306 | ret = s5p_mfc_init_pm(dev); | |
1307 | if (ret < 0) { | |
1308 | dev_err(&pdev->dev, "failed to get mfc clock source\n"); | |
e4fac74d | 1309 | goto err_dma; |
af935746 KD |
1310 | } |
1311 | ||
af935746 | 1312 | mutex_init(&dev->mfc_mutex); |
7c96f59e MS |
1313 | init_waitqueue_head(&dev->queue); |
1314 | dev->hw_lock = 0; | |
1315 | INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); | |
1316 | atomic_set(&dev->watchdog_cnt, 0); | |
e99e88a9 | 1317 | timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0); |
af935746 KD |
1318 | |
1319 | ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); | |
1320 | if (ret) | |
1321 | goto err_v4l2_dev_reg; | |
af935746 KD |
1322 | |
1323 | /* decoder */ | |
1324 | vfd = video_device_alloc(); | |
1325 | if (!vfd) { | |
1326 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1327 | ret = -ENOMEM; | |
1328 | goto err_dec_alloc; | |
1329 | } | |
d0ce898c | 1330 | vfd->fops = &s5p_mfc_fops; |
af935746 | 1331 | vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); |
d0ce898c | 1332 | vfd->release = video_device_release; |
af935746 KD |
1333 | vfd->lock = &dev->mfc_mutex; |
1334 | vfd->v4l2_dev = &dev->v4l2_dev; | |
954f340f | 1335 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1336 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); |
1337 | dev->vfd_dec = vfd; | |
af935746 KD |
1338 | video_set_drvdata(vfd, dev); |
1339 | ||
1340 | /* encoder */ | |
1341 | vfd = video_device_alloc(); | |
1342 | if (!vfd) { | |
1343 | v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); | |
1344 | ret = -ENOMEM; | |
1345 | goto err_enc_alloc; | |
1346 | } | |
d0ce898c | 1347 | vfd->fops = &s5p_mfc_fops; |
af935746 | 1348 | vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); |
d0ce898c | 1349 | vfd->release = video_device_release; |
af935746 KD |
1350 | vfd->lock = &dev->mfc_mutex; |
1351 | vfd->v4l2_dev = &dev->v4l2_dev; | |
cdcf45e7 | 1352 | vfd->vfl_dir = VFL_DIR_M2M; |
af935746 KD |
1353 | snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); |
1354 | dev->vfd_enc = vfd; | |
af935746 KD |
1355 | video_set_drvdata(vfd, dev); |
1356 | platform_set_drvdata(pdev, dev); | |
1357 | ||
43a1ea1f AK |
1358 | /* Initialize HW ops and commands based on MFC version */ |
1359 | s5p_mfc_init_hw_ops(dev); | |
1360 | s5p_mfc_init_hw_cmds(dev); | |
6a9c6f68 | 1361 | s5p_mfc_init_regs(dev); |
43a1ea1f | 1362 | |
c974c436 JMC |
1363 | /* Register decoder and encoder */ |
1364 | ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0); | |
1365 | if (ret) { | |
1366 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
c974c436 JMC |
1367 | goto err_dec_reg; |
1368 | } | |
1369 | v4l2_info(&dev->v4l2_dev, | |
1370 | "decoder registered as /dev/video%d\n", dev->vfd_dec->num); | |
1371 | ||
1372 | ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0); | |
1373 | if (ret) { | |
1374 | v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); | |
c974c436 JMC |
1375 | goto err_enc_reg; |
1376 | } | |
1377 | v4l2_info(&dev->v4l2_dev, | |
1378 | "encoder registered as /dev/video%d\n", dev->vfd_enc->num); | |
1379 | ||
af935746 KD |
1380 | pr_debug("%s--\n", __func__); |
1381 | return 0; | |
1382 | ||
1383 | /* Deinit MFC if probe had failed */ | |
1384 | err_enc_reg: | |
af935746 KD |
1385 | video_unregister_device(dev->vfd_dec); |
1386 | err_dec_reg: | |
c974c436 JMC |
1387 | video_device_release(dev->vfd_enc); |
1388 | err_enc_alloc: | |
af935746 KD |
1389 | video_device_release(dev->vfd_dec); |
1390 | err_dec_alloc: | |
1391 | v4l2_device_unregister(&dev->v4l2_dev); | |
1392 | err_v4l2_dev_reg: | |
af935746 | 1393 | s5p_mfc_final_pm(dev); |
e4fac74d MS |
1394 | err_dma: |
1395 | s5p_mfc_unconfigure_dma_memory(dev); | |
d310f478 | 1396 | |
af935746 KD |
1397 | pr_debug("%s-- with error\n", __func__); |
1398 | return ret; | |
1399 | ||
1400 | } | |
1401 | ||
1402 | /* Remove the driver */ | |
4c62e976 | 1403 | static int s5p_mfc_remove(struct platform_device *pdev) |
af935746 KD |
1404 | { |
1405 | struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); | |
d695c12c SK |
1406 | struct s5p_mfc_ctx *ctx; |
1407 | int i; | |
af935746 KD |
1408 | |
1409 | v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); | |
1410 | ||
d695c12c SK |
1411 | /* |
1412 | * Clear ctx dev pointer to avoid races between s5p_mfc_remove() | |
1413 | * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev | |
1414 | * after s5p_mfc_remove() is run during unbind. | |
1415 | */ | |
1416 | mutex_lock(&dev->mfc_mutex); | |
1417 | for (i = 0; i < MFC_NUM_CONTEXTS; i++) { | |
1418 | ctx = dev->ctx[i]; | |
1419 | if (!ctx) | |
1420 | continue; | |
1421 | /* clear ctx->dev */ | |
1422 | ctx->dev = NULL; | |
1423 | } | |
1424 | mutex_unlock(&dev->mfc_mutex); | |
1425 | ||
af935746 | 1426 | del_timer_sync(&dev->watchdog_timer); |
ed90013e | 1427 | flush_work(&dev->watchdog_work); |
af935746 KD |
1428 | |
1429 | video_unregister_device(dev->vfd_enc); | |
1430 | video_unregister_device(dev->vfd_dec); | |
6610ef08 SK |
1431 | video_device_release(dev->vfd_enc); |
1432 | video_device_release(dev->vfd_dec); | |
af935746 | 1433 | v4l2_device_unregister(&dev->v4l2_dev); |
c79667dd | 1434 | s5p_mfc_unconfigure_dma_memory(dev); |
af935746 | 1435 | |
af935746 | 1436 | s5p_mfc_final_pm(dev); |
af935746 KD |
1437 | return 0; |
1438 | } | |
1439 | ||
1440 | #ifdef CONFIG_PM_SLEEP | |
1441 | ||
1442 | static int s5p_mfc_suspend(struct device *dev) | |
1443 | { | |
1444 | struct platform_device *pdev = to_platform_device(dev); | |
1445 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1446 | int ret; | |
1447 | ||
1448 | if (m_dev->num_inst == 0) | |
1449 | return 0; | |
81c9bcfb | 1450 | |
af935746 KD |
1451 | if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { |
1452 | mfc_err("Error: going to suspend for a second time\n"); | |
1453 | return -EIO; | |
1454 | } | |
1455 | ||
1456 | /* Check if we're processing then wait if it necessary. */ | |
1457 | while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { | |
1458 | /* Try and lock the HW */ | |
1459 | /* Wait on the interrupt waitqueue */ | |
1460 | ret = wait_event_interruptible_timeout(m_dev->queue, | |
76a4ddbd | 1461 | m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT)); |
af935746 KD |
1462 | if (ret == 0) { |
1463 | mfc_err("Waiting for hardware to finish timed out\n"); | |
64370994 | 1464 | clear_bit(0, &m_dev->enter_suspend); |
af935746 KD |
1465 | return -EIO; |
1466 | } | |
1467 | } | |
81c9bcfb | 1468 | |
64370994 P |
1469 | ret = s5p_mfc_sleep(m_dev); |
1470 | if (ret) { | |
1471 | clear_bit(0, &m_dev->enter_suspend); | |
1472 | clear_bit(0, &m_dev->hw_lock); | |
1473 | } | |
1474 | return ret; | |
af935746 KD |
1475 | } |
1476 | ||
1477 | static int s5p_mfc_resume(struct device *dev) | |
1478 | { | |
1479 | struct platform_device *pdev = to_platform_device(dev); | |
1480 | struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); | |
1481 | ||
1482 | if (m_dev->num_inst == 0) | |
1483 | return 0; | |
1484 | return s5p_mfc_wakeup(m_dev); | |
1485 | } | |
1486 | #endif | |
1487 | ||
af935746 KD |
1488 | /* Power management */ |
1489 | static const struct dev_pm_ops s5p_mfc_pm_ops = { | |
1490 | SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) | |
af935746 KD |
1491 | }; |
1492 | ||
ca5ea0c5 | 1493 | static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { |
8f532a7f AK |
1494 | .h264_ctx = MFC_H264_CTX_BUF_SIZE, |
1495 | .non_h264_ctx = MFC_CTX_BUF_SIZE, | |
1496 | .dsc = DESC_BUF_SIZE, | |
1497 | .shm = SHARED_BUF_SIZE, | |
1498 | }; | |
1499 | ||
ca5ea0c5 | 1500 | static struct s5p_mfc_buf_size buf_size_v5 = { |
8f532a7f AK |
1501 | .fw = MAX_FW_SIZE, |
1502 | .cpb = MAX_CPB_SIZE, | |
1503 | .priv = &mfc_buf_size_v5, | |
1504 | }; | |
1505 | ||
8f532a7f AK |
1506 | static struct s5p_mfc_variant mfc_drvdata_v5 = { |
1507 | .version = MFC_VERSION, | |
9aa5f008 | 1508 | .version_bit = MFC_V5_BIT, |
8f532a7f AK |
1509 | .port_num = MFC_NUM_PORTS, |
1510 | .buf_size = &buf_size_v5, | |
77ba6b73 | 1511 | .fw_name[0] = "s5p-mfc.fw", |
1bce6fb3 MS |
1512 | .clk_names = {"mfc", "sclk_mfc"}, |
1513 | .num_clocks = 2, | |
c5086f13 | 1514 | .use_clock_gating = true, |
f96f3cfa JP |
1515 | }; |
1516 | ||
ca5ea0c5 | 1517 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { |
f96f3cfa JP |
1518 | .dev_ctx = MFC_CTX_BUF_SIZE_V6, |
1519 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, | |
1520 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, | |
1521 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, | |
1522 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, | |
1523 | }; | |
1524 | ||
ca5ea0c5 | 1525 | static struct s5p_mfc_buf_size buf_size_v6 = { |
f96f3cfa JP |
1526 | .fw = MAX_FW_SIZE_V6, |
1527 | .cpb = MAX_CPB_SIZE_V6, | |
1528 | .priv = &mfc_buf_size_v6, | |
1529 | }; | |
1530 | ||
f96f3cfa JP |
1531 | static struct s5p_mfc_variant mfc_drvdata_v6 = { |
1532 | .version = MFC_VERSION_V6, | |
9aa5f008 | 1533 | .version_bit = MFC_V6_BIT, |
f96f3cfa JP |
1534 | .port_num = MFC_NUM_PORTS_V6, |
1535 | .buf_size = &buf_size_v6, | |
77ba6b73 AK |
1536 | .fw_name[0] = "s5p-mfc-v6.fw", |
1537 | /* | |
1538 | * v6-v2 firmware contains bug fixes and interface change | |
1539 | * for init buffer command | |
1540 | */ | |
1541 | .fw_name[1] = "s5p-mfc-v6-v2.fw", | |
1bce6fb3 MS |
1542 | .clk_names = {"mfc"}, |
1543 | .num_clocks = 1, | |
8f532a7f AK |
1544 | }; |
1545 | ||
ca5ea0c5 | 1546 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { |
5441e9da AK |
1547 | .dev_ctx = MFC_CTX_BUF_SIZE_V7, |
1548 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, | |
1549 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, | |
1550 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7, | |
1551 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, | |
1552 | }; | |
1553 | ||
ca5ea0c5 | 1554 | static struct s5p_mfc_buf_size buf_size_v7 = { |
5441e9da AK |
1555 | .fw = MAX_FW_SIZE_V7, |
1556 | .cpb = MAX_CPB_SIZE_V7, | |
1557 | .priv = &mfc_buf_size_v7, | |
1558 | }; | |
1559 | ||
5441e9da AK |
1560 | static struct s5p_mfc_variant mfc_drvdata_v7 = { |
1561 | .version = MFC_VERSION_V7, | |
9aa5f008 | 1562 | .version_bit = MFC_V7_BIT, |
5441e9da AK |
1563 | .port_num = MFC_NUM_PORTS_V7, |
1564 | .buf_size = &buf_size_v7, | |
77ba6b73 | 1565 | .fw_name[0] = "s5p-mfc-v7.fw", |
1bce6fb3 MS |
1566 | .clk_names = {"mfc", "sclk_mfc"}, |
1567 | .num_clocks = 2, | |
5441e9da AK |
1568 | }; |
1569 | ||
ca5ea0c5 | 1570 | static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = { |
e2b9deb2 KA |
1571 | .dev_ctx = MFC_CTX_BUF_SIZE_V8, |
1572 | .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8, | |
1573 | .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8, | |
3e594ce7 KA |
1574 | .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8, |
1575 | .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8, | |
e2b9deb2 KA |
1576 | }; |
1577 | ||
ca5ea0c5 | 1578 | static struct s5p_mfc_buf_size buf_size_v8 = { |
e2b9deb2 KA |
1579 | .fw = MAX_FW_SIZE_V8, |
1580 | .cpb = MAX_CPB_SIZE_V8, | |
1581 | .priv = &mfc_buf_size_v8, | |
1582 | }; | |
1583 | ||
e2b9deb2 KA |
1584 | static struct s5p_mfc_variant mfc_drvdata_v8 = { |
1585 | .version = MFC_VERSION_V8, | |
1586 | .version_bit = MFC_V8_BIT, | |
1587 | .port_num = MFC_NUM_PORTS_V8, | |
1588 | .buf_size = &buf_size_v8, | |
77ba6b73 | 1589 | .fw_name[0] = "s5p-mfc-v8.fw", |
1bce6fb3 MS |
1590 | .clk_names = {"mfc"}, |
1591 | .num_clocks = 1, | |
e2b9deb2 KA |
1592 | }; |
1593 | ||
00361133 MS |
1594 | static struct s5p_mfc_variant mfc_drvdata_v8_5433 = { |
1595 | .version = MFC_VERSION_V8, | |
1596 | .version_bit = MFC_V8_BIT, | |
1597 | .port_num = MFC_NUM_PORTS_V8, | |
1598 | .buf_size = &buf_size_v8, | |
00361133 MS |
1599 | .fw_name[0] = "s5p-mfc-v8.fw", |
1600 | .clk_names = {"pclk", "aclk", "aclk_xiu"}, | |
1601 | .num_clocks = 3, | |
1602 | }; | |
1603 | ||
b27a23be AK |
1604 | static const struct of_device_id exynos_mfc_match[] = { |
1605 | { | |
1606 | .compatible = "samsung,mfc-v5", | |
1607 | .data = &mfc_drvdata_v5, | |
1608 | }, { | |
1609 | .compatible = "samsung,mfc-v6", | |
1610 | .data = &mfc_drvdata_v6, | |
5441e9da AK |
1611 | }, { |
1612 | .compatible = "samsung,mfc-v7", | |
1613 | .data = &mfc_drvdata_v7, | |
e2b9deb2 KA |
1614 | }, { |
1615 | .compatible = "samsung,mfc-v8", | |
1616 | .data = &mfc_drvdata_v8, | |
00361133 MS |
1617 | }, { |
1618 | .compatible = "samsung,exynos5433-mfc", | |
1619 | .data = &mfc_drvdata_v8_5433, | |
b27a23be AK |
1620 | }, |
1621 | {}, | |
1622 | }; | |
1623 | MODULE_DEVICE_TABLE(of, exynos_mfc_match); | |
1624 | ||
1e393e90 | 1625 | static struct platform_driver s5p_mfc_driver = { |
8f532a7f | 1626 | .probe = s5p_mfc_probe, |
4c62e976 | 1627 | .remove = s5p_mfc_remove, |
af935746 KD |
1628 | .driver = { |
1629 | .name = S5P_MFC_NAME, | |
b27a23be AK |
1630 | .pm = &s5p_mfc_pm_ops, |
1631 | .of_match_table = exynos_mfc_match, | |
af935746 KD |
1632 | }, |
1633 | }; | |
1634 | ||
1d6629b1 | 1635 | module_platform_driver(s5p_mfc_driver); |
af935746 KD |
1636 | |
1637 | MODULE_LICENSE("GPL"); | |
1638 | MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); | |
1639 | MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); | |
1640 |