Commit | Line | Data |
---|---|---|
5f3cc447 | 1 | /* |
3a3f9449 | 2 | * Samsung S5P/EXYNOS4 SoC series camera interface (camera capture) driver |
5f3cc447 | 3 | * |
0c9204d3 SN |
4 | * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd. |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
5f3cc447 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
5f3cc447 SN |
14 | #include <linux/types.h> |
15 | #include <linux/errno.h> | |
16 | #include <linux/bug.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/device.h> | |
e9e21083 | 19 | #include <linux/pm_runtime.h> |
5f3cc447 SN |
20 | #include <linux/list.h> |
21 | #include <linux/slab.h> | |
5f3cc447 SN |
22 | |
23 | #include <linux/videodev2.h> | |
24 | #include <media/v4l2-device.h> | |
25 | #include <media/v4l2-ioctl.h> | |
26 | #include <media/v4l2-mem2mem.h> | |
2dab38e2 SN |
27 | #include <media/videobuf2-core.h> |
28 | #include <media/videobuf2-dma-contig.h> | |
5f3cc447 | 29 | |
131b6c61 | 30 | #include "fimc-mdevice.h" |
5f3cc447 | 31 | #include "fimc-core.h" |
c83a1ff0 | 32 | #include "fimc-reg.h" |
5f3cc447 | 33 | |
bb7c276e | 34 | static int fimc_capture_hw_init(struct fimc_dev *fimc) |
9e803a04 SN |
35 | { |
36 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
0f735f52 | 37 | struct fimc_pipeline *p = &fimc->pipeline; |
9e803a04 SN |
38 | struct fimc_sensor_info *sensor; |
39 | unsigned long flags; | |
40 | int ret = 0; | |
41 | ||
0f735f52 | 42 | if (p->subdevs[IDX_SENSOR] == NULL || ctx == NULL) |
9e803a04 SN |
43 | return -ENXIO; |
44 | if (ctx->s_frame.fmt == NULL) | |
45 | return -EINVAL; | |
46 | ||
0f735f52 | 47 | sensor = v4l2_get_subdev_hostdata(p->subdevs[IDX_SENSOR]); |
9e803a04 SN |
48 | |
49 | spin_lock_irqsave(&fimc->slock, flags); | |
50 | fimc_prepare_dma_offset(ctx, &ctx->d_frame); | |
51 | fimc_set_yuv_order(ctx); | |
52 | ||
6612a082 SN |
53 | fimc_hw_set_camera_polarity(fimc, &sensor->pdata); |
54 | fimc_hw_set_camera_type(fimc, &sensor->pdata); | |
55 | fimc_hw_set_camera_source(fimc, &sensor->pdata); | |
9e803a04 SN |
56 | fimc_hw_set_camera_offset(fimc, &ctx->s_frame); |
57 | ||
58 | ret = fimc_set_scaler_info(ctx); | |
59 | if (!ret) { | |
60 | fimc_hw_set_input_path(ctx); | |
61 | fimc_hw_set_prescaler(ctx); | |
62 | fimc_hw_set_mainscaler(ctx); | |
63 | fimc_hw_set_target_format(ctx); | |
64 | fimc_hw_set_rotation(ctx); | |
9448ab7d | 65 | fimc_hw_set_effect(ctx); |
9e803a04 SN |
66 | fimc_hw_set_output_path(ctx); |
67 | fimc_hw_set_out_dma(ctx); | |
dafb9c70 SN |
68 | if (fimc->variant->has_alpha) |
69 | fimc_hw_set_rgb_alpha(ctx); | |
237e0265 | 70 | clear_bit(ST_CAPT_APPLY_CFG, &fimc->state); |
9e803a04 SN |
71 | } |
72 | spin_unlock_irqrestore(&fimc->slock, flags); | |
73 | return ret; | |
74 | } | |
75 | ||
bb7c276e SN |
76 | /* |
77 | * Reinitialize the driver so it is ready to start the streaming again. | |
78 | * Set fimc->state to indicate stream off and the hardware shut down state. | |
79 | * If not suspending (@suspend is false), return any buffers to videobuf2. | |
80 | * Otherwise put any owned buffers onto the pending buffers queue, so they | |
81 | * can be re-spun when the device is being resumed. Also perform FIMC | |
82 | * software reset and disable streaming on the whole pipeline if required. | |
83 | */ | |
3e4748d8 | 84 | static int fimc_capture_state_cleanup(struct fimc_dev *fimc, bool suspend) |
5f3cc447 | 85 | { |
bd323e28 | 86 | struct fimc_vid_cap *cap = &fimc->vid_cap; |
2dab38e2 | 87 | struct fimc_vid_buffer *buf; |
bd323e28 | 88 | unsigned long flags; |
3e4748d8 | 89 | bool streaming; |
5f3cc447 SN |
90 | |
91 | spin_lock_irqsave(&fimc->slock, flags); | |
3e4748d8 | 92 | streaming = fimc->state & (1 << ST_CAPT_ISP_STREAM); |
5f3cc447 | 93 | |
3e4748d8 SN |
94 | fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_SHUT | |
95 | 1 << ST_CAPT_STREAM | 1 << ST_CAPT_ISP_STREAM); | |
aa333122 SN |
96 | if (suspend) |
97 | fimc->state |= (1 << ST_CAPT_SUSPENDED); | |
98 | else | |
3e4748d8 | 99 | fimc->state &= ~(1 << ST_CAPT_PEND | 1 << ST_CAPT_SUSPENDED); |
2dab38e2 | 100 | |
3e4748d8 SN |
101 | /* Release unused buffers */ |
102 | while (!suspend && !list_empty(&cap->pending_buf_q)) { | |
0295202c | 103 | buf = fimc_pending_queue_pop(cap); |
2dab38e2 SN |
104 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); |
105 | } | |
3e4748d8 | 106 | /* If suspending put unused buffers onto pending queue */ |
2dab38e2 | 107 | while (!list_empty(&cap->active_buf_q)) { |
0295202c | 108 | buf = fimc_active_queue_pop(cap); |
3e4748d8 SN |
109 | if (suspend) |
110 | fimc_pending_queue_add(cap, buf); | |
111 | else | |
112 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); | |
2dab38e2 | 113 | } |
2c1bb62e SN |
114 | |
115 | fimc_hw_reset(fimc); | |
116 | cap->buf_index = 0; | |
117 | ||
5f3cc447 | 118 | spin_unlock_irqrestore(&fimc->slock, flags); |
4db5e27e | 119 | |
3e4748d8 | 120 | if (streaming) |
b9ee31e6 SN |
121 | return fimc_pipeline_call(fimc, set_stream, |
122 | &fimc->pipeline, 0); | |
4db5e27e SN |
123 | else |
124 | return 0; | |
bd323e28 MS |
125 | } |
126 | ||
3e4748d8 | 127 | static int fimc_stop_capture(struct fimc_dev *fimc, bool suspend) |
bd323e28 | 128 | { |
bd323e28 MS |
129 | unsigned long flags; |
130 | ||
131 | if (!fimc_capture_active(fimc)) | |
132 | return 0; | |
133 | ||
134 | spin_lock_irqsave(&fimc->slock, flags); | |
135 | set_bit(ST_CAPT_SHUT, &fimc->state); | |
136 | fimc_deactivate_capture(fimc); | |
137 | spin_unlock_irqrestore(&fimc->slock, flags); | |
138 | ||
139 | wait_event_timeout(fimc->irq_queue, | |
140 | !test_bit(ST_CAPT_SHUT, &fimc->state), | |
3e4748d8 | 141 | (2*HZ/10)); /* 200 ms */ |
5f3cc447 | 142 | |
3e4748d8 | 143 | return fimc_capture_state_cleanup(fimc, suspend); |
5f3cc447 SN |
144 | } |
145 | ||
237e0265 SN |
146 | /** |
147 | * fimc_capture_config_update - apply the camera interface configuration | |
148 | * | |
149 | * To be called from within the interrupt handler with fimc.slock | |
150 | * spinlock held. It updates the camera pixel crop, rotation and | |
151 | * image flip in H/W. | |
152 | */ | |
97d97422 | 153 | static int fimc_capture_config_update(struct fimc_ctx *ctx) |
237e0265 SN |
154 | { |
155 | struct fimc_dev *fimc = ctx->fimc_dev; | |
156 | int ret; | |
157 | ||
237e0265 | 158 | fimc_hw_set_camera_offset(fimc, &ctx->s_frame); |
efb13c3d | 159 | |
237e0265 | 160 | ret = fimc_set_scaler_info(ctx); |
efb13c3d SN |
161 | if (ret) |
162 | return ret; | |
163 | ||
164 | fimc_hw_set_prescaler(ctx); | |
165 | fimc_hw_set_mainscaler(ctx); | |
166 | fimc_hw_set_target_format(ctx); | |
167 | fimc_hw_set_rotation(ctx); | |
9448ab7d | 168 | fimc_hw_set_effect(ctx); |
efb13c3d SN |
169 | fimc_prepare_dma_offset(ctx, &ctx->d_frame); |
170 | fimc_hw_set_out_dma(ctx); | |
171 | if (fimc->variant->has_alpha) | |
172 | fimc_hw_set_rgb_alpha(ctx); | |
173 | ||
174 | clear_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
237e0265 SN |
175 | return ret; |
176 | } | |
bd323e28 | 177 | |
97d97422 SN |
178 | void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf) |
179 | { | |
14783d25 | 180 | struct v4l2_subdev *csis = fimc->pipeline.subdevs[IDX_CSIS]; |
97d97422 | 181 | struct fimc_vid_cap *cap = &fimc->vid_cap; |
14783d25 | 182 | struct fimc_frame *f = &cap->ctx->d_frame; |
97d97422 SN |
183 | struct fimc_vid_buffer *v_buf; |
184 | struct timeval *tv; | |
185 | struct timespec ts; | |
186 | ||
187 | if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) { | |
188 | wake_up(&fimc->irq_queue); | |
189 | goto done; | |
190 | } | |
191 | ||
192 | if (!list_empty(&cap->active_buf_q) && | |
193 | test_bit(ST_CAPT_RUN, &fimc->state) && deq_buf) { | |
194 | ktime_get_real_ts(&ts); | |
195 | ||
196 | v_buf = fimc_active_queue_pop(cap); | |
197 | ||
198 | tv = &v_buf->vb.v4l2_buf.timestamp; | |
199 | tv->tv_sec = ts.tv_sec; | |
200 | tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC; | |
201 | v_buf->vb.v4l2_buf.sequence = cap->frame_count++; | |
202 | ||
203 | vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE); | |
204 | } | |
205 | ||
206 | if (!list_empty(&cap->pending_buf_q)) { | |
207 | ||
208 | v_buf = fimc_pending_queue_pop(cap); | |
209 | fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index); | |
210 | v_buf->index = cap->buf_index; | |
211 | ||
212 | /* Move the buffer to the capture active queue */ | |
213 | fimc_active_queue_add(cap, v_buf); | |
214 | ||
215 | dbg("next frame: %d, done frame: %d", | |
216 | fimc_hw_get_frame_index(fimc), v_buf->index); | |
217 | ||
218 | if (++cap->buf_index >= FIMC_MAX_OUT_BUFS) | |
219 | cap->buf_index = 0; | |
220 | } | |
14783d25 SN |
221 | /* |
222 | * Set up a buffer at MIPI-CSIS if current image format | |
223 | * requires the frame embedded data capture. | |
224 | */ | |
225 | if (f->fmt->mdataplanes && !list_empty(&cap->active_buf_q)) { | |
226 | unsigned int plane = ffs(f->fmt->mdataplanes) - 1; | |
227 | unsigned int size = f->payload[plane]; | |
228 | s32 index = fimc_hw_get_frame_index(fimc); | |
229 | void *vaddr; | |
230 | ||
231 | list_for_each_entry(v_buf, &cap->active_buf_q, list) { | |
232 | if (v_buf->index != index) | |
233 | continue; | |
234 | vaddr = vb2_plane_vaddr(&v_buf->vb, plane); | |
235 | v4l2_subdev_call(csis, video, s_rx_buffer, | |
236 | vaddr, &size); | |
237 | break; | |
238 | } | |
239 | } | |
97d97422 SN |
240 | |
241 | if (cap->active_buf_cnt == 0) { | |
242 | if (deq_buf) | |
243 | clear_bit(ST_CAPT_RUN, &fimc->state); | |
244 | ||
245 | if (++cap->buf_index >= FIMC_MAX_OUT_BUFS) | |
246 | cap->buf_index = 0; | |
247 | } else { | |
248 | set_bit(ST_CAPT_RUN, &fimc->state); | |
249 | } | |
250 | ||
bb7c276e SN |
251 | if (test_bit(ST_CAPT_APPLY_CFG, &fimc->state)) |
252 | fimc_capture_config_update(cap->ctx); | |
97d97422 SN |
253 | done: |
254 | if (cap->active_buf_cnt == 1) { | |
255 | fimc_deactivate_capture(fimc); | |
256 | clear_bit(ST_CAPT_STREAM, &fimc->state); | |
257 | } | |
258 | ||
259 | dbg("frame: %d, active_buf_cnt: %d", | |
260 | fimc_hw_get_frame_index(fimc), cap->active_buf_cnt); | |
261 | } | |
262 | ||
263 | ||
bd323e28 | 264 | static int start_streaming(struct vb2_queue *q, unsigned int count) |
2dab38e2 SN |
265 | { |
266 | struct fimc_ctx *ctx = q->drv_priv; | |
267 | struct fimc_dev *fimc = ctx->fimc_dev; | |
9e803a04 | 268 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; |
bd323e28 | 269 | int min_bufs; |
2dab38e2 SN |
270 | int ret; |
271 | ||
9e803a04 | 272 | vid_cap->frame_count = 0; |
8ec737ff | 273 | |
bb7c276e SN |
274 | ret = fimc_capture_hw_init(fimc); |
275 | if (ret) { | |
276 | fimc_capture_state_cleanup(fimc, false); | |
277 | return ret; | |
278 | } | |
2dab38e2 | 279 | |
2dab38e2 SN |
280 | set_bit(ST_CAPT_PEND, &fimc->state); |
281 | ||
bd323e28 MS |
282 | min_bufs = fimc->vid_cap.reqbufs_count > 1 ? 2 : 1; |
283 | ||
4db5e27e SN |
284 | if (vid_cap->active_buf_cnt >= min_bufs && |
285 | !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) { | |
bd323e28 MS |
286 | fimc_activate_capture(ctx); |
287 | ||
4db5e27e | 288 | if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state)) |
b9ee31e6 SN |
289 | fimc_pipeline_call(fimc, set_stream, |
290 | &fimc->pipeline, 1); | |
4db5e27e SN |
291 | } |
292 | ||
2dab38e2 SN |
293 | return 0; |
294 | } | |
295 | ||
296 | static int stop_streaming(struct vb2_queue *q) | |
297 | { | |
298 | struct fimc_ctx *ctx = q->drv_priv; | |
299 | struct fimc_dev *fimc = ctx->fimc_dev; | |
2dab38e2 | 300 | |
4ecbf5d1 | 301 | if (!fimc_capture_active(fimc)) |
2dab38e2 | 302 | return -EINVAL; |
2dab38e2 | 303 | |
3e4748d8 | 304 | return fimc_stop_capture(fimc, false); |
2dab38e2 SN |
305 | } |
306 | ||
e9e21083 SN |
307 | int fimc_capture_suspend(struct fimc_dev *fimc) |
308 | { | |
3e4748d8 SN |
309 | bool suspend = fimc_capture_busy(fimc); |
310 | ||
311 | int ret = fimc_stop_capture(fimc, suspend); | |
312 | if (ret) | |
313 | return ret; | |
b9ee31e6 | 314 | return fimc_pipeline_call(fimc, close, &fimc->pipeline); |
e9e21083 SN |
315 | } |
316 | ||
3e4748d8 SN |
317 | static void buffer_queue(struct vb2_buffer *vb); |
318 | ||
e9e21083 SN |
319 | int fimc_capture_resume(struct fimc_dev *fimc) |
320 | { | |
3e4748d8 SN |
321 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; |
322 | struct fimc_vid_buffer *buf; | |
323 | int i; | |
324 | ||
325 | if (!test_and_clear_bit(ST_CAPT_SUSPENDED, &fimc->state)) | |
326 | return 0; | |
327 | ||
328 | INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q); | |
329 | vid_cap->buf_index = 0; | |
b9ee31e6 SN |
330 | fimc_pipeline_call(fimc, open, &fimc->pipeline, |
331 | &vid_cap->vfd.entity, false); | |
bb7c276e | 332 | fimc_capture_hw_init(fimc); |
3e4748d8 SN |
333 | |
334 | clear_bit(ST_CAPT_SUSPENDED, &fimc->state); | |
335 | ||
336 | for (i = 0; i < vid_cap->reqbufs_count; i++) { | |
337 | if (list_empty(&vid_cap->pending_buf_q)) | |
338 | break; | |
339 | buf = fimc_pending_queue_pop(vid_cap); | |
340 | buffer_queue(&buf->vb); | |
341 | } | |
e9e21083 | 342 | return 0; |
3e4748d8 | 343 | |
e9e21083 SN |
344 | } |
345 | ||
63746be5 | 346 | static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt, |
fc714e70 GL |
347 | unsigned int *num_buffers, unsigned int *num_planes, |
348 | unsigned int sizes[], void *allocators[]) | |
2dab38e2 | 349 | { |
63746be5 | 350 | const struct v4l2_pix_format_mplane *pixm = NULL; |
2dab38e2 | 351 | struct fimc_ctx *ctx = vq->drv_priv; |
63746be5 SN |
352 | struct fimc_frame *frame = &ctx->d_frame; |
353 | struct fimc_fmt *fmt = frame->fmt; | |
354 | unsigned long wh; | |
ef7af59b | 355 | int i; |
2dab38e2 | 356 | |
63746be5 SN |
357 | if (pfmt) { |
358 | pixm = &pfmt->fmt.pix_mp; | |
359 | fmt = fimc_find_format(&pixm->pixelformat, NULL, | |
360 | FMT_FLAGS_CAM | FMT_FLAGS_M2M, -1); | |
361 | wh = pixm->width * pixm->height; | |
362 | } else { | |
363 | wh = frame->f_width * frame->f_height; | |
364 | } | |
365 | ||
366 | if (fmt == NULL) | |
2dab38e2 SN |
367 | return -EINVAL; |
368 | ||
ef7af59b | 369 | *num_planes = fmt->memplanes; |
2dab38e2 | 370 | |
ef7af59b | 371 | for (i = 0; i < fmt->memplanes; i++) { |
63746be5 SN |
372 | unsigned int size = (wh * fmt->depth[i]) / 8; |
373 | if (pixm) | |
374 | sizes[i] = max(size, pixm->plane_fmt[i].sizeimage); | |
14783d25 SN |
375 | else if (fimc_fmt_is_user_defined(fmt->color)) |
376 | sizes[i] = frame->payload[i]; | |
63746be5 | 377 | else |
d547ab66 SN |
378 | sizes[i] = max_t(u32, size, frame->payload[i]); |
379 | ||
ef7af59b SN |
380 | allocators[i] = ctx->fimc_dev->alloc_ctx; |
381 | } | |
2dab38e2 | 382 | |
ef7af59b | 383 | return 0; |
2dab38e2 SN |
384 | } |
385 | ||
2dab38e2 SN |
386 | static int buffer_prepare(struct vb2_buffer *vb) |
387 | { | |
388 | struct vb2_queue *vq = vb->vb2_queue; | |
389 | struct fimc_ctx *ctx = vq->drv_priv; | |
2dab38e2 SN |
390 | int i; |
391 | ||
4db5e27e | 392 | if (ctx->d_frame.fmt == NULL) |
ef7af59b | 393 | return -EINVAL; |
2dab38e2 | 394 | |
ef7af59b | 395 | for (i = 0; i < ctx->d_frame.fmt->memplanes; i++) { |
4db5e27e | 396 | unsigned long size = ctx->d_frame.payload[i]; |
2dab38e2 SN |
397 | |
398 | if (vb2_plane_size(vb, i) < size) { | |
31d34d9b | 399 | v4l2_err(&ctx->fimc_dev->vid_cap.vfd, |
30c9939d | 400 | "User buffer too small (%ld < %ld)\n", |
2dab38e2 SN |
401 | vb2_plane_size(vb, i), size); |
402 | return -EINVAL; | |
403 | } | |
2dab38e2 SN |
404 | vb2_set_plane_payload(vb, i, size); |
405 | } | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | static void buffer_queue(struct vb2_buffer *vb) | |
411 | { | |
2dab38e2 SN |
412 | struct fimc_vid_buffer *buf |
413 | = container_of(vb, struct fimc_vid_buffer, vb); | |
4db5e27e SN |
414 | struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); |
415 | struct fimc_dev *fimc = ctx->fimc_dev; | |
2dab38e2 SN |
416 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; |
417 | unsigned long flags; | |
8ec737ff | 418 | int min_bufs; |
2dab38e2 SN |
419 | |
420 | spin_lock_irqsave(&fimc->slock, flags); | |
8ec737ff SK |
421 | fimc_prepare_addr(ctx, &buf->vb, &ctx->d_frame, &buf->paddr); |
422 | ||
3e4748d8 SN |
423 | if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) && |
424 | !test_bit(ST_CAPT_STREAM, &fimc->state) && | |
425 | vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) { | |
8ec737ff SK |
426 | /* Setup the buffer directly for processing. */ |
427 | int buf_id = (vid_cap->reqbufs_count == 1) ? -1 : | |
428 | vid_cap->buf_index; | |
2dab38e2 | 429 | |
8ec737ff SK |
430 | fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id); |
431 | buf->index = vid_cap->buf_index; | |
0295202c | 432 | fimc_active_queue_add(vid_cap, buf); |
2dab38e2 | 433 | |
8ec737ff SK |
434 | if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS) |
435 | vid_cap->buf_index = 0; | |
436 | } else { | |
437 | fimc_pending_queue_add(vid_cap, buf); | |
2dab38e2 | 438 | } |
8ec737ff SK |
439 | |
440 | min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1; | |
441 | ||
4db5e27e | 442 | |
bd323e28 MS |
443 | if (vb2_is_streaming(&vid_cap->vbq) && |
444 | vid_cap->active_buf_cnt >= min_bufs && | |
4db5e27e | 445 | !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) { |
8ec737ff | 446 | fimc_activate_capture(ctx); |
4db5e27e | 447 | spin_unlock_irqrestore(&fimc->slock, flags); |
8ec737ff | 448 | |
4db5e27e | 449 | if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state)) |
b9ee31e6 SN |
450 | fimc_pipeline_call(fimc, set_stream, |
451 | &fimc->pipeline, 1); | |
4db5e27e SN |
452 | return; |
453 | } | |
2dab38e2 SN |
454 | spin_unlock_irqrestore(&fimc->slock, flags); |
455 | } | |
456 | ||
457 | static void fimc_lock(struct vb2_queue *vq) | |
458 | { | |
459 | struct fimc_ctx *ctx = vb2_get_drv_priv(vq); | |
460 | mutex_lock(&ctx->fimc_dev->lock); | |
461 | } | |
462 | ||
463 | static void fimc_unlock(struct vb2_queue *vq) | |
464 | { | |
465 | struct fimc_ctx *ctx = vb2_get_drv_priv(vq); | |
466 | mutex_unlock(&ctx->fimc_dev->lock); | |
467 | } | |
468 | ||
469 | static struct vb2_ops fimc_capture_qops = { | |
470 | .queue_setup = queue_setup, | |
471 | .buf_prepare = buffer_prepare, | |
472 | .buf_queue = buffer_queue, | |
2dab38e2 SN |
473 | .wait_prepare = fimc_unlock, |
474 | .wait_finish = fimc_lock, | |
475 | .start_streaming = start_streaming, | |
476 | .stop_streaming = stop_streaming, | |
477 | }; | |
478 | ||
131b6c61 SN |
479 | /** |
480 | * fimc_capture_ctrls_create - initialize the control handler | |
481 | * Initialize the capture video node control handler and fill it | |
482 | * with the FIMC controls. Inherit any sensor's controls if the | |
483 | * 'user_subdev_api' flag is false (default behaviour). | |
484 | * This function need to be called with the graph mutex held. | |
485 | */ | |
486 | int fimc_capture_ctrls_create(struct fimc_dev *fimc) | |
487 | { | |
488 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; | |
489 | int ret; | |
490 | ||
491 | if (WARN_ON(vid_cap->ctx == NULL)) | |
492 | return -ENXIO; | |
9448ab7d | 493 | if (vid_cap->ctx->ctrls.ready) |
131b6c61 SN |
494 | return 0; |
495 | ||
496 | ret = fimc_ctrls_create(vid_cap->ctx); | |
9448ab7d | 497 | if (ret || vid_cap->user_subdev_api || !vid_cap->ctx->ctrls.ready) |
131b6c61 SN |
498 | return ret; |
499 | ||
9448ab7d | 500 | return v4l2_ctrl_add_handler(&vid_cap->ctx->ctrls.handler, |
34a6b7d0 | 501 | fimc->pipeline.subdevs[IDX_SENSOR]->ctrl_handler, NULL); |
131b6c61 SN |
502 | } |
503 | ||
237e0265 SN |
504 | static int fimc_capture_set_default_format(struct fimc_dev *fimc); |
505 | ||
5f3cc447 SN |
506 | static int fimc_capture_open(struct file *file) |
507 | { | |
508 | struct fimc_dev *fimc = video_drvdata(file); | |
c2d430af | 509 | int ret = -EBUSY; |
5f3cc447 SN |
510 | |
511 | dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state); | |
512 | ||
c2d430af SN |
513 | if (mutex_lock_interruptible(&fimc->lock)) |
514 | return -ERESTARTSYS; | |
515 | ||
5f3cc447 | 516 | if (fimc_m2m_active(fimc)) |
c2d430af | 517 | goto unlock; |
5f3cc447 | 518 | |
3e4748d8 | 519 | set_bit(ST_CAPT_BUSY, &fimc->state); |
e3fc82e8 SN |
520 | ret = pm_runtime_get_sync(&fimc->pdev->dev); |
521 | if (ret < 0) | |
c2d430af | 522 | goto unlock; |
4db5e27e | 523 | |
e3fc82e8 | 524 | ret = v4l2_fh_open(file); |
c2d430af SN |
525 | if (ret) { |
526 | pm_runtime_put(&fimc->pdev->dev); | |
527 | goto unlock; | |
528 | } | |
e3fc82e8 | 529 | |
c2d430af | 530 | if (++fimc->vid_cap.refcnt == 1) { |
b9ee31e6 SN |
531 | ret = fimc_pipeline_call(fimc, open, &fimc->pipeline, |
532 | &fimc->vid_cap.vfd.entity, true); | |
e3fc82e8 | 533 | |
c2d430af SN |
534 | if (!ret && !fimc->vid_cap.user_subdev_api) |
535 | ret = fimc_capture_set_default_format(fimc); | |
536 | ||
537 | if (!ret) | |
538 | ret = fimc_capture_ctrls_create(fimc); | |
e3fc82e8 | 539 | |
c2d430af SN |
540 | if (ret < 0) { |
541 | clear_bit(ST_CAPT_BUSY, &fimc->state); | |
542 | pm_runtime_put_sync(&fimc->pdev->dev); | |
543 | fimc->vid_cap.refcnt--; | |
544 | v4l2_fh_release(file); | |
545 | } | |
546 | } | |
547 | unlock: | |
548 | mutex_unlock(&fimc->lock); | |
131b6c61 | 549 | return ret; |
5f3cc447 SN |
550 | } |
551 | ||
552 | static int fimc_capture_close(struct file *file) | |
553 | { | |
554 | struct fimc_dev *fimc = video_drvdata(file); | |
c2d430af | 555 | int ret; |
5f3cc447 | 556 | |
5f3cc447 SN |
557 | dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state); |
558 | ||
ba6b372c | 559 | mutex_lock(&fimc->lock); |
c2d430af | 560 | |
5f3cc447 | 561 | if (--fimc->vid_cap.refcnt == 0) { |
3e4748d8 SN |
562 | clear_bit(ST_CAPT_BUSY, &fimc->state); |
563 | fimc_stop_capture(fimc, false); | |
b9ee31e6 | 564 | fimc_pipeline_call(fimc, close, &fimc->pipeline); |
3e4748d8 | 565 | clear_bit(ST_CAPT_SUSPENDED, &fimc->state); |
5f3cc447 SN |
566 | } |
567 | ||
e9e21083 SN |
568 | pm_runtime_put(&fimc->pdev->dev); |
569 | ||
3e4748d8 SN |
570 | if (fimc->vid_cap.refcnt == 0) { |
571 | vb2_queue_release(&fimc->vid_cap.vbq); | |
572 | fimc_ctrls_delete(fimc->vid_cap.ctx); | |
573 | } | |
c2d430af SN |
574 | |
575 | ret = v4l2_fh_release(file); | |
576 | ||
577 | mutex_unlock(&fimc->lock); | |
578 | return ret; | |
5f3cc447 SN |
579 | } |
580 | ||
581 | static unsigned int fimc_capture_poll(struct file *file, | |
582 | struct poll_table_struct *wait) | |
583 | { | |
e578588e | 584 | struct fimc_dev *fimc = video_drvdata(file); |
c2d430af | 585 | int ret; |
5f3cc447 | 586 | |
c2d430af SN |
587 | if (mutex_lock_interruptible(&fimc->lock)) |
588 | return POLL_ERR; | |
589 | ||
590 | ret = vb2_poll(&fimc->vid_cap.vbq, file, wait); | |
591 | mutex_unlock(&fimc->lock); | |
592 | ||
593 | return ret; | |
5f3cc447 SN |
594 | } |
595 | ||
596 | static int fimc_capture_mmap(struct file *file, struct vm_area_struct *vma) | |
597 | { | |
e578588e | 598 | struct fimc_dev *fimc = video_drvdata(file); |
c2d430af SN |
599 | int ret; |
600 | ||
601 | if (mutex_lock_interruptible(&fimc->lock)) | |
602 | return -ERESTARTSYS; | |
5f3cc447 | 603 | |
c2d430af SN |
604 | ret = vb2_mmap(&fimc->vid_cap.vbq, vma); |
605 | mutex_unlock(&fimc->lock); | |
606 | ||
607 | return ret; | |
5f3cc447 SN |
608 | } |
609 | ||
5f3cc447 SN |
610 | static const struct v4l2_file_operations fimc_capture_fops = { |
611 | .owner = THIS_MODULE, | |
612 | .open = fimc_capture_open, | |
613 | .release = fimc_capture_close, | |
614 | .poll = fimc_capture_poll, | |
615 | .unlocked_ioctl = video_ioctl2, | |
616 | .mmap = fimc_capture_mmap, | |
617 | }; | |
618 | ||
237e0265 SN |
619 | /* |
620 | * Format and crop negotiation helpers | |
621 | */ | |
622 | ||
623 | static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx, | |
624 | u32 *width, u32 *height, | |
625 | u32 *code, u32 *fourcc, int pad) | |
626 | { | |
627 | bool rotation = ctx->rotation == 90 || ctx->rotation == 270; | |
628 | struct fimc_dev *fimc = ctx->fimc_dev; | |
bb7c276e | 629 | struct fimc_variant *var = fimc->variant; |
237e0265 SN |
630 | struct fimc_pix_limit *pl = var->pix_limit; |
631 | struct fimc_frame *dst = &ctx->d_frame; | |
632 | u32 depth, min_w, max_w, min_h, align_h = 3; | |
633 | u32 mask = FMT_FLAGS_CAM; | |
634 | struct fimc_fmt *ffmt; | |
635 | ||
14783d25 | 636 | /* Conversion from/to JPEG or User Defined format is not supported */ |
237e0265 | 637 | if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE && |
14783d25 SN |
638 | fimc_fmt_is_user_defined(ctx->s_frame.fmt->color)) |
639 | *code = ctx->s_frame.fmt->mbus_code; | |
237e0265 SN |
640 | |
641 | if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad != FIMC_SD_PAD_SINK) | |
642 | mask |= FMT_FLAGS_M2M; | |
643 | ||
644 | ffmt = fimc_find_format(fourcc, code, mask, 0); | |
645 | if (WARN_ON(!ffmt)) | |
646 | return NULL; | |
647 | if (code) | |
648 | *code = ffmt->mbus_code; | |
649 | if (fourcc) | |
650 | *fourcc = ffmt->fourcc; | |
651 | ||
652 | if (pad == FIMC_SD_PAD_SINK) { | |
14783d25 | 653 | max_w = fimc_fmt_is_user_defined(ffmt->color) ? |
237e0265 SN |
654 | pl->scaler_dis_w : pl->scaler_en_w; |
655 | /* Apply the camera input interface pixel constraints */ | |
656 | v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4, | |
657 | height, max_t(u32, *height, 32), | |
658 | FIMC_CAMIF_MAX_HEIGHT, | |
14783d25 SN |
659 | fimc_fmt_is_user_defined(ffmt->color) ? |
660 | 3 : 1, | |
237e0265 SN |
661 | 0); |
662 | return ffmt; | |
663 | } | |
664 | /* Can't scale or crop in transparent (JPEG) transfer mode */ | |
14783d25 | 665 | if (fimc_fmt_is_user_defined(ffmt->color)) { |
237e0265 SN |
666 | *width = ctx->s_frame.f_width; |
667 | *height = ctx->s_frame.f_height; | |
668 | return ffmt; | |
669 | } | |
670 | /* Apply the scaler and the output DMA constraints */ | |
671 | max_w = rotation ? pl->out_rot_en_w : pl->out_rot_dis_w; | |
fed07f84 SN |
672 | if (ctx->state & FIMC_COMPOSE) { |
673 | min_w = dst->offs_h + dst->width; | |
674 | min_h = dst->offs_v + dst->height; | |
675 | } else { | |
676 | min_w = var->min_out_pixsize; | |
677 | min_h = var->min_out_pixsize; | |
678 | } | |
9c63afcb | 679 | if (var->min_vsize_align == 1 && !rotation) |
237e0265 SN |
680 | align_h = fimc_fmt_is_rgb(ffmt->color) ? 0 : 1; |
681 | ||
682 | depth = fimc_get_format_depth(ffmt); | |
683 | v4l_bound_align_image(width, min_w, max_w, | |
684 | ffs(var->min_out_pixsize) - 1, | |
685 | height, min_h, FIMC_CAMIF_MAX_HEIGHT, | |
686 | align_h, | |
687 | 64/(ALIGN(depth, 8))); | |
688 | ||
689 | dbg("pad%d: code: 0x%x, %dx%d. dst fmt: %dx%d", | |
690 | pad, code ? *code : 0, *width, *height, | |
691 | dst->f_width, dst->f_height); | |
692 | ||
693 | return ffmt; | |
694 | } | |
695 | ||
fed07f84 SN |
696 | static void fimc_capture_try_selection(struct fimc_ctx *ctx, |
697 | struct v4l2_rect *r, | |
698 | int target) | |
237e0265 SN |
699 | { |
700 | bool rotate = ctx->rotation == 90 || ctx->rotation == 270; | |
701 | struct fimc_dev *fimc = ctx->fimc_dev; | |
bb7c276e | 702 | struct fimc_variant *var = fimc->variant; |
237e0265 SN |
703 | struct fimc_pix_limit *pl = var->pix_limit; |
704 | struct fimc_frame *sink = &ctx->s_frame; | |
705 | u32 max_w, max_h, min_w = 0, min_h = 0, min_sz; | |
706 | u32 align_sz = 0, align_h = 4; | |
707 | u32 max_sc_h, max_sc_v; | |
708 | ||
709 | /* In JPEG transparent transfer mode cropping is not supported */ | |
14783d25 | 710 | if (fimc_fmt_is_user_defined(ctx->d_frame.fmt->color)) { |
237e0265 SN |
711 | r->width = sink->f_width; |
712 | r->height = sink->f_height; | |
713 | r->left = r->top = 0; | |
714 | return; | |
715 | } | |
c1334823 | 716 | if (target == V4L2_SEL_TGT_COMPOSE) { |
237e0265 SN |
717 | if (ctx->rotation != 90 && ctx->rotation != 270) |
718 | align_h = 1; | |
719 | max_sc_h = min(SCALER_MAX_HRATIO, 1 << (ffs(sink->width) - 3)); | |
720 | max_sc_v = min(SCALER_MAX_VRATIO, 1 << (ffs(sink->height) - 1)); | |
721 | min_sz = var->min_out_pixsize; | |
722 | } else { | |
723 | u32 depth = fimc_get_format_depth(sink->fmt); | |
724 | align_sz = 64/ALIGN(depth, 8); | |
725 | min_sz = var->min_inp_pixsize; | |
726 | min_w = min_h = min_sz; | |
727 | max_sc_h = max_sc_v = 1; | |
728 | } | |
729 | /* | |
fed07f84 | 730 | * For the compose rectangle the following constraints must be met: |
237e0265 SN |
731 | * - it must fit in the sink pad format rectangle (f_width/f_height); |
732 | * - maximum downscaling ratio is 64; | |
733 | * - maximum crop size depends if the rotator is used or not; | |
734 | * - the sink pad format width/height must be 4 multiple of the | |
735 | * prescaler ratios determined by sink pad size and source pad crop, | |
736 | * the prescaler ratio is returned by fimc_get_scaler_factor(). | |
737 | */ | |
738 | max_w = min_t(u32, | |
739 | rotate ? pl->out_rot_en_w : pl->out_rot_dis_w, | |
740 | rotate ? sink->f_height : sink->f_width); | |
741 | max_h = min_t(u32, FIMC_CAMIF_MAX_HEIGHT, sink->f_height); | |
fed07f84 | 742 | |
c1334823 | 743 | if (target == V4L2_SEL_TGT_COMPOSE) { |
237e0265 SN |
744 | min_w = min_t(u32, max_w, sink->f_width / max_sc_h); |
745 | min_h = min_t(u32, max_h, sink->f_height / max_sc_v); | |
746 | if (rotate) { | |
747 | swap(max_sc_h, max_sc_v); | |
748 | swap(min_w, min_h); | |
749 | } | |
750 | } | |
751 | v4l_bound_align_image(&r->width, min_w, max_w, ffs(min_sz) - 1, | |
752 | &r->height, min_h, max_h, align_h, | |
753 | align_sz); | |
fed07f84 | 754 | /* Adjust left/top if crop/compose rectangle is out of bounds */ |
237e0265 SN |
755 | r->left = clamp_t(u32, r->left, 0, sink->f_width - r->width); |
756 | r->top = clamp_t(u32, r->top, 0, sink->f_height - r->height); | |
757 | r->left = round_down(r->left, var->hor_offs_align); | |
758 | ||
fed07f84 SN |
759 | dbg("target %#x: (%d,%d)/%dx%d, sink fmt: %dx%d", |
760 | target, r->left, r->top, r->width, r->height, | |
237e0265 SN |
761 | sink->f_width, sink->f_height); |
762 | } | |
763 | ||
764 | /* | |
765 | * The video node ioctl operations | |
766 | */ | |
5f3cc447 SN |
767 | static int fimc_vidioc_querycap_capture(struct file *file, void *priv, |
768 | struct v4l2_capability *cap) | |
769 | { | |
e578588e | 770 | struct fimc_dev *fimc = video_drvdata(file); |
5f3cc447 SN |
771 | |
772 | strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1); | |
773 | strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1); | |
774 | cap->bus_info[0] = 0; | |
8f401543 | 775 | cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE_MPLANE; |
5f3cc447 SN |
776 | |
777 | return 0; | |
778 | } | |
779 | ||
cf52df8a SN |
780 | static int fimc_cap_enum_fmt_mplane(struct file *file, void *priv, |
781 | struct v4l2_fmtdesc *f) | |
782 | { | |
783 | struct fimc_fmt *fmt; | |
784 | ||
785 | fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM | FMT_FLAGS_M2M, | |
786 | f->index); | |
787 | if (!fmt) | |
788 | return -EINVAL; | |
789 | strncpy(f->description, fmt->name, sizeof(f->description) - 1); | |
790 | f->pixelformat = fmt->fourcc; | |
791 | if (fmt->fourcc == V4L2_MBUS_FMT_JPEG_1X8) | |
792 | f->flags |= V4L2_FMT_FLAG_COMPRESSED; | |
793 | return 0; | |
794 | } | |
795 | ||
237e0265 SN |
796 | /** |
797 | * fimc_pipeline_try_format - negotiate and/or set formats at pipeline | |
798 | * elements | |
799 | * @ctx: FIMC capture context | |
800 | * @tfmt: media bus format to try/set on subdevs | |
801 | * @fmt_id: fimc pixel format id corresponding to returned @tfmt (output) | |
802 | * @set: true to set format on subdevs, false to try only | |
803 | */ | |
804 | static int fimc_pipeline_try_format(struct fimc_ctx *ctx, | |
805 | struct v4l2_mbus_framefmt *tfmt, | |
806 | struct fimc_fmt **fmt_id, | |
807 | bool set) | |
808 | { | |
809 | struct fimc_dev *fimc = ctx->fimc_dev; | |
0f735f52 SN |
810 | struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR]; |
811 | struct v4l2_subdev *csis = fimc->pipeline.subdevs[IDX_CSIS]; | |
237e0265 SN |
812 | struct v4l2_subdev_format sfmt; |
813 | struct v4l2_mbus_framefmt *mf = &sfmt.format; | |
814 | struct fimc_fmt *ffmt = NULL; | |
815 | int ret, i = 0; | |
816 | ||
817 | if (WARN_ON(!sd || !tfmt)) | |
818 | return -EINVAL; | |
5f3cc447 | 819 | |
237e0265 SN |
820 | memset(&sfmt, 0, sizeof(sfmt)); |
821 | sfmt.format = *tfmt; | |
822 | ||
823 | sfmt.which = set ? V4L2_SUBDEV_FORMAT_ACTIVE : V4L2_SUBDEV_FORMAT_TRY; | |
824 | while (1) { | |
825 | ffmt = fimc_find_format(NULL, mf->code != 0 ? &mf->code : NULL, | |
826 | FMT_FLAGS_CAM, i++); | |
827 | if (ffmt == NULL) { | |
828 | /* | |
829 | * Notify user-space if common pixel code for | |
830 | * host and sensor does not exist. | |
831 | */ | |
832 | return -EINVAL; | |
833 | } | |
834 | mf->code = tfmt->code = ffmt->mbus_code; | |
5f3cc447 | 835 | |
237e0265 SN |
836 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &sfmt); |
837 | if (ret) | |
838 | return ret; | |
839 | if (mf->code != tfmt->code) { | |
840 | mf->code = 0; | |
841 | continue; | |
842 | } | |
b1aa6089 | 843 | if (mf->width != tfmt->width || mf->height != tfmt->height) { |
237e0265 SN |
844 | u32 fcc = ffmt->fourcc; |
845 | tfmt->width = mf->width; | |
846 | tfmt->height = mf->height; | |
847 | ffmt = fimc_capture_try_format(ctx, | |
848 | &tfmt->width, &tfmt->height, | |
849 | NULL, &fcc, FIMC_SD_PAD_SOURCE); | |
850 | if (ffmt && ffmt->mbus_code) | |
851 | mf->code = ffmt->mbus_code; | |
b1aa6089 JL |
852 | if (mf->width != tfmt->width || |
853 | mf->height != tfmt->height) | |
237e0265 SN |
854 | continue; |
855 | tfmt->code = mf->code; | |
856 | } | |
857 | if (csis) | |
858 | ret = v4l2_subdev_call(csis, pad, set_fmt, NULL, &sfmt); | |
5f3cc447 | 859 | |
237e0265 | 860 | if (mf->code == tfmt->code && |
b1aa6089 | 861 | mf->width == tfmt->width && mf->height == tfmt->height) |
237e0265 SN |
862 | break; |
863 | } | |
5f3cc447 | 864 | |
237e0265 SN |
865 | if (fmt_id && ffmt) |
866 | *fmt_id = ffmt; | |
867 | *tfmt = *mf; | |
5f3cc447 | 868 | |
237e0265 SN |
869 | dbg("code: 0x%x, %dx%d, %p", mf->code, mf->width, mf->height, ffmt); |
870 | return 0; | |
871 | } | |
5f3cc447 | 872 | |
14783d25 SN |
873 | /** |
874 | * fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters | |
875 | * @sensor: pointer to the sensor subdev | |
876 | * @plane_fmt: provides plane sizes corresponding to the frame layout entries | |
877 | * @try: true to set the frame parameters, false to query only | |
878 | * | |
879 | * This function is used by this driver only for compressed/blob data formats. | |
880 | */ | |
881 | static int fimc_get_sensor_frame_desc(struct v4l2_subdev *sensor, | |
882 | struct v4l2_plane_pix_format *plane_fmt, | |
883 | unsigned int num_planes, bool try) | |
884 | { | |
885 | struct v4l2_mbus_frame_desc fd; | |
886 | int i, ret; | |
887 | ||
888 | for (i = 0; i < num_planes; i++) | |
889 | fd.entry[i].length = plane_fmt[i].sizeimage; | |
890 | ||
891 | if (try) | |
892 | ret = v4l2_subdev_call(sensor, pad, set_frame_desc, 0, &fd); | |
893 | else | |
894 | ret = v4l2_subdev_call(sensor, pad, get_frame_desc, 0, &fd); | |
895 | ||
896 | if (ret < 0) | |
897 | return ret; | |
898 | ||
899 | if (num_planes != fd.num_entries) | |
900 | return -EINVAL; | |
901 | ||
902 | for (i = 0; i < num_planes; i++) | |
903 | plane_fmt[i].sizeimage = fd.entry[i].length; | |
904 | ||
905 | if (fd.entry[0].length > FIMC_MAX_JPEG_BUF_SIZE) { | |
906 | v4l2_err(sensor->v4l2_dev, "Unsupported buffer size: %u\n", | |
907 | fd.entry[0].length); | |
908 | ||
909 | return -EINVAL; | |
910 | } | |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
e578588e SN |
915 | static int fimc_cap_g_fmt_mplane(struct file *file, void *fh, |
916 | struct v4l2_format *f) | |
917 | { | |
918 | struct fimc_dev *fimc = video_drvdata(file); | |
919 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
920 | ||
e578588e SN |
921 | return fimc_fill_format(&ctx->d_frame, f); |
922 | } | |
923 | ||
924 | static int fimc_cap_try_fmt_mplane(struct file *file, void *fh, | |
925 | struct v4l2_format *f) | |
926 | { | |
237e0265 | 927 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; |
e578588e SN |
928 | struct fimc_dev *fimc = video_drvdata(file); |
929 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
237e0265 SN |
930 | struct v4l2_mbus_framefmt mf; |
931 | struct fimc_fmt *ffmt = NULL; | |
932 | ||
14783d25 | 933 | if (fimc_jpeg_fourcc(pix->pixelformat)) { |
237e0265 SN |
934 | fimc_capture_try_format(ctx, &pix->width, &pix->height, |
935 | NULL, &pix->pixelformat, | |
936 | FIMC_SD_PAD_SINK); | |
937 | ctx->s_frame.f_width = pix->width; | |
938 | ctx->s_frame.f_height = pix->height; | |
939 | } | |
940 | ffmt = fimc_capture_try_format(ctx, &pix->width, &pix->height, | |
941 | NULL, &pix->pixelformat, | |
942 | FIMC_SD_PAD_SOURCE); | |
943 | if (!ffmt) | |
944 | return -EINVAL; | |
945 | ||
946 | if (!fimc->vid_cap.user_subdev_api) { | |
14783d25 | 947 | mf.width = pix->width; |
237e0265 | 948 | mf.height = pix->height; |
14783d25 | 949 | mf.code = ffmt->mbus_code; |
237e0265 SN |
950 | fimc_md_graph_lock(fimc); |
951 | fimc_pipeline_try_format(ctx, &mf, &ffmt, false); | |
952 | fimc_md_graph_unlock(fimc); | |
14783d25 SN |
953 | pix->width = mf.width; |
954 | pix->height = mf.height; | |
237e0265 SN |
955 | if (ffmt) |
956 | pix->pixelformat = ffmt->fourcc; | |
957 | } | |
e578588e | 958 | |
237e0265 | 959 | fimc_adjust_mplane_format(ffmt, pix->width, pix->height, pix); |
14783d25 SN |
960 | |
961 | if (ffmt->flags & FMT_FLAGS_COMPRESSED) | |
962 | fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR], | |
963 | pix->plane_fmt, ffmt->memplanes, true); | |
964 | ||
4db5e27e | 965 | return 0; |
e578588e SN |
966 | } |
967 | ||
14783d25 SN |
968 | static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx, |
969 | enum fimc_color_fmt color) | |
ee7160e5 | 970 | { |
14783d25 SN |
971 | bool jpeg = fimc_fmt_is_user_defined(color); |
972 | ||
ee7160e5 SN |
973 | ctx->scaler.enabled = !jpeg; |
974 | fimc_ctrls_activate(ctx, !jpeg); | |
975 | ||
976 | if (jpeg) | |
977 | set_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state); | |
978 | else | |
979 | clear_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state); | |
980 | } | |
981 | ||
237e0265 | 982 | static int fimc_capture_set_format(struct fimc_dev *fimc, struct v4l2_format *f) |
5f3cc447 | 983 | { |
e578588e | 984 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; |
237e0265 SN |
985 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; |
986 | struct v4l2_mbus_framefmt *mf = &fimc->vid_cap.mf; | |
987 | struct fimc_frame *ff = &ctx->d_frame; | |
988 | struct fimc_fmt *s_fmt = NULL; | |
989 | int ret, i; | |
5f3cc447 | 990 | |
237e0265 | 991 | if (vb2_is_busy(&fimc->vid_cap.vbq)) |
ef7af59b | 992 | return -EBUSY; |
5f3cc447 | 993 | |
237e0265 | 994 | /* Pre-configure format at camera interface input, for JPEG only */ |
14783d25 | 995 | if (fimc_jpeg_fourcc(pix->pixelformat)) { |
237e0265 SN |
996 | fimc_capture_try_format(ctx, &pix->width, &pix->height, |
997 | NULL, &pix->pixelformat, | |
998 | FIMC_SD_PAD_SINK); | |
999 | ctx->s_frame.f_width = pix->width; | |
1000 | ctx->s_frame.f_height = pix->height; | |
1001 | } | |
1002 | /* Try the format at the scaler and the DMA output */ | |
1003 | ff->fmt = fimc_capture_try_format(ctx, &pix->width, &pix->height, | |
1004 | NULL, &pix->pixelformat, | |
1005 | FIMC_SD_PAD_SOURCE); | |
1006 | if (!ff->fmt) | |
8293ebfc | 1007 | return -EINVAL; |
dafb9c70 SN |
1008 | |
1009 | /* Update RGB Alpha control state and value range */ | |
1010 | fimc_alpha_ctrl_update(ctx); | |
1011 | ||
237e0265 SN |
1012 | /* Try to match format at the host and the sensor */ |
1013 | if (!fimc->vid_cap.user_subdev_api) { | |
1014 | mf->code = ff->fmt->mbus_code; | |
1015 | mf->width = pix->width; | |
1016 | mf->height = pix->height; | |
1017 | ||
1018 | fimc_md_graph_lock(fimc); | |
1019 | ret = fimc_pipeline_try_format(ctx, mf, &s_fmt, true); | |
1020 | fimc_md_graph_unlock(fimc); | |
1021 | if (ret) | |
1022 | return ret; | |
1023 | pix->width = mf->width; | |
1024 | pix->height = mf->height; | |
1025 | } | |
d547ab66 | 1026 | |
237e0265 | 1027 | fimc_adjust_mplane_format(ff->fmt, pix->width, pix->height, pix); |
14783d25 SN |
1028 | |
1029 | if (ff->fmt->flags & FMT_FLAGS_COMPRESSED) { | |
1030 | ret = fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR], | |
1031 | pix->plane_fmt, ff->fmt->memplanes, | |
1032 | true); | |
1033 | if (ret < 0) | |
1034 | return ret; | |
1035 | } | |
1036 | ||
1037 | for (i = 0; i < ff->fmt->memplanes; i++) | |
d547ab66 | 1038 | ff->payload[i] = pix->plane_fmt[i].sizeimage; |
237e0265 SN |
1039 | |
1040 | set_frame_bounds(ff, pix->width, pix->height); | |
1041 | /* Reset the composition rectangle if not yet configured */ | |
fed07f84 | 1042 | if (!(ctx->state & FIMC_COMPOSE)) |
237e0265 SN |
1043 | set_frame_crop(ff, 0, 0, pix->width, pix->height); |
1044 | ||
14783d25 | 1045 | fimc_capture_mark_jpeg_xfer(ctx, ff->fmt->color); |
ee7160e5 | 1046 | |
237e0265 SN |
1047 | /* Reset cropping and set format at the camera interface input */ |
1048 | if (!fimc->vid_cap.user_subdev_api) { | |
1049 | ctx->s_frame.fmt = s_fmt; | |
1050 | set_frame_bounds(&ctx->s_frame, pix->width, pix->height); | |
1051 | set_frame_crop(&ctx->s_frame, 0, 0, pix->width, pix->height); | |
045030fa | 1052 | } |
ef7af59b | 1053 | |
237e0265 SN |
1054 | return ret; |
1055 | } | |
5f3cc447 | 1056 | |
237e0265 SN |
1057 | static int fimc_cap_s_fmt_mplane(struct file *file, void *priv, |
1058 | struct v4l2_format *f) | |
1059 | { | |
1060 | struct fimc_dev *fimc = video_drvdata(file); | |
5f3cc447 | 1061 | |
237e0265 | 1062 | return fimc_capture_set_format(fimc, f); |
5f3cc447 SN |
1063 | } |
1064 | ||
1065 | static int fimc_cap_enum_input(struct file *file, void *priv, | |
3e002182 | 1066 | struct v4l2_input *i) |
5f3cc447 | 1067 | { |
e578588e | 1068 | struct fimc_dev *fimc = video_drvdata(file); |
0f735f52 | 1069 | struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR]; |
5f3cc447 | 1070 | |
3e002182 | 1071 | if (i->index != 0) |
5f3cc447 SN |
1072 | return -EINVAL; |
1073 | ||
5f3cc447 | 1074 | i->type = V4L2_INPUT_TYPE_CAMERA; |
4db5e27e SN |
1075 | if (sd) |
1076 | strlcpy(i->name, sd->name, sizeof(i->name)); | |
5f3cc447 SN |
1077 | return 0; |
1078 | } | |
1079 | ||
3e002182 | 1080 | static int fimc_cap_s_input(struct file *file, void *priv, unsigned int i) |
5f3cc447 | 1081 | { |
3e002182 | 1082 | return i == 0 ? i : -EINVAL; |
5f3cc447 SN |
1083 | } |
1084 | ||
3e002182 | 1085 | static int fimc_cap_g_input(struct file *file, void *priv, unsigned int *i) |
5f3cc447 | 1086 | { |
3e002182 | 1087 | *i = 0; |
5f3cc447 SN |
1088 | return 0; |
1089 | } | |
1090 | ||
237e0265 SN |
1091 | /** |
1092 | * fimc_pipeline_validate - check for formats inconsistencies | |
1093 | * between source and sink pad of each link | |
1094 | * | |
1095 | * Return 0 if all formats match or -EPIPE otherwise. | |
1096 | */ | |
1097 | static int fimc_pipeline_validate(struct fimc_dev *fimc) | |
1098 | { | |
1099 | struct v4l2_subdev_format sink_fmt, src_fmt; | |
1100 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; | |
1101 | struct v4l2_subdev *sd; | |
1102 | struct media_pad *pad; | |
1103 | int ret; | |
1104 | ||
1105 | /* Start with the video capture node pad */ | |
1106 | pad = media_entity_remote_source(&vid_cap->vd_pad); | |
1107 | if (pad == NULL) | |
1108 | return -EPIPE; | |
1109 | /* FIMC.{N} subdevice */ | |
1110 | sd = media_entity_to_v4l2_subdev(pad->entity); | |
1111 | ||
1112 | while (1) { | |
1113 | /* Retrieve format at the sink pad */ | |
1114 | pad = &sd->entity.pads[0]; | |
1115 | if (!(pad->flags & MEDIA_PAD_FL_SINK)) | |
1116 | break; | |
1117 | /* Don't call FIMC subdev operation to avoid nested locking */ | |
693f5c40 | 1118 | if (sd == &fimc->vid_cap.subdev) { |
237e0265 SN |
1119 | struct fimc_frame *ff = &vid_cap->ctx->s_frame; |
1120 | sink_fmt.format.width = ff->f_width; | |
1121 | sink_fmt.format.height = ff->f_height; | |
1122 | sink_fmt.format.code = ff->fmt ? ff->fmt->mbus_code : 0; | |
1123 | } else { | |
1124 | sink_fmt.pad = pad->index; | |
1125 | sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
1126 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt); | |
1127 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
1128 | return -EPIPE; | |
1129 | } | |
1130 | /* Retrieve format at the source pad */ | |
1131 | pad = media_entity_remote_source(pad); | |
1132 | if (pad == NULL || | |
1133 | media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV) | |
1134 | break; | |
1135 | ||
1136 | sd = media_entity_to_v4l2_subdev(pad->entity); | |
1137 | src_fmt.pad = pad->index; | |
1138 | src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
1139 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt); | |
1140 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
1141 | return -EPIPE; | |
1142 | ||
1143 | if (src_fmt.format.width != sink_fmt.format.width || | |
1144 | src_fmt.format.height != sink_fmt.format.height || | |
1145 | src_fmt.format.code != sink_fmt.format.code) | |
1146 | return -EPIPE; | |
14783d25 SN |
1147 | |
1148 | if (sd == fimc->pipeline.subdevs[IDX_SENSOR] && | |
1149 | fimc_user_defined_mbus_fmt(src_fmt.format.code)) { | |
1150 | struct v4l2_plane_pix_format plane_fmt[FIMC_MAX_PLANES]; | |
1151 | struct fimc_frame *frame = &vid_cap->ctx->d_frame; | |
1152 | unsigned int i; | |
1153 | ||
1154 | ret = fimc_get_sensor_frame_desc(sd, plane_fmt, | |
1155 | frame->fmt->memplanes, | |
1156 | false); | |
1157 | if (ret < 0) | |
1158 | return -EPIPE; | |
1159 | ||
1160 | for (i = 0; i < frame->fmt->memplanes; i++) | |
1161 | if (frame->payload[i] < plane_fmt[i].sizeimage) | |
1162 | return -EPIPE; | |
1163 | } | |
237e0265 SN |
1164 | } |
1165 | return 0; | |
1166 | } | |
1167 | ||
5f3cc447 | 1168 | static int fimc_cap_streamon(struct file *file, void *priv, |
2dab38e2 | 1169 | enum v4l2_buf_type type) |
5f3cc447 | 1170 | { |
e578588e | 1171 | struct fimc_dev *fimc = video_drvdata(file); |
4db5e27e | 1172 | struct fimc_pipeline *p = &fimc->pipeline; |
f676fa06 | 1173 | struct v4l2_subdev *sd = p->subdevs[IDX_SENSOR]; |
237e0265 | 1174 | int ret; |
5f3cc447 | 1175 | |
4db5e27e | 1176 | if (fimc_capture_active(fimc)) |
8293ebfc | 1177 | return -EBUSY; |
5f3cc447 | 1178 | |
f676fa06 | 1179 | ret = media_entity_pipeline_start(&sd->entity, p->m_pipeline); |
a60a2959 SA |
1180 | if (ret < 0) |
1181 | return ret; | |
5f3cc447 | 1182 | |
237e0265 SN |
1183 | if (fimc->vid_cap.user_subdev_api) { |
1184 | ret = fimc_pipeline_validate(fimc); | |
f676fa06 SK |
1185 | if (ret < 0) { |
1186 | media_entity_pipeline_stop(&sd->entity); | |
237e0265 | 1187 | return ret; |
f676fa06 | 1188 | } |
237e0265 | 1189 | } |
8293ebfc | 1190 | return vb2_streamon(&fimc->vid_cap.vbq, type); |
5f3cc447 SN |
1191 | } |
1192 | ||
1193 | static int fimc_cap_streamoff(struct file *file, void *priv, | |
8293ebfc | 1194 | enum v4l2_buf_type type) |
5f3cc447 | 1195 | { |
e578588e | 1196 | struct fimc_dev *fimc = video_drvdata(file); |
0f735f52 | 1197 | struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR]; |
4db5e27e | 1198 | int ret; |
5f3cc447 | 1199 | |
4db5e27e SN |
1200 | ret = vb2_streamoff(&fimc->vid_cap.vbq, type); |
1201 | if (ret == 0) | |
1202 | media_entity_pipeline_stop(&sd->entity); | |
1203 | return ret; | |
5f3cc447 SN |
1204 | } |
1205 | ||
1206 | static int fimc_cap_reqbufs(struct file *file, void *priv, | |
ef7af59b | 1207 | struct v4l2_requestbuffers *reqbufs) |
5f3cc447 | 1208 | { |
e578588e SN |
1209 | struct fimc_dev *fimc = video_drvdata(file); |
1210 | int ret = vb2_reqbufs(&fimc->vid_cap.vbq, reqbufs); | |
5f3cc447 | 1211 | |
5f3cc447 | 1212 | if (!ret) |
e578588e | 1213 | fimc->vid_cap.reqbufs_count = reqbufs->count; |
5f3cc447 SN |
1214 | return ret; |
1215 | } | |
1216 | ||
1217 | static int fimc_cap_querybuf(struct file *file, void *priv, | |
1218 | struct v4l2_buffer *buf) | |
1219 | { | |
e578588e | 1220 | struct fimc_dev *fimc = video_drvdata(file); |
5f3cc447 | 1221 | |
e578588e | 1222 | return vb2_querybuf(&fimc->vid_cap.vbq, buf); |
5f3cc447 SN |
1223 | } |
1224 | ||
1225 | static int fimc_cap_qbuf(struct file *file, void *priv, | |
1226 | struct v4l2_buffer *buf) | |
1227 | { | |
e578588e SN |
1228 | struct fimc_dev *fimc = video_drvdata(file); |
1229 | ||
1230 | return vb2_qbuf(&fimc->vid_cap.vbq, buf); | |
5f3cc447 SN |
1231 | } |
1232 | ||
b28d61b6 TS |
1233 | static int fimc_cap_expbuf(struct file *file, void *priv, |
1234 | struct v4l2_exportbuffer *eb) | |
1235 | { | |
1236 | struct fimc_dev *fimc = video_drvdata(file); | |
1237 | ||
1238 | return vb2_expbuf(&fimc->vid_cap.vbq, eb); | |
1239 | } | |
1240 | ||
5f3cc447 SN |
1241 | static int fimc_cap_dqbuf(struct file *file, void *priv, |
1242 | struct v4l2_buffer *buf) | |
1243 | { | |
e578588e SN |
1244 | struct fimc_dev *fimc = video_drvdata(file); |
1245 | ||
1246 | return vb2_dqbuf(&fimc->vid_cap.vbq, buf, file->f_flags & O_NONBLOCK); | |
5f3cc447 SN |
1247 | } |
1248 | ||
3b4c34aa SN |
1249 | static int fimc_cap_create_bufs(struct file *file, void *priv, |
1250 | struct v4l2_create_buffers *create) | |
1251 | { | |
1252 | struct fimc_dev *fimc = video_drvdata(file); | |
1253 | ||
1254 | return vb2_create_bufs(&fimc->vid_cap.vbq, create); | |
1255 | } | |
1256 | ||
1257 | static int fimc_cap_prepare_buf(struct file *file, void *priv, | |
1258 | struct v4l2_buffer *b) | |
1259 | { | |
1260 | struct fimc_dev *fimc = video_drvdata(file); | |
1261 | ||
1262 | return vb2_prepare_buf(&fimc->vid_cap.vbq, b); | |
1263 | } | |
1264 | ||
f9331d11 SN |
1265 | static int fimc_cap_g_selection(struct file *file, void *fh, |
1266 | struct v4l2_selection *s) | |
e004e02f | 1267 | { |
e578588e | 1268 | struct fimc_dev *fimc = video_drvdata(file); |
f9331d11 SN |
1269 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; |
1270 | struct fimc_frame *f = &ctx->s_frame; | |
e004e02f | 1271 | |
f9331d11 | 1272 | if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) |
e004e02f SN |
1273 | return -EINVAL; |
1274 | ||
f9331d11 SN |
1275 | switch (s->target) { |
1276 | case V4L2_SEL_TGT_COMPOSE_DEFAULT: | |
1277 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: | |
1278 | f = &ctx->d_frame; | |
1279 | case V4L2_SEL_TGT_CROP_BOUNDS: | |
1280 | case V4L2_SEL_TGT_CROP_DEFAULT: | |
1281 | s->r.left = 0; | |
1282 | s->r.top = 0; | |
1283 | s->r.width = f->o_width; | |
1284 | s->r.height = f->o_height; | |
1285 | return 0; | |
e004e02f | 1286 | |
c1334823 | 1287 | case V4L2_SEL_TGT_COMPOSE: |
f9331d11 | 1288 | f = &ctx->d_frame; |
c1334823 | 1289 | case V4L2_SEL_TGT_CROP: |
f9331d11 SN |
1290 | s->r.left = f->offs_h; |
1291 | s->r.top = f->offs_v; | |
1292 | s->r.width = f->width; | |
1293 | s->r.height = f->height; | |
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | return -EINVAL; | |
e004e02f SN |
1298 | } |
1299 | ||
f9331d11 | 1300 | /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */ |
7e566be2 | 1301 | static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b) |
e004e02f | 1302 | { |
f9331d11 SN |
1303 | if (a->left < b->left || a->top < b->top) |
1304 | return 0; | |
1305 | if (a->left + a->width > b->left + b->width) | |
1306 | return 0; | |
1307 | if (a->top + a->height > b->top + b->height) | |
1308 | return 0; | |
e004e02f | 1309 | |
f9331d11 | 1310 | return 1; |
e004e02f SN |
1311 | } |
1312 | ||
f9331d11 SN |
1313 | static int fimc_cap_s_selection(struct file *file, void *fh, |
1314 | struct v4l2_selection *s) | |
5f3cc447 | 1315 | { |
e578588e SN |
1316 | struct fimc_dev *fimc = video_drvdata(file); |
1317 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
f9331d11 SN |
1318 | struct v4l2_rect rect = s->r; |
1319 | struct fimc_frame *f; | |
237e0265 | 1320 | unsigned long flags; |
f9331d11 SN |
1321 | |
1322 | if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) | |
1323 | return -EINVAL; | |
1324 | ||
c1334823 | 1325 | if (s->target == V4L2_SEL_TGT_COMPOSE) |
f9331d11 | 1326 | f = &ctx->d_frame; |
c1334823 | 1327 | else if (s->target == V4L2_SEL_TGT_CROP) |
f9331d11 | 1328 | f = &ctx->s_frame; |
fed07f84 | 1329 | else |
f9331d11 | 1330 | return -EINVAL; |
f9331d11 | 1331 | |
fed07f84 | 1332 | fimc_capture_try_selection(ctx, &rect, s->target); |
f9331d11 SN |
1333 | |
1334 | if (s->flags & V4L2_SEL_FLAG_LE && | |
1335 | !enclosed_rectangle(&rect, &s->r)) | |
1336 | return -ERANGE; | |
5f3cc447 | 1337 | |
f9331d11 SN |
1338 | if (s->flags & V4L2_SEL_FLAG_GE && |
1339 | !enclosed_rectangle(&s->r, &rect)) | |
1340 | return -ERANGE; | |
5f3cc447 | 1341 | |
f9331d11 | 1342 | s->r = rect; |
237e0265 | 1343 | spin_lock_irqsave(&fimc->slock, flags); |
f9331d11 SN |
1344 | set_frame_crop(f, s->r.left, s->r.top, s->r.width, |
1345 | s->r.height); | |
237e0265 | 1346 | spin_unlock_irqrestore(&fimc->slock, flags); |
8293ebfc | 1347 | |
f9331d11 | 1348 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); |
8293ebfc | 1349 | return 0; |
5f3cc447 SN |
1350 | } |
1351 | ||
5f3cc447 SN |
1352 | static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = { |
1353 | .vidioc_querycap = fimc_vidioc_querycap_capture, | |
1354 | ||
cf52df8a | 1355 | .vidioc_enum_fmt_vid_cap_mplane = fimc_cap_enum_fmt_mplane, |
e578588e | 1356 | .vidioc_try_fmt_vid_cap_mplane = fimc_cap_try_fmt_mplane, |
ef7af59b | 1357 | .vidioc_s_fmt_vid_cap_mplane = fimc_cap_s_fmt_mplane, |
e578588e | 1358 | .vidioc_g_fmt_vid_cap_mplane = fimc_cap_g_fmt_mplane, |
5f3cc447 SN |
1359 | |
1360 | .vidioc_reqbufs = fimc_cap_reqbufs, | |
1361 | .vidioc_querybuf = fimc_cap_querybuf, | |
1362 | ||
1363 | .vidioc_qbuf = fimc_cap_qbuf, | |
1364 | .vidioc_dqbuf = fimc_cap_dqbuf, | |
b28d61b6 | 1365 | .vidioc_expbuf = fimc_cap_expbuf, |
5f3cc447 | 1366 | |
3b4c34aa SN |
1367 | .vidioc_prepare_buf = fimc_cap_prepare_buf, |
1368 | .vidioc_create_bufs = fimc_cap_create_bufs, | |
1369 | ||
5f3cc447 SN |
1370 | .vidioc_streamon = fimc_cap_streamon, |
1371 | .vidioc_streamoff = fimc_cap_streamoff, | |
1372 | ||
f9331d11 SN |
1373 | .vidioc_g_selection = fimc_cap_g_selection, |
1374 | .vidioc_s_selection = fimc_cap_s_selection, | |
5f3cc447 SN |
1375 | |
1376 | .vidioc_enum_input = fimc_cap_enum_input, | |
1377 | .vidioc_s_input = fimc_cap_s_input, | |
1378 | .vidioc_g_input = fimc_cap_g_input, | |
1379 | }; | |
1380 | ||
237e0265 | 1381 | /* Capture subdev media entity operations */ |
d09a7dc8 SN |
1382 | static int fimc_link_setup(struct media_entity *entity, |
1383 | const struct media_pad *local, | |
1384 | const struct media_pad *remote, u32 flags) | |
1385 | { | |
237e0265 SN |
1386 | struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); |
1387 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1388 | ||
1389 | if (media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV) | |
1390 | return -EINVAL; | |
d09a7dc8 SN |
1391 | |
1392 | if (WARN_ON(fimc == NULL)) | |
1393 | return 0; | |
1394 | ||
1395 | dbg("%s --> %s, flags: 0x%x. input: 0x%x", | |
1396 | local->entity->name, remote->entity->name, flags, | |
1397 | fimc->vid_cap.input); | |
1398 | ||
1399 | if (flags & MEDIA_LNK_FL_ENABLED) { | |
1400 | if (fimc->vid_cap.input != 0) | |
1401 | return -EBUSY; | |
1402 | fimc->vid_cap.input = sd->grp_id; | |
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | fimc->vid_cap.input = 0; | |
1407 | return 0; | |
1408 | } | |
1409 | ||
237e0265 | 1410 | static const struct media_entity_operations fimc_sd_media_ops = { |
d09a7dc8 SN |
1411 | .link_setup = fimc_link_setup, |
1412 | }; | |
1413 | ||
e1d72f4d SN |
1414 | /** |
1415 | * fimc_sensor_notify - v4l2_device notification from a sensor subdev | |
1416 | * @sd: pointer to a subdev generating the notification | |
1417 | * @notification: the notification type, must be S5P_FIMC_TX_END_NOTIFY | |
1418 | * @arg: pointer to an u32 type integer that stores the frame payload value | |
1419 | * | |
1420 | * The End Of Frame notification sent by sensor subdev in its still capture | |
1421 | * mode. If there is only a single VSYNC generated by the sensor at the | |
1422 | * beginning of a frame transmission, FIMC does not issue the LastIrq | |
1423 | * (end of frame) interrupt. And this notification is used to complete the | |
1424 | * frame capture and returning a buffer to user-space. Subdev drivers should | |
1425 | * call this notification from their last 'End of frame capture' interrupt. | |
1426 | */ | |
1427 | void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification, | |
1428 | void *arg) | |
1429 | { | |
1430 | struct fimc_sensor_info *sensor; | |
1431 | struct fimc_vid_buffer *buf; | |
1432 | struct fimc_md *fmd; | |
1433 | struct fimc_dev *fimc; | |
1434 | unsigned long flags; | |
1435 | ||
1436 | if (sd == NULL) | |
1437 | return; | |
1438 | ||
1439 | sensor = v4l2_get_subdev_hostdata(sd); | |
1440 | fmd = entity_to_fimc_mdev(&sd->entity); | |
1441 | ||
1442 | spin_lock_irqsave(&fmd->slock, flags); | |
1443 | fimc = sensor ? sensor->host : NULL; | |
1444 | ||
1445 | if (fimc && arg && notification == S5P_FIMC_TX_END_NOTIFY && | |
1446 | test_bit(ST_CAPT_PEND, &fimc->state)) { | |
1447 | unsigned long irq_flags; | |
1448 | spin_lock_irqsave(&fimc->slock, irq_flags); | |
1449 | if (!list_empty(&fimc->vid_cap.active_buf_q)) { | |
1450 | buf = list_entry(fimc->vid_cap.active_buf_q.next, | |
1451 | struct fimc_vid_buffer, list); | |
1452 | vb2_set_plane_payload(&buf->vb, 0, *((u32 *)arg)); | |
1453 | } | |
97d97422 | 1454 | fimc_capture_irq_handler(fimc, 1); |
e1d72f4d SN |
1455 | fimc_deactivate_capture(fimc); |
1456 | spin_unlock_irqrestore(&fimc->slock, irq_flags); | |
1457 | } | |
1458 | spin_unlock_irqrestore(&fmd->slock, flags); | |
1459 | } | |
1460 | ||
237e0265 SN |
1461 | static int fimc_subdev_enum_mbus_code(struct v4l2_subdev *sd, |
1462 | struct v4l2_subdev_fh *fh, | |
1463 | struct v4l2_subdev_mbus_code_enum *code) | |
1464 | { | |
1465 | struct fimc_fmt *fmt; | |
1466 | ||
1467 | fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, code->index); | |
1468 | if (!fmt) | |
1469 | return -EINVAL; | |
1470 | code->code = fmt->mbus_code; | |
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static int fimc_subdev_get_fmt(struct v4l2_subdev *sd, | |
1475 | struct v4l2_subdev_fh *fh, | |
1476 | struct v4l2_subdev_format *fmt) | |
1477 | { | |
1478 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1479 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
1480 | struct v4l2_mbus_framefmt *mf; | |
1481 | struct fimc_frame *ff; | |
1482 | ||
1483 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1484 | mf = v4l2_subdev_get_try_format(fh, fmt->pad); | |
1485 | fmt->format = *mf; | |
1486 | return 0; | |
1487 | } | |
1488 | mf = &fmt->format; | |
1489 | mf->colorspace = V4L2_COLORSPACE_JPEG; | |
1490 | ff = fmt->pad == FIMC_SD_PAD_SINK ? &ctx->s_frame : &ctx->d_frame; | |
1491 | ||
1492 | mutex_lock(&fimc->lock); | |
1493 | /* The pixel code is same on both input and output pad */ | |
1494 | if (!WARN_ON(ctx->s_frame.fmt == NULL)) | |
1495 | mf->code = ctx->s_frame.fmt->mbus_code; | |
1496 | mf->width = ff->f_width; | |
1497 | mf->height = ff->f_height; | |
1498 | mutex_unlock(&fimc->lock); | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | static int fimc_subdev_set_fmt(struct v4l2_subdev *sd, | |
1504 | struct v4l2_subdev_fh *fh, | |
1505 | struct v4l2_subdev_format *fmt) | |
1506 | { | |
1507 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1508 | struct v4l2_mbus_framefmt *mf = &fmt->format; | |
1509 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
1510 | struct fimc_frame *ff; | |
1511 | struct fimc_fmt *ffmt; | |
1512 | ||
1513 | dbg("pad%d: code: 0x%x, %dx%d", | |
1514 | fmt->pad, mf->code, mf->width, mf->height); | |
1515 | ||
1516 | if (fmt->pad == FIMC_SD_PAD_SOURCE && | |
1517 | vb2_is_busy(&fimc->vid_cap.vbq)) | |
1518 | return -EBUSY; | |
1519 | ||
1520 | mutex_lock(&fimc->lock); | |
1521 | ffmt = fimc_capture_try_format(ctx, &mf->width, &mf->height, | |
1522 | &mf->code, NULL, fmt->pad); | |
1523 | mutex_unlock(&fimc->lock); | |
1524 | mf->colorspace = V4L2_COLORSPACE_JPEG; | |
1525 | ||
1526 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1527 | mf = v4l2_subdev_get_try_format(fh, fmt->pad); | |
1528 | *mf = fmt->format; | |
1529 | return 0; | |
1530 | } | |
dafb9c70 SN |
1531 | /* Update RGB Alpha control state and value range */ |
1532 | fimc_alpha_ctrl_update(ctx); | |
1533 | ||
14783d25 | 1534 | fimc_capture_mark_jpeg_xfer(ctx, ffmt->color); |
ee7160e5 | 1535 | |
237e0265 SN |
1536 | ff = fmt->pad == FIMC_SD_PAD_SINK ? |
1537 | &ctx->s_frame : &ctx->d_frame; | |
1538 | ||
1539 | mutex_lock(&fimc->lock); | |
1540 | set_frame_bounds(ff, mf->width, mf->height); | |
393a23fc | 1541 | fimc->vid_cap.mf = *mf; |
237e0265 SN |
1542 | ff->fmt = ffmt; |
1543 | ||
1544 | /* Reset the crop rectangle if required. */ | |
fed07f84 | 1545 | if (!(fmt->pad == FIMC_SD_PAD_SOURCE && (ctx->state & FIMC_COMPOSE))) |
237e0265 SN |
1546 | set_frame_crop(ff, 0, 0, mf->width, mf->height); |
1547 | ||
1548 | if (fmt->pad == FIMC_SD_PAD_SINK) | |
fed07f84 | 1549 | ctx->state &= ~FIMC_COMPOSE; |
237e0265 SN |
1550 | mutex_unlock(&fimc->lock); |
1551 | return 0; | |
1552 | } | |
1553 | ||
fed07f84 SN |
1554 | static int fimc_subdev_get_selection(struct v4l2_subdev *sd, |
1555 | struct v4l2_subdev_fh *fh, | |
1556 | struct v4l2_subdev_selection *sel) | |
237e0265 SN |
1557 | { |
1558 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1559 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
fed07f84 SN |
1560 | struct fimc_frame *f = &ctx->s_frame; |
1561 | struct v4l2_rect *r = &sel->r; | |
1562 | struct v4l2_rect *try_sel; | |
1563 | ||
1564 | if (sel->pad != FIMC_SD_PAD_SINK) | |
1565 | return -EINVAL; | |
1566 | ||
1567 | mutex_lock(&fimc->lock); | |
237e0265 | 1568 | |
fed07f84 | 1569 | switch (sel->target) { |
5689b288 | 1570 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: |
fed07f84 | 1571 | f = &ctx->d_frame; |
5689b288 | 1572 | case V4L2_SEL_TGT_CROP_BOUNDS: |
fed07f84 SN |
1573 | r->width = f->o_width; |
1574 | r->height = f->o_height; | |
1575 | r->left = 0; | |
1576 | r->top = 0; | |
1577 | mutex_unlock(&fimc->lock); | |
237e0265 | 1578 | return 0; |
fed07f84 | 1579 | |
5689b288 | 1580 | case V4L2_SEL_TGT_CROP: |
fed07f84 SN |
1581 | try_sel = v4l2_subdev_get_try_crop(fh, sel->pad); |
1582 | break; | |
5689b288 | 1583 | case V4L2_SEL_TGT_COMPOSE: |
fed07f84 SN |
1584 | try_sel = v4l2_subdev_get_try_compose(fh, sel->pad); |
1585 | f = &ctx->d_frame; | |
1586 | break; | |
1587 | default: | |
1588 | mutex_unlock(&fimc->lock); | |
1589 | return -EINVAL; | |
237e0265 | 1590 | } |
237e0265 | 1591 | |
fed07f84 SN |
1592 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
1593 | sel->r = *try_sel; | |
1594 | } else { | |
1595 | r->left = f->offs_h; | |
1596 | r->top = f->offs_v; | |
1597 | r->width = f->width; | |
1598 | r->height = f->height; | |
1599 | } | |
237e0265 | 1600 | |
fed07f84 SN |
1601 | dbg("target %#x: l:%d, t:%d, %dx%d, f_w: %d, f_h: %d", |
1602 | sel->pad, r->left, r->top, r->width, r->height, | |
1603 | f->f_width, f->f_height); | |
237e0265 | 1604 | |
fed07f84 | 1605 | mutex_unlock(&fimc->lock); |
237e0265 SN |
1606 | return 0; |
1607 | } | |
1608 | ||
fed07f84 SN |
1609 | static int fimc_subdev_set_selection(struct v4l2_subdev *sd, |
1610 | struct v4l2_subdev_fh *fh, | |
1611 | struct v4l2_subdev_selection *sel) | |
237e0265 SN |
1612 | { |
1613 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1614 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
fed07f84 SN |
1615 | struct fimc_frame *f = &ctx->s_frame; |
1616 | struct v4l2_rect *r = &sel->r; | |
1617 | struct v4l2_rect *try_sel; | |
237e0265 SN |
1618 | unsigned long flags; |
1619 | ||
fed07f84 SN |
1620 | if (sel->pad != FIMC_SD_PAD_SINK) |
1621 | return -EINVAL; | |
237e0265 SN |
1622 | |
1623 | mutex_lock(&fimc->lock); | |
c1334823 | 1624 | fimc_capture_try_selection(ctx, r, V4L2_SEL_TGT_CROP); |
237e0265 | 1625 | |
fed07f84 | 1626 | switch (sel->target) { |
5689b288 | 1627 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: |
fed07f84 | 1628 | f = &ctx->d_frame; |
5689b288 | 1629 | case V4L2_SEL_TGT_CROP_BOUNDS: |
fed07f84 SN |
1630 | r->width = f->o_width; |
1631 | r->height = f->o_height; | |
1632 | r->left = 0; | |
1633 | r->top = 0; | |
5be4fe63 | 1634 | mutex_unlock(&fimc->lock); |
237e0265 | 1635 | return 0; |
fed07f84 | 1636 | |
5689b288 | 1637 | case V4L2_SEL_TGT_CROP: |
fed07f84 SN |
1638 | try_sel = v4l2_subdev_get_try_crop(fh, sel->pad); |
1639 | break; | |
5689b288 | 1640 | case V4L2_SEL_TGT_COMPOSE: |
fed07f84 SN |
1641 | try_sel = v4l2_subdev_get_try_compose(fh, sel->pad); |
1642 | f = &ctx->d_frame; | |
1643 | break; | |
1644 | default: | |
1645 | mutex_unlock(&fimc->lock); | |
1646 | return -EINVAL; | |
237e0265 | 1647 | } |
237e0265 | 1648 | |
fed07f84 SN |
1649 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
1650 | *try_sel = sel->r; | |
1651 | } else { | |
1652 | spin_lock_irqsave(&fimc->slock, flags); | |
1653 | set_frame_crop(f, r->left, r->top, r->width, r->height); | |
1654 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
1655 | spin_unlock_irqrestore(&fimc->slock, flags); | |
5689b288 | 1656 | if (sel->target == V4L2_SEL_TGT_COMPOSE) |
fed07f84 SN |
1657 | ctx->state |= FIMC_COMPOSE; |
1658 | } | |
237e0265 | 1659 | |
fed07f84 | 1660 | dbg("target %#x: (%d,%d)/%dx%d", sel->target, r->left, r->top, |
237e0265 SN |
1661 | r->width, r->height); |
1662 | ||
1663 | mutex_unlock(&fimc->lock); | |
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static struct v4l2_subdev_pad_ops fimc_subdev_pad_ops = { | |
1668 | .enum_mbus_code = fimc_subdev_enum_mbus_code, | |
fed07f84 SN |
1669 | .get_selection = fimc_subdev_get_selection, |
1670 | .set_selection = fimc_subdev_set_selection, | |
237e0265 SN |
1671 | .get_fmt = fimc_subdev_get_fmt, |
1672 | .set_fmt = fimc_subdev_set_fmt, | |
237e0265 SN |
1673 | }; |
1674 | ||
1675 | static struct v4l2_subdev_ops fimc_subdev_ops = { | |
1676 | .pad = &fimc_subdev_pad_ops, | |
1677 | }; | |
1678 | ||
237e0265 SN |
1679 | /* Set default format at the sensor and host interface */ |
1680 | static int fimc_capture_set_default_format(struct fimc_dev *fimc) | |
1681 | { | |
1682 | struct v4l2_format fmt = { | |
1683 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, | |
1684 | .fmt.pix_mp = { | |
1685 | .width = 640, | |
1686 | .height = 480, | |
1687 | .pixelformat = V4L2_PIX_FMT_YUYV, | |
1688 | .field = V4L2_FIELD_NONE, | |
1689 | .colorspace = V4L2_COLORSPACE_JPEG, | |
1690 | }, | |
1691 | }; | |
1692 | ||
1693 | return fimc_capture_set_format(fimc, &fmt); | |
1694 | } | |
1695 | ||
ef7af59b | 1696 | /* fimc->lock must be already initialized */ |
693f5c40 | 1697 | static int fimc_register_capture_device(struct fimc_dev *fimc, |
30c9939d | 1698 | struct v4l2_device *v4l2_dev) |
5f3cc447 | 1699 | { |
31d34d9b | 1700 | struct video_device *vfd = &fimc->vid_cap.vfd; |
5f3cc447 SN |
1701 | struct fimc_vid_cap *vid_cap; |
1702 | struct fimc_ctx *ctx; | |
2dab38e2 | 1703 | struct vb2_queue *q; |
30c9939d | 1704 | int ret = -ENOMEM; |
5f3cc447 | 1705 | |
26ee7f47 | 1706 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
5f3cc447 SN |
1707 | if (!ctx) |
1708 | return -ENOMEM; | |
1709 | ||
1710 | ctx->fimc_dev = fimc; | |
3d112d9a SN |
1711 | ctx->in_path = FIMC_IO_CAMERA; |
1712 | ctx->out_path = FIMC_IO_DMA; | |
5f3cc447 | 1713 | ctx->state = FIMC_CTX_CAP; |
237e0265 | 1714 | ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0); |
693f5c40 | 1715 | ctx->d_frame.fmt = ctx->s_frame.fmt; |
5f3cc447 | 1716 | |
31d34d9b | 1717 | memset(vfd, 0, sizeof(*vfd)); |
693f5c40 | 1718 | snprintf(vfd->name, sizeof(vfd->name), "fimc.%d.capture", fimc->id); |
5f3cc447 SN |
1719 | |
1720 | vfd->fops = &fimc_capture_fops; | |
1721 | vfd->ioctl_ops = &fimc_capture_ioctl_ops; | |
574e1717 | 1722 | vfd->v4l2_dev = v4l2_dev; |
5f3cc447 | 1723 | vfd->minor = -1; |
31d34d9b | 1724 | vfd->release = video_device_release_empty; |
8293ebfc | 1725 | vfd->lock = &fimc->lock; |
c2d430af | 1726 | |
5f3cc447 SN |
1727 | video_set_drvdata(vfd, fimc); |
1728 | ||
1729 | vid_cap = &fimc->vid_cap; | |
5f3cc447 SN |
1730 | vid_cap->active_buf_cnt = 0; |
1731 | vid_cap->reqbufs_count = 0; | |
1732 | vid_cap->refcnt = 0; | |
5f3cc447 SN |
1733 | |
1734 | INIT_LIST_HEAD(&vid_cap->pending_buf_q); | |
1735 | INIT_LIST_HEAD(&vid_cap->active_buf_q); | |
5f3cc447 SN |
1736 | vid_cap->ctx = ctx; |
1737 | ||
2dab38e2 SN |
1738 | q = &fimc->vid_cap.vbq; |
1739 | memset(q, 0, sizeof(*q)); | |
ef7af59b | 1740 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; |
9bd09fd7 | 1741 | q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; |
2dab38e2 SN |
1742 | q->drv_priv = fimc->vid_cap.ctx; |
1743 | q->ops = &fimc_capture_qops; | |
1744 | q->mem_ops = &vb2_dma_contig_memops; | |
1745 | q->buf_struct_size = sizeof(struct fimc_vid_buffer); | |
1746 | ||
41fd087f SN |
1747 | ret = vb2_queue_init(q); |
1748 | if (ret) | |
1749 | goto err_ent; | |
5f3cc447 | 1750 | |
693f5c40 SN |
1751 | vid_cap->vd_pad.flags = MEDIA_PAD_FL_SINK; |
1752 | ret = media_entity_init(&vfd->entity, 1, &vid_cap->vd_pad, 0); | |
574e1717 SN |
1753 | if (ret) |
1754 | goto err_ent; | |
693f5c40 SN |
1755 | |
1756 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1); | |
237e0265 | 1757 | if (ret) |
693f5c40 SN |
1758 | goto err_vd; |
1759 | ||
1760 | v4l2_info(v4l2_dev, "Registered %s as /dev/%s\n", | |
1761 | vfd->name, video_device_node_name(vfd)); | |
574e1717 | 1762 | |
9448ab7d | 1763 | vfd->ctrl_handler = &ctx->ctrls.handler; |
5f3cc447 SN |
1764 | return 0; |
1765 | ||
693f5c40 | 1766 | err_vd: |
237e0265 | 1767 | media_entity_cleanup(&vfd->entity); |
574e1717 | 1768 | err_ent: |
cfd77310 | 1769 | kfree(ctx); |
5f3cc447 SN |
1770 | return ret; |
1771 | } | |
1772 | ||
693f5c40 | 1773 | static int fimc_capture_subdev_registered(struct v4l2_subdev *sd) |
5f3cc447 | 1774 | { |
693f5c40 SN |
1775 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); |
1776 | int ret; | |
5f3cc447 | 1777 | |
bbc5296f SN |
1778 | if (fimc == NULL) |
1779 | return -ENXIO; | |
1780 | ||
693f5c40 SN |
1781 | ret = fimc_register_m2m_device(fimc, sd->v4l2_dev); |
1782 | if (ret) | |
1783 | return ret; | |
1784 | ||
97d66c47 SN |
1785 | fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd); |
1786 | ||
693f5c40 | 1787 | ret = fimc_register_capture_device(fimc, sd->v4l2_dev); |
97d66c47 | 1788 | if (ret) { |
693f5c40 | 1789 | fimc_unregister_m2m_device(fimc); |
97d66c47 SN |
1790 | fimc->pipeline_ops = NULL; |
1791 | } | |
693f5c40 SN |
1792 | |
1793 | return ret; | |
1794 | } | |
1795 | ||
1796 | static void fimc_capture_subdev_unregistered(struct v4l2_subdev *sd) | |
1797 | { | |
1798 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1799 | ||
1800 | if (fimc == NULL) | |
1801 | return; | |
1802 | ||
1803 | fimc_unregister_m2m_device(fimc); | |
1804 | ||
31d34d9b SN |
1805 | if (video_is_registered(&fimc->vid_cap.vfd)) { |
1806 | video_unregister_device(&fimc->vid_cap.vfd); | |
1807 | media_entity_cleanup(&fimc->vid_cap.vfd.entity); | |
97d66c47 | 1808 | fimc->pipeline_ops = NULL; |
574e1717 SN |
1809 | } |
1810 | kfree(fimc->vid_cap.ctx); | |
96a85742 | 1811 | fimc->vid_cap.ctx = NULL; |
5f3cc447 | 1812 | } |
693f5c40 SN |
1813 | |
1814 | static const struct v4l2_subdev_internal_ops fimc_capture_sd_internal_ops = { | |
1815 | .registered = fimc_capture_subdev_registered, | |
1816 | .unregistered = fimc_capture_subdev_unregistered, | |
1817 | }; | |
1818 | ||
1819 | int fimc_initialize_capture_subdev(struct fimc_dev *fimc) | |
1820 | { | |
1821 | struct v4l2_subdev *sd = &fimc->vid_cap.subdev; | |
1822 | int ret; | |
1823 | ||
1824 | v4l2_subdev_init(sd, &fimc_subdev_ops); | |
1825 | sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE; | |
1826 | snprintf(sd->name, sizeof(sd->name), "FIMC.%d", fimc->pdev->id); | |
1827 | ||
1828 | fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK; | |
1829 | fimc->vid_cap.sd_pads[FIMC_SD_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; | |
1830 | ret = media_entity_init(&sd->entity, FIMC_SD_PADS_NUM, | |
1831 | fimc->vid_cap.sd_pads, 0); | |
1832 | if (ret) | |
1833 | return ret; | |
1834 | ||
1835 | sd->entity.ops = &fimc_sd_media_ops; | |
1836 | sd->internal_ops = &fimc_capture_sd_internal_ops; | |
1837 | v4l2_set_subdevdata(sd, fimc); | |
1838 | return 0; | |
1839 | } | |
1840 | ||
1841 | void fimc_unregister_capture_subdev(struct fimc_dev *fimc) | |
1842 | { | |
1843 | struct v4l2_subdev *sd = &fimc->vid_cap.subdev; | |
1844 | ||
1845 | v4l2_device_unregister_subdev(sd); | |
1846 | media_entity_cleanup(&sd->entity); | |
1847 | v4l2_set_subdevdata(sd, NULL); | |
1848 | } |