projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| babde1c2 SN |
1 | /* |
| 2 | * Register definition file for s3c24xx/s3c64xx SoC CAMIF driver | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com> | |
| 5 | * Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef CAMIF_REGS_H_ | |
| 13 | #define CAMIF_REGS_H_ | |
| 14 | ||
| 15 | #include "camif-core.h" | |
| d647f0b7 | 16 | #include <media/drv-intf/s3c_camif.h> |
| babde1c2 SN |
17 | |
| 18 | /* | |
| 19 | * The id argument indicates the processing path: | |
| 20 | * id = 0 - codec (FIMC C), 1 - preview (FIMC P). | |
| 21 | */ | |
| 22 | ||
| 23 | /* Camera input format */ | |
| 24 | #define S3C_CAMIF_REG_CISRCFMT 0x00 | |
| 25 | #define CISRCFMT_ITU601_8BIT (1 << 31) | |
| 26 | #define CISRCFMT_ITU656_8BIT (0 << 31) | |
| 27 | #define CISRCFMT_ORDER422_YCBYCR (0 << 14) | |
| 28 | #define CISRCFMT_ORDER422_YCRYCB (1 << 14) | |
| 29 | #define CISRCFMT_ORDER422_CBYCRY (2 << 14) | |
| 30 | #define CISRCFMT_ORDER422_CRYCBY (3 << 14) | |
| 31 | #define CISRCFMT_ORDER422_MASK (3 << 14) | |
| 32 | #define CISRCFMT_SIZE_CAM_MASK (0x1fff << 16 | 0x1fff) | |
| 33 | ||
| 34 | /* Window offset */ | |
| 35 | #define S3C_CAMIF_REG_CIWDOFST 0x04 | |
| 36 | #define CIWDOFST_WINOFSEN (1 << 31) | |
| 37 | #define CIWDOFST_CLROVCOFIY (1 << 30) | |
| 38 | #define CIWDOFST_CLROVRLB_PR (1 << 28) | |
| 39 | /* #define CIWDOFST_CLROVPRFIY (1 << 27) */ | |
| 40 | #define CIWDOFST_CLROVCOFICB (1 << 15) | |
| 41 | #define CIWDOFST_CLROVCOFICR (1 << 14) | |
| 42 | #define CIWDOFST_CLROVPRFICB (1 << 13) | |
| 43 | #define CIWDOFST_CLROVPRFICR (1 << 12) | |
| 44 | #define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff) | |
| 45 | ||
| 46 | /* Window offset 2 */ | |
| 47 | #define S3C_CAMIF_REG_CIWDOFST2 0x14 | |
| 48 | #define CIWDOFST2_OFST2_MASK (0xfff << 16 | 0xfff) | |
| 49 | ||
| 50 | /* Global control */ | |
| 51 | #define S3C_CAMIF_REG_CIGCTRL 0x08 | |
| 52 | #define CIGCTRL_SWRST (1 << 31) | |
| 53 | #define CIGCTRL_CAMRST (1 << 30) | |
| 54 | #define CIGCTRL_TESTPATTERN_NORMAL (0 << 27) | |
| 55 | #define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) | |
| 56 | #define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) | |
| 57 | #define CIGCTRL_TESTPATTERN_VER_INC (3 << 27) | |
| 58 | #define CIGCTRL_TESTPATTERN_MASK (3 << 27) | |
| 59 | #define CIGCTRL_INVPOLPCLK (1 << 26) | |
| 60 | #define CIGCTRL_INVPOLVSYNC (1 << 25) | |
| 61 | #define CIGCTRL_INVPOLHREF (1 << 24) | |
| 62 | #define CIGCTRL_IRQ_OVFEN (1 << 22) | |
| 63 | #define CIGCTRL_HREF_MASK (1 << 21) | |
| 64 | #define CIGCTRL_IRQ_LEVEL (1 << 20) | |
| 65 | /* IRQ_CLR_C, IRQ_CLR_P */ | |
| 66 | #define CIGCTRL_IRQ_CLR(id) (1 << (19 - (id))) | |
| 67 | #define CIGCTRL_FIELDMODE (1 << 2) | |
| 68 | #define CIGCTRL_INVPOLFIELD (1 << 1) | |
| 69 | #define CIGCTRL_CAM_INTERLACE (1 << 0) | |
| 70 | ||
| 71 | /* Y DMA output frame start address. n = 0..3. */ | |
| 72 | #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) | |
| 73 | /* Cb plane output DMA start address. n = 0..3. Only codec path. */ | |
| 74 | #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4) | |
| 75 | /* Cr plane output DMA start address. n = 0..3. Only codec path. */ | |
| 76 | #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4) | |
| 77 | ||
| 78 | /* CICOTRGFMT, CIPRTRGFMT - Target format */ | |
| 79 | #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) | |
| 80 | #define CITRGFMT_IN422 (1 << 31) /* only for s3c24xx */ | |
| 81 | #define CITRGFMT_OUT422 (1 << 30) /* only for s3c24xx */ | |
| 82 | #define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */ | |
| 83 | #define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */ | |
| 84 | #define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */ | |
| 85 | #define CITRGFMT_OUTFORMAT_RGB (3 << 29) /* only for s3c6410 */ | |
| 86 | #define CITRGFMT_OUTFORMAT_MASK (3 << 29) /* only for s3c6410 */ | |
| 87 | #define CITRGFMT_TARGETHSIZE(x) ((x) << 16) | |
| 88 | #define CITRGFMT_FLIP_NORMAL (0 << 14) | |
| 89 | #define CITRGFMT_FLIP_X_MIRROR (1 << 14) | |
| 90 | #define CITRGFMT_FLIP_Y_MIRROR (2 << 14) | |
| 91 | #define CITRGFMT_FLIP_180 (3 << 14) | |
| 92 | #define CITRGFMT_FLIP_MASK (3 << 14) | |
| 93 | /* Preview path only */ | |
| 94 | #define CITRGFMT_ROT90_PR (1 << 13) | |
| 95 | #define CITRGFMT_TARGETVSIZE(x) ((x) << 0) | |
| 96 | #define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff) | |
| 97 | ||
| 98 | /* CICOCTRL, CIPRCTRL. Output DMA control. */ | |
| 99 | #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs))) | |
| 100 | #define CICTRL_BURST_MASK (0xfffff << 4) | |
| 101 | /* xBURSTn - 5-bits width */ | |
| 102 | #define CICTRL_YBURST1(x) ((x) << 19) | |
| 103 | #define CICTRL_YBURST2(x) ((x) << 14) | |
| 104 | #define CICTRL_RGBBURST1(x) ((x) << 19) | |
| 105 | #define CICTRL_RGBBURST2(x) ((x) << 14) | |
| 106 | #define CICTRL_CBURST1(x) ((x) << 9) | |
| 107 | #define CICTRL_CBURST2(x) ((x) << 4) | |
| 108 | #define CICTRL_LASTIRQ_ENABLE (1 << 2) | |
| 109 | #define CICTRL_ORDER422_MASK (3 << 0) | |
| 110 | ||
| 111 | /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */ | |
| 112 | #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs))) | |
| 113 | ||
| 114 | /* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */ | |
| 115 | #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs))) | |
| 116 | ||
| 117 | /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */ | |
| 118 | #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) | |
| 119 | #define CISCCTRL_SCALERBYPASS (1 << 31) | |
| 120 | /* s3c244x preview path only, s3c64xx both */ | |
| 121 | #define CIPRSCCTRL_SAMPLE (1 << 31) | |
| 122 | /* 0 - 16-bit RGB, 1 - 24-bit RGB */ | |
| 123 | #define CIPRSCCTRL_RGB_FORMAT_24BIT (1 << 30) /* only for s3c244x */ | |
| 124 | #define CIPRSCCTRL_SCALEUP_H (1 << 29) /* only for s3c244x */ | |
| 125 | #define CIPRSCCTRL_SCALEUP_V (1 << 28) /* only for s3c244x */ | |
| 126 | /* s3c64xx */ | |
| 127 | #define CISCCTRL_SCALEUP_H (1 << 30) | |
| 128 | #define CISCCTRL_SCALEUP_V (1 << 29) | |
| 129 | #define CISCCTRL_SCALEUP_MASK (0x3 << 29) | |
| 130 | #define CISCCTRL_CSCR2Y_WIDE (1 << 28) | |
| 131 | #define CISCCTRL_CSCY2R_WIDE (1 << 27) | |
| 132 | #define CISCCTRL_LCDPATHEN_FIFO (1 << 26) | |
| 133 | #define CISCCTRL_INTERLACE (1 << 25) | |
| 134 | #define CISCCTRL_SCALERSTART (1 << 15) | |
| 135 | #define CISCCTRL_INRGB_FMT_RGB565 (0 << 13) | |
| 136 | #define CISCCTRL_INRGB_FMT_RGB666 (1 << 13) | |
| 137 | #define CISCCTRL_INRGB_FMT_RGB888 (2 << 13) | |
| 138 | #define CISCCTRL_INRGB_FMT_MASK (3 << 13) | |
| 139 | #define CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) | |
| 140 | #define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) | |
| 141 | #define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) | |
| 142 | #define CISCCTRL_OUTRGB_FMT_MASK (3 << 11) | |
| 143 | #define CISCCTRL_EXTRGB_EXTENSION (1 << 10) | |
| 144 | #define CISCCTRL_ONE2ONE (1 << 9) | |
| 145 | #define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff) | |
| 146 | ||
| 147 | /* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */ | |
| 148 | #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs))) | |
| 149 | #define CITAREA_MASK 0xfffffff | |
| 150 | ||
| 151 | /* Codec (id = 0) or preview (id = 1) path status. */ | |
| 152 | #define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs))) | |
| 153 | #define CISTATUS_OVFIY_STATUS (1 << 31) | |
| 154 | #define CISTATUS_OVFICB_STATUS (1 << 30) | |
| 155 | #define CISTATUS_OVFICR_STATUS (1 << 29) | |
| 156 | #define CISTATUS_OVF_MASK (0x7 << 29) | |
| 157 | #define CIPRSTATUS_OVF_MASK (0x3 << 30) | |
| 158 | #define CISTATUS_VSYNC_STATUS (1 << 28) | |
| 159 | #define CISTATUS_FRAMECNT_MASK (3 << 26) | |
| 160 | #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3) | |
| 161 | #define CISTATUS_WINOFSTEN_STATUS (1 << 25) | |
| 162 | #define CISTATUS_IMGCPTEN_STATUS (1 << 22) | |
| 163 | #define CISTATUS_IMGCPTENSC_STATUS (1 << 21) | |
| 164 | #define CISTATUS_VSYNC_A_STATUS (1 << 20) | |
| 165 | #define CISTATUS_FRAMEEND_STATUS (1 << 19) /* 17 on s3c64xx */ | |
| 166 | ||
| 167 | /* Image capture enable */ | |
| 168 | #define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs)) | |
| 169 | #define CIIMGCPT_IMGCPTEN (1 << 31) | |
| 170 | #define CIIMGCPT_IMGCPTEN_SC(id) (1 << (30 - (id))) | |
| 171 | /* Frame control: 1 - one-shot, 0 - free run */ | |
| 172 | #define CIIMGCPT_CPT_FREN_ENABLE(id) (1 << (25 - (id))) | |
| 173 | #define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18) | |
| 174 | #define CIIMGCPT_CPT_FRMOD_CNT (1 << 18) | |
| 175 | ||
| 176 | /* Capture sequence */ | |
| 177 | #define S3C_CAMIF_REG_CICPTSEQ 0xc4 | |
| 178 | ||
| 179 | /* Image effects */ | |
| 180 | #define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs)) | |
| 181 | #define CIIMGEFF_IE_ENABLE(id) (1 << (30 + (id))) | |
| 182 | #define CIIMGEFF_IE_ENABLE_MASK (3 << 30) | |
| 183 | /* Image effect: 1 - after scaler, 0 - before scaler */ | |
| 184 | #define CIIMGEFF_IE_AFTER_SC (1 << 29) | |
| 185 | #define CIIMGEFF_FIN_MASK (7 << 26) | |
| 186 | #define CIIMGEFF_FIN_BYPASS (0 << 26) | |
| 187 | #define CIIMGEFF_FIN_ARBITRARY (1 << 26) | |
| 188 | #define CIIMGEFF_FIN_NEGATIVE (2 << 26) | |
| 189 | #define CIIMGEFF_FIN_ARTFREEZE (3 << 26) | |
| 190 | #define CIIMGEFF_FIN_EMBOSSING (4 << 26) | |
| 191 | #define CIIMGEFF_FIN_SILHOUETTE (5 << 26) | |
| 192 | #define CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff) | |
| 193 | #define CIIMGEFF_PAT_CB(x) ((x) << 13) | |
| 194 | #define CIIMGEFF_PAT_CR(x) (x) | |
| 195 | ||
| 196 | /* MSCOY0SA, MSPRY0SA. Y/Cb/Cr frame start address for input DMA. */ | |
| 197 | #define S3C_CAMIF_REG_MSY0SA(id) (0xd4 + ((id) * 0x2c)) | |
| 198 | #define S3C_CAMIF_REG_MSCB0SA(id) (0xd8 + ((id) * 0x2c)) | |
| 199 | #define S3C_CAMIF_REG_MSCR0SA(id) (0xdc + ((id) * 0x2c)) | |
| 200 | ||
| 201 | /* MSCOY0END, MSCOY0END. Y/Cb/Cr frame end address for input DMA. */ | |
| 202 | #define S3C_CAMIF_REG_MSY0END(id) (0xe0 + ((id) * 0x2c)) | |
| 203 | #define S3C_CAMIF_REG_MSCB0END(id) (0xe4 + ((id) * 0x2c)) | |
| 204 | #define S3C_CAMIF_REG_MSCR0END(id) (0xe8 + ((id) * 0x2c)) | |
| 205 | ||
| 206 | /* MSPRYOFF, MSPRYOFF. Y/Cb/Cr offset. n: 0 - codec, 1 - preview. */ | |
| 207 | #define S3C_CAMIF_REG_MSYOFF(id) (0x118 + ((id) * 0x2c)) | |
| 208 | #define S3C_CAMIF_REG_MSCBOFF(id) (0x11c + ((id) * 0x2c)) | |
| 209 | #define S3C_CAMIF_REG_MSCROFF(id) (0x120 + ((id) * 0x2c)) | |
| 210 | ||
| 211 | /* Real input DMA data size. n = 0 - codec, 1 - preview. */ | |
| 212 | #define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c) | |
| 213 | #define AUTOLOAD_ENABLE (1 << 31) | |
| 214 | #define ADDR_CH_DIS (1 << 30) | |
| 215 | #define MSHEIGHT(x) (((x) & 0x3ff) << 16) | |
| 216 | #define MSWIDTH(x) ((x) & 0x3ff) | |
| 217 | ||
| 218 | /* Input DMA control. n = 0 - codec, 1 - preview */ | |
| 219 | #define S3C_CAMIF_REG_MSCTRL(id) (0xfc + (id) * 0x2c) | |
| 220 | #define MSCTRL_ORDER422_M_YCBYCR (0 << 4) | |
| 221 | #define MSCTRL_ORDER422_M_YCRYCB (1 << 4) | |
| 222 | #define MSCTRL_ORDER422_M_CBYCRY (2 << 4) | |
| 223 | #define MSCTRL_ORDER422_M_CRYCBY (3 << 4) | |
| 224 | /* 0 - camera, 1 - DMA */ | |
| 225 | #define MSCTRL_SEL_DMA_CAM (1 << 3) | |
| 226 | #define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1) | |
| 227 | #define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1) | |
| 228 | #define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1) | |
| 229 | #define MSCTRL_INFORMAT_M_RGB (3 << 1) | |
| 230 | #define MSCTRL_ENVID_M (1 << 0) | |
| 231 | ||
| 232 | /* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */ | |
| 233 | #define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c) | |
| 234 | #define S3C_CAMIF_REG_CISSCB(id) (0x130 + (id) * 0x0c) | |
| 235 | #define S3C_CAMIF_REG_CISSCR(id) (0x134 + (id) * 0x0c) | |
| 236 | #define S3C_CISS_OFFS_INITIAL(x) ((x) << 16) | |
| 237 | #define S3C_CISS_OFFS_LINE(x) ((x) << 0) | |
| 238 | ||
| 239 | /* ------------------------------------------------------------------ */ | |
| 240 | ||
| 241 | void camif_hw_reset(struct camif_dev *camif); | |
| 242 | void camif_hw_clear_pending_irq(struct camif_vp *vp); | |
| 243 | void camif_hw_clear_fifo_overflow(struct camif_vp *vp); | |
| 244 | void camif_hw_set_lastirq(struct camif_vp *vp, int enable); | |
| 245 | void camif_hw_set_input_path(struct camif_vp *vp); | |
| 246 | void camif_hw_enable_scaler(struct camif_vp *vp, bool on); | |
| 247 | void camif_hw_enable_capture(struct camif_vp *vp); | |
| 248 | void camif_hw_disable_capture(struct camif_vp *vp); | |
| 249 | void camif_hw_set_camera_bus(struct camif_dev *camif); | |
| 250 | void camif_hw_set_source_format(struct camif_dev *camif); | |
| 251 | void camif_hw_set_camera_crop(struct camif_dev *camif); | |
| 252 | void camif_hw_set_scaler(struct camif_vp *vp); | |
| 253 | void camif_hw_set_flip(struct camif_vp *vp); | |
| 254 | void camif_hw_set_output_dma(struct camif_vp *vp); | |
| 255 | void camif_hw_set_target_format(struct camif_vp *vp); | |
| 256 | void camif_hw_set_test_pattern(struct camif_dev *camif, unsigned int pattern); | |
| 257 | void camif_hw_set_effect(struct camif_dev *camif, unsigned int effect, | |
| 258 | unsigned int cr, unsigned int cb); | |
| 259 | void camif_hw_set_output_addr(struct camif_vp *vp, struct camif_addr *paddr, | |
| 260 | int index); | |
| 261 | void camif_hw_dump_regs(struct camif_dev *camif, const char *label); | |
| 262 | ||
| 263 | static inline u32 camif_hw_get_status(struct camif_vp *vp) | |
| 264 | { | |
| 265 | return readl(vp->camif->io_base + S3C_CAMIF_REG_CISTATUS(vp->id, | |
| 266 | vp->offset)); | |
| 267 | } | |
| 268 | ||
| 269 | #endif /* CAMIF_REGS_H_ */ |