Commit | Line | Data |
---|---|---|
4af81310 SN |
1 | /* |
2 | * Samsung EXYNOS FIMC-LITE (camera host interface) driver | |
3 | * | |
8a0c28f5 SN |
4 | * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd. |
5 | * Author: Sylwester Nawrocki <s.nawrocki@samsung.com> | |
4af81310 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__ | |
12 | ||
13 | #include <linux/bug.h> | |
4c8f0629 | 14 | #include <linux/clk.h> |
4af81310 SN |
15 | #include <linux/device.h> |
16 | #include <linux/errno.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/module.h> | |
eb62d9e9 | 21 | #include <linux/of.h> |
4af81310 SN |
22 | #include <linux/types.h> |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/videodev2.h> | |
27 | ||
28 | #include <media/v4l2-device.h> | |
29 | #include <media/v4l2-ioctl.h> | |
30 | #include <media/v4l2-mem2mem.h> | |
31 | #include <media/videobuf2-core.h> | |
32 | #include <media/videobuf2-dma-contig.h> | |
b9ee31e6 | 33 | #include <media/s5p_fimc.h> |
4af81310 | 34 | |
045a1fac | 35 | #include "common.h" |
4c8f0629 | 36 | #include "fimc-core.h" |
b9ee31e6 | 37 | #include "fimc-lite.h" |
4af81310 SN |
38 | #include "fimc-lite-reg.h" |
39 | ||
40 | static int debug; | |
41 | module_param(debug, int, 0644); | |
42 | ||
43 | static const struct fimc_fmt fimc_lite_formats[] = { | |
44 | { | |
45 | .name = "YUV 4:2:2 packed, YCbYCr", | |
46 | .fourcc = V4L2_PIX_FMT_YUYV, | |
1c26190a | 47 | .colorspace = V4L2_COLORSPACE_JPEG, |
4af81310 SN |
48 | .depth = { 16 }, |
49 | .color = FIMC_FMT_YCBYCR422, | |
50 | .memplanes = 1, | |
51 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, | |
e90ad659 | 52 | .flags = FMT_FLAGS_YUV, |
4af81310 SN |
53 | }, { |
54 | .name = "YUV 4:2:2 packed, CbYCrY", | |
55 | .fourcc = V4L2_PIX_FMT_UYVY, | |
1c26190a | 56 | .colorspace = V4L2_COLORSPACE_JPEG, |
4af81310 SN |
57 | .depth = { 16 }, |
58 | .color = FIMC_FMT_CBYCRY422, | |
59 | .memplanes = 1, | |
60 | .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8, | |
e90ad659 | 61 | .flags = FMT_FLAGS_YUV, |
4af81310 SN |
62 | }, { |
63 | .name = "YUV 4:2:2 packed, CrYCbY", | |
64 | .fourcc = V4L2_PIX_FMT_VYUY, | |
1c26190a | 65 | .colorspace = V4L2_COLORSPACE_JPEG, |
4af81310 SN |
66 | .depth = { 16 }, |
67 | .color = FIMC_FMT_CRYCBY422, | |
68 | .memplanes = 1, | |
69 | .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8, | |
e90ad659 | 70 | .flags = FMT_FLAGS_YUV, |
4af81310 SN |
71 | }, { |
72 | .name = "YUV 4:2:2 packed, YCrYCb", | |
73 | .fourcc = V4L2_PIX_FMT_YVYU, | |
1c26190a | 74 | .colorspace = V4L2_COLORSPACE_JPEG, |
4af81310 SN |
75 | .depth = { 16 }, |
76 | .color = FIMC_FMT_YCRYCB422, | |
77 | .memplanes = 1, | |
78 | .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8, | |
e90ad659 | 79 | .flags = FMT_FLAGS_YUV, |
4af81310 SN |
80 | }, { |
81 | .name = "RAW8 (GRBG)", | |
82 | .fourcc = V4L2_PIX_FMT_SGRBG8, | |
1c26190a | 83 | .colorspace = V4L2_COLORSPACE_SRGB, |
4af81310 SN |
84 | .depth = { 8 }, |
85 | .color = FIMC_FMT_RAW8, | |
86 | .memplanes = 1, | |
87 | .mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8, | |
e90ad659 | 88 | .flags = FMT_FLAGS_RAW_BAYER, |
4af81310 SN |
89 | }, { |
90 | .name = "RAW10 (GRBG)", | |
91 | .fourcc = V4L2_PIX_FMT_SGRBG10, | |
1c26190a | 92 | .colorspace = V4L2_COLORSPACE_SRGB, |
3396b096 | 93 | .depth = { 16 }, |
4af81310 SN |
94 | .color = FIMC_FMT_RAW10, |
95 | .memplanes = 1, | |
96 | .mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10, | |
e90ad659 | 97 | .flags = FMT_FLAGS_RAW_BAYER, |
4af81310 SN |
98 | }, { |
99 | .name = "RAW12 (GRBG)", | |
100 | .fourcc = V4L2_PIX_FMT_SGRBG12, | |
1c26190a | 101 | .colorspace = V4L2_COLORSPACE_SRGB, |
3396b096 | 102 | .depth = { 16 }, |
4af81310 SN |
103 | .color = FIMC_FMT_RAW12, |
104 | .memplanes = 1, | |
105 | .mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12, | |
e90ad659 | 106 | .flags = FMT_FLAGS_RAW_BAYER, |
4af81310 SN |
107 | }, |
108 | }; | |
109 | ||
110 | /** | |
111 | * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code | |
112 | * @pixelformat: fourcc to match, ignored if null | |
113 | * @mbus_code: media bus code to match, ignored if null | |
e90ad659 | 114 | * @mask: the color format flags to match |
4af81310 SN |
115 | * @index: index to the fimc_lite_formats array, ignored if negative |
116 | */ | |
117 | static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat, | |
e90ad659 | 118 | const u32 *mbus_code, unsigned int mask, int index) |
4af81310 SN |
119 | { |
120 | const struct fimc_fmt *fmt, *def_fmt = NULL; | |
121 | unsigned int i; | |
122 | int id = 0; | |
123 | ||
124 | if (index >= (int)ARRAY_SIZE(fimc_lite_formats)) | |
125 | return NULL; | |
126 | ||
127 | for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) { | |
128 | fmt = &fimc_lite_formats[i]; | |
e90ad659 SN |
129 | if (mask && !(fmt->flags & mask)) |
130 | continue; | |
4af81310 SN |
131 | if (pixelformat && fmt->fourcc == *pixelformat) |
132 | return fmt; | |
133 | if (mbus_code && fmt->mbus_code == *mbus_code) | |
134 | return fmt; | |
135 | if (index == id) | |
136 | def_fmt = fmt; | |
137 | id++; | |
138 | } | |
139 | return def_fmt; | |
140 | } | |
141 | ||
6319d6a0 | 142 | static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output) |
4af81310 | 143 | { |
4c8f0629 | 144 | struct fimc_source_info *si; |
4af81310 SN |
145 | unsigned long flags; |
146 | ||
756e6e14 | 147 | if (fimc->sensor == NULL) |
4af81310 SN |
148 | return -ENXIO; |
149 | ||
e90ad659 | 150 | if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL) |
4af81310 SN |
151 | return -EINVAL; |
152 | ||
6319d6a0 | 153 | /* Get sensor configuration data from the sensor subdev */ |
756e6e14 | 154 | si = v4l2_get_subdev_hostdata(fimc->sensor); |
4c8f0629 SN |
155 | if (!si) |
156 | return -EINVAL; | |
157 | ||
4af81310 SN |
158 | spin_lock_irqsave(&fimc->slock, flags); |
159 | ||
4c8f0629 | 160 | flite_hw_set_camera_bus(fimc, si); |
4af81310 SN |
161 | flite_hw_set_source_format(fimc, &fimc->inp_frame); |
162 | flite_hw_set_window_offset(fimc, &fimc->inp_frame); | |
086eca29 | 163 | flite_hw_set_dma_buf_mask(fimc, 0); |
6319d6a0 | 164 | flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output); |
4af81310 SN |
165 | flite_hw_set_interrupt_mask(fimc); |
166 | flite_hw_set_test_pattern(fimc, fimc->test_pattern->val); | |
167 | ||
168 | if (debug > 0) | |
169 | flite_hw_dump_regs(fimc, __func__); | |
170 | ||
171 | spin_unlock_irqrestore(&fimc->slock, flags); | |
172 | return 0; | |
173 | } | |
174 | ||
175 | /* | |
176 | * Reinitialize the driver so it is ready to start the streaming again. | |
177 | * Set fimc->state to indicate stream off and the hardware shut down state. | |
178 | * If not suspending (@suspend is false), return any buffers to videobuf2. | |
179 | * Otherwise put any owned buffers onto the pending buffers queue, so they | |
180 | * can be re-spun when the device is being resumed. Also perform FIMC | |
181 | * software reset and disable streaming on the whole pipeline if required. | |
182 | */ | |
183 | static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend) | |
184 | { | |
185 | struct flite_buffer *buf; | |
186 | unsigned long flags; | |
187 | bool streaming; | |
188 | ||
189 | spin_lock_irqsave(&fimc->slock, flags); | |
190 | streaming = fimc->state & (1 << ST_SENSOR_STREAM); | |
191 | ||
192 | fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF | | |
193 | 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM); | |
194 | if (suspend) | |
195 | fimc->state |= (1 << ST_FLITE_SUSPENDED); | |
196 | else | |
197 | fimc->state &= ~(1 << ST_FLITE_PENDING | | |
198 | 1 << ST_FLITE_SUSPENDED); | |
199 | ||
200 | /* Release unused buffers */ | |
201 | while (!suspend && !list_empty(&fimc->pending_buf_q)) { | |
202 | buf = fimc_lite_pending_queue_pop(fimc); | |
203 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); | |
204 | } | |
205 | /* If suspending put unused buffers onto pending queue */ | |
206 | while (!list_empty(&fimc->active_buf_q)) { | |
207 | buf = fimc_lite_active_queue_pop(fimc); | |
208 | if (suspend) | |
209 | fimc_lite_pending_queue_add(fimc, buf); | |
210 | else | |
211 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); | |
212 | } | |
213 | ||
214 | spin_unlock_irqrestore(&fimc->slock, flags); | |
215 | ||
216 | flite_hw_reset(fimc); | |
217 | ||
218 | if (!streaming) | |
219 | return 0; | |
220 | ||
403dfbec | 221 | return fimc_pipeline_call(&fimc->ve, set_stream, 0); |
4af81310 SN |
222 | } |
223 | ||
224 | static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend) | |
225 | { | |
226 | unsigned long flags; | |
227 | ||
228 | if (!fimc_lite_active(fimc)) | |
229 | return 0; | |
230 | ||
231 | spin_lock_irqsave(&fimc->slock, flags); | |
232 | set_bit(ST_FLITE_OFF, &fimc->state); | |
233 | flite_hw_capture_stop(fimc); | |
234 | spin_unlock_irqrestore(&fimc->slock, flags); | |
235 | ||
236 | wait_event_timeout(fimc->irq_queue, | |
237 | !test_bit(ST_FLITE_OFF, &fimc->state), | |
238 | (2*HZ/10)); /* 200 ms */ | |
239 | ||
240 | return fimc_lite_reinit(fimc, suspend); | |
241 | } | |
242 | ||
243 | /* Must be called with fimc.slock spinlock held. */ | |
244 | static void fimc_lite_config_update(struct fimc_lite *fimc) | |
245 | { | |
246 | flite_hw_set_window_offset(fimc, &fimc->inp_frame); | |
247 | flite_hw_set_dma_window(fimc, &fimc->out_frame); | |
248 | flite_hw_set_test_pattern(fimc, fimc->test_pattern->val); | |
249 | clear_bit(ST_FLITE_CONFIG, &fimc->state); | |
250 | } | |
251 | ||
252 | static irqreturn_t flite_irq_handler(int irq, void *priv) | |
253 | { | |
254 | struct fimc_lite *fimc = priv; | |
255 | struct flite_buffer *vbuf; | |
256 | unsigned long flags; | |
257 | struct timeval *tv; | |
258 | struct timespec ts; | |
259 | u32 intsrc; | |
260 | ||
261 | spin_lock_irqsave(&fimc->slock, flags); | |
262 | ||
263 | intsrc = flite_hw_get_interrupt_source(fimc); | |
264 | flite_hw_clear_pending_irq(fimc); | |
265 | ||
266 | if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) { | |
267 | wake_up(&fimc->irq_queue); | |
268 | goto done; | |
269 | } | |
270 | ||
271 | if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) { | |
272 | clear_bit(ST_FLITE_RUN, &fimc->state); | |
273 | fimc->events.data_overflow++; | |
274 | } | |
275 | ||
276 | if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) { | |
277 | flite_hw_clear_last_capture_end(fimc); | |
278 | clear_bit(ST_FLITE_STREAM, &fimc->state); | |
279 | wake_up(&fimc->irq_queue); | |
280 | } | |
281 | ||
03878bb4 | 282 | if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) |
4af81310 SN |
283 | goto done; |
284 | ||
285 | if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) && | |
286 | test_bit(ST_FLITE_RUN, &fimc->state) && | |
4af81310 | 287 | !list_empty(&fimc->pending_buf_q)) { |
086eca29 SN |
288 | vbuf = fimc_lite_pending_queue_pop(fimc); |
289 | flite_hw_set_dma_buffer(fimc, vbuf); | |
290 | fimc_lite_active_queue_add(fimc, vbuf); | |
291 | } | |
292 | ||
293 | if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMEND) && | |
294 | test_bit(ST_FLITE_RUN, &fimc->state) && | |
295 | !list_empty(&fimc->active_buf_q)) { | |
4af81310 SN |
296 | vbuf = fimc_lite_active_queue_pop(fimc); |
297 | ktime_get_ts(&ts); | |
298 | tv = &vbuf->vb.v4l2_buf.timestamp; | |
299 | tv->tv_sec = ts.tv_sec; | |
300 | tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC; | |
301 | vbuf->vb.v4l2_buf.sequence = fimc->frame_count++; | |
086eca29 | 302 | flite_hw_mask_dma_buffer(fimc, vbuf->index); |
4af81310 | 303 | vb2_buffer_done(&vbuf->vb, VB2_BUF_STATE_DONE); |
4af81310 SN |
304 | } |
305 | ||
306 | if (test_bit(ST_FLITE_CONFIG, &fimc->state)) | |
307 | fimc_lite_config_update(fimc); | |
308 | ||
309 | if (list_empty(&fimc->pending_buf_q)) { | |
310 | flite_hw_capture_stop(fimc); | |
311 | clear_bit(ST_FLITE_STREAM, &fimc->state); | |
312 | } | |
313 | done: | |
314 | set_bit(ST_FLITE_RUN, &fimc->state); | |
315 | spin_unlock_irqrestore(&fimc->slock, flags); | |
316 | return IRQ_HANDLED; | |
317 | } | |
318 | ||
319 | static int start_streaming(struct vb2_queue *q, unsigned int count) | |
320 | { | |
321 | struct fimc_lite *fimc = q->drv_priv; | |
086eca29 | 322 | unsigned long flags; |
4af81310 SN |
323 | int ret; |
324 | ||
086eca29 SN |
325 | spin_lock_irqsave(&fimc->slock, flags); |
326 | ||
327 | fimc->buf_index = 0; | |
4af81310 SN |
328 | fimc->frame_count = 0; |
329 | ||
086eca29 SN |
330 | spin_unlock_irqrestore(&fimc->slock, flags); |
331 | ||
6319d6a0 | 332 | ret = fimc_lite_hw_init(fimc, false); |
4af81310 SN |
333 | if (ret) { |
334 | fimc_lite_reinit(fimc, false); | |
335 | return ret; | |
336 | } | |
337 | ||
338 | set_bit(ST_FLITE_PENDING, &fimc->state); | |
339 | ||
340 | if (!list_empty(&fimc->active_buf_q) && | |
341 | !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) { | |
342 | flite_hw_capture_start(fimc); | |
343 | ||
344 | if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state)) | |
403dfbec | 345 | fimc_pipeline_call(&fimc->ve, set_stream, 1); |
4af81310 SN |
346 | } |
347 | if (debug > 0) | |
348 | flite_hw_dump_regs(fimc, __func__); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static int stop_streaming(struct vb2_queue *q) | |
354 | { | |
355 | struct fimc_lite *fimc = q->drv_priv; | |
356 | ||
357 | if (!fimc_lite_active(fimc)) | |
358 | return -EINVAL; | |
359 | ||
360 | return fimc_lite_stop_capture(fimc, false); | |
361 | } | |
362 | ||
363 | static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt, | |
364 | unsigned int *num_buffers, unsigned int *num_planes, | |
365 | unsigned int sizes[], void *allocators[]) | |
366 | { | |
367 | const struct v4l2_pix_format_mplane *pixm = NULL; | |
368 | struct fimc_lite *fimc = vq->drv_priv; | |
369 | struct flite_frame *frame = &fimc->out_frame; | |
e90ad659 | 370 | const struct fimc_fmt *fmt = frame->fmt; |
4af81310 SN |
371 | unsigned long wh; |
372 | int i; | |
373 | ||
374 | if (pfmt) { | |
375 | pixm = &pfmt->fmt.pix_mp; | |
e90ad659 | 376 | fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0, -1); |
4af81310 SN |
377 | wh = pixm->width * pixm->height; |
378 | } else { | |
379 | wh = frame->f_width * frame->f_height; | |
380 | } | |
381 | ||
382 | if (fmt == NULL) | |
383 | return -EINVAL; | |
384 | ||
385 | *num_planes = fmt->memplanes; | |
386 | ||
387 | for (i = 0; i < fmt->memplanes; i++) { | |
388 | unsigned int size = (wh * fmt->depth[i]) / 8; | |
389 | if (pixm) | |
390 | sizes[i] = max(size, pixm->plane_fmt[i].sizeimage); | |
391 | else | |
392 | sizes[i] = size; | |
393 | allocators[i] = fimc->alloc_ctx; | |
394 | } | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static int buffer_prepare(struct vb2_buffer *vb) | |
400 | { | |
401 | struct vb2_queue *vq = vb->vb2_queue; | |
402 | struct fimc_lite *fimc = vq->drv_priv; | |
403 | int i; | |
404 | ||
e90ad659 | 405 | if (fimc->out_frame.fmt == NULL) |
4af81310 SN |
406 | return -EINVAL; |
407 | ||
e90ad659 | 408 | for (i = 0; i < fimc->out_frame.fmt->memplanes; i++) { |
4af81310 SN |
409 | unsigned long size = fimc->payload[i]; |
410 | ||
411 | if (vb2_plane_size(vb, i) < size) { | |
bc7584b0 | 412 | v4l2_err(&fimc->ve.vdev, |
4af81310 SN |
413 | "User buffer too small (%ld < %ld)\n", |
414 | vb2_plane_size(vb, i), size); | |
415 | return -EINVAL; | |
416 | } | |
417 | vb2_set_plane_payload(vb, i, size); | |
418 | } | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | static void buffer_queue(struct vb2_buffer *vb) | |
424 | { | |
425 | struct flite_buffer *buf | |
426 | = container_of(vb, struct flite_buffer, vb); | |
427 | struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue); | |
428 | unsigned long flags; | |
429 | ||
430 | spin_lock_irqsave(&fimc->slock, flags); | |
431 | buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0); | |
432 | ||
086eca29 SN |
433 | buf->index = fimc->buf_index++; |
434 | if (fimc->buf_index >= fimc->reqbufs_count) | |
435 | fimc->buf_index = 0; | |
436 | ||
4af81310 SN |
437 | if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) && |
438 | !test_bit(ST_FLITE_STREAM, &fimc->state) && | |
439 | list_empty(&fimc->active_buf_q)) { | |
086eca29 | 440 | flite_hw_set_dma_buffer(fimc, buf); |
4af81310 SN |
441 | fimc_lite_active_queue_add(fimc, buf); |
442 | } else { | |
443 | fimc_lite_pending_queue_add(fimc, buf); | |
444 | } | |
445 | ||
446 | if (vb2_is_streaming(&fimc->vb_queue) && | |
447 | !list_empty(&fimc->pending_buf_q) && | |
448 | !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) { | |
449 | flite_hw_capture_start(fimc); | |
450 | spin_unlock_irqrestore(&fimc->slock, flags); | |
451 | ||
452 | if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state)) | |
403dfbec | 453 | fimc_pipeline_call(&fimc->ve, set_stream, 1); |
4af81310 SN |
454 | return; |
455 | } | |
456 | spin_unlock_irqrestore(&fimc->slock, flags); | |
457 | } | |
458 | ||
4af81310 SN |
459 | static const struct vb2_ops fimc_lite_qops = { |
460 | .queue_setup = queue_setup, | |
461 | .buf_prepare = buffer_prepare, | |
462 | .buf_queue = buffer_queue, | |
ee12b049 SN |
463 | .wait_prepare = vb2_ops_wait_prepare, |
464 | .wait_finish = vb2_ops_wait_finish, | |
4af81310 SN |
465 | .start_streaming = start_streaming, |
466 | .stop_streaming = stop_streaming, | |
467 | }; | |
468 | ||
469 | static void fimc_lite_clear_event_counters(struct fimc_lite *fimc) | |
470 | { | |
471 | unsigned long flags; | |
472 | ||
473 | spin_lock_irqsave(&fimc->slock, flags); | |
474 | memset(&fimc->events, 0, sizeof(fimc->events)); | |
475 | spin_unlock_irqrestore(&fimc->slock, flags); | |
476 | } | |
477 | ||
478 | static int fimc_lite_open(struct file *file) | |
479 | { | |
480 | struct fimc_lite *fimc = video_drvdata(file); | |
bc7584b0 | 481 | struct media_entity *me = &fimc->ve.vdev.entity; |
e3fc82e8 | 482 | int ret; |
4af81310 | 483 | |
740ad921 | 484 | mutex_lock(&fimc->lock); |
03878bb4 | 485 | if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) { |
6319d6a0 | 486 | ret = -EBUSY; |
ee12b049 | 487 | goto unlock; |
6319d6a0 SN |
488 | } |
489 | ||
4af81310 | 490 | set_bit(ST_FLITE_IN_USE, &fimc->state); |
e3fc82e8 SN |
491 | ret = pm_runtime_get_sync(&fimc->pdev->dev); |
492 | if (ret < 0) | |
ee12b049 | 493 | goto unlock; |
4af81310 | 494 | |
e3fc82e8 SN |
495 | ret = v4l2_fh_open(file); |
496 | if (ret < 0) | |
ee12b049 | 497 | goto err_pm; |
4af81310 | 498 | |
ee12b049 SN |
499 | if (!v4l2_fh_is_singular_file(file) || |
500 | atomic_read(&fimc->out_path) != FIMC_IO_DMA) | |
501 | goto unlock; | |
4af81310 | 502 | |
42625fdf SN |
503 | mutex_lock(&me->parent->graph_mutex); |
504 | ||
403dfbec | 505 | ret = fimc_pipeline_call(&fimc->ve, open, me, true); |
42625fdf SN |
506 | |
507 | /* Mark video pipeline ending at this video node as in use. */ | |
508 | if (ret == 0) | |
509 | me->use_count++; | |
510 | ||
511 | mutex_unlock(&me->parent->graph_mutex); | |
512 | ||
ee12b049 | 513 | if (!ret) { |
4e39da01 | 514 | fimc_lite_clear_event_counters(fimc); |
ee12b049 | 515 | goto unlock; |
4e39da01 | 516 | } |
ee12b049 SN |
517 | |
518 | v4l2_fh_release(file); | |
519 | err_pm: | |
520 | pm_runtime_put_sync(&fimc->pdev->dev); | |
521 | clear_bit(ST_FLITE_IN_USE, &fimc->state); | |
522 | unlock: | |
4e39da01 | 523 | mutex_unlock(&fimc->lock); |
4af81310 SN |
524 | return ret; |
525 | } | |
526 | ||
ee12b049 | 527 | static int fimc_lite_release(struct file *file) |
4af81310 SN |
528 | { |
529 | struct fimc_lite *fimc = video_drvdata(file); | |
42625fdf | 530 | struct media_entity *entity = &fimc->ve.vdev.entity; |
4e39da01 | 531 | |
ddc43d6d | 532 | mutex_lock(&fimc->lock); |
4af81310 | 533 | |
ee12b049 | 534 | if (v4l2_fh_is_singular_file(file) && |
03878bb4 | 535 | atomic_read(&fimc->out_path) == FIMC_IO_DMA) { |
9ea89e2b | 536 | if (fimc->streaming) { |
42625fdf | 537 | media_entity_pipeline_stop(entity); |
9ea89e2b SN |
538 | fimc->streaming = false; |
539 | } | |
4af81310 | 540 | fimc_lite_stop_capture(fimc, false); |
403dfbec SN |
541 | fimc_pipeline_call(&fimc->ve, close); |
542 | clear_bit(ST_FLITE_IN_USE, &fimc->state); | |
543 | ||
42625fdf SN |
544 | mutex_lock(&entity->parent->graph_mutex); |
545 | entity->use_count--; | |
546 | mutex_unlock(&entity->parent->graph_mutex); | |
4af81310 SN |
547 | } |
548 | ||
1380f575 | 549 | _vb2_fop_release(file, NULL); |
4af81310 | 550 | pm_runtime_put(&fimc->pdev->dev); |
ee12b049 | 551 | clear_bit(ST_FLITE_SUSPENDED, &fimc->state); |
4af81310 | 552 | |
4e39da01 | 553 | mutex_unlock(&fimc->lock); |
ee12b049 | 554 | return 0; |
4af81310 SN |
555 | } |
556 | ||
557 | static const struct v4l2_file_operations fimc_lite_fops = { | |
558 | .owner = THIS_MODULE, | |
559 | .open = fimc_lite_open, | |
ee12b049 SN |
560 | .release = fimc_lite_release, |
561 | .poll = vb2_fop_poll, | |
4af81310 | 562 | .unlocked_ioctl = video_ioctl2, |
ee12b049 | 563 | .mmap = vb2_fop_mmap, |
4af81310 SN |
564 | }; |
565 | ||
566 | /* | |
567 | * Format and crop negotiation helpers | |
568 | */ | |
569 | ||
b1d2dc5c SN |
570 | static const struct fimc_fmt *fimc_lite_subdev_try_fmt(struct fimc_lite *fimc, |
571 | struct v4l2_subdev_fh *fh, | |
572 | struct v4l2_subdev_format *format) | |
4af81310 | 573 | { |
9c8399c8 | 574 | struct flite_drvdata *dd = fimc->dd; |
b1d2dc5c SN |
575 | struct v4l2_mbus_framefmt *mf = &format->format; |
576 | const struct fimc_fmt *fmt = NULL; | |
577 | ||
578 | if (format->pad == FLITE_SD_PAD_SINK) { | |
579 | v4l_bound_align_image(&mf->width, 8, dd->max_width, | |
580 | ffs(dd->out_width_align) - 1, | |
581 | &mf->height, 0, dd->max_height, 0, 0); | |
4af81310 | 582 | |
b1d2dc5c SN |
583 | fmt = fimc_lite_find_format(NULL, &mf->code, 0, 0); |
584 | if (WARN_ON(!fmt)) | |
585 | return NULL; | |
586 | ||
1c26190a | 587 | mf->colorspace = fmt->colorspace; |
b1d2dc5c | 588 | mf->code = fmt->mbus_code; |
4af81310 | 589 | } else { |
b1d2dc5c SN |
590 | struct flite_frame *sink = &fimc->inp_frame; |
591 | struct v4l2_mbus_framefmt *sink_fmt; | |
592 | struct v4l2_rect *rect; | |
4af81310 | 593 | |
b1d2dc5c SN |
594 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { |
595 | sink_fmt = v4l2_subdev_get_try_format(fh, | |
596 | FLITE_SD_PAD_SINK); | |
e90ad659 | 597 | |
b1d2dc5c | 598 | mf->code = sink_fmt->code; |
1c26190a | 599 | mf->colorspace = sink_fmt->colorspace; |
b1d2dc5c SN |
600 | |
601 | rect = v4l2_subdev_get_try_crop(fh, | |
602 | FLITE_SD_PAD_SINK); | |
603 | } else { | |
604 | mf->code = sink->fmt->mbus_code; | |
1c26190a | 605 | mf->colorspace = sink->fmt->colorspace; |
b1d2dc5c SN |
606 | rect = &sink->rect; |
607 | } | |
608 | ||
609 | /* Allow changing format only on sink pad */ | |
610 | mf->width = rect->width; | |
611 | mf->height = rect->height; | |
612 | } | |
e90ad659 | 613 | |
b1d2dc5c SN |
614 | mf->field = V4L2_FIELD_NONE; |
615 | ||
616 | v4l2_dbg(1, debug, &fimc->subdev, "code: %#x (%d), %dx%d\n", | |
617 | mf->code, mf->colorspace, mf->width, mf->height); | |
4af81310 SN |
618 | |
619 | return fmt; | |
620 | } | |
621 | ||
622 | static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r) | |
623 | { | |
624 | struct flite_frame *frame = &fimc->inp_frame; | |
625 | ||
626 | v4l_bound_align_image(&r->width, 0, frame->f_width, 0, | |
627 | &r->height, 0, frame->f_height, 0, 0); | |
628 | ||
629 | /* Adjust left/top if cropping rectangle got out of bounds */ | |
630 | r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width); | |
9c8399c8 | 631 | r->left = round_down(r->left, fimc->dd->win_hor_offs_align); |
4af81310 SN |
632 | r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height); |
633 | ||
969e877c | 634 | v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d\n", |
4af81310 SN |
635 | r->left, r->top, r->width, r->height, |
636 | frame->f_width, frame->f_height); | |
637 | } | |
638 | ||
639 | static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r) | |
640 | { | |
641 | struct flite_frame *frame = &fimc->out_frame; | |
642 | struct v4l2_rect *crop_rect = &fimc->inp_frame.rect; | |
643 | ||
644 | /* Scaling is not supported so we enforce compose rectangle size | |
645 | same as size of the sink crop rectangle. */ | |
646 | r->width = crop_rect->width; | |
647 | r->height = crop_rect->height; | |
648 | ||
649 | /* Adjust left/top if the composing rectangle got out of bounds */ | |
650 | r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width); | |
9c8399c8 | 651 | r->left = round_down(r->left, fimc->dd->out_hor_offs_align); |
4af81310 SN |
652 | r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height); |
653 | ||
969e877c | 654 | v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d\n", |
4af81310 SN |
655 | r->left, r->top, r->width, r->height, |
656 | frame->f_width, frame->f_height); | |
657 | } | |
658 | ||
659 | /* | |
660 | * Video node ioctl operations | |
661 | */ | |
793ad32d | 662 | static int fimc_lite_querycap(struct file *file, void *priv, |
4af81310 SN |
663 | struct v4l2_capability *cap) |
664 | { | |
793ad32d SN |
665 | struct fimc_lite *fimc = video_drvdata(file); |
666 | ||
4af81310 | 667 | strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver)); |
793ad32d SN |
668 | strlcpy(cap->card, FIMC_LITE_DRV_NAME, sizeof(cap->card)); |
669 | snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", | |
670 | dev_name(&fimc->pdev->dev)); | |
671 | ||
672 | cap->device_caps = V4L2_CAP_STREAMING; | |
673 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
4af81310 SN |
674 | return 0; |
675 | } | |
676 | ||
677 | static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv, | |
678 | struct v4l2_fmtdesc *f) | |
679 | { | |
680 | const struct fimc_fmt *fmt; | |
681 | ||
682 | if (f->index >= ARRAY_SIZE(fimc_lite_formats)) | |
683 | return -EINVAL; | |
684 | ||
685 | fmt = &fimc_lite_formats[f->index]; | |
686 | strlcpy(f->description, fmt->name, sizeof(f->description)); | |
687 | f->pixelformat = fmt->fourcc; | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int fimc_lite_g_fmt_mplane(struct file *file, void *fh, | |
693 | struct v4l2_format *f) | |
694 | { | |
695 | struct fimc_lite *fimc = video_drvdata(file); | |
696 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; | |
697 | struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0]; | |
698 | struct flite_frame *frame = &fimc->out_frame; | |
e90ad659 | 699 | const struct fimc_fmt *fmt = frame->fmt; |
4af81310 SN |
700 | |
701 | plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8; | |
702 | plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height; | |
703 | ||
704 | pixm->num_planes = fmt->memplanes; | |
705 | pixm->pixelformat = fmt->fourcc; | |
706 | pixm->width = frame->f_width; | |
707 | pixm->height = frame->f_height; | |
708 | pixm->field = V4L2_FIELD_NONE; | |
1c26190a | 709 | pixm->colorspace = fmt->colorspace; |
4af81310 SN |
710 | return 0; |
711 | } | |
712 | ||
713 | static int fimc_lite_try_fmt(struct fimc_lite *fimc, | |
714 | struct v4l2_pix_format_mplane *pixm, | |
715 | const struct fimc_fmt **ffmt) | |
716 | { | |
4af81310 | 717 | u32 bpl = pixm->plane_fmt[0].bytesperline; |
9c8399c8 | 718 | struct flite_drvdata *dd = fimc->dd; |
e90ad659 | 719 | const struct fimc_fmt *inp_fmt = fimc->inp_frame.fmt; |
4af81310 SN |
720 | const struct fimc_fmt *fmt; |
721 | ||
e90ad659 SN |
722 | if (WARN_ON(inp_fmt == NULL)) |
723 | return -EINVAL; | |
724 | /* | |
725 | * We allow some flexibility only for YUV formats. In case of raw | |
726 | * raw Bayer the FIMC-LITE's output format must match its camera | |
727 | * interface input format. | |
728 | */ | |
729 | if (inp_fmt->flags & FMT_FLAGS_YUV) | |
730 | fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, | |
731 | inp_fmt->flags, 0); | |
732 | else | |
733 | fmt = inp_fmt; | |
734 | ||
4af81310 SN |
735 | if (WARN_ON(fmt == NULL)) |
736 | return -EINVAL; | |
737 | if (ffmt) | |
738 | *ffmt = fmt; | |
9c8399c8 SN |
739 | v4l_bound_align_image(&pixm->width, 8, dd->max_width, |
740 | ffs(dd->out_width_align) - 1, | |
741 | &pixm->height, 0, dd->max_height, 0, 0); | |
4af81310 SN |
742 | |
743 | if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width)) | |
744 | pixm->plane_fmt[0].bytesperline = (pixm->width * | |
745 | fmt->depth[0]) / 8; | |
746 | ||
747 | if (pixm->plane_fmt[0].sizeimage == 0) | |
748 | pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height * | |
749 | fmt->depth[0]) / 8; | |
750 | pixm->num_planes = fmt->memplanes; | |
751 | pixm->pixelformat = fmt->fourcc; | |
1c26190a | 752 | pixm->colorspace = fmt->colorspace; |
4af81310 SN |
753 | pixm->field = V4L2_FIELD_NONE; |
754 | return 0; | |
755 | } | |
756 | ||
757 | static int fimc_lite_try_fmt_mplane(struct file *file, void *fh, | |
758 | struct v4l2_format *f) | |
759 | { | |
760 | struct fimc_lite *fimc = video_drvdata(file); | |
4af81310 SN |
761 | return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL); |
762 | } | |
763 | ||
764 | static int fimc_lite_s_fmt_mplane(struct file *file, void *priv, | |
765 | struct v4l2_format *f) | |
766 | { | |
767 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; | |
768 | struct fimc_lite *fimc = video_drvdata(file); | |
769 | struct flite_frame *frame = &fimc->out_frame; | |
770 | const struct fimc_fmt *fmt = NULL; | |
771 | int ret; | |
772 | ||
773 | if (vb2_is_busy(&fimc->vb_queue)) | |
774 | return -EBUSY; | |
775 | ||
776 | ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt); | |
777 | if (ret < 0) | |
778 | return ret; | |
779 | ||
e90ad659 | 780 | frame->fmt = fmt; |
4af81310 SN |
781 | fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8, |
782 | pixm->plane_fmt[0].sizeimage); | |
783 | frame->f_width = pixm->width; | |
784 | frame->f_height = pixm->height; | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static int fimc_pipeline_validate(struct fimc_lite *fimc) | |
790 | { | |
791 | struct v4l2_subdev *sd = &fimc->subdev; | |
792 | struct v4l2_subdev_format sink_fmt, src_fmt; | |
793 | struct media_pad *pad; | |
794 | int ret; | |
795 | ||
796 | while (1) { | |
797 | /* Retrieve format at the sink pad */ | |
798 | pad = &sd->entity.pads[0]; | |
799 | if (!(pad->flags & MEDIA_PAD_FL_SINK)) | |
800 | break; | |
801 | /* Don't call FIMC subdev operation to avoid nested locking */ | |
802 | if (sd == &fimc->subdev) { | |
803 | struct flite_frame *ff = &fimc->out_frame; | |
804 | sink_fmt.format.width = ff->f_width; | |
805 | sink_fmt.format.height = ff->f_height; | |
e90ad659 | 806 | sink_fmt.format.code = fimc->inp_frame.fmt->mbus_code; |
4af81310 SN |
807 | } else { |
808 | sink_fmt.pad = pad->index; | |
809 | sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
810 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, | |
811 | &sink_fmt); | |
812 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
813 | return -EPIPE; | |
814 | } | |
815 | /* Retrieve format at the source pad */ | |
1bddf1b3 | 816 | pad = media_entity_remote_pad(pad); |
4af81310 SN |
817 | if (pad == NULL || |
818 | media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV) | |
819 | break; | |
820 | ||
821 | sd = media_entity_to_v4l2_subdev(pad->entity); | |
822 | src_fmt.pad = pad->index; | |
823 | src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; | |
824 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt); | |
825 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
826 | return -EPIPE; | |
827 | ||
828 | if (src_fmt.format.width != sink_fmt.format.width || | |
829 | src_fmt.format.height != sink_fmt.format.height || | |
830 | src_fmt.format.code != sink_fmt.format.code) | |
831 | return -EPIPE; | |
832 | } | |
833 | return 0; | |
834 | } | |
835 | ||
836 | static int fimc_lite_streamon(struct file *file, void *priv, | |
837 | enum v4l2_buf_type type) | |
838 | { | |
839 | struct fimc_lite *fimc = video_drvdata(file); | |
bc7584b0 | 840 | struct media_entity *entity = &fimc->ve.vdev.entity; |
4af81310 SN |
841 | int ret; |
842 | ||
843 | if (fimc_lite_active(fimc)) | |
844 | return -EBUSY; | |
845 | ||
403dfbec | 846 | ret = media_entity_pipeline_start(entity, &fimc->ve.pipe->mp); |
a1a5861b SK |
847 | if (ret < 0) |
848 | return ret; | |
4af81310 SN |
849 | |
850 | ret = fimc_pipeline_validate(fimc); | |
ee12b049 SN |
851 | if (ret < 0) |
852 | goto err_p_stop; | |
4af81310 | 853 | |
045a1fac | 854 | fimc->sensor = fimc_find_remote_sensor(&fimc->subdev.entity); |
756e6e14 | 855 | |
ee12b049 | 856 | ret = vb2_ioctl_streamon(file, priv, type); |
9ea89e2b SN |
857 | if (!ret) { |
858 | fimc->streaming = true; | |
ee12b049 | 859 | return ret; |
9ea89e2b SN |
860 | } |
861 | ||
ee12b049 SN |
862 | err_p_stop: |
863 | media_entity_pipeline_stop(entity); | |
864 | return 0; | |
4af81310 SN |
865 | } |
866 | ||
867 | static int fimc_lite_streamoff(struct file *file, void *priv, | |
868 | enum v4l2_buf_type type) | |
869 | { | |
870 | struct fimc_lite *fimc = video_drvdata(file); | |
4af81310 SN |
871 | int ret; |
872 | ||
ee12b049 | 873 | ret = vb2_ioctl_streamoff(file, priv, type); |
9ea89e2b SN |
874 | if (ret < 0) |
875 | return ret; | |
876 | ||
bc7584b0 | 877 | media_entity_pipeline_stop(&fimc->ve.vdev.entity); |
9ea89e2b SN |
878 | fimc->streaming = false; |
879 | return 0; | |
4af81310 SN |
880 | } |
881 | ||
882 | static int fimc_lite_reqbufs(struct file *file, void *priv, | |
883 | struct v4l2_requestbuffers *reqbufs) | |
884 | { | |
885 | struct fimc_lite *fimc = video_drvdata(file); | |
886 | int ret; | |
887 | ||
888 | reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count); | |
ee12b049 | 889 | ret = vb2_ioctl_reqbufs(file, priv, reqbufs); |
f68247fc | 890 | if (!ret) |
4af81310 SN |
891 | fimc->reqbufs_count = reqbufs->count; |
892 | ||
893 | return ret; | |
894 | } | |
895 | ||
4af81310 SN |
896 | /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */ |
897 | static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b) | |
898 | { | |
899 | if (a->left < b->left || a->top < b->top) | |
900 | return 0; | |
901 | if (a->left + a->width > b->left + b->width) | |
902 | return 0; | |
903 | if (a->top + a->height > b->top + b->height) | |
904 | return 0; | |
905 | ||
906 | return 1; | |
907 | } | |
908 | ||
909 | static int fimc_lite_g_selection(struct file *file, void *fh, | |
910 | struct v4l2_selection *sel) | |
911 | { | |
912 | struct fimc_lite *fimc = video_drvdata(file); | |
913 | struct flite_frame *f = &fimc->out_frame; | |
914 | ||
915 | if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) | |
916 | return -EINVAL; | |
917 | ||
918 | switch (sel->target) { | |
919 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: | |
920 | case V4L2_SEL_TGT_COMPOSE_DEFAULT: | |
921 | sel->r.left = 0; | |
922 | sel->r.top = 0; | |
923 | sel->r.width = f->f_width; | |
924 | sel->r.height = f->f_height; | |
925 | return 0; | |
926 | ||
c1334823 | 927 | case V4L2_SEL_TGT_COMPOSE: |
4af81310 SN |
928 | sel->r = f->rect; |
929 | return 0; | |
930 | } | |
931 | ||
932 | return -EINVAL; | |
933 | } | |
934 | ||
935 | static int fimc_lite_s_selection(struct file *file, void *fh, | |
936 | struct v4l2_selection *sel) | |
937 | { | |
938 | struct fimc_lite *fimc = video_drvdata(file); | |
939 | struct flite_frame *f = &fimc->out_frame; | |
940 | struct v4l2_rect rect = sel->r; | |
941 | unsigned long flags; | |
942 | ||
943 | if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE || | |
c1334823 | 944 | sel->target != V4L2_SEL_TGT_COMPOSE) |
4af81310 SN |
945 | return -EINVAL; |
946 | ||
947 | fimc_lite_try_compose(fimc, &rect); | |
948 | ||
949 | if ((sel->flags & V4L2_SEL_FLAG_LE) && | |
950 | !enclosed_rectangle(&rect, &sel->r)) | |
951 | return -ERANGE; | |
952 | ||
953 | if ((sel->flags & V4L2_SEL_FLAG_GE) && | |
954 | !enclosed_rectangle(&sel->r, &rect)) | |
955 | return -ERANGE; | |
956 | ||
957 | sel->r = rect; | |
958 | spin_lock_irqsave(&fimc->slock, flags); | |
959 | f->rect = rect; | |
960 | set_bit(ST_FLITE_CONFIG, &fimc->state); | |
961 | spin_unlock_irqrestore(&fimc->slock, flags); | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = { | |
793ad32d | 967 | .vidioc_querycap = fimc_lite_querycap, |
4af81310 SN |
968 | .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane, |
969 | .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane, | |
970 | .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane, | |
971 | .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane, | |
972 | .vidioc_g_selection = fimc_lite_g_selection, | |
973 | .vidioc_s_selection = fimc_lite_s_selection, | |
974 | .vidioc_reqbufs = fimc_lite_reqbufs, | |
ee12b049 SN |
975 | .vidioc_querybuf = vb2_ioctl_querybuf, |
976 | .vidioc_prepare_buf = vb2_ioctl_prepare_buf, | |
977 | .vidioc_create_bufs = vb2_ioctl_create_bufs, | |
978 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
979 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
4af81310 SN |
980 | .vidioc_streamon = fimc_lite_streamon, |
981 | .vidioc_streamoff = fimc_lite_streamoff, | |
982 | }; | |
983 | ||
984 | /* Capture subdev media entity operations */ | |
985 | static int fimc_lite_link_setup(struct media_entity *entity, | |
986 | const struct media_pad *local, | |
987 | const struct media_pad *remote, u32 flags) | |
988 | { | |
989 | struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); | |
990 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
991 | unsigned int remote_ent_type = media_entity_type(remote->entity); | |
6319d6a0 | 992 | int ret = 0; |
4af81310 SN |
993 | |
994 | if (WARN_ON(fimc == NULL)) | |
995 | return 0; | |
996 | ||
969e877c | 997 | v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x\n", |
6319d6a0 | 998 | __func__, remote->entity->name, local->entity->name, |
4af81310 SN |
999 | flags, fimc->source_subdev_grp_id); |
1000 | ||
6319d6a0 SN |
1001 | switch (local->index) { |
1002 | case FLITE_SD_PAD_SINK: | |
1003 | if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV) { | |
1004 | ret = -EINVAL; | |
1005 | break; | |
1006 | } | |
4af81310 | 1007 | if (flags & MEDIA_LNK_FL_ENABLED) { |
6319d6a0 SN |
1008 | if (fimc->source_subdev_grp_id == 0) |
1009 | fimc->source_subdev_grp_id = sd->grp_id; | |
1010 | else | |
1011 | ret = -EBUSY; | |
1012 | } else { | |
1013 | fimc->source_subdev_grp_id = 0; | |
1014 | fimc->sensor = NULL; | |
4af81310 | 1015 | } |
6319d6a0 | 1016 | break; |
4af81310 | 1017 | |
6319d6a0 SN |
1018 | case FLITE_SD_PAD_SOURCE_DMA: |
1019 | if (!(flags & MEDIA_LNK_FL_ENABLED)) | |
03878bb4 | 1020 | atomic_set(&fimc->out_path, FIMC_IO_NONE); |
6319d6a0 | 1021 | else if (remote_ent_type == MEDIA_ENT_T_DEVNODE) |
03878bb4 | 1022 | atomic_set(&fimc->out_path, FIMC_IO_DMA); |
6319d6a0 SN |
1023 | else |
1024 | ret = -EINVAL; | |
4af81310 SN |
1025 | break; |
1026 | ||
6319d6a0 SN |
1027 | case FLITE_SD_PAD_SOURCE_ISP: |
1028 | if (!(flags & MEDIA_LNK_FL_ENABLED)) | |
03878bb4 | 1029 | atomic_set(&fimc->out_path, FIMC_IO_NONE); |
6319d6a0 | 1030 | else if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV) |
03878bb4 | 1031 | atomic_set(&fimc->out_path, FIMC_IO_ISP); |
4af81310 | 1032 | else |
6319d6a0 | 1033 | ret = -EINVAL; |
4af81310 SN |
1034 | break; |
1035 | ||
1036 | default: | |
1037 | v4l2_err(sd, "Invalid pad index\n"); | |
6319d6a0 | 1038 | ret = -EINVAL; |
4af81310 | 1039 | } |
03878bb4 | 1040 | mb(); |
4af81310 | 1041 | |
6319d6a0 | 1042 | return ret; |
4af81310 SN |
1043 | } |
1044 | ||
1045 | static const struct media_entity_operations fimc_lite_subdev_media_ops = { | |
1046 | .link_setup = fimc_lite_link_setup, | |
1047 | }; | |
1048 | ||
1049 | static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd, | |
1050 | struct v4l2_subdev_fh *fh, | |
1051 | struct v4l2_subdev_mbus_code_enum *code) | |
1052 | { | |
1053 | const struct fimc_fmt *fmt; | |
1054 | ||
e90ad659 | 1055 | fmt = fimc_lite_find_format(NULL, NULL, 0, code->index); |
4af81310 SN |
1056 | if (!fmt) |
1057 | return -EINVAL; | |
1058 | code->code = fmt->mbus_code; | |
1059 | return 0; | |
1060 | } | |
1061 | ||
b1d2dc5c SN |
1062 | static struct v4l2_mbus_framefmt *__fimc_lite_subdev_get_try_fmt( |
1063 | struct v4l2_subdev_fh *fh, unsigned int pad) | |
1064 | { | |
1065 | if (pad != FLITE_SD_PAD_SINK) | |
1066 | pad = FLITE_SD_PAD_SOURCE_DMA; | |
1067 | ||
1068 | return v4l2_subdev_get_try_format(fh, pad); | |
1069 | } | |
1070 | ||
4af81310 SN |
1071 | static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd, |
1072 | struct v4l2_subdev_fh *fh, | |
1073 | struct v4l2_subdev_format *fmt) | |
1074 | { | |
1075 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
1076 | struct v4l2_mbus_framefmt *mf = &fmt->format; | |
e90ad659 | 1077 | struct flite_frame *f = &fimc->inp_frame; |
4af81310 SN |
1078 | |
1079 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
b1d2dc5c | 1080 | mf = __fimc_lite_subdev_get_try_fmt(fh, fmt->pad); |
4af81310 SN |
1081 | fmt->format = *mf; |
1082 | return 0; | |
1083 | } | |
4af81310 SN |
1084 | |
1085 | mutex_lock(&fimc->lock); | |
1c26190a | 1086 | mf->colorspace = f->fmt->colorspace; |
e90ad659 | 1087 | mf->code = f->fmt->mbus_code; |
4af81310 SN |
1088 | |
1089 | if (fmt->pad == FLITE_SD_PAD_SINK) { | |
1090 | /* full camera input frame size */ | |
1091 | mf->width = f->f_width; | |
1092 | mf->height = f->f_height; | |
1093 | } else { | |
1094 | /* crop size */ | |
1095 | mf->width = f->rect.width; | |
1096 | mf->height = f->rect.height; | |
1097 | } | |
1098 | mutex_unlock(&fimc->lock); | |
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd, | |
1103 | struct v4l2_subdev_fh *fh, | |
1104 | struct v4l2_subdev_format *fmt) | |
1105 | { | |
1106 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
1107 | struct v4l2_mbus_framefmt *mf = &fmt->format; | |
1108 | struct flite_frame *sink = &fimc->inp_frame; | |
9356ac76 | 1109 | struct flite_frame *source = &fimc->out_frame; |
4af81310 SN |
1110 | const struct fimc_fmt *ffmt; |
1111 | ||
969e877c | 1112 | v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d\n", |
4af81310 SN |
1113 | fmt->pad, mf->code, mf->width, mf->height); |
1114 | ||
4af81310 SN |
1115 | mutex_lock(&fimc->lock); |
1116 | ||
03878bb4 SN |
1117 | if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP && |
1118 | sd->entity.stream_count > 0) || | |
1119 | (atomic_read(&fimc->out_path) == FIMC_IO_DMA && | |
1120 | vb2_is_busy(&fimc->vb_queue))) { | |
4af81310 SN |
1121 | mutex_unlock(&fimc->lock); |
1122 | return -EBUSY; | |
1123 | } | |
1124 | ||
b1d2dc5c | 1125 | ffmt = fimc_lite_subdev_try_fmt(fimc, fh, fmt); |
4af81310 SN |
1126 | |
1127 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
b1d2dc5c SN |
1128 | struct v4l2_mbus_framefmt *src_fmt; |
1129 | ||
1130 | mf = __fimc_lite_subdev_get_try_fmt(fh, fmt->pad); | |
4af81310 | 1131 | *mf = fmt->format; |
b1d2dc5c SN |
1132 | |
1133 | if (fmt->pad == FLITE_SD_PAD_SINK) { | |
1134 | unsigned int pad = FLITE_SD_PAD_SOURCE_DMA; | |
1135 | src_fmt = __fimc_lite_subdev_get_try_fmt(fh, pad); | |
1136 | *src_fmt = *mf; | |
1137 | } | |
1138 | ||
4af81310 SN |
1139 | mutex_unlock(&fimc->lock); |
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | if (fmt->pad == FLITE_SD_PAD_SINK) { | |
1144 | sink->f_width = mf->width; | |
1145 | sink->f_height = mf->height; | |
e90ad659 | 1146 | sink->fmt = ffmt; |
4af81310 SN |
1147 | /* Set sink crop rectangle */ |
1148 | sink->rect.width = mf->width; | |
1149 | sink->rect.height = mf->height; | |
1150 | sink->rect.left = 0; | |
1151 | sink->rect.top = 0; | |
9356ac76 SN |
1152 | /* Reset source format and crop rectangle */ |
1153 | source->rect = sink->rect; | |
1154 | source->f_width = mf->width; | |
1155 | source->f_height = mf->height; | |
4af81310 SN |
1156 | } |
1157 | ||
1158 | mutex_unlock(&fimc->lock); | |
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd, | |
1163 | struct v4l2_subdev_fh *fh, | |
1164 | struct v4l2_subdev_selection *sel) | |
1165 | { | |
1166 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
1167 | struct flite_frame *f = &fimc->inp_frame; | |
1168 | ||
5689b288 SA |
1169 | if ((sel->target != V4L2_SEL_TGT_CROP && |
1170 | sel->target != V4L2_SEL_TGT_CROP_BOUNDS) || | |
1171 | sel->pad != FLITE_SD_PAD_SINK) | |
4af81310 SN |
1172 | return -EINVAL; |
1173 | ||
1174 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1175 | sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad); | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | mutex_lock(&fimc->lock); | |
5689b288 | 1180 | if (sel->target == V4L2_SEL_TGT_CROP) { |
4af81310 SN |
1181 | sel->r = f->rect; |
1182 | } else { | |
1183 | sel->r.left = 0; | |
1184 | sel->r.top = 0; | |
1185 | sel->r.width = f->f_width; | |
1186 | sel->r.height = f->f_height; | |
1187 | } | |
1188 | mutex_unlock(&fimc->lock); | |
1189 | ||
969e877c | 1190 | v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n", |
4af81310 SN |
1191 | __func__, f->rect.left, f->rect.top, f->rect.width, |
1192 | f->rect.height, f->f_width, f->f_height); | |
1193 | ||
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd, | |
1198 | struct v4l2_subdev_fh *fh, | |
1199 | struct v4l2_subdev_selection *sel) | |
1200 | { | |
1201 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
1202 | struct flite_frame *f = &fimc->inp_frame; | |
1203 | int ret = 0; | |
1204 | ||
5689b288 | 1205 | if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK) |
4af81310 SN |
1206 | return -EINVAL; |
1207 | ||
1208 | mutex_lock(&fimc->lock); | |
1209 | fimc_lite_try_crop(fimc, &sel->r); | |
1210 | ||
1211 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1212 | *v4l2_subdev_get_try_crop(fh, sel->pad) = sel->r; | |
1213 | } else { | |
1214 | unsigned long flags; | |
1215 | spin_lock_irqsave(&fimc->slock, flags); | |
1216 | f->rect = sel->r; | |
1217 | /* Same crop rectangle on the source pad */ | |
1218 | fimc->out_frame.rect = sel->r; | |
1219 | set_bit(ST_FLITE_CONFIG, &fimc->state); | |
1220 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1221 | } | |
1222 | mutex_unlock(&fimc->lock); | |
1223 | ||
969e877c | 1224 | v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n", |
4af81310 SN |
1225 | __func__, f->rect.left, f->rect.top, f->rect.width, |
1226 | f->rect.height, f->f_width, f->f_height); | |
1227 | ||
1228 | return ret; | |
1229 | } | |
1230 | ||
1231 | static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on) | |
1232 | { | |
1233 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
6319d6a0 SN |
1234 | unsigned long flags; |
1235 | int ret; | |
4af81310 | 1236 | |
6319d6a0 SN |
1237 | /* |
1238 | * Find sensor subdev linked to FIMC-LITE directly or through | |
1239 | * MIPI-CSIS. This is required for configuration where FIMC-LITE | |
1240 | * is used as a subdev only and feeds data internally to FIMC-IS. | |
1241 | * The pipeline links are protected through entity.stream_count | |
1242 | * so there is no need to take the media graph mutex here. | |
1243 | */ | |
045a1fac | 1244 | fimc->sensor = fimc_find_remote_sensor(&sd->entity); |
6319d6a0 | 1245 | |
03878bb4 | 1246 | if (atomic_read(&fimc->out_path) != FIMC_IO_ISP) |
4af81310 SN |
1247 | return -ENOIOCTLCMD; |
1248 | ||
03878bb4 | 1249 | mutex_lock(&fimc->lock); |
6319d6a0 SN |
1250 | if (on) { |
1251 | flite_hw_reset(fimc); | |
1252 | ret = fimc_lite_hw_init(fimc, true); | |
1253 | if (!ret) { | |
1254 | spin_lock_irqsave(&fimc->slock, flags); | |
1255 | flite_hw_capture_start(fimc); | |
1256 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1257 | } | |
1258 | } else { | |
1259 | set_bit(ST_FLITE_OFF, &fimc->state); | |
4af81310 | 1260 | |
6319d6a0 SN |
1261 | spin_lock_irqsave(&fimc->slock, flags); |
1262 | flite_hw_capture_stop(fimc); | |
1263 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1264 | ||
1265 | ret = wait_event_timeout(fimc->irq_queue, | |
1266 | !test_bit(ST_FLITE_OFF, &fimc->state), | |
1267 | msecs_to_jiffies(200)); | |
1268 | if (ret == 0) | |
1269 | v4l2_err(sd, "s_stream(0) timeout\n"); | |
1270 | clear_bit(ST_FLITE_RUN, &fimc->state); | |
1271 | } | |
1272 | ||
1273 | mutex_unlock(&fimc->lock); | |
1274 | return ret; | |
4af81310 SN |
1275 | } |
1276 | ||
4af81310 SN |
1277 | static int fimc_lite_log_status(struct v4l2_subdev *sd) |
1278 | { | |
1279 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
1280 | ||
1281 | flite_hw_dump_regs(fimc, __func__); | |
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static int fimc_lite_subdev_registered(struct v4l2_subdev *sd) | |
1286 | { | |
1287 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
1288 | struct vb2_queue *q = &fimc->vb_queue; | |
bc7584b0 | 1289 | struct video_device *vfd = &fimc->ve.vdev; |
4af81310 SN |
1290 | int ret; |
1291 | ||
1bcd7041 | 1292 | memset(vfd, 0, sizeof(*vfd)); |
03878bb4 | 1293 | atomic_set(&fimc->out_path, FIMC_IO_DMA); |
4af81310 | 1294 | |
4af81310 SN |
1295 | snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture", |
1296 | fimc->index); | |
1297 | ||
1298 | vfd->fops = &fimc_lite_fops; | |
1299 | vfd->ioctl_ops = &fimc_lite_ioctl_ops; | |
1300 | vfd->v4l2_dev = sd->v4l2_dev; | |
1301 | vfd->minor = -1; | |
1bcd7041 | 1302 | vfd->release = video_device_release_empty; |
ee12b049 | 1303 | vfd->queue = q; |
4af81310 SN |
1304 | fimc->reqbufs_count = 0; |
1305 | ||
1306 | INIT_LIST_HEAD(&fimc->pending_buf_q); | |
1307 | INIT_LIST_HEAD(&fimc->active_buf_q); | |
1308 | ||
1309 | memset(q, 0, sizeof(*q)); | |
1310 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; | |
1311 | q->io_modes = VB2_MMAP | VB2_USERPTR; | |
1312 | q->ops = &fimc_lite_qops; | |
1313 | q->mem_ops = &vb2_dma_contig_memops; | |
1314 | q->buf_struct_size = sizeof(struct flite_buffer); | |
1315 | q->drv_priv = fimc; | |
6aa69f99 | 1316 | q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; |
ee12b049 | 1317 | q->lock = &fimc->lock; |
4af81310 | 1318 | |
41fd087f SN |
1319 | ret = vb2_queue_init(q); |
1320 | if (ret < 0) | |
1321 | return ret; | |
4af81310 SN |
1322 | |
1323 | fimc->vd_pad.flags = MEDIA_PAD_FL_SINK; | |
1324 | ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0); | |
1bcd7041 SN |
1325 | if (ret < 0) |
1326 | return ret; | |
4af81310 SN |
1327 | |
1328 | video_set_drvdata(vfd, fimc); | |
403dfbec | 1329 | fimc->ve.pipe = v4l2_get_subdev_hostdata(sd); |
4af81310 SN |
1330 | |
1331 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1); | |
1bcd7041 SN |
1332 | if (ret < 0) { |
1333 | media_entity_cleanup(&vfd->entity); | |
403dfbec | 1334 | fimc->ve.pipe = NULL; |
1bcd7041 SN |
1335 | return ret; |
1336 | } | |
4af81310 SN |
1337 | |
1338 | v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n", | |
1339 | vfd->name, video_device_node_name(vfd)); | |
1340 | return 0; | |
4af81310 SN |
1341 | } |
1342 | ||
1343 | static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd) | |
1344 | { | |
1345 | struct fimc_lite *fimc = v4l2_get_subdevdata(sd); | |
1346 | ||
1347 | if (fimc == NULL) | |
1348 | return; | |
1349 | ||
26d63d13 SN |
1350 | mutex_lock(&fimc->lock); |
1351 | ||
bc7584b0 SN |
1352 | if (video_is_registered(&fimc->ve.vdev)) { |
1353 | video_unregister_device(&fimc->ve.vdev); | |
1354 | media_entity_cleanup(&fimc->ve.vdev.entity); | |
403dfbec | 1355 | fimc->ve.pipe = NULL; |
4af81310 | 1356 | } |
26d63d13 SN |
1357 | |
1358 | mutex_unlock(&fimc->lock); | |
4af81310 SN |
1359 | } |
1360 | ||
1361 | static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = { | |
1362 | .registered = fimc_lite_subdev_registered, | |
1363 | .unregistered = fimc_lite_subdev_unregistered, | |
1364 | }; | |
1365 | ||
1366 | static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = { | |
1367 | .enum_mbus_code = fimc_lite_subdev_enum_mbus_code, | |
1368 | .get_selection = fimc_lite_subdev_get_selection, | |
1369 | .set_selection = fimc_lite_subdev_set_selection, | |
1370 | .get_fmt = fimc_lite_subdev_get_fmt, | |
1371 | .set_fmt = fimc_lite_subdev_set_fmt, | |
1372 | }; | |
1373 | ||
1374 | static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = { | |
1375 | .s_stream = fimc_lite_subdev_s_stream, | |
1376 | }; | |
1377 | ||
1378 | static const struct v4l2_subdev_core_ops fimc_lite_core_ops = { | |
4af81310 SN |
1379 | .log_status = fimc_lite_log_status, |
1380 | }; | |
1381 | ||
1382 | static struct v4l2_subdev_ops fimc_lite_subdev_ops = { | |
1383 | .core = &fimc_lite_core_ops, | |
1384 | .video = &fimc_lite_subdev_video_ops, | |
1385 | .pad = &fimc_lite_subdev_pad_ops, | |
1386 | }; | |
1387 | ||
1388 | static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl) | |
1389 | { | |
1390 | struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite, | |
1391 | ctrl_handler); | |
1392 | set_bit(ST_FLITE_CONFIG, &fimc->state); | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = { | |
1397 | .s_ctrl = fimc_lite_s_ctrl, | |
1398 | }; | |
1399 | ||
1400 | static const struct v4l2_ctrl_config fimc_lite_ctrl = { | |
1401 | .ops = &fimc_lite_ctrl_ops, | |
1402 | .id = V4L2_CTRL_CLASS_USER | 0x1001, | |
1403 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
1404 | .name = "Test Pattern 640x480", | |
4cec1893 | 1405 | .step = 1, |
4af81310 SN |
1406 | }; |
1407 | ||
a055d970 SN |
1408 | static void fimc_lite_set_default_config(struct fimc_lite *fimc) |
1409 | { | |
1410 | struct flite_frame *sink = &fimc->inp_frame; | |
1411 | struct flite_frame *source = &fimc->out_frame; | |
1412 | ||
1413 | sink->fmt = &fimc_lite_formats[0]; | |
1414 | sink->f_width = FLITE_DEFAULT_WIDTH; | |
1415 | sink->f_height = FLITE_DEFAULT_HEIGHT; | |
1416 | ||
1417 | sink->rect.width = FLITE_DEFAULT_WIDTH; | |
1418 | sink->rect.height = FLITE_DEFAULT_HEIGHT; | |
1419 | sink->rect.left = 0; | |
1420 | sink->rect.top = 0; | |
1421 | ||
1422 | *source = *sink; | |
1423 | } | |
1424 | ||
4af81310 SN |
1425 | static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc) |
1426 | { | |
1427 | struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler; | |
1428 | struct v4l2_subdev *sd = &fimc->subdev; | |
1429 | int ret; | |
1430 | ||
1431 | v4l2_subdev_init(sd, &fimc_lite_subdev_ops); | |
5a66561f | 1432 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
4af81310 SN |
1433 | snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index); |
1434 | ||
6319d6a0 SN |
1435 | fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK; |
1436 | fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE; | |
1437 | fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE; | |
1438 | ret = media_entity_init(&sd->entity, FLITE_SD_PADS_NUM, | |
4af81310 SN |
1439 | fimc->subdev_pads, 0); |
1440 | if (ret) | |
1441 | return ret; | |
1442 | ||
1443 | v4l2_ctrl_handler_init(handler, 1); | |
1444 | fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl, | |
1445 | NULL); | |
1446 | if (handler->error) { | |
1447 | media_entity_cleanup(&sd->entity); | |
1448 | return handler->error; | |
1449 | } | |
1450 | ||
1451 | sd->ctrl_handler = handler; | |
1452 | sd->internal_ops = &fimc_lite_subdev_internal_ops; | |
1453 | sd->entity.ops = &fimc_lite_subdev_media_ops; | |
a59ed48f | 1454 | sd->owner = THIS_MODULE; |
4af81310 SN |
1455 | v4l2_set_subdevdata(sd, fimc); |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc) | |
1461 | { | |
1462 | struct v4l2_subdev *sd = &fimc->subdev; | |
1463 | ||
1464 | v4l2_device_unregister_subdev(sd); | |
1465 | media_entity_cleanup(&sd->entity); | |
1466 | v4l2_ctrl_handler_free(&fimc->ctrl_handler); | |
1467 | v4l2_set_subdevdata(sd, NULL); | |
1468 | } | |
1469 | ||
1470 | static void fimc_lite_clk_put(struct fimc_lite *fimc) | |
1471 | { | |
24f99dd0 | 1472 | if (IS_ERR(fimc->clock)) |
4af81310 SN |
1473 | return; |
1474 | ||
1475 | clk_unprepare(fimc->clock); | |
1476 | clk_put(fimc->clock); | |
24f99dd0 | 1477 | fimc->clock = ERR_PTR(-EINVAL); |
4af81310 SN |
1478 | } |
1479 | ||
1480 | static int fimc_lite_clk_get(struct fimc_lite *fimc) | |
1481 | { | |
1482 | int ret; | |
1483 | ||
1484 | fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME); | |
1485 | if (IS_ERR(fimc->clock)) | |
1486 | return PTR_ERR(fimc->clock); | |
1487 | ||
1488 | ret = clk_prepare(fimc->clock); | |
1489 | if (ret < 0) { | |
1490 | clk_put(fimc->clock); | |
24f99dd0 | 1491 | fimc->clock = ERR_PTR(-EINVAL); |
4af81310 SN |
1492 | } |
1493 | return ret; | |
1494 | } | |
1495 | ||
eb62d9e9 SN |
1496 | static const struct of_device_id flite_of_match[]; |
1497 | ||
4c62e976 | 1498 | static int fimc_lite_probe(struct platform_device *pdev) |
4af81310 | 1499 | { |
eb62d9e9 SN |
1500 | struct flite_drvdata *drv_data = NULL; |
1501 | struct device *dev = &pdev->dev; | |
1502 | const struct of_device_id *of_id; | |
4af81310 SN |
1503 | struct fimc_lite *fimc; |
1504 | struct resource *res; | |
1505 | int ret; | |
1506 | ||
6a40cbbe SK |
1507 | if (!dev->of_node) |
1508 | return -ENODEV; | |
1509 | ||
eb62d9e9 | 1510 | fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL); |
4af81310 SN |
1511 | if (!fimc) |
1512 | return -ENOMEM; | |
1513 | ||
6a40cbbe SK |
1514 | of_id = of_match_node(flite_of_match, dev->of_node); |
1515 | if (of_id) | |
1516 | drv_data = (struct flite_drvdata *)of_id->data; | |
1517 | fimc->index = of_alias_get_id(dev->of_node, "fimc-lite"); | |
eb62d9e9 | 1518 | |
086eca29 SN |
1519 | if (!drv_data || fimc->index >= drv_data->num_instances || |
1520 | fimc->index < 0) { | |
1521 | dev_err(dev, "Wrong %s node alias\n", | |
1522 | dev->of_node->full_name); | |
eb62d9e9 | 1523 | return -EINVAL; |
086eca29 | 1524 | } |
eb62d9e9 | 1525 | |
9c8399c8 | 1526 | fimc->dd = drv_data; |
4af81310 SN |
1527 | fimc->pdev = pdev; |
1528 | ||
1529 | init_waitqueue_head(&fimc->irq_queue); | |
1530 | spin_lock_init(&fimc->slock); | |
1531 | mutex_init(&fimc->lock); | |
1532 | ||
1533 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
eb62d9e9 | 1534 | fimc->regs = devm_ioremap_resource(dev, res); |
f23999ec TR |
1535 | if (IS_ERR(fimc->regs)) |
1536 | return PTR_ERR(fimc->regs); | |
4af81310 SN |
1537 | |
1538 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1539 | if (res == NULL) { | |
eb62d9e9 | 1540 | dev_err(dev, "Failed to get IRQ resource\n"); |
4af81310 SN |
1541 | return -ENXIO; |
1542 | } | |
1543 | ||
1544 | ret = fimc_lite_clk_get(fimc); | |
1545 | if (ret) | |
1546 | return ret; | |
1547 | ||
eb62d9e9 SN |
1548 | ret = devm_request_irq(dev, res->start, flite_irq_handler, |
1549 | 0, dev_name(dev), fimc); | |
4af81310 | 1550 | if (ret) { |
eb62d9e9 | 1551 | dev_err(dev, "Failed to install irq (%d)\n", ret); |
84f14456 | 1552 | goto err_clk_put; |
4af81310 SN |
1553 | } |
1554 | ||
1555 | /* The video node will be created within the subdev's registered() op */ | |
1556 | ret = fimc_lite_create_capture_subdev(fimc); | |
1557 | if (ret) | |
84f14456 | 1558 | goto err_clk_put; |
4af81310 SN |
1559 | |
1560 | platform_set_drvdata(pdev, fimc); | |
eb62d9e9 | 1561 | pm_runtime_enable(dev); |
84f14456 SN |
1562 | |
1563 | if (!pm_runtime_enabled(dev)) { | |
1564 | ret = clk_enable(fimc->clock); | |
1565 | if (ret < 0) | |
a27a19d6 | 1566 | goto err_sd; |
84f14456 | 1567 | } |
4af81310 | 1568 | |
eb62d9e9 | 1569 | fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev); |
4af81310 SN |
1570 | if (IS_ERR(fimc->alloc_ctx)) { |
1571 | ret = PTR_ERR(fimc->alloc_ctx); | |
84f14456 | 1572 | goto err_clk_dis; |
4af81310 | 1573 | } |
a055d970 | 1574 | |
a055d970 SN |
1575 | fimc_lite_set_default_config(fimc); |
1576 | ||
eb62d9e9 | 1577 | dev_dbg(dev, "FIMC-LITE.%d registered successfully\n", |
4af81310 SN |
1578 | fimc->index); |
1579 | return 0; | |
84f14456 SN |
1580 | |
1581 | err_clk_dis: | |
a27a19d6 SN |
1582 | if (!pm_runtime_enabled(dev)) |
1583 | clk_disable(fimc->clock); | |
4af81310 SN |
1584 | err_sd: |
1585 | fimc_lite_unregister_capture_subdev(fimc); | |
84f14456 | 1586 | err_clk_put: |
4af81310 SN |
1587 | fimc_lite_clk_put(fimc); |
1588 | return ret; | |
1589 | } | |
1590 | ||
656e62dc | 1591 | #ifdef CONFIG_PM_RUNTIME |
4af81310 SN |
1592 | static int fimc_lite_runtime_resume(struct device *dev) |
1593 | { | |
1594 | struct fimc_lite *fimc = dev_get_drvdata(dev); | |
1595 | ||
1596 | clk_enable(fimc->clock); | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | static int fimc_lite_runtime_suspend(struct device *dev) | |
1601 | { | |
1602 | struct fimc_lite *fimc = dev_get_drvdata(dev); | |
1603 | ||
1604 | clk_disable(fimc->clock); | |
1605 | return 0; | |
1606 | } | |
656e62dc | 1607 | #endif |
4af81310 SN |
1608 | |
1609 | #ifdef CONFIG_PM_SLEEP | |
1610 | static int fimc_lite_resume(struct device *dev) | |
1611 | { | |
1612 | struct fimc_lite *fimc = dev_get_drvdata(dev); | |
1613 | struct flite_buffer *buf; | |
1614 | unsigned long flags; | |
1615 | int i; | |
1616 | ||
1617 | spin_lock_irqsave(&fimc->slock, flags); | |
1618 | if (!test_and_clear_bit(ST_LPM, &fimc->state) || | |
1619 | !test_bit(ST_FLITE_IN_USE, &fimc->state)) { | |
1620 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1621 | return 0; | |
1622 | } | |
1623 | flite_hw_reset(fimc); | |
1624 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1625 | ||
1626 | if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state)) | |
1627 | return 0; | |
1628 | ||
1629 | INIT_LIST_HEAD(&fimc->active_buf_q); | |
403dfbec | 1630 | fimc_pipeline_call(&fimc->ve, open, |
bc7584b0 | 1631 | &fimc->ve.vdev.entity, false); |
03878bb4 | 1632 | fimc_lite_hw_init(fimc, atomic_read(&fimc->out_path) == FIMC_IO_ISP); |
4af81310 SN |
1633 | clear_bit(ST_FLITE_SUSPENDED, &fimc->state); |
1634 | ||
1635 | for (i = 0; i < fimc->reqbufs_count; i++) { | |
1636 | if (list_empty(&fimc->pending_buf_q)) | |
1637 | break; | |
1638 | buf = fimc_lite_pending_queue_pop(fimc); | |
1639 | buffer_queue(&buf->vb); | |
1640 | } | |
1641 | return 0; | |
1642 | } | |
1643 | ||
1644 | static int fimc_lite_suspend(struct device *dev) | |
1645 | { | |
1646 | struct fimc_lite *fimc = dev_get_drvdata(dev); | |
1647 | bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state); | |
1648 | int ret; | |
1649 | ||
1650 | if (test_and_set_bit(ST_LPM, &fimc->state)) | |
1651 | return 0; | |
1652 | ||
1653 | ret = fimc_lite_stop_capture(fimc, suspend); | |
316efab3 | 1654 | if (ret < 0 || !fimc_lite_active(fimc)) |
4af81310 SN |
1655 | return ret; |
1656 | ||
403dfbec | 1657 | return fimc_pipeline_call(&fimc->ve, close); |
4af81310 SN |
1658 | } |
1659 | #endif /* CONFIG_PM_SLEEP */ | |
1660 | ||
4c62e976 | 1661 | static int fimc_lite_remove(struct platform_device *pdev) |
4af81310 SN |
1662 | { |
1663 | struct fimc_lite *fimc = platform_get_drvdata(pdev); | |
1664 | struct device *dev = &pdev->dev; | |
1665 | ||
1666 | pm_runtime_disable(dev); | |
1667 | pm_runtime_set_suspended(dev); | |
1668 | fimc_lite_unregister_capture_subdev(fimc); | |
1669 | vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx); | |
1670 | fimc_lite_clk_put(fimc); | |
1671 | ||
1672 | dev_info(dev, "Driver unloaded\n"); | |
1673 | return 0; | |
1674 | } | |
1675 | ||
eb62d9e9 SN |
1676 | static const struct dev_pm_ops fimc_lite_pm_ops = { |
1677 | SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume) | |
1678 | SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume, | |
1679 | NULL) | |
1680 | }; | |
1681 | ||
9c8399c8 SN |
1682 | /* EXYNOS4212, EXYNOS4412 */ |
1683 | static struct flite_drvdata fimc_lite_drvdata_exynos4 = { | |
4af81310 SN |
1684 | .max_width = 8192, |
1685 | .max_height = 8192, | |
1686 | .out_width_align = 8, | |
1687 | .win_hor_offs_align = 2, | |
1688 | .out_hor_offs_align = 8, | |
086eca29 SN |
1689 | .max_dma_bufs = 1, |
1690 | .num_instances = 2, | |
1691 | }; | |
1692 | ||
1693 | /* EXYNOS5250 */ | |
1694 | static struct flite_drvdata fimc_lite_drvdata_exynos5 = { | |
1695 | .max_width = 8192, | |
1696 | .max_height = 8192, | |
1697 | .out_width_align = 8, | |
1698 | .win_hor_offs_align = 2, | |
1699 | .out_hor_offs_align = 8, | |
1700 | .max_dma_bufs = 32, | |
1701 | .num_instances = 3, | |
4af81310 SN |
1702 | }; |
1703 | ||
eb62d9e9 SN |
1704 | static const struct of_device_id flite_of_match[] = { |
1705 | { | |
1706 | .compatible = "samsung,exynos4212-fimc-lite", | |
1707 | .data = &fimc_lite_drvdata_exynos4, | |
1708 | }, | |
086eca29 SN |
1709 | { |
1710 | .compatible = "samsung,exynos5250-fimc-lite", | |
1711 | .data = &fimc_lite_drvdata_exynos5, | |
1712 | }, | |
eb62d9e9 | 1713 | { /* sentinel */ }, |
4af81310 | 1714 | }; |
eb62d9e9 | 1715 | MODULE_DEVICE_TABLE(of, flite_of_match); |
4af81310 SN |
1716 | |
1717 | static struct platform_driver fimc_lite_driver = { | |
1718 | .probe = fimc_lite_probe, | |
4c62e976 | 1719 | .remove = fimc_lite_remove, |
4af81310 | 1720 | .driver = { |
eb62d9e9 | 1721 | .of_match_table = flite_of_match, |
4af81310 SN |
1722 | .name = FIMC_LITE_DRV_NAME, |
1723 | .owner = THIS_MODULE, | |
1724 | .pm = &fimc_lite_pm_ops, | |
1725 | } | |
1726 | }; | |
1727 | module_platform_driver(fimc_lite_driver); | |
1728 | MODULE_LICENSE("GPL"); | |
1729 | MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME); |