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9a761e43 SN |
1 | /* |
2 | * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * | |
6 | * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com> | |
7 | * Younghwan Joo <yhwan.joo@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__ | |
14 | ||
15 | #include <linux/device.h> | |
16 | #include <linux/debugfs.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/dma-contiguous.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/firmware.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
687b81d0 | 24 | #include <linux/i2c.h> |
9a761e43 SN |
25 | #include <linux/of_irq.h> |
26 | #include <linux/of_address.h> | |
fd9fdb78 | 27 | #include <linux/of_graph.h> |
9a761e43 SN |
28 | #include <linux/of_platform.h> |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/pm_runtime.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/types.h> | |
33 | #include <linux/videodev2.h> | |
9a761e43 SN |
34 | #include <media/videobuf2-dma-contig.h> |
35 | ||
36 | #include "media-dev.h" | |
37 | #include "fimc-is.h" | |
38 | #include "fimc-is-command.h" | |
39 | #include "fimc-is-errno.h" | |
40 | #include "fimc-is-i2c.h" | |
41 | #include "fimc-is-param.h" | |
42 | #include "fimc-is-regs.h" | |
43 | ||
44 | ||
45 | static char *fimc_is_clocks[ISS_CLKS_MAX] = { | |
46 | [ISS_CLK_PPMUISPX] = "ppmuispx", | |
47 | [ISS_CLK_PPMUISPMX] = "ppmuispmx", | |
48 | [ISS_CLK_LITE0] = "lite0", | |
49 | [ISS_CLK_LITE1] = "lite1", | |
50 | [ISS_CLK_MPLL] = "mpll", | |
9a761e43 SN |
51 | [ISS_CLK_ISP] = "isp", |
52 | [ISS_CLK_DRC] = "drc", | |
53 | [ISS_CLK_FD] = "fd", | |
54 | [ISS_CLK_MCUISP] = "mcuisp", | |
55 | [ISS_CLK_UART] = "uart", | |
56 | [ISS_CLK_ISP_DIV0] = "ispdiv0", | |
57 | [ISS_CLK_ISP_DIV1] = "ispdiv1", | |
58 | [ISS_CLK_MCUISP_DIV0] = "mcuispdiv0", | |
59 | [ISS_CLK_MCUISP_DIV1] = "mcuispdiv1", | |
60 | [ISS_CLK_ACLK200] = "aclk200", | |
61 | [ISS_CLK_ACLK200_DIV] = "div_aclk200", | |
62 | [ISS_CLK_ACLK400MCUISP] = "aclk400mcuisp", | |
63 | [ISS_CLK_ACLK400MCUISP_DIV] = "div_aclk400mcuisp", | |
64 | }; | |
65 | ||
66 | static void fimc_is_put_clocks(struct fimc_is *is) | |
67 | { | |
68 | int i; | |
69 | ||
70 | for (i = 0; i < ISS_CLKS_MAX; i++) { | |
71 | if (IS_ERR(is->clocks[i])) | |
72 | continue; | |
9a761e43 SN |
73 | clk_put(is->clocks[i]); |
74 | is->clocks[i] = ERR_PTR(-EINVAL); | |
75 | } | |
76 | } | |
77 | ||
78 | static int fimc_is_get_clocks(struct fimc_is *is) | |
79 | { | |
80 | int i, ret; | |
81 | ||
82 | for (i = 0; i < ISS_CLKS_MAX; i++) | |
83 | is->clocks[i] = ERR_PTR(-EINVAL); | |
84 | ||
85 | for (i = 0; i < ISS_CLKS_MAX; i++) { | |
86 | is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]); | |
87 | if (IS_ERR(is->clocks[i])) { | |
88 | ret = PTR_ERR(is->clocks[i]); | |
89 | goto err; | |
90 | } | |
9a761e43 SN |
91 | } |
92 | ||
93 | return 0; | |
94 | err: | |
95 | fimc_is_put_clocks(is); | |
96 | dev_err(&is->pdev->dev, "failed to get clock: %s\n", | |
97 | fimc_is_clocks[i]); | |
b4155d7d | 98 | return ret; |
9a761e43 SN |
99 | } |
100 | ||
101 | static int fimc_is_setup_clocks(struct fimc_is *is) | |
102 | { | |
103 | int ret; | |
104 | ||
105 | ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200], | |
106 | is->clocks[ISS_CLK_ACLK200_DIV]); | |
107 | if (ret < 0) | |
108 | return ret; | |
109 | ||
110 | ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP], | |
111 | is->clocks[ISS_CLK_ACLK400MCUISP_DIV]); | |
112 | if (ret < 0) | |
113 | return ret; | |
114 | ||
115 | ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY); | |
116 | if (ret < 0) | |
117 | return ret; | |
118 | ||
119 | ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY); | |
120 | if (ret < 0) | |
121 | return ret; | |
122 | ||
123 | ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0], | |
124 | ATCLK_MCUISP_FREQUENCY); | |
125 | if (ret < 0) | |
126 | return ret; | |
127 | ||
128 | return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1], | |
129 | ATCLK_MCUISP_FREQUENCY); | |
130 | } | |
131 | ||
e0e9f67a | 132 | static int fimc_is_enable_clocks(struct fimc_is *is) |
9a761e43 SN |
133 | { |
134 | int i, ret; | |
135 | ||
136 | for (i = 0; i < ISS_GATE_CLKS_MAX; i++) { | |
137 | if (IS_ERR(is->clocks[i])) | |
138 | continue; | |
b4155d7d | 139 | ret = clk_prepare_enable(is->clocks[i]); |
9a761e43 SN |
140 | if (ret < 0) { |
141 | dev_err(&is->pdev->dev, "clock %s enable failed\n", | |
142 | fimc_is_clocks[i]); | |
143 | for (--i; i >= 0; i--) | |
144 | clk_disable(is->clocks[i]); | |
145 | return ret; | |
146 | } | |
147 | pr_debug("enabled clock: %s\n", fimc_is_clocks[i]); | |
148 | } | |
149 | return 0; | |
150 | } | |
151 | ||
e0e9f67a | 152 | static void fimc_is_disable_clocks(struct fimc_is *is) |
9a761e43 SN |
153 | { |
154 | int i; | |
155 | ||
156 | for (i = 0; i < ISS_GATE_CLKS_MAX; i++) { | |
157 | if (!IS_ERR(is->clocks[i])) { | |
b4155d7d | 158 | clk_disable_unprepare(is->clocks[i]); |
9a761e43 SN |
159 | pr_debug("disabled clock: %s\n", fimc_is_clocks[i]); |
160 | } | |
161 | } | |
162 | } | |
163 | ||
d265d9ac SN |
164 | static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index, |
165 | struct device_node *node) | |
9a761e43 | 166 | { |
d265d9ac | 167 | struct fimc_is_sensor *sensor = &is->sensor[index]; |
9a761e43 SN |
168 | u32 tmp = 0; |
169 | int ret; | |
170 | ||
d265d9ac SN |
171 | sensor->drvdata = fimc_is_sensor_get_drvdata(node); |
172 | if (!sensor->drvdata) { | |
173 | dev_err(&is->pdev->dev, "no driver data found for: %s\n", | |
174 | node->full_name); | |
175 | return -EINVAL; | |
176 | } | |
177 | ||
463b21fb | 178 | node = of_graph_get_next_endpoint(node, NULL); |
d265d9ac | 179 | if (!node) |
9a761e43 | 180 | return -ENXIO; |
d265d9ac | 181 | |
463b21fb | 182 | node = of_graph_get_remote_port(node); |
d265d9ac | 183 | if (!node) |
9a761e43 SN |
184 | return -ENXIO; |
185 | ||
186 | /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */ | |
d265d9ac SN |
187 | ret = of_property_read_u32(node, "reg", &tmp); |
188 | if (ret < 0) { | |
189 | dev_err(&is->pdev->dev, "reg property not found at: %s\n", | |
190 | node->full_name); | |
191 | return ret; | |
192 | } | |
9a761e43 | 193 | |
d265d9ac SN |
194 | sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0; |
195 | return 0; | |
9a761e43 SN |
196 | } |
197 | ||
198 | static int fimc_is_register_subdevs(struct fimc_is *is) | |
199 | { | |
d265d9ac SN |
200 | struct device_node *i2c_bus, *child; |
201 | int ret, index = 0; | |
9a761e43 SN |
202 | |
203 | ret = fimc_isp_subdev_create(&is->isp); | |
204 | if (ret < 0) | |
205 | return ret; | |
206 | ||
34947b8a SN |
207 | /* Initialize memory allocator context for the ISP DMA. */ |
208 | is->isp.alloc_ctx = is->alloc_ctx; | |
9a761e43 | 209 | |
d265d9ac SN |
210 | for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) { |
211 | for_each_available_child_of_node(i2c_bus, child) { | |
212 | ret = fimc_is_parse_sensor_config(is, index, child); | |
9a761e43 | 213 | |
d265d9ac SN |
214 | if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) { |
215 | of_node_put(child); | |
216 | return ret; | |
9a761e43 | 217 | } |
d265d9ac | 218 | index++; |
9a761e43 SN |
219 | } |
220 | } | |
221 | return 0; | |
9a761e43 SN |
222 | } |
223 | ||
224 | static int fimc_is_unregister_subdevs(struct fimc_is *is) | |
225 | { | |
226 | fimc_isp_subdev_destroy(&is->isp); | |
9a761e43 SN |
227 | return 0; |
228 | } | |
229 | ||
230 | static int fimc_is_load_setfile(struct fimc_is *is, char *file_name) | |
231 | { | |
232 | const struct firmware *fw; | |
233 | void *buf; | |
234 | int ret; | |
235 | ||
236 | ret = request_firmware(&fw, file_name, &is->pdev->dev); | |
237 | if (ret < 0) { | |
238 | dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret); | |
239 | return ret; | |
240 | } | |
241 | buf = is->memory.vaddr + is->setfile.base; | |
242 | memcpy(buf, fw->data, fw->size); | |
243 | fimc_is_mem_barrier(); | |
244 | is->setfile.size = fw->size; | |
245 | ||
246 | pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf); | |
247 | ||
248 | memcpy(is->fw.setfile_info, | |
249 | fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN, | |
250 | FIMC_IS_SETFILE_INFO_LEN - 1); | |
251 | ||
252 | is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0'; | |
253 | is->setfile.state = 1; | |
254 | ||
255 | pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n", | |
256 | is->setfile.base, fw->size); | |
257 | ||
258 | release_firmware(fw); | |
259 | return ret; | |
260 | } | |
261 | ||
262 | int fimc_is_cpu_set_power(struct fimc_is *is, int on) | |
263 | { | |
264 | unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT; | |
265 | ||
266 | if (on) { | |
267 | /* Disable watchdog */ | |
268 | mcuctl_write(0, is, REG_WDT_ISP); | |
269 | ||
270 | /* Cortex-A5 start address setting */ | |
271 | mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR); | |
272 | ||
273 | /* Enable and start Cortex-A5 */ | |
274 | pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION); | |
275 | pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION); | |
276 | } else { | |
277 | /* A5 power off */ | |
278 | pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION); | |
279 | pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION); | |
280 | ||
281 | while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) { | |
282 | if (timeout == 0) | |
283 | return -ETIME; | |
284 | timeout--; | |
285 | udelay(1); | |
286 | } | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | /* Wait until @bit of @is->state is set to @state in the interrupt handler. */ | |
293 | int fimc_is_wait_event(struct fimc_is *is, unsigned long bit, | |
294 | unsigned int state, unsigned int timeout) | |
295 | { | |
296 | ||
297 | int ret = wait_event_timeout(is->irq_queue, | |
298 | !state ^ test_bit(bit, &is->state), | |
299 | timeout); | |
300 | if (ret == 0) { | |
301 | dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__); | |
302 | return -ETIME; | |
303 | } | |
304 | return 0; | |
305 | } | |
306 | ||
307 | int fimc_is_start_firmware(struct fimc_is *is) | |
308 | { | |
309 | struct device *dev = &is->pdev->dev; | |
310 | int ret; | |
311 | ||
3cf138a6 SN |
312 | if (is->fw.f_w == NULL) { |
313 | dev_err(dev, "firmware is not loaded\n"); | |
314 | return -EINVAL; | |
315 | } | |
316 | ||
9a761e43 SN |
317 | memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size); |
318 | wmb(); | |
319 | ||
320 | ret = fimc_is_cpu_set_power(is, 1); | |
321 | if (ret < 0) | |
322 | return ret; | |
323 | ||
324 | ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1, | |
325 | msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT)); | |
326 | if (ret < 0) | |
327 | dev_err(dev, "FIMC-IS CPU power on failed\n"); | |
328 | ||
329 | return ret; | |
330 | } | |
331 | ||
332 | /* Allocate working memory for the FIMC-IS CPU. */ | |
333 | static int fimc_is_alloc_cpu_memory(struct fimc_is *is) | |
334 | { | |
335 | struct device *dev = &is->pdev->dev; | |
336 | ||
337 | is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE, | |
338 | &is->memory.paddr, GFP_KERNEL); | |
339 | if (is->memory.vaddr == NULL) | |
340 | return -ENOMEM; | |
341 | ||
342 | is->memory.size = FIMC_IS_CPU_MEM_SIZE; | |
343 | memset(is->memory.vaddr, 0, is->memory.size); | |
344 | ||
345 | dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr); | |
346 | ||
347 | if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) { | |
348 | dev_err(dev, "invalid firmware memory alignment: %#x\n", | |
349 | (u32)is->memory.paddr); | |
350 | dma_free_coherent(dev, is->memory.size, is->memory.vaddr, | |
351 | is->memory.paddr); | |
352 | return -EIO; | |
353 | } | |
354 | ||
355 | is->is_p_region = (struct is_region *)(is->memory.vaddr + | |
356 | FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE); | |
357 | ||
358 | is->is_dma_p_region = is->memory.paddr + | |
359 | FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE; | |
360 | ||
361 | is->is_shared_region = (struct is_share_region *)(is->memory.vaddr + | |
362 | FIMC_IS_SHARED_REGION_OFFSET); | |
363 | return 0; | |
364 | } | |
365 | ||
366 | static void fimc_is_free_cpu_memory(struct fimc_is *is) | |
367 | { | |
368 | struct device *dev = &is->pdev->dev; | |
369 | ||
404a90ab SN |
370 | if (is->memory.vaddr == NULL) |
371 | return; | |
372 | ||
9a761e43 SN |
373 | dma_free_coherent(dev, is->memory.size, is->memory.vaddr, |
374 | is->memory.paddr); | |
375 | } | |
376 | ||
377 | static void fimc_is_load_firmware(const struct firmware *fw, void *context) | |
378 | { | |
379 | struct fimc_is *is = context; | |
380 | struct device *dev = &is->pdev->dev; | |
381 | void *buf; | |
382 | int ret; | |
383 | ||
384 | if (fw == NULL) { | |
385 | dev_err(dev, "firmware request failed\n"); | |
386 | return; | |
387 | } | |
388 | mutex_lock(&is->lock); | |
389 | ||
390 | if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) { | |
7d4020c3 | 391 | dev_err(dev, "wrong firmware size: %zu\n", fw->size); |
9a761e43 SN |
392 | goto done; |
393 | } | |
394 | ||
395 | is->fw.size = fw->size; | |
396 | ||
397 | ret = fimc_is_alloc_cpu_memory(is); | |
398 | if (ret < 0) { | |
399 | dev_err(dev, "failed to allocate FIMC-IS CPU memory\n"); | |
400 | goto done; | |
401 | } | |
402 | ||
403 | memcpy(is->memory.vaddr, fw->data, fw->size); | |
404 | wmb(); | |
405 | ||
406 | /* Read firmware description. */ | |
407 | buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN); | |
408 | memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN); | |
409 | is->fw.info[FIMC_IS_FW_INFO_LEN] = 0; | |
410 | ||
411 | buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN); | |
412 | memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN); | |
413 | is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0; | |
414 | ||
415 | is->fw.state = 1; | |
416 | ||
417 | dev_info(dev, "loaded firmware: %s, rev. %s\n", | |
418 | is->fw.info, is->fw.version); | |
7d4020c3 | 419 | dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr); |
9a761e43 SN |
420 | |
421 | is->is_shared_region->chip_id = 0xe4412; | |
422 | is->is_shared_region->chip_rev_no = 1; | |
423 | ||
424 | fimc_is_mem_barrier(); | |
425 | ||
426 | /* | |
427 | * FIXME: The firmware is not being released for now, as it is | |
428 | * needed around for copying to the IS working memory every | |
429 | * time before the Cortex-A5 is restarted. | |
430 | */ | |
332b295d | 431 | release_firmware(is->fw.f_w); |
9a761e43 SN |
432 | is->fw.f_w = fw; |
433 | done: | |
434 | mutex_unlock(&is->lock); | |
435 | } | |
436 | ||
437 | static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name) | |
438 | { | |
439 | return request_firmware_nowait(THIS_MODULE, | |
440 | FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev, | |
441 | GFP_KERNEL, is, fimc_is_load_firmware); | |
442 | } | |
443 | ||
444 | /* General IS interrupt handler */ | |
445 | static void fimc_is_general_irq_handler(struct fimc_is *is) | |
446 | { | |
447 | is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10)); | |
448 | ||
449 | switch (is->i2h_cmd.cmd) { | |
450 | case IHC_GET_SENSOR_NUM: | |
451 | fimc_is_hw_get_params(is, 1); | |
452 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
453 | fimc_is_hw_set_sensor_num(is); | |
454 | pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]); | |
455 | break; | |
456 | case IHC_SET_FACE_MARK: | |
457 | case IHC_FRAME_DONE: | |
458 | fimc_is_hw_get_params(is, 2); | |
459 | break; | |
460 | case IHC_SET_SHOT_MARK: | |
461 | case IHC_AA_DONE: | |
462 | case IH_REPLY_DONE: | |
463 | fimc_is_hw_get_params(is, 3); | |
464 | break; | |
465 | case IH_REPLY_NOT_DONE: | |
466 | fimc_is_hw_get_params(is, 4); | |
467 | break; | |
468 | case IHC_NOT_READY: | |
469 | break; | |
470 | default: | |
471 | pr_info("unknown command: %#x\n", is->i2h_cmd.cmd); | |
472 | } | |
473 | ||
474 | fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL); | |
475 | ||
476 | switch (is->i2h_cmd.cmd) { | |
477 | case IHC_GET_SENSOR_NUM: | |
478 | fimc_is_hw_set_intgr0_gd0(is); | |
479 | set_bit(IS_ST_A5_PWR_ON, &is->state); | |
480 | break; | |
481 | ||
482 | case IHC_SET_SHOT_MARK: | |
483 | break; | |
484 | ||
485 | case IHC_SET_FACE_MARK: | |
486 | is->fd_header.count = is->i2h_cmd.args[0]; | |
487 | is->fd_header.index = is->i2h_cmd.args[1]; | |
488 | is->fd_header.offset = 0; | |
489 | break; | |
490 | ||
491 | case IHC_FRAME_DONE: | |
492 | break; | |
493 | ||
494 | case IHC_AA_DONE: | |
495 | pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0], | |
496 | is->i2h_cmd.args[1], is->i2h_cmd.args[2]); | |
497 | break; | |
498 | ||
499 | case IH_REPLY_DONE: | |
500 | pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]); | |
501 | ||
502 | switch (is->i2h_cmd.args[0]) { | |
503 | case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO: | |
504 | /* Get CAC margin */ | |
505 | set_bit(IS_ST_CHANGE_MODE, &is->state); | |
506 | is->isp.cac_margin_x = is->i2h_cmd.args[1]; | |
507 | is->isp.cac_margin_y = is->i2h_cmd.args[2]; | |
508 | pr_debug("CAC margin (x,y): (%d,%d)\n", | |
509 | is->isp.cac_margin_x, is->isp.cac_margin_y); | |
510 | break; | |
511 | ||
512 | case HIC_STREAM_ON: | |
513 | clear_bit(IS_ST_STREAM_OFF, &is->state); | |
514 | set_bit(IS_ST_STREAM_ON, &is->state); | |
515 | break; | |
516 | ||
517 | case HIC_STREAM_OFF: | |
518 | clear_bit(IS_ST_STREAM_ON, &is->state); | |
519 | set_bit(IS_ST_STREAM_OFF, &is->state); | |
520 | break; | |
521 | ||
522 | case HIC_SET_PARAMETER: | |
0e761b21 PC |
523 | is->config[is->config_index].p_region_index[0] = 0; |
524 | is->config[is->config_index].p_region_index[1] = 0; | |
9a761e43 SN |
525 | set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); |
526 | pr_debug("HIC_SET_PARAMETER\n"); | |
527 | break; | |
528 | ||
529 | case HIC_GET_PARAMETER: | |
530 | break; | |
531 | ||
532 | case HIC_SET_TUNE: | |
533 | break; | |
534 | ||
535 | case HIC_GET_STATUS: | |
536 | break; | |
537 | ||
538 | case HIC_OPEN_SENSOR: | |
539 | set_bit(IS_ST_OPEN_SENSOR, &is->state); | |
540 | pr_debug("data lanes: %d, settle line: %d\n", | |
541 | is->i2h_cmd.args[2], is->i2h_cmd.args[1]); | |
542 | break; | |
543 | ||
544 | case HIC_CLOSE_SENSOR: | |
545 | clear_bit(IS_ST_OPEN_SENSOR, &is->state); | |
546 | is->sensor_index = 0; | |
547 | break; | |
548 | ||
549 | case HIC_MSG_TEST: | |
550 | pr_debug("config MSG level completed\n"); | |
551 | break; | |
552 | ||
553 | case HIC_POWER_DOWN: | |
554 | clear_bit(IS_ST_PWR_SUBIP_ON, &is->state); | |
555 | break; | |
556 | ||
557 | case HIC_GET_SET_FILE_ADDR: | |
558 | is->setfile.base = is->i2h_cmd.args[1]; | |
559 | set_bit(IS_ST_SETFILE_LOADED, &is->state); | |
560 | break; | |
561 | ||
562 | case HIC_LOAD_SET_FILE: | |
563 | set_bit(IS_ST_SETFILE_LOADED, &is->state); | |
564 | break; | |
565 | } | |
566 | break; | |
567 | ||
568 | case IH_REPLY_NOT_DONE: | |
569 | pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0], | |
570 | is->i2h_cmd.args[1], | |
571 | fimc_is_strerr(is->i2h_cmd.args[1])); | |
572 | ||
573 | if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG) | |
574 | pr_err("IS_ERROR_TIME_OUT\n"); | |
575 | ||
576 | switch (is->i2h_cmd.args[1]) { | |
577 | case IS_ERROR_SET_PARAMETER: | |
578 | fimc_is_mem_barrier(); | |
579 | } | |
580 | ||
581 | switch (is->i2h_cmd.args[0]) { | |
582 | case HIC_SET_PARAMETER: | |
0e761b21 PC |
583 | is->config[is->config_index].p_region_index[0] = 0; |
584 | is->config[is->config_index].p_region_index[1] = 0; | |
9a761e43 SN |
585 | set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); |
586 | break; | |
587 | } | |
588 | break; | |
589 | ||
590 | case IHC_NOT_READY: | |
591 | pr_err("IS control sequence error: Not Ready\n"); | |
592 | break; | |
593 | } | |
594 | ||
595 | wake_up(&is->irq_queue); | |
596 | } | |
597 | ||
598 | static irqreturn_t fimc_is_irq_handler(int irq, void *priv) | |
599 | { | |
600 | struct fimc_is *is = priv; | |
601 | unsigned long flags; | |
602 | u32 status; | |
603 | ||
604 | spin_lock_irqsave(&is->slock, flags); | |
605 | status = mcuctl_read(is, MCUCTL_REG_INTSR1); | |
606 | ||
607 | if (status & (1UL << FIMC_IS_INT_GENERAL)) | |
608 | fimc_is_general_irq_handler(is); | |
609 | ||
610 | if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP)) | |
611 | fimc_isp_irq_handler(is); | |
612 | ||
613 | spin_unlock_irqrestore(&is->slock, flags); | |
614 | return IRQ_HANDLED; | |
615 | } | |
616 | ||
617 | static int fimc_is_hw_open_sensor(struct fimc_is *is, | |
618 | struct fimc_is_sensor *sensor) | |
619 | { | |
620 | struct sensor_open_extended *soe = (void *)&is->is_p_region->shared; | |
621 | ||
622 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
623 | ||
624 | soe->self_calibration_mode = 1; | |
625 | soe->actuator_type = 0; | |
626 | soe->mipi_lane_num = 0; | |
627 | soe->mclk = 0; | |
628 | soe->mipi_speed = 0; | |
629 | soe->fast_open_sensor = 0; | |
630 | soe->i2c_sclk = 88000000; | |
631 | ||
632 | fimc_is_mem_barrier(); | |
633 | ||
a13ddcae JA |
634 | /* |
635 | * Some user space use cases hang up here without this | |
636 | * empirically chosen delay. | |
637 | */ | |
638 | udelay(100); | |
639 | ||
9a761e43 SN |
640 | mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0)); |
641 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
642 | mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2)); | |
643 | mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3)); | |
644 | mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4)); | |
645 | ||
646 | fimc_is_hw_set_intgr0_gd0(is); | |
647 | ||
648 | return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1, | |
d265d9ac | 649 | sensor->drvdata->open_timeout); |
9a761e43 SN |
650 | } |
651 | ||
652 | ||
653 | int fimc_is_hw_initialize(struct fimc_is *is) | |
654 | { | |
3530ef0a | 655 | const int config_ids[] = { |
9a761e43 SN |
656 | IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO, |
657 | IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO | |
658 | }; | |
659 | struct device *dev = &is->pdev->dev; | |
660 | u32 prev_id; | |
661 | int i, ret; | |
662 | ||
d265d9ac SN |
663 | /* Sensor initialization. Only one sensor is currently supported. */ |
664 | ret = fimc_is_hw_open_sensor(is, &is->sensor[0]); | |
9a761e43 SN |
665 | if (ret < 0) |
666 | return ret; | |
667 | ||
668 | /* Get the setfile address. */ | |
669 | fimc_is_hw_get_setfile_addr(is); | |
670 | ||
671 | ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1, | |
672 | FIMC_IS_CONFIG_TIMEOUT); | |
673 | if (ret < 0) { | |
674 | dev_err(dev, "get setfile address timed out\n"); | |
675 | return ret; | |
676 | } | |
677 | pr_debug("setfile.base: %#x\n", is->setfile.base); | |
678 | ||
679 | /* Load the setfile. */ | |
680 | fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3); | |
681 | clear_bit(IS_ST_SETFILE_LOADED, &is->state); | |
682 | fimc_is_hw_load_setfile(is); | |
683 | ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1, | |
684 | FIMC_IS_CONFIG_TIMEOUT); | |
685 | if (ret < 0) { | |
686 | dev_err(dev, "loading setfile timed out\n"); | |
687 | return ret; | |
688 | } | |
689 | ||
690 | pr_debug("setfile: base: %#x, size: %d\n", | |
691 | is->setfile.base, is->setfile.size); | |
692 | pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info); | |
693 | ||
694 | /* Check magic number. */ | |
695 | if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] != | |
696 | FIMC_IS_MAGIC_NUMBER) { | |
697 | dev_err(dev, "magic number error!\n"); | |
698 | return -EIO; | |
699 | } | |
700 | ||
7d4020c3 MCC |
701 | pr_debug("shared region: %pad, parameter region: %pad\n", |
702 | &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET, | |
703 | &is->is_dma_p_region); | |
9a761e43 SN |
704 | |
705 | is->setfile.sub_index = 0; | |
706 | ||
707 | /* Stream off. */ | |
708 | fimc_is_hw_stream_off(is); | |
709 | ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1, | |
710 | FIMC_IS_CONFIG_TIMEOUT); | |
711 | if (ret < 0) { | |
712 | dev_err(dev, "stream off timeout\n"); | |
713 | return ret; | |
714 | } | |
715 | ||
716 | /* Preserve previous mode. */ | |
3530ef0a | 717 | prev_id = is->config_index; |
9a761e43 SN |
718 | |
719 | /* Set initial parameter values. */ | |
3530ef0a SN |
720 | for (i = 0; i < ARRAY_SIZE(config_ids); i++) { |
721 | is->config_index = config_ids[i]; | |
9a761e43 SN |
722 | fimc_is_set_initial_params(is); |
723 | ret = fimc_is_itf_s_param(is, true); | |
724 | if (ret < 0) { | |
3530ef0a | 725 | is->config_index = prev_id; |
9a761e43 SN |
726 | return ret; |
727 | } | |
728 | } | |
3530ef0a | 729 | is->config_index = prev_id; |
9a761e43 SN |
730 | |
731 | set_bit(IS_ST_INIT_DONE, &is->state); | |
732 | dev_info(dev, "initialization sequence completed (%d)\n", | |
3530ef0a | 733 | is->config_index); |
9a761e43 SN |
734 | return 0; |
735 | } | |
736 | ||
737 | static int fimc_is_log_show(struct seq_file *s, void *data) | |
738 | { | |
739 | struct fimc_is *is = s->private; | |
740 | const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET; | |
741 | ||
742 | if (is->memory.vaddr == NULL) { | |
743 | dev_err(&is->pdev->dev, "firmware memory is not initialized\n"); | |
744 | return -EIO; | |
745 | } | |
746 | ||
747 | seq_printf(s, "%s\n", buf); | |
748 | return 0; | |
749 | } | |
750 | ||
751 | static int fimc_is_debugfs_open(struct inode *inode, struct file *file) | |
752 | { | |
753 | return single_open(file, fimc_is_log_show, inode->i_private); | |
754 | } | |
755 | ||
756 | static const struct file_operations fimc_is_debugfs_fops = { | |
757 | .open = fimc_is_debugfs_open, | |
758 | .read = seq_read, | |
759 | .llseek = seq_lseek, | |
760 | .release = single_release, | |
761 | }; | |
762 | ||
763 | static void fimc_is_debugfs_remove(struct fimc_is *is) | |
764 | { | |
450f5f54 | 765 | debugfs_remove_recursive(is->debugfs_entry); |
9a761e43 SN |
766 | is->debugfs_entry = NULL; |
767 | } | |
768 | ||
769 | static int fimc_is_debugfs_create(struct fimc_is *is) | |
770 | { | |
771 | struct dentry *dentry; | |
772 | ||
773 | is->debugfs_entry = debugfs_create_dir("fimc_is", NULL); | |
774 | ||
775 | dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry, | |
776 | is, &fimc_is_debugfs_fops); | |
777 | if (!dentry) | |
778 | fimc_is_debugfs_remove(is); | |
779 | ||
780 | return is->debugfs_entry == NULL ? -EIO : 0; | |
781 | } | |
782 | ||
283bf33b SN |
783 | static int fimc_is_runtime_resume(struct device *dev); |
784 | static int fimc_is_runtime_suspend(struct device *dev); | |
785 | ||
9a761e43 SN |
786 | static int fimc_is_probe(struct platform_device *pdev) |
787 | { | |
788 | struct device *dev = &pdev->dev; | |
789 | struct fimc_is *is; | |
790 | struct resource res; | |
791 | struct device_node *node; | |
792 | int ret; | |
793 | ||
794 | is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL); | |
795 | if (!is) | |
796 | return -ENOMEM; | |
797 | ||
798 | is->pdev = pdev; | |
799 | is->isp.pdev = pdev; | |
800 | ||
801 | init_waitqueue_head(&is->irq_queue); | |
802 | spin_lock_init(&is->slock); | |
803 | mutex_init(&is->lock); | |
804 | ||
805 | ret = of_address_to_resource(dev->of_node, 0, &res); | |
806 | if (ret < 0) | |
807 | return ret; | |
808 | ||
809 | is->regs = devm_ioremap_resource(dev, &res); | |
810 | if (IS_ERR(is->regs)) | |
811 | return PTR_ERR(is->regs); | |
812 | ||
813 | node = of_get_child_by_name(dev->of_node, "pmu"); | |
814 | if (!node) | |
815 | return -ENODEV; | |
816 | ||
817 | is->pmu_regs = of_iomap(node, 0); | |
818 | if (!is->pmu_regs) | |
819 | return -ENOMEM; | |
820 | ||
821 | is->irq = irq_of_parse_and_map(dev->of_node, 0); | |
9a7a848d | 822 | if (!is->irq) { |
9a761e43 | 823 | dev_err(dev, "no irq found\n"); |
9a7a848d | 824 | return -EINVAL; |
9a761e43 SN |
825 | } |
826 | ||
827 | ret = fimc_is_get_clocks(is); | |
828 | if (ret < 0) | |
829 | return ret; | |
830 | ||
831 | platform_set_drvdata(pdev, is); | |
832 | ||
833 | ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is); | |
834 | if (ret < 0) { | |
835 | dev_err(dev, "irq request failed\n"); | |
836 | goto err_clk; | |
837 | } | |
838 | pm_runtime_enable(dev); | |
b34f51fa | 839 | |
283bf33b SN |
840 | if (!pm_runtime_enabled(dev)) { |
841 | ret = fimc_is_runtime_resume(dev); | |
842 | if (ret < 0) | |
843 | goto err_irq; | |
844 | } | |
845 | ||
722a860e | 846 | ret = pm_runtime_get_sync(dev); |
9a761e43 | 847 | if (ret < 0) |
283bf33b | 848 | goto err_pm; |
9a761e43 | 849 | |
9a761e43 SN |
850 | is->alloc_ctx = vb2_dma_contig_init_ctx(dev); |
851 | if (IS_ERR(is->alloc_ctx)) { | |
852 | ret = PTR_ERR(is->alloc_ctx); | |
283bf33b | 853 | goto err_pm; |
9a761e43 SN |
854 | } |
855 | /* | |
856 | * Register FIMC-IS V4L2 subdevs to this driver. The video nodes | |
857 | * will be created within the subdev's registered() callback. | |
858 | */ | |
859 | ret = fimc_is_register_subdevs(is); | |
860 | if (ret < 0) | |
861 | goto err_vb; | |
862 | ||
863 | ret = fimc_is_debugfs_create(is); | |
864 | if (ret < 0) | |
865 | goto err_sd; | |
866 | ||
867 | ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME); | |
868 | if (ret < 0) | |
869 | goto err_dfs; | |
870 | ||
722a860e SN |
871 | pm_runtime_put_sync(dev); |
872 | ||
9a761e43 SN |
873 | dev_dbg(dev, "FIMC-IS registered successfully\n"); |
874 | return 0; | |
875 | ||
876 | err_dfs: | |
877 | fimc_is_debugfs_remove(is); | |
9a761e43 SN |
878 | err_sd: |
879 | fimc_is_unregister_subdevs(is); | |
da8cec30 SN |
880 | err_vb: |
881 | vb2_dma_contig_cleanup_ctx(is->alloc_ctx); | |
283bf33b SN |
882 | err_pm: |
883 | if (!pm_runtime_enabled(dev)) | |
884 | fimc_is_runtime_suspend(dev); | |
9a761e43 SN |
885 | err_irq: |
886 | free_irq(is->irq, is); | |
9a761e43 SN |
887 | err_clk: |
888 | fimc_is_put_clocks(is); | |
889 | return ret; | |
890 | } | |
891 | ||
892 | static int fimc_is_runtime_resume(struct device *dev) | |
893 | { | |
894 | struct fimc_is *is = dev_get_drvdata(dev); | |
722a860e | 895 | int ret; |
9a761e43 | 896 | |
722a860e SN |
897 | ret = fimc_is_setup_clocks(is); |
898 | if (ret) | |
899 | return ret; | |
9a761e43 SN |
900 | |
901 | return fimc_is_enable_clocks(is); | |
902 | } | |
903 | ||
904 | static int fimc_is_runtime_suspend(struct device *dev) | |
905 | { | |
906 | struct fimc_is *is = dev_get_drvdata(dev); | |
907 | ||
722a860e | 908 | fimc_is_disable_clocks(is); |
9a761e43 SN |
909 | return 0; |
910 | } | |
911 | ||
912 | #ifdef CONFIG_PM_SLEEP | |
913 | static int fimc_is_resume(struct device *dev) | |
914 | { | |
915 | /* TODO: */ | |
916 | return 0; | |
917 | } | |
918 | ||
919 | static int fimc_is_suspend(struct device *dev) | |
920 | { | |
921 | struct fimc_is *is = dev_get_drvdata(dev); | |
922 | ||
923 | /* TODO: */ | |
924 | if (test_bit(IS_ST_A5_PWR_ON, &is->state)) | |
925 | return -EBUSY; | |
926 | ||
927 | return 0; | |
928 | } | |
929 | #endif /* CONFIG_PM_SLEEP */ | |
930 | ||
931 | static int fimc_is_remove(struct platform_device *pdev) | |
932 | { | |
283bf33b SN |
933 | struct device *dev = &pdev->dev; |
934 | struct fimc_is *is = dev_get_drvdata(dev); | |
9a761e43 | 935 | |
283bf33b SN |
936 | pm_runtime_disable(dev); |
937 | pm_runtime_set_suspended(dev); | |
938 | if (!pm_runtime_status_suspended(dev)) | |
939 | fimc_is_runtime_suspend(dev); | |
9a761e43 SN |
940 | free_irq(is->irq, is); |
941 | fimc_is_unregister_subdevs(is); | |
942 | vb2_dma_contig_cleanup_ctx(is->alloc_ctx); | |
943 | fimc_is_put_clocks(is); | |
944 | fimc_is_debugfs_remove(is); | |
332b295d | 945 | release_firmware(is->fw.f_w); |
9a761e43 SN |
946 | fimc_is_free_cpu_memory(is); |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | static const struct of_device_id fimc_is_of_match[] = { | |
952 | { .compatible = "samsung,exynos4212-fimc-is" }, | |
953 | { /* sentinel */ }, | |
954 | }; | |
955 | MODULE_DEVICE_TABLE(of, fimc_is_of_match); | |
956 | ||
957 | static const struct dev_pm_ops fimc_is_pm_ops = { | |
958 | SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume) | |
959 | SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume, | |
960 | NULL) | |
961 | }; | |
962 | ||
963 | static struct platform_driver fimc_is_driver = { | |
964 | .probe = fimc_is_probe, | |
965 | .remove = fimc_is_remove, | |
966 | .driver = { | |
967 | .of_match_table = fimc_is_of_match, | |
968 | .name = FIMC_IS_DRV_NAME, | |
9a761e43 SN |
969 | .pm = &fimc_is_pm_ops, |
970 | } | |
971 | }; | |
972 | ||
973 | static int fimc_is_module_init(void) | |
974 | { | |
975 | int ret; | |
976 | ||
9a761e43 SN |
977 | ret = fimc_is_register_i2c_driver(); |
978 | if (ret < 0) | |
d265d9ac | 979 | return ret; |
9a761e43 SN |
980 | |
981 | ret = platform_driver_register(&fimc_is_driver); | |
9a761e43 | 982 | |
d265d9ac SN |
983 | if (ret < 0) |
984 | fimc_is_unregister_i2c_driver(); | |
985 | ||
9a761e43 SN |
986 | return ret; |
987 | } | |
988 | ||
989 | static void fimc_is_module_exit(void) | |
990 | { | |
0e30c7e1 SN |
991 | fimc_is_unregister_i2c_driver(); |
992 | platform_driver_unregister(&fimc_is_driver); | |
9a761e43 SN |
993 | } |
994 | ||
995 | module_init(fimc_is_module_init); | |
996 | module_exit(fimc_is_module_exit); | |
997 | ||
998 | MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME); | |
999 | MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>"); | |
1000 | MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); | |
fdb49827 | 1001 | MODULE_LICENSE("GPL v2"); |