Commit | Line | Data |
---|---|---|
5f3cc447 | 1 | /* |
3a3f9449 | 2 | * Samsung S5P/EXYNOS4 SoC series camera interface (camera capture) driver |
5f3cc447 | 3 | * |
0c9204d3 SN |
4 | * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd. |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
5f3cc447 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
5f3cc447 SN |
14 | #include <linux/types.h> |
15 | #include <linux/errno.h> | |
16 | #include <linux/bug.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/device.h> | |
e9e21083 | 19 | #include <linux/pm_runtime.h> |
5f3cc447 SN |
20 | #include <linux/list.h> |
21 | #include <linux/slab.h> | |
5f3cc447 SN |
22 | |
23 | #include <linux/videodev2.h> | |
24 | #include <media/v4l2-device.h> | |
25 | #include <media/v4l2-ioctl.h> | |
26 | #include <media/v4l2-mem2mem.h> | |
c139990e | 27 | #include <media/videobuf2-v4l2.h> |
2dab38e2 | 28 | #include <media/videobuf2-dma-contig.h> |
5f3cc447 | 29 | |
4403106d | 30 | #include "common.h" |
5f3cc447 | 31 | #include "fimc-core.h" |
c83a1ff0 | 32 | #include "fimc-reg.h" |
4403106d | 33 | #include "media-dev.h" |
5f3cc447 | 34 | |
bb7c276e | 35 | static int fimc_capture_hw_init(struct fimc_dev *fimc) |
9e803a04 | 36 | { |
88fa8311 | 37 | struct fimc_source_info *si = &fimc->vid_cap.source_config; |
9e803a04 | 38 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; |
88fa8311 | 39 | int ret; |
9e803a04 | 40 | unsigned long flags; |
9e803a04 | 41 | |
88fa8311 | 42 | if (ctx == NULL || ctx->s_frame.fmt == NULL) |
9e803a04 SN |
43 | return -EINVAL; |
44 | ||
88fa8311 SN |
45 | if (si->fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK) { |
46 | ret = fimc_hw_camblk_cfg_writeback(fimc); | |
47 | if (ret < 0) | |
48 | return ret; | |
49 | } | |
9e803a04 SN |
50 | |
51 | spin_lock_irqsave(&fimc->slock, flags); | |
52 | fimc_prepare_dma_offset(ctx, &ctx->d_frame); | |
53 | fimc_set_yuv_order(ctx); | |
54 | ||
88fa8311 SN |
55 | fimc_hw_set_camera_polarity(fimc, si); |
56 | fimc_hw_set_camera_type(fimc, si); | |
57 | fimc_hw_set_camera_source(fimc, si); | |
9e803a04 SN |
58 | fimc_hw_set_camera_offset(fimc, &ctx->s_frame); |
59 | ||
60 | ret = fimc_set_scaler_info(ctx); | |
61 | if (!ret) { | |
62 | fimc_hw_set_input_path(ctx); | |
63 | fimc_hw_set_prescaler(ctx); | |
64 | fimc_hw_set_mainscaler(ctx); | |
65 | fimc_hw_set_target_format(ctx); | |
66 | fimc_hw_set_rotation(ctx); | |
9448ab7d | 67 | fimc_hw_set_effect(ctx); |
9e803a04 SN |
68 | fimc_hw_set_output_path(ctx); |
69 | fimc_hw_set_out_dma(ctx); | |
e80cb1fa | 70 | if (fimc->drv_data->alpha_color) |
dafb9c70 | 71 | fimc_hw_set_rgb_alpha(ctx); |
237e0265 | 72 | clear_bit(ST_CAPT_APPLY_CFG, &fimc->state); |
9e803a04 SN |
73 | } |
74 | spin_unlock_irqrestore(&fimc->slock, flags); | |
75 | return ret; | |
76 | } | |
77 | ||
bb7c276e SN |
78 | /* |
79 | * Reinitialize the driver so it is ready to start the streaming again. | |
80 | * Set fimc->state to indicate stream off and the hardware shut down state. | |
81 | * If not suspending (@suspend is false), return any buffers to videobuf2. | |
82 | * Otherwise put any owned buffers onto the pending buffers queue, so they | |
83 | * can be re-spun when the device is being resumed. Also perform FIMC | |
84 | * software reset and disable streaming on the whole pipeline if required. | |
85 | */ | |
3e4748d8 | 86 | static int fimc_capture_state_cleanup(struct fimc_dev *fimc, bool suspend) |
5f3cc447 | 87 | { |
bd323e28 | 88 | struct fimc_vid_cap *cap = &fimc->vid_cap; |
2dab38e2 | 89 | struct fimc_vid_buffer *buf; |
bd323e28 | 90 | unsigned long flags; |
3e4748d8 | 91 | bool streaming; |
5f3cc447 SN |
92 | |
93 | spin_lock_irqsave(&fimc->slock, flags); | |
3e4748d8 | 94 | streaming = fimc->state & (1 << ST_CAPT_ISP_STREAM); |
5f3cc447 | 95 | |
3e4748d8 SN |
96 | fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_SHUT | |
97 | 1 << ST_CAPT_STREAM | 1 << ST_CAPT_ISP_STREAM); | |
aa333122 SN |
98 | if (suspend) |
99 | fimc->state |= (1 << ST_CAPT_SUSPENDED); | |
100 | else | |
3e4748d8 | 101 | fimc->state &= ~(1 << ST_CAPT_PEND | 1 << ST_CAPT_SUSPENDED); |
2dab38e2 | 102 | |
3e4748d8 SN |
103 | /* Release unused buffers */ |
104 | while (!suspend && !list_empty(&cap->pending_buf_q)) { | |
0295202c | 105 | buf = fimc_pending_queue_pop(cap); |
2d700715 | 106 | vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); |
2dab38e2 | 107 | } |
3e4748d8 | 108 | /* If suspending put unused buffers onto pending queue */ |
2dab38e2 | 109 | while (!list_empty(&cap->active_buf_q)) { |
0295202c | 110 | buf = fimc_active_queue_pop(cap); |
3e4748d8 SN |
111 | if (suspend) |
112 | fimc_pending_queue_add(cap, buf); | |
113 | else | |
2d700715 | 114 | vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); |
2dab38e2 | 115 | } |
2c1bb62e SN |
116 | |
117 | fimc_hw_reset(fimc); | |
118 | cap->buf_index = 0; | |
119 | ||
5f3cc447 | 120 | spin_unlock_irqrestore(&fimc->slock, flags); |
4db5e27e | 121 | |
3e4748d8 | 122 | if (streaming) |
403dfbec | 123 | return fimc_pipeline_call(&cap->ve, set_stream, 0); |
4db5e27e SN |
124 | else |
125 | return 0; | |
bd323e28 MS |
126 | } |
127 | ||
3e4748d8 | 128 | static int fimc_stop_capture(struct fimc_dev *fimc, bool suspend) |
bd323e28 | 129 | { |
bd323e28 MS |
130 | unsigned long flags; |
131 | ||
132 | if (!fimc_capture_active(fimc)) | |
133 | return 0; | |
134 | ||
135 | spin_lock_irqsave(&fimc->slock, flags); | |
136 | set_bit(ST_CAPT_SHUT, &fimc->state); | |
137 | fimc_deactivate_capture(fimc); | |
138 | spin_unlock_irqrestore(&fimc->slock, flags); | |
139 | ||
140 | wait_event_timeout(fimc->irq_queue, | |
141 | !test_bit(ST_CAPT_SHUT, &fimc->state), | |
3e4748d8 | 142 | (2*HZ/10)); /* 200 ms */ |
5f3cc447 | 143 | |
3e4748d8 | 144 | return fimc_capture_state_cleanup(fimc, suspend); |
5f3cc447 SN |
145 | } |
146 | ||
237e0265 SN |
147 | /** |
148 | * fimc_capture_config_update - apply the camera interface configuration | |
3b060ba0 | 149 | * @ctx: FIMC capture context |
237e0265 SN |
150 | * |
151 | * To be called from within the interrupt handler with fimc.slock | |
152 | * spinlock held. It updates the camera pixel crop, rotation and | |
153 | * image flip in H/W. | |
154 | */ | |
97d97422 | 155 | static int fimc_capture_config_update(struct fimc_ctx *ctx) |
237e0265 SN |
156 | { |
157 | struct fimc_dev *fimc = ctx->fimc_dev; | |
158 | int ret; | |
159 | ||
237e0265 | 160 | fimc_hw_set_camera_offset(fimc, &ctx->s_frame); |
efb13c3d | 161 | |
237e0265 | 162 | ret = fimc_set_scaler_info(ctx); |
efb13c3d SN |
163 | if (ret) |
164 | return ret; | |
165 | ||
166 | fimc_hw_set_prescaler(ctx); | |
167 | fimc_hw_set_mainscaler(ctx); | |
168 | fimc_hw_set_target_format(ctx); | |
169 | fimc_hw_set_rotation(ctx); | |
9448ab7d | 170 | fimc_hw_set_effect(ctx); |
efb13c3d SN |
171 | fimc_prepare_dma_offset(ctx, &ctx->d_frame); |
172 | fimc_hw_set_out_dma(ctx); | |
e80cb1fa | 173 | if (fimc->drv_data->alpha_color) |
efb13c3d SN |
174 | fimc_hw_set_rgb_alpha(ctx); |
175 | ||
176 | clear_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
237e0265 SN |
177 | return ret; |
178 | } | |
bd323e28 | 179 | |
97d97422 SN |
180 | void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf) |
181 | { | |
182 | struct fimc_vid_cap *cap = &fimc->vid_cap; | |
403dfbec SN |
183 | struct fimc_pipeline *p = to_fimc_pipeline(cap->ve.pipe); |
184 | struct v4l2_subdev *csis = p->subdevs[IDX_CSIS]; | |
14783d25 | 185 | struct fimc_frame *f = &cap->ctx->d_frame; |
97d97422 | 186 | struct fimc_vid_buffer *v_buf; |
97d97422 SN |
187 | |
188 | if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) { | |
189 | wake_up(&fimc->irq_queue); | |
190 | goto done; | |
191 | } | |
192 | ||
193 | if (!list_empty(&cap->active_buf_q) && | |
194 | test_bit(ST_CAPT_RUN, &fimc->state) && deq_buf) { | |
97d97422 SN |
195 | v_buf = fimc_active_queue_pop(cap); |
196 | ||
d6dd645e | 197 | v_buf->vb.vb2_buf.timestamp = ktime_get_ns(); |
2d700715 | 198 | v_buf->vb.sequence = cap->frame_count++; |
97d97422 | 199 | |
2d700715 | 200 | vb2_buffer_done(&v_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); |
97d97422 SN |
201 | } |
202 | ||
203 | if (!list_empty(&cap->pending_buf_q)) { | |
204 | ||
205 | v_buf = fimc_pending_queue_pop(cap); | |
206 | fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index); | |
207 | v_buf->index = cap->buf_index; | |
208 | ||
209 | /* Move the buffer to the capture active queue */ | |
210 | fimc_active_queue_add(cap, v_buf); | |
211 | ||
212 | dbg("next frame: %d, done frame: %d", | |
213 | fimc_hw_get_frame_index(fimc), v_buf->index); | |
214 | ||
215 | if (++cap->buf_index >= FIMC_MAX_OUT_BUFS) | |
216 | cap->buf_index = 0; | |
217 | } | |
14783d25 SN |
218 | /* |
219 | * Set up a buffer at MIPI-CSIS if current image format | |
220 | * requires the frame embedded data capture. | |
221 | */ | |
222 | if (f->fmt->mdataplanes && !list_empty(&cap->active_buf_q)) { | |
223 | unsigned int plane = ffs(f->fmt->mdataplanes) - 1; | |
224 | unsigned int size = f->payload[plane]; | |
225 | s32 index = fimc_hw_get_frame_index(fimc); | |
226 | void *vaddr; | |
227 | ||
228 | list_for_each_entry(v_buf, &cap->active_buf_q, list) { | |
229 | if (v_buf->index != index) | |
230 | continue; | |
2d700715 | 231 | vaddr = vb2_plane_vaddr(&v_buf->vb.vb2_buf, plane); |
14783d25 SN |
232 | v4l2_subdev_call(csis, video, s_rx_buffer, |
233 | vaddr, &size); | |
234 | break; | |
235 | } | |
236 | } | |
97d97422 SN |
237 | |
238 | if (cap->active_buf_cnt == 0) { | |
239 | if (deq_buf) | |
240 | clear_bit(ST_CAPT_RUN, &fimc->state); | |
241 | ||
242 | if (++cap->buf_index >= FIMC_MAX_OUT_BUFS) | |
243 | cap->buf_index = 0; | |
244 | } else { | |
245 | set_bit(ST_CAPT_RUN, &fimc->state); | |
246 | } | |
247 | ||
bb7c276e SN |
248 | if (test_bit(ST_CAPT_APPLY_CFG, &fimc->state)) |
249 | fimc_capture_config_update(cap->ctx); | |
97d97422 SN |
250 | done: |
251 | if (cap->active_buf_cnt == 1) { | |
252 | fimc_deactivate_capture(fimc); | |
253 | clear_bit(ST_CAPT_STREAM, &fimc->state); | |
254 | } | |
255 | ||
256 | dbg("frame: %d, active_buf_cnt: %d", | |
257 | fimc_hw_get_frame_index(fimc), cap->active_buf_cnt); | |
258 | } | |
259 | ||
260 | ||
bd323e28 | 261 | static int start_streaming(struct vb2_queue *q, unsigned int count) |
2dab38e2 SN |
262 | { |
263 | struct fimc_ctx *ctx = q->drv_priv; | |
264 | struct fimc_dev *fimc = ctx->fimc_dev; | |
9e803a04 | 265 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; |
bd323e28 | 266 | int min_bufs; |
2dab38e2 SN |
267 | int ret; |
268 | ||
9e803a04 | 269 | vid_cap->frame_count = 0; |
8ec737ff | 270 | |
bb7c276e SN |
271 | ret = fimc_capture_hw_init(fimc); |
272 | if (ret) { | |
273 | fimc_capture_state_cleanup(fimc, false); | |
274 | return ret; | |
275 | } | |
2dab38e2 | 276 | |
2dab38e2 SN |
277 | set_bit(ST_CAPT_PEND, &fimc->state); |
278 | ||
bd323e28 MS |
279 | min_bufs = fimc->vid_cap.reqbufs_count > 1 ? 2 : 1; |
280 | ||
4db5e27e SN |
281 | if (vid_cap->active_buf_cnt >= min_bufs && |
282 | !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) { | |
bd323e28 MS |
283 | fimc_activate_capture(ctx); |
284 | ||
4db5e27e | 285 | if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state)) |
403dfbec | 286 | return fimc_pipeline_call(&vid_cap->ve, set_stream, 1); |
4db5e27e SN |
287 | } |
288 | ||
2dab38e2 SN |
289 | return 0; |
290 | } | |
291 | ||
e37559b2 | 292 | static void stop_streaming(struct vb2_queue *q) |
2dab38e2 SN |
293 | { |
294 | struct fimc_ctx *ctx = q->drv_priv; | |
295 | struct fimc_dev *fimc = ctx->fimc_dev; | |
2dab38e2 | 296 | |
4ecbf5d1 | 297 | if (!fimc_capture_active(fimc)) |
e37559b2 | 298 | return; |
2dab38e2 | 299 | |
e37559b2 | 300 | fimc_stop_capture(fimc, false); |
2dab38e2 SN |
301 | } |
302 | ||
e9e21083 SN |
303 | int fimc_capture_suspend(struct fimc_dev *fimc) |
304 | { | |
3e4748d8 SN |
305 | bool suspend = fimc_capture_busy(fimc); |
306 | ||
307 | int ret = fimc_stop_capture(fimc, suspend); | |
308 | if (ret) | |
309 | return ret; | |
403dfbec | 310 | return fimc_pipeline_call(&fimc->vid_cap.ve, close); |
e9e21083 SN |
311 | } |
312 | ||
3e4748d8 SN |
313 | static void buffer_queue(struct vb2_buffer *vb); |
314 | ||
e9e21083 SN |
315 | int fimc_capture_resume(struct fimc_dev *fimc) |
316 | { | |
3e4748d8 | 317 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; |
bc7584b0 | 318 | struct exynos_video_entity *ve = &vid_cap->ve; |
3e4748d8 SN |
319 | struct fimc_vid_buffer *buf; |
320 | int i; | |
321 | ||
322 | if (!test_and_clear_bit(ST_CAPT_SUSPENDED, &fimc->state)) | |
323 | return 0; | |
324 | ||
325 | INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q); | |
326 | vid_cap->buf_index = 0; | |
403dfbec | 327 | fimc_pipeline_call(ve, open, &ve->vdev.entity, false); |
bb7c276e | 328 | fimc_capture_hw_init(fimc); |
3e4748d8 SN |
329 | |
330 | clear_bit(ST_CAPT_SUSPENDED, &fimc->state); | |
331 | ||
332 | for (i = 0; i < vid_cap->reqbufs_count; i++) { | |
333 | if (list_empty(&vid_cap->pending_buf_q)) | |
334 | break; | |
335 | buf = fimc_pending_queue_pop(vid_cap); | |
2d700715 | 336 | buffer_queue(&buf->vb.vb2_buf); |
3e4748d8 | 337 | } |
e9e21083 | 338 | return 0; |
3e4748d8 | 339 | |
e9e21083 SN |
340 | } |
341 | ||
df9ecb0c | 342 | static int queue_setup(struct vb2_queue *vq, |
fc714e70 | 343 | unsigned int *num_buffers, unsigned int *num_planes, |
36c0f8b3 | 344 | unsigned int sizes[], struct device *alloc_devs[]) |
2dab38e2 SN |
345 | { |
346 | struct fimc_ctx *ctx = vq->drv_priv; | |
63746be5 SN |
347 | struct fimc_frame *frame = &ctx->d_frame; |
348 | struct fimc_fmt *fmt = frame->fmt; | |
df9ecb0c | 349 | unsigned long wh = frame->f_width * frame->f_height; |
ef7af59b | 350 | int i; |
2dab38e2 | 351 | |
63746be5 | 352 | if (fmt == NULL) |
2dab38e2 SN |
353 | return -EINVAL; |
354 | ||
df9ecb0c HV |
355 | if (*num_planes) { |
356 | if (*num_planes != fmt->memplanes) | |
357 | return -EINVAL; | |
2548fee6 | 358 | for (i = 0; i < *num_planes; i++) |
df9ecb0c HV |
359 | if (sizes[i] < (wh * fmt->depth[i]) / 8) |
360 | return -EINVAL; | |
df9ecb0c HV |
361 | return 0; |
362 | } | |
363 | ||
ef7af59b | 364 | *num_planes = fmt->memplanes; |
2dab38e2 | 365 | |
ef7af59b | 366 | for (i = 0; i < fmt->memplanes; i++) { |
63746be5 | 367 | unsigned int size = (wh * fmt->depth[i]) / 8; |
df9ecb0c HV |
368 | |
369 | if (fimc_fmt_is_user_defined(fmt->color)) | |
14783d25 | 370 | sizes[i] = frame->payload[i]; |
63746be5 | 371 | else |
d547ab66 | 372 | sizes[i] = max_t(u32, size, frame->payload[i]); |
ef7af59b | 373 | } |
2dab38e2 | 374 | |
ef7af59b | 375 | return 0; |
2dab38e2 SN |
376 | } |
377 | ||
2dab38e2 SN |
378 | static int buffer_prepare(struct vb2_buffer *vb) |
379 | { | |
380 | struct vb2_queue *vq = vb->vb2_queue; | |
381 | struct fimc_ctx *ctx = vq->drv_priv; | |
2dab38e2 SN |
382 | int i; |
383 | ||
4db5e27e | 384 | if (ctx->d_frame.fmt == NULL) |
ef7af59b | 385 | return -EINVAL; |
2dab38e2 | 386 | |
ef7af59b | 387 | for (i = 0; i < ctx->d_frame.fmt->memplanes; i++) { |
4db5e27e | 388 | unsigned long size = ctx->d_frame.payload[i]; |
2dab38e2 SN |
389 | |
390 | if (vb2_plane_size(vb, i) < size) { | |
bc7584b0 | 391 | v4l2_err(&ctx->fimc_dev->vid_cap.ve.vdev, |
30c9939d | 392 | "User buffer too small (%ld < %ld)\n", |
2dab38e2 SN |
393 | vb2_plane_size(vb, i), size); |
394 | return -EINVAL; | |
395 | } | |
2dab38e2 SN |
396 | vb2_set_plane_payload(vb, i, size); |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static void buffer_queue(struct vb2_buffer *vb) | |
403 | { | |
2d700715 | 404 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
2dab38e2 | 405 | struct fimc_vid_buffer *buf |
2d700715 | 406 | = container_of(vbuf, struct fimc_vid_buffer, vb); |
4db5e27e SN |
407 | struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); |
408 | struct fimc_dev *fimc = ctx->fimc_dev; | |
2dab38e2 | 409 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; |
bc7584b0 | 410 | struct exynos_video_entity *ve = &vid_cap->ve; |
2dab38e2 | 411 | unsigned long flags; |
8ec737ff | 412 | int min_bufs; |
2dab38e2 SN |
413 | |
414 | spin_lock_irqsave(&fimc->slock, flags); | |
2d700715 | 415 | fimc_prepare_addr(ctx, &buf->vb.vb2_buf, &ctx->d_frame, &buf->paddr); |
8ec737ff | 416 | |
3e4748d8 SN |
417 | if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) && |
418 | !test_bit(ST_CAPT_STREAM, &fimc->state) && | |
419 | vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) { | |
8ec737ff SK |
420 | /* Setup the buffer directly for processing. */ |
421 | int buf_id = (vid_cap->reqbufs_count == 1) ? -1 : | |
422 | vid_cap->buf_index; | |
2dab38e2 | 423 | |
8ec737ff SK |
424 | fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id); |
425 | buf->index = vid_cap->buf_index; | |
0295202c | 426 | fimc_active_queue_add(vid_cap, buf); |
2dab38e2 | 427 | |
8ec737ff SK |
428 | if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS) |
429 | vid_cap->buf_index = 0; | |
430 | } else { | |
431 | fimc_pending_queue_add(vid_cap, buf); | |
2dab38e2 | 432 | } |
8ec737ff SK |
433 | |
434 | min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1; | |
435 | ||
4db5e27e | 436 | |
bd323e28 MS |
437 | if (vb2_is_streaming(&vid_cap->vbq) && |
438 | vid_cap->active_buf_cnt >= min_bufs && | |
4db5e27e | 439 | !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) { |
76323e50 AH |
440 | int ret; |
441 | ||
8ec737ff | 442 | fimc_activate_capture(ctx); |
4db5e27e | 443 | spin_unlock_irqrestore(&fimc->slock, flags); |
8ec737ff | 444 | |
76323e50 AH |
445 | if (test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state)) |
446 | return; | |
447 | ||
403dfbec | 448 | ret = fimc_pipeline_call(ve, set_stream, 1); |
76323e50 | 449 | if (ret < 0) |
bc7584b0 | 450 | v4l2_err(&ve->vdev, "stream on failed: %d\n", ret); |
4db5e27e SN |
451 | return; |
452 | } | |
2dab38e2 SN |
453 | spin_unlock_irqrestore(&fimc->slock, flags); |
454 | } | |
455 | ||
b7b361f0 | 456 | static const struct vb2_ops fimc_capture_qops = { |
2dab38e2 SN |
457 | .queue_setup = queue_setup, |
458 | .buf_prepare = buffer_prepare, | |
459 | .buf_queue = buffer_queue, | |
c444914a SN |
460 | .wait_prepare = vb2_ops_wait_prepare, |
461 | .wait_finish = vb2_ops_wait_finish, | |
2dab38e2 SN |
462 | .start_streaming = start_streaming, |
463 | .stop_streaming = stop_streaming, | |
464 | }; | |
465 | ||
237e0265 SN |
466 | static int fimc_capture_set_default_format(struct fimc_dev *fimc); |
467 | ||
5f3cc447 SN |
468 | static int fimc_capture_open(struct file *file) |
469 | { | |
470 | struct fimc_dev *fimc = video_drvdata(file); | |
4403106d SN |
471 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
472 | struct exynos_video_entity *ve = &vc->ve; | |
c2d430af | 473 | int ret = -EBUSY; |
5f3cc447 SN |
474 | |
475 | dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state); | |
476 | ||
740ad921 | 477 | mutex_lock(&fimc->lock); |
c2d430af | 478 | |
5f3cc447 | 479 | if (fimc_m2m_active(fimc)) |
c2d430af | 480 | goto unlock; |
5f3cc447 | 481 | |
3e4748d8 | 482 | set_bit(ST_CAPT_BUSY, &fimc->state); |
e3fc82e8 SN |
483 | ret = pm_runtime_get_sync(&fimc->pdev->dev); |
484 | if (ret < 0) | |
c2d430af | 485 | goto unlock; |
4db5e27e | 486 | |
e3fc82e8 | 487 | ret = v4l2_fh_open(file); |
c2d430af | 488 | if (ret) { |
4bd728a1 | 489 | pm_runtime_put_sync(&fimc->pdev->dev); |
c2d430af SN |
490 | goto unlock; |
491 | } | |
e3fc82e8 | 492 | |
c444914a | 493 | if (v4l2_fh_is_singular_file(file)) { |
42625fdf SN |
494 | fimc_md_graph_lock(ve); |
495 | ||
403dfbec SN |
496 | ret = fimc_pipeline_call(ve, open, &ve->vdev.entity, true); |
497 | ||
4403106d SN |
498 | if (ret == 0 && vc->user_subdev_api && vc->inh_sensor_ctrls) { |
499 | /* | |
500 | * Recreate controls of the the video node to drop | |
501 | * any controls inherited from the sensor subdev. | |
502 | */ | |
503 | fimc_ctrls_delete(vc->ctx); | |
504 | ||
505 | ret = fimc_ctrls_create(vc->ctx); | |
506 | if (ret == 0) | |
507 | vc->inh_sensor_ctrls = false; | |
508 | } | |
42625fdf SN |
509 | if (ret == 0) |
510 | ve->vdev.entity.use_count++; | |
511 | ||
512 | fimc_md_graph_unlock(ve); | |
e3fc82e8 | 513 | |
7536b424 SN |
514 | if (ret == 0) |
515 | ret = fimc_capture_set_default_format(fimc); | |
516 | ||
c2d430af SN |
517 | if (ret < 0) { |
518 | clear_bit(ST_CAPT_BUSY, &fimc->state); | |
519 | pm_runtime_put_sync(&fimc->pdev->dev); | |
c2d430af SN |
520 | v4l2_fh_release(file); |
521 | } | |
522 | } | |
523 | unlock: | |
524 | mutex_unlock(&fimc->lock); | |
131b6c61 | 525 | return ret; |
5f3cc447 SN |
526 | } |
527 | ||
c444914a | 528 | static int fimc_capture_release(struct file *file) |
5f3cc447 SN |
529 | { |
530 | struct fimc_dev *fimc = video_drvdata(file); | |
9ea89e2b | 531 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
42625fdf | 532 | bool close = v4l2_fh_is_singular_file(file); |
c2d430af | 533 | int ret; |
5f3cc447 | 534 | |
5f3cc447 SN |
535 | dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state); |
536 | ||
ba6b372c | 537 | mutex_lock(&fimc->lock); |
c2d430af | 538 | |
42625fdf | 539 | if (close && vc->streaming) { |
20b85227 | 540 | media_pipeline_stop(&vc->ve.vdev.entity); |
42625fdf SN |
541 | vc->streaming = false; |
542 | } | |
543 | ||
1380f575 | 544 | ret = _vb2_fop_release(file, NULL); |
42625fdf SN |
545 | |
546 | if (close) { | |
3e4748d8 | 547 | clear_bit(ST_CAPT_BUSY, &fimc->state); |
403dfbec | 548 | fimc_pipeline_call(&vc->ve, close); |
3e4748d8 | 549 | clear_bit(ST_CAPT_SUSPENDED, &fimc->state); |
42625fdf SN |
550 | |
551 | fimc_md_graph_lock(&vc->ve); | |
552 | vc->ve.vdev.entity.use_count--; | |
553 | fimc_md_graph_unlock(&vc->ve); | |
5f3cc447 SN |
554 | } |
555 | ||
4bd728a1 | 556 | pm_runtime_put_sync(&fimc->pdev->dev); |
c2d430af SN |
557 | mutex_unlock(&fimc->lock); |
558 | ||
559 | return ret; | |
5f3cc447 SN |
560 | } |
561 | ||
5f3cc447 SN |
562 | static const struct v4l2_file_operations fimc_capture_fops = { |
563 | .owner = THIS_MODULE, | |
564 | .open = fimc_capture_open, | |
c444914a SN |
565 | .release = fimc_capture_release, |
566 | .poll = vb2_fop_poll, | |
5f3cc447 | 567 | .unlocked_ioctl = video_ioctl2, |
c444914a | 568 | .mmap = vb2_fop_mmap, |
5f3cc447 SN |
569 | }; |
570 | ||
237e0265 SN |
571 | /* |
572 | * Format and crop negotiation helpers | |
573 | */ | |
574 | ||
575 | static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx, | |
576 | u32 *width, u32 *height, | |
577 | u32 *code, u32 *fourcc, int pad) | |
578 | { | |
579 | bool rotation = ctx->rotation == 90 || ctx->rotation == 270; | |
580 | struct fimc_dev *fimc = ctx->fimc_dev; | |
405f230c SN |
581 | const struct fimc_variant *var = fimc->variant; |
582 | const struct fimc_pix_limit *pl = var->pix_limit; | |
237e0265 SN |
583 | struct fimc_frame *dst = &ctx->d_frame; |
584 | u32 depth, min_w, max_w, min_h, align_h = 3; | |
585 | u32 mask = FMT_FLAGS_CAM; | |
586 | struct fimc_fmt *ffmt; | |
587 | ||
14783d25 | 588 | /* Conversion from/to JPEG or User Defined format is not supported */ |
237e0265 | 589 | if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE && |
14783d25 SN |
590 | fimc_fmt_is_user_defined(ctx->s_frame.fmt->color)) |
591 | *code = ctx->s_frame.fmt->mbus_code; | |
237e0265 | 592 | |
88fa8311 | 593 | if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad == FIMC_SD_PAD_SOURCE) |
237e0265 SN |
594 | mask |= FMT_FLAGS_M2M; |
595 | ||
88fa8311 SN |
596 | if (pad == FIMC_SD_PAD_SINK_FIFO) |
597 | mask = FMT_FLAGS_WRITEBACK; | |
598 | ||
237e0265 SN |
599 | ffmt = fimc_find_format(fourcc, code, mask, 0); |
600 | if (WARN_ON(!ffmt)) | |
601 | return NULL; | |
88fa8311 | 602 | |
237e0265 SN |
603 | if (code) |
604 | *code = ffmt->mbus_code; | |
605 | if (fourcc) | |
606 | *fourcc = ffmt->fourcc; | |
607 | ||
88fa8311 | 608 | if (pad != FIMC_SD_PAD_SOURCE) { |
14783d25 | 609 | max_w = fimc_fmt_is_user_defined(ffmt->color) ? |
237e0265 SN |
610 | pl->scaler_dis_w : pl->scaler_en_w; |
611 | /* Apply the camera input interface pixel constraints */ | |
612 | v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4, | |
613 | height, max_t(u32, *height, 32), | |
614 | FIMC_CAMIF_MAX_HEIGHT, | |
14783d25 SN |
615 | fimc_fmt_is_user_defined(ffmt->color) ? |
616 | 3 : 1, | |
237e0265 SN |
617 | 0); |
618 | return ffmt; | |
619 | } | |
620 | /* Can't scale or crop in transparent (JPEG) transfer mode */ | |
14783d25 | 621 | if (fimc_fmt_is_user_defined(ffmt->color)) { |
237e0265 SN |
622 | *width = ctx->s_frame.f_width; |
623 | *height = ctx->s_frame.f_height; | |
624 | return ffmt; | |
625 | } | |
626 | /* Apply the scaler and the output DMA constraints */ | |
627 | max_w = rotation ? pl->out_rot_en_w : pl->out_rot_dis_w; | |
fed07f84 SN |
628 | if (ctx->state & FIMC_COMPOSE) { |
629 | min_w = dst->offs_h + dst->width; | |
630 | min_h = dst->offs_v + dst->height; | |
631 | } else { | |
632 | min_w = var->min_out_pixsize; | |
633 | min_h = var->min_out_pixsize; | |
634 | } | |
9c63afcb | 635 | if (var->min_vsize_align == 1 && !rotation) |
237e0265 SN |
636 | align_h = fimc_fmt_is_rgb(ffmt->color) ? 0 : 1; |
637 | ||
638 | depth = fimc_get_format_depth(ffmt); | |
639 | v4l_bound_align_image(width, min_w, max_w, | |
640 | ffs(var->min_out_pixsize) - 1, | |
641 | height, min_h, FIMC_CAMIF_MAX_HEIGHT, | |
642 | align_h, | |
643 | 64/(ALIGN(depth, 8))); | |
644 | ||
645 | dbg("pad%d: code: 0x%x, %dx%d. dst fmt: %dx%d", | |
646 | pad, code ? *code : 0, *width, *height, | |
647 | dst->f_width, dst->f_height); | |
648 | ||
649 | return ffmt; | |
650 | } | |
651 | ||
fed07f84 SN |
652 | static void fimc_capture_try_selection(struct fimc_ctx *ctx, |
653 | struct v4l2_rect *r, | |
654 | int target) | |
237e0265 SN |
655 | { |
656 | bool rotate = ctx->rotation == 90 || ctx->rotation == 270; | |
657 | struct fimc_dev *fimc = ctx->fimc_dev; | |
405f230c SN |
658 | const struct fimc_variant *var = fimc->variant; |
659 | const struct fimc_pix_limit *pl = var->pix_limit; | |
237e0265 SN |
660 | struct fimc_frame *sink = &ctx->s_frame; |
661 | u32 max_w, max_h, min_w = 0, min_h = 0, min_sz; | |
662 | u32 align_sz = 0, align_h = 4; | |
663 | u32 max_sc_h, max_sc_v; | |
664 | ||
665 | /* In JPEG transparent transfer mode cropping is not supported */ | |
14783d25 | 666 | if (fimc_fmt_is_user_defined(ctx->d_frame.fmt->color)) { |
237e0265 SN |
667 | r->width = sink->f_width; |
668 | r->height = sink->f_height; | |
669 | r->left = r->top = 0; | |
670 | return; | |
671 | } | |
c1334823 | 672 | if (target == V4L2_SEL_TGT_COMPOSE) { |
237e0265 SN |
673 | if (ctx->rotation != 90 && ctx->rotation != 270) |
674 | align_h = 1; | |
675 | max_sc_h = min(SCALER_MAX_HRATIO, 1 << (ffs(sink->width) - 3)); | |
676 | max_sc_v = min(SCALER_MAX_VRATIO, 1 << (ffs(sink->height) - 1)); | |
677 | min_sz = var->min_out_pixsize; | |
678 | } else { | |
679 | u32 depth = fimc_get_format_depth(sink->fmt); | |
680 | align_sz = 64/ALIGN(depth, 8); | |
681 | min_sz = var->min_inp_pixsize; | |
682 | min_w = min_h = min_sz; | |
683 | max_sc_h = max_sc_v = 1; | |
684 | } | |
685 | /* | |
fed07f84 | 686 | * For the compose rectangle the following constraints must be met: |
237e0265 SN |
687 | * - it must fit in the sink pad format rectangle (f_width/f_height); |
688 | * - maximum downscaling ratio is 64; | |
689 | * - maximum crop size depends if the rotator is used or not; | |
690 | * - the sink pad format width/height must be 4 multiple of the | |
691 | * prescaler ratios determined by sink pad size and source pad crop, | |
692 | * the prescaler ratio is returned by fimc_get_scaler_factor(). | |
693 | */ | |
694 | max_w = min_t(u32, | |
695 | rotate ? pl->out_rot_en_w : pl->out_rot_dis_w, | |
696 | rotate ? sink->f_height : sink->f_width); | |
697 | max_h = min_t(u32, FIMC_CAMIF_MAX_HEIGHT, sink->f_height); | |
fed07f84 | 698 | |
c1334823 | 699 | if (target == V4L2_SEL_TGT_COMPOSE) { |
237e0265 SN |
700 | min_w = min_t(u32, max_w, sink->f_width / max_sc_h); |
701 | min_h = min_t(u32, max_h, sink->f_height / max_sc_v); | |
702 | if (rotate) { | |
703 | swap(max_sc_h, max_sc_v); | |
704 | swap(min_w, min_h); | |
705 | } | |
706 | } | |
707 | v4l_bound_align_image(&r->width, min_w, max_w, ffs(min_sz) - 1, | |
708 | &r->height, min_h, max_h, align_h, | |
709 | align_sz); | |
fed07f84 | 710 | /* Adjust left/top if crop/compose rectangle is out of bounds */ |
237e0265 SN |
711 | r->left = clamp_t(u32, r->left, 0, sink->f_width - r->width); |
712 | r->top = clamp_t(u32, r->top, 0, sink->f_height - r->height); | |
713 | r->left = round_down(r->left, var->hor_offs_align); | |
714 | ||
fed07f84 SN |
715 | dbg("target %#x: (%d,%d)/%dx%d, sink fmt: %dx%d", |
716 | target, r->left, r->top, r->width, r->height, | |
237e0265 SN |
717 | sink->f_width, sink->f_height); |
718 | } | |
719 | ||
720 | /* | |
721 | * The video node ioctl operations | |
722 | */ | |
aceb59ed | 723 | static int fimc_cap_querycap(struct file *file, void *priv, |
5f3cc447 SN |
724 | struct v4l2_capability *cap) |
725 | { | |
e578588e | 726 | struct fimc_dev *fimc = video_drvdata(file); |
5f3cc447 | 727 | |
aceb59ed SN |
728 | __fimc_vidioc_querycap(&fimc->pdev->dev, cap, V4L2_CAP_STREAMING | |
729 | V4L2_CAP_VIDEO_CAPTURE_MPLANE); | |
5f3cc447 SN |
730 | return 0; |
731 | } | |
732 | ||
cf52df8a SN |
733 | static int fimc_cap_enum_fmt_mplane(struct file *file, void *priv, |
734 | struct v4l2_fmtdesc *f) | |
735 | { | |
736 | struct fimc_fmt *fmt; | |
737 | ||
738 | fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM | FMT_FLAGS_M2M, | |
739 | f->index); | |
740 | if (!fmt) | |
741 | return -EINVAL; | |
742 | strncpy(f->description, fmt->name, sizeof(f->description) - 1); | |
743 | f->pixelformat = fmt->fourcc; | |
27ffaeb0 | 744 | if (fmt->fourcc == MEDIA_BUS_FMT_JPEG_1X8) |
cf52df8a SN |
745 | f->flags |= V4L2_FMT_FLAG_COMPRESSED; |
746 | return 0; | |
747 | } | |
748 | ||
47800bc4 SN |
749 | static struct media_entity *fimc_pipeline_get_head(struct media_entity *me) |
750 | { | |
751 | struct media_pad *pad = &me->pads[0]; | |
752 | ||
753 | while (!(pad->flags & MEDIA_PAD_FL_SOURCE)) { | |
1bddf1b3 | 754 | pad = media_entity_remote_pad(pad); |
47800bc4 SN |
755 | if (!pad) |
756 | break; | |
757 | me = pad->entity; | |
758 | pad = &me->pads[0]; | |
759 | } | |
760 | ||
761 | return me; | |
762 | } | |
763 | ||
237e0265 SN |
764 | /** |
765 | * fimc_pipeline_try_format - negotiate and/or set formats at pipeline | |
766 | * elements | |
767 | * @ctx: FIMC capture context | |
768 | * @tfmt: media bus format to try/set on subdevs | |
769 | * @fmt_id: fimc pixel format id corresponding to returned @tfmt (output) | |
770 | * @set: true to set format on subdevs, false to try only | |
771 | */ | |
772 | static int fimc_pipeline_try_format(struct fimc_ctx *ctx, | |
773 | struct v4l2_mbus_framefmt *tfmt, | |
774 | struct fimc_fmt **fmt_id, | |
775 | bool set) | |
776 | { | |
777 | struct fimc_dev *fimc = ctx->fimc_dev; | |
403dfbec SN |
778 | struct fimc_pipeline *p = to_fimc_pipeline(fimc->vid_cap.ve.pipe); |
779 | struct v4l2_subdev *sd = p->subdevs[IDX_SENSOR]; | |
237e0265 SN |
780 | struct v4l2_subdev_format sfmt; |
781 | struct v4l2_mbus_framefmt *mf = &sfmt.format; | |
47800bc4 SN |
782 | struct media_entity *me; |
783 | struct fimc_fmt *ffmt; | |
784 | struct media_pad *pad; | |
785 | int ret, i = 1; | |
786 | u32 fcc; | |
237e0265 SN |
787 | |
788 | if (WARN_ON(!sd || !tfmt)) | |
789 | return -EINVAL; | |
5f3cc447 | 790 | |
237e0265 SN |
791 | memset(&sfmt, 0, sizeof(sfmt)); |
792 | sfmt.format = *tfmt; | |
237e0265 | 793 | sfmt.which = set ? V4L2_SUBDEV_FORMAT_ACTIVE : V4L2_SUBDEV_FORMAT_TRY; |
47800bc4 SN |
794 | |
795 | me = fimc_pipeline_get_head(&sd->entity); | |
796 | ||
237e0265 SN |
797 | while (1) { |
798 | ffmt = fimc_find_format(NULL, mf->code != 0 ? &mf->code : NULL, | |
799 | FMT_FLAGS_CAM, i++); | |
800 | if (ffmt == NULL) { | |
801 | /* | |
802 | * Notify user-space if common pixel code for | |
803 | * host and sensor does not exist. | |
804 | */ | |
805 | return -EINVAL; | |
806 | } | |
807 | mf->code = tfmt->code = ffmt->mbus_code; | |
5f3cc447 | 808 | |
47800bc4 SN |
809 | /* set format on all pipeline subdevs */ |
810 | while (me != &fimc->vid_cap.subdev.entity) { | |
811 | sd = media_entity_to_v4l2_subdev(me); | |
812 | ||
813 | sfmt.pad = 0; | |
814 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &sfmt); | |
815 | if (ret) | |
816 | return ret; | |
817 | ||
818 | if (me->pads[0].flags & MEDIA_PAD_FL_SINK) { | |
819 | sfmt.pad = me->num_pads - 1; | |
820 | mf->code = tfmt->code; | |
821 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, | |
822 | &sfmt); | |
823 | if (ret) | |
824 | return ret; | |
825 | } | |
826 | ||
1bddf1b3 | 827 | pad = media_entity_remote_pad(&me->pads[sfmt.pad]); |
47800bc4 SN |
828 | if (!pad) |
829 | return -EINVAL; | |
830 | me = pad->entity; | |
237e0265 | 831 | } |
5f3cc447 | 832 | |
47800bc4 SN |
833 | if (mf->code != tfmt->code) |
834 | continue; | |
835 | ||
836 | fcc = ffmt->fourcc; | |
837 | tfmt->width = mf->width; | |
838 | tfmt->height = mf->height; | |
839 | ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height, | |
88fa8311 | 840 | NULL, &fcc, FIMC_SD_PAD_SINK_CAM); |
47800bc4 SN |
841 | ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height, |
842 | NULL, &fcc, FIMC_SD_PAD_SOURCE); | |
843 | if (ffmt && ffmt->mbus_code) | |
844 | mf->code = ffmt->mbus_code; | |
845 | if (mf->width != tfmt->width || mf->height != tfmt->height) | |
846 | continue; | |
847 | tfmt->code = mf->code; | |
848 | break; | |
237e0265 | 849 | } |
5f3cc447 | 850 | |
237e0265 SN |
851 | if (fmt_id && ffmt) |
852 | *fmt_id = ffmt; | |
853 | *tfmt = *mf; | |
5f3cc447 | 854 | |
237e0265 SN |
855 | return 0; |
856 | } | |
5f3cc447 | 857 | |
14783d25 SN |
858 | /** |
859 | * fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters | |
860 | * @sensor: pointer to the sensor subdev | |
861 | * @plane_fmt: provides plane sizes corresponding to the frame layout entries | |
3b060ba0 | 862 | * @num_planes: number of planes |
14783d25 SN |
863 | * @try: true to set the frame parameters, false to query only |
864 | * | |
865 | * This function is used by this driver only for compressed/blob data formats. | |
866 | */ | |
867 | static int fimc_get_sensor_frame_desc(struct v4l2_subdev *sensor, | |
868 | struct v4l2_plane_pix_format *plane_fmt, | |
869 | unsigned int num_planes, bool try) | |
870 | { | |
871 | struct v4l2_mbus_frame_desc fd; | |
872 | int i, ret; | |
1c9f5bd7 | 873 | int pad; |
14783d25 SN |
874 | |
875 | for (i = 0; i < num_planes; i++) | |
876 | fd.entry[i].length = plane_fmt[i].sizeimage; | |
877 | ||
1c9f5bd7 | 878 | pad = sensor->entity.num_pads - 1; |
14783d25 | 879 | if (try) |
1c9f5bd7 | 880 | ret = v4l2_subdev_call(sensor, pad, set_frame_desc, pad, &fd); |
14783d25 | 881 | else |
1c9f5bd7 | 882 | ret = v4l2_subdev_call(sensor, pad, get_frame_desc, pad, &fd); |
14783d25 SN |
883 | |
884 | if (ret < 0) | |
885 | return ret; | |
886 | ||
887 | if (num_planes != fd.num_entries) | |
888 | return -EINVAL; | |
889 | ||
890 | for (i = 0; i < num_planes; i++) | |
891 | plane_fmt[i].sizeimage = fd.entry[i].length; | |
892 | ||
893 | if (fd.entry[0].length > FIMC_MAX_JPEG_BUF_SIZE) { | |
894 | v4l2_err(sensor->v4l2_dev, "Unsupported buffer size: %u\n", | |
895 | fd.entry[0].length); | |
896 | ||
897 | return -EINVAL; | |
898 | } | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
e578588e SN |
903 | static int fimc_cap_g_fmt_mplane(struct file *file, void *fh, |
904 | struct v4l2_format *f) | |
905 | { | |
906 | struct fimc_dev *fimc = video_drvdata(file); | |
e578588e | 907 | |
fa8880be SN |
908 | __fimc_get_format(&fimc->vid_cap.ctx->d_frame, f); |
909 | return 0; | |
e578588e SN |
910 | } |
911 | ||
7536b424 SN |
912 | /* |
913 | * Try or set format on the fimc.X.capture video node and additionally | |
914 | * on the whole pipeline if @try is false. | |
915 | * Locking: the caller must _not_ hold the graph mutex. | |
916 | */ | |
917 | static int __video_try_or_set_format(struct fimc_dev *fimc, | |
918 | struct v4l2_format *f, bool try, | |
919 | struct fimc_fmt **inp_fmt, | |
920 | struct fimc_fmt **out_fmt) | |
e578588e | 921 | { |
237e0265 | 922 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; |
7536b424 SN |
923 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
924 | struct exynos_video_entity *ve = &vc->ve; | |
925 | struct fimc_ctx *ctx = vc->ctx; | |
926 | unsigned int width = 0, height = 0; | |
740ad921 SN |
927 | int ret = 0; |
928 | ||
7536b424 | 929 | /* Pre-configure format at the camera input interface, for JPEG only */ |
14783d25 | 930 | if (fimc_jpeg_fourcc(pix->pixelformat)) { |
237e0265 SN |
931 | fimc_capture_try_format(ctx, &pix->width, &pix->height, |
932 | NULL, &pix->pixelformat, | |
88fa8311 | 933 | FIMC_SD_PAD_SINK_CAM); |
7536b424 SN |
934 | if (try) { |
935 | width = pix->width; | |
936 | height = pix->height; | |
937 | } else { | |
938 | ctx->s_frame.f_width = pix->width; | |
939 | ctx->s_frame.f_height = pix->height; | |
940 | } | |
237e0265 | 941 | } |
7536b424 SN |
942 | |
943 | /* Try the format at the scaler and the DMA output */ | |
944 | *out_fmt = fimc_capture_try_format(ctx, &pix->width, &pix->height, | |
945 | NULL, &pix->pixelformat, | |
946 | FIMC_SD_PAD_SOURCE); | |
947 | if (*out_fmt == NULL) | |
42625fdf | 948 | return -EINVAL; |
237e0265 | 949 | |
7536b424 SN |
950 | /* Restore image width/height for JPEG (no resizing supported). */ |
951 | if (try && fimc_jpeg_fourcc(pix->pixelformat)) { | |
952 | pix->width = width; | |
953 | pix->height = height; | |
954 | } | |
955 | ||
956 | /* Try to match format at the host and the sensor */ | |
957 | if (!vc->user_subdev_api) { | |
958 | struct v4l2_mbus_framefmt mbus_fmt; | |
959 | struct v4l2_mbus_framefmt *mf; | |
960 | ||
961 | mf = try ? &mbus_fmt : &fimc->vid_cap.ci_fmt; | |
962 | ||
963 | mf->code = (*out_fmt)->mbus_code; | |
964 | mf->width = pix->width; | |
965 | mf->height = pix->height; | |
42625fdf SN |
966 | |
967 | fimc_md_graph_lock(ve); | |
7536b424 | 968 | ret = fimc_pipeline_try_format(ctx, mf, inp_fmt, try); |
42625fdf SN |
969 | fimc_md_graph_unlock(ve); |
970 | ||
7536b424 SN |
971 | if (ret < 0) |
972 | return ret; | |
973 | ||
974 | pix->width = mf->width; | |
975 | pix->height = mf->height; | |
237e0265 | 976 | } |
e578588e | 977 | |
7536b424 SN |
978 | fimc_adjust_mplane_format(*out_fmt, pix->width, pix->height, pix); |
979 | ||
980 | if ((*out_fmt)->flags & FMT_FLAGS_COMPRESSED) { | |
981 | struct v4l2_subdev *sensor; | |
14783d25 | 982 | |
403dfbec SN |
983 | fimc_md_graph_lock(ve); |
984 | ||
985 | sensor = __fimc_md_get_subdev(ve->pipe, IDX_SENSOR); | |
986 | if (sensor) | |
987 | fimc_get_sensor_frame_desc(sensor, pix->plane_fmt, | |
7536b424 | 988 | (*out_fmt)->memplanes, try); |
403dfbec SN |
989 | else |
990 | ret = -EPIPE; | |
991 | ||
992 | fimc_md_graph_unlock(ve); | |
993 | } | |
14783d25 | 994 | |
740ad921 | 995 | return ret; |
e578588e SN |
996 | } |
997 | ||
7536b424 SN |
998 | static int fimc_cap_try_fmt_mplane(struct file *file, void *fh, |
999 | struct v4l2_format *f) | |
1000 | { | |
1001 | struct fimc_dev *fimc = video_drvdata(file); | |
1002 | struct fimc_fmt *out_fmt = NULL, *inp_fmt = NULL; | |
1003 | ||
1004 | return __video_try_or_set_format(fimc, f, true, &inp_fmt, &out_fmt); | |
1005 | } | |
1006 | ||
14783d25 SN |
1007 | static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx, |
1008 | enum fimc_color_fmt color) | |
ee7160e5 | 1009 | { |
14783d25 SN |
1010 | bool jpeg = fimc_fmt_is_user_defined(color); |
1011 | ||
ee7160e5 SN |
1012 | ctx->scaler.enabled = !jpeg; |
1013 | fimc_ctrls_activate(ctx, !jpeg); | |
1014 | ||
1015 | if (jpeg) | |
1016 | set_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state); | |
1017 | else | |
1018 | clear_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state); | |
1019 | } | |
1020 | ||
740ad921 SN |
1021 | static int __fimc_capture_set_format(struct fimc_dev *fimc, |
1022 | struct v4l2_format *f) | |
5f3cc447 | 1023 | { |
7536b424 SN |
1024 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
1025 | struct fimc_ctx *ctx = vc->ctx; | |
237e0265 | 1026 | struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; |
237e0265 | 1027 | struct fimc_frame *ff = &ctx->d_frame; |
7536b424 | 1028 | struct fimc_fmt *inp_fmt = NULL; |
237e0265 | 1029 | int ret, i; |
5f3cc447 | 1030 | |
237e0265 | 1031 | if (vb2_is_busy(&fimc->vid_cap.vbq)) |
ef7af59b | 1032 | return -EBUSY; |
5f3cc447 | 1033 | |
7536b424 SN |
1034 | ret = __video_try_or_set_format(fimc, f, false, &inp_fmt, &ff->fmt); |
1035 | if (ret < 0) | |
1036 | return ret; | |
dafb9c70 SN |
1037 | |
1038 | /* Update RGB Alpha control state and value range */ | |
1039 | fimc_alpha_ctrl_update(ctx); | |
1040 | ||
fa8880be SN |
1041 | for (i = 0; i < ff->fmt->memplanes; i++) { |
1042 | ff->bytesperline[i] = pix->plane_fmt[i].bytesperline; | |
d547ab66 | 1043 | ff->payload[i] = pix->plane_fmt[i].sizeimage; |
fa8880be | 1044 | } |
237e0265 SN |
1045 | |
1046 | set_frame_bounds(ff, pix->width, pix->height); | |
1047 | /* Reset the composition rectangle if not yet configured */ | |
fed07f84 | 1048 | if (!(ctx->state & FIMC_COMPOSE)) |
237e0265 SN |
1049 | set_frame_crop(ff, 0, 0, pix->width, pix->height); |
1050 | ||
14783d25 | 1051 | fimc_capture_mark_jpeg_xfer(ctx, ff->fmt->color); |
ee7160e5 | 1052 | |
237e0265 | 1053 | /* Reset cropping and set format at the camera interface input */ |
7536b424 SN |
1054 | if (!vc->user_subdev_api) { |
1055 | ctx->s_frame.fmt = inp_fmt; | |
237e0265 SN |
1056 | set_frame_bounds(&ctx->s_frame, pix->width, pix->height); |
1057 | set_frame_crop(&ctx->s_frame, 0, 0, pix->width, pix->height); | |
045030fa | 1058 | } |
ef7af59b | 1059 | |
237e0265 SN |
1060 | return ret; |
1061 | } | |
5f3cc447 | 1062 | |
237e0265 SN |
1063 | static int fimc_cap_s_fmt_mplane(struct file *file, void *priv, |
1064 | struct v4l2_format *f) | |
1065 | { | |
1066 | struct fimc_dev *fimc = video_drvdata(file); | |
740ad921 | 1067 | |
7536b424 | 1068 | return __fimc_capture_set_format(fimc, f); |
5f3cc447 SN |
1069 | } |
1070 | ||
1071 | static int fimc_cap_enum_input(struct file *file, void *priv, | |
3e002182 | 1072 | struct v4l2_input *i) |
5f3cc447 | 1073 | { |
e578588e | 1074 | struct fimc_dev *fimc = video_drvdata(file); |
403dfbec SN |
1075 | struct exynos_video_entity *ve = &fimc->vid_cap.ve; |
1076 | struct v4l2_subdev *sd; | |
5f3cc447 | 1077 | |
3e002182 | 1078 | if (i->index != 0) |
5f3cc447 SN |
1079 | return -EINVAL; |
1080 | ||
5f3cc447 | 1081 | i->type = V4L2_INPUT_TYPE_CAMERA; |
403dfbec SN |
1082 | fimc_md_graph_lock(ve); |
1083 | sd = __fimc_md_get_subdev(ve->pipe, IDX_SENSOR); | |
1084 | fimc_md_graph_unlock(ve); | |
1085 | ||
4db5e27e SN |
1086 | if (sd) |
1087 | strlcpy(i->name, sd->name, sizeof(i->name)); | |
403dfbec | 1088 | |
5f3cc447 SN |
1089 | return 0; |
1090 | } | |
1091 | ||
3e002182 | 1092 | static int fimc_cap_s_input(struct file *file, void *priv, unsigned int i) |
5f3cc447 | 1093 | { |
3e002182 | 1094 | return i == 0 ? i : -EINVAL; |
5f3cc447 SN |
1095 | } |
1096 | ||
3e002182 | 1097 | static int fimc_cap_g_input(struct file *file, void *priv, unsigned int *i) |
5f3cc447 | 1098 | { |
3e002182 | 1099 | *i = 0; |
5f3cc447 SN |
1100 | return 0; |
1101 | } | |
1102 | ||
237e0265 SN |
1103 | /** |
1104 | * fimc_pipeline_validate - check for formats inconsistencies | |
1105 | * between source and sink pad of each link | |
3b060ba0 | 1106 | * @fimc: the FIMC device this context applies to |
237e0265 SN |
1107 | * |
1108 | * Return 0 if all formats match or -EPIPE otherwise. | |
1109 | */ | |
1110 | static int fimc_pipeline_validate(struct fimc_dev *fimc) | |
1111 | { | |
1112 | struct v4l2_subdev_format sink_fmt, src_fmt; | |
88fa8311 SN |
1113 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
1114 | struct v4l2_subdev *sd = &vc->subdev; | |
403dfbec | 1115 | struct fimc_pipeline *p = to_fimc_pipeline(vc->ve.pipe); |
88fa8311 SN |
1116 | struct media_pad *sink_pad, *src_pad; |
1117 | int i, ret; | |
237e0265 SN |
1118 | |
1119 | while (1) { | |
88fa8311 SN |
1120 | /* |
1121 | * Find current entity sink pad and any remote sink pad linked | |
1122 | * to it. We stop if there is no sink pad in current entity or | |
1123 | * it is not linked to any other remote entity. | |
1124 | */ | |
1125 | src_pad = NULL; | |
1126 | ||
1127 | for (i = 0; i < sd->entity.num_pads; i++) { | |
1128 | struct media_pad *p = &sd->entity.pads[i]; | |
1129 | ||
1130 | if (p->flags & MEDIA_PAD_FL_SINK) { | |
1131 | sink_pad = p; | |
1bddf1b3 | 1132 | src_pad = media_entity_remote_pad(sink_pad); |
88fa8311 SN |
1133 | if (src_pad) |
1134 | break; | |
1135 | } | |
1136 | } | |
1137 | ||
3efdf62c | 1138 | if (!src_pad || !is_media_entity_v4l2_subdev(src_pad->entity)) |
237e0265 | 1139 | break; |
88fa8311 | 1140 | |
237e0265 | 1141 | /* Don't call FIMC subdev operation to avoid nested locking */ |
88fa8311 SN |
1142 | if (sd == &vc->subdev) { |
1143 | struct fimc_frame *ff = &vc->ctx->s_frame; | |
237e0265 SN |
1144 | sink_fmt.format.width = ff->f_width; |
1145 | sink_fmt.format.height = ff->f_height; | |
1146 | sink_fmt.format.code = ff->fmt ? ff->fmt->mbus_code : 0; | |
1147 | } else { | |
88fa8311 | 1148 | sink_fmt.pad = sink_pad->index; |
237e0265 SN |
1149 | sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; |
1150 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt); | |
1151 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
1152 | return -EPIPE; | |
1153 | } | |
237e0265 | 1154 | |
88fa8311 SN |
1155 | /* Retrieve format at the source pad */ |
1156 | sd = media_entity_to_v4l2_subdev(src_pad->entity); | |
1157 | src_fmt.pad = src_pad->index; | |
237e0265 SN |
1158 | src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; |
1159 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt); | |
1160 | if (ret < 0 && ret != -ENOIOCTLCMD) | |
1161 | return -EPIPE; | |
1162 | ||
1163 | if (src_fmt.format.width != sink_fmt.format.width || | |
1164 | src_fmt.format.height != sink_fmt.format.height || | |
1165 | src_fmt.format.code != sink_fmt.format.code) | |
1166 | return -EPIPE; | |
14783d25 | 1167 | |
403dfbec | 1168 | if (sd == p->subdevs[IDX_SENSOR] && |
14783d25 SN |
1169 | fimc_user_defined_mbus_fmt(src_fmt.format.code)) { |
1170 | struct v4l2_plane_pix_format plane_fmt[FIMC_MAX_PLANES]; | |
88fa8311 | 1171 | struct fimc_frame *frame = &vc->ctx->d_frame; |
14783d25 SN |
1172 | unsigned int i; |
1173 | ||
1174 | ret = fimc_get_sensor_frame_desc(sd, plane_fmt, | |
1175 | frame->fmt->memplanes, | |
1176 | false); | |
1177 | if (ret < 0) | |
1178 | return -EPIPE; | |
1179 | ||
1180 | for (i = 0; i < frame->fmt->memplanes; i++) | |
1181 | if (frame->payload[i] < plane_fmt[i].sizeimage) | |
1182 | return -EPIPE; | |
1183 | } | |
237e0265 SN |
1184 | } |
1185 | return 0; | |
1186 | } | |
1187 | ||
5f3cc447 | 1188 | static int fimc_cap_streamon(struct file *file, void *priv, |
2dab38e2 | 1189 | enum v4l2_buf_type type) |
5f3cc447 | 1190 | { |
e578588e | 1191 | struct fimc_dev *fimc = video_drvdata(file); |
95c4a17f | 1192 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
bc7584b0 | 1193 | struct media_entity *entity = &vc->ve.vdev.entity; |
88fa8311 SN |
1194 | struct fimc_source_info *si = NULL; |
1195 | struct v4l2_subdev *sd; | |
237e0265 | 1196 | int ret; |
5f3cc447 | 1197 | |
4db5e27e | 1198 | if (fimc_capture_active(fimc)) |
8293ebfc | 1199 | return -EBUSY; |
5f3cc447 | 1200 | |
20b85227 | 1201 | ret = media_pipeline_start(entity, &vc->ve.pipe->mp); |
a60a2959 SA |
1202 | if (ret < 0) |
1203 | return ret; | |
5f3cc447 | 1204 | |
403dfbec | 1205 | sd = __fimc_md_get_subdev(vc->ve.pipe, IDX_SENSOR); |
88fa8311 SN |
1206 | if (sd) |
1207 | si = v4l2_get_subdev_hostdata(sd); | |
1208 | ||
1209 | if (si == NULL) { | |
1210 | ret = -EPIPE; | |
1211 | goto err_p_stop; | |
1212 | } | |
1213 | /* | |
1214 | * Save configuration data related to currently attached image | |
1215 | * sensor or other data source, e.g. FIMC-IS. | |
1216 | */ | |
1217 | vc->source_config = *si; | |
1218 | ||
1219 | if (vc->input == GRP_ID_FIMC_IS) | |
1220 | vc->source_config.fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK; | |
1221 | ||
95c4a17f | 1222 | if (vc->user_subdev_api) { |
237e0265 | 1223 | ret = fimc_pipeline_validate(fimc); |
95c4a17f SN |
1224 | if (ret < 0) |
1225 | goto err_p_stop; | |
237e0265 | 1226 | } |
95c4a17f | 1227 | |
c444914a | 1228 | ret = vb2_ioctl_streamon(file, priv, type); |
9ea89e2b SN |
1229 | if (!ret) { |
1230 | vc->streaming = true; | |
95c4a17f | 1231 | return ret; |
9ea89e2b | 1232 | } |
95c4a17f SN |
1233 | |
1234 | err_p_stop: | |
20b85227 | 1235 | media_pipeline_stop(entity); |
95c4a17f | 1236 | return ret; |
5f3cc447 SN |
1237 | } |
1238 | ||
1239 | static int fimc_cap_streamoff(struct file *file, void *priv, | |
8293ebfc | 1240 | enum v4l2_buf_type type) |
5f3cc447 | 1241 | { |
e578588e | 1242 | struct fimc_dev *fimc = video_drvdata(file); |
bc7584b0 | 1243 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
4db5e27e | 1244 | int ret; |
5f3cc447 | 1245 | |
c444914a | 1246 | ret = vb2_ioctl_streamoff(file, priv, type); |
9ea89e2b SN |
1247 | if (ret < 0) |
1248 | return ret; | |
95c4a17f | 1249 | |
20b85227 | 1250 | media_pipeline_stop(&vc->ve.vdev.entity); |
bc7584b0 | 1251 | vc->streaming = false; |
9ea89e2b | 1252 | return 0; |
5f3cc447 SN |
1253 | } |
1254 | ||
1255 | static int fimc_cap_reqbufs(struct file *file, void *priv, | |
ef7af59b | 1256 | struct v4l2_requestbuffers *reqbufs) |
5f3cc447 | 1257 | { |
e578588e | 1258 | struct fimc_dev *fimc = video_drvdata(file); |
c444914a SN |
1259 | int ret; |
1260 | ||
1261 | ret = vb2_ioctl_reqbufs(file, priv, reqbufs); | |
5f3cc447 | 1262 | |
5f3cc447 | 1263 | if (!ret) |
e578588e | 1264 | fimc->vid_cap.reqbufs_count = reqbufs->count; |
3b4c34aa | 1265 | |
c444914a | 1266 | return ret; |
3b4c34aa SN |
1267 | } |
1268 | ||
f9331d11 SN |
1269 | static int fimc_cap_g_selection(struct file *file, void *fh, |
1270 | struct v4l2_selection *s) | |
e004e02f | 1271 | { |
e578588e | 1272 | struct fimc_dev *fimc = video_drvdata(file); |
f9331d11 SN |
1273 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; |
1274 | struct fimc_frame *f = &ctx->s_frame; | |
e004e02f | 1275 | |
eaec420f | 1276 | if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
e004e02f SN |
1277 | return -EINVAL; |
1278 | ||
f9331d11 SN |
1279 | switch (s->target) { |
1280 | case V4L2_SEL_TGT_COMPOSE_DEFAULT: | |
1281 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: | |
1282 | f = &ctx->d_frame; | |
06eeefe8 | 1283 | /* fall through */ |
f9331d11 SN |
1284 | case V4L2_SEL_TGT_CROP_BOUNDS: |
1285 | case V4L2_SEL_TGT_CROP_DEFAULT: | |
1286 | s->r.left = 0; | |
1287 | s->r.top = 0; | |
1288 | s->r.width = f->o_width; | |
1289 | s->r.height = f->o_height; | |
1290 | return 0; | |
e004e02f | 1291 | |
c1334823 | 1292 | case V4L2_SEL_TGT_COMPOSE: |
f9331d11 | 1293 | f = &ctx->d_frame; |
06eeefe8 | 1294 | /* fall through */ |
c1334823 | 1295 | case V4L2_SEL_TGT_CROP: |
f9331d11 SN |
1296 | s->r.left = f->offs_h; |
1297 | s->r.top = f->offs_v; | |
1298 | s->r.width = f->width; | |
1299 | s->r.height = f->height; | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | return -EINVAL; | |
e004e02f SN |
1304 | } |
1305 | ||
f9331d11 | 1306 | /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */ |
7e566be2 | 1307 | static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b) |
e004e02f | 1308 | { |
f9331d11 SN |
1309 | if (a->left < b->left || a->top < b->top) |
1310 | return 0; | |
1311 | if (a->left + a->width > b->left + b->width) | |
1312 | return 0; | |
1313 | if (a->top + a->height > b->top + b->height) | |
1314 | return 0; | |
e004e02f | 1315 | |
f9331d11 | 1316 | return 1; |
e004e02f SN |
1317 | } |
1318 | ||
f9331d11 SN |
1319 | static int fimc_cap_s_selection(struct file *file, void *fh, |
1320 | struct v4l2_selection *s) | |
5f3cc447 | 1321 | { |
e578588e SN |
1322 | struct fimc_dev *fimc = video_drvdata(file); |
1323 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
f9331d11 SN |
1324 | struct v4l2_rect rect = s->r; |
1325 | struct fimc_frame *f; | |
237e0265 | 1326 | unsigned long flags; |
f9331d11 | 1327 | |
eaec420f | 1328 | if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
f9331d11 SN |
1329 | return -EINVAL; |
1330 | ||
c1334823 | 1331 | if (s->target == V4L2_SEL_TGT_COMPOSE) |
f9331d11 | 1332 | f = &ctx->d_frame; |
c1334823 | 1333 | else if (s->target == V4L2_SEL_TGT_CROP) |
f9331d11 | 1334 | f = &ctx->s_frame; |
fed07f84 | 1335 | else |
f9331d11 | 1336 | return -EINVAL; |
f9331d11 | 1337 | |
fed07f84 | 1338 | fimc_capture_try_selection(ctx, &rect, s->target); |
f9331d11 SN |
1339 | |
1340 | if (s->flags & V4L2_SEL_FLAG_LE && | |
1341 | !enclosed_rectangle(&rect, &s->r)) | |
1342 | return -ERANGE; | |
5f3cc447 | 1343 | |
f9331d11 SN |
1344 | if (s->flags & V4L2_SEL_FLAG_GE && |
1345 | !enclosed_rectangle(&s->r, &rect)) | |
1346 | return -ERANGE; | |
5f3cc447 | 1347 | |
f9331d11 | 1348 | s->r = rect; |
237e0265 | 1349 | spin_lock_irqsave(&fimc->slock, flags); |
f9331d11 SN |
1350 | set_frame_crop(f, s->r.left, s->r.top, s->r.width, |
1351 | s->r.height); | |
237e0265 | 1352 | spin_unlock_irqrestore(&fimc->slock, flags); |
8293ebfc | 1353 | |
f9331d11 | 1354 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); |
8293ebfc | 1355 | return 0; |
5f3cc447 SN |
1356 | } |
1357 | ||
5f3cc447 | 1358 | static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = { |
aceb59ed | 1359 | .vidioc_querycap = fimc_cap_querycap, |
5f3cc447 | 1360 | |
cf52df8a | 1361 | .vidioc_enum_fmt_vid_cap_mplane = fimc_cap_enum_fmt_mplane, |
e578588e | 1362 | .vidioc_try_fmt_vid_cap_mplane = fimc_cap_try_fmt_mplane, |
ef7af59b | 1363 | .vidioc_s_fmt_vid_cap_mplane = fimc_cap_s_fmt_mplane, |
e578588e | 1364 | .vidioc_g_fmt_vid_cap_mplane = fimc_cap_g_fmt_mplane, |
5f3cc447 SN |
1365 | |
1366 | .vidioc_reqbufs = fimc_cap_reqbufs, | |
c444914a SN |
1367 | .vidioc_querybuf = vb2_ioctl_querybuf, |
1368 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
1369 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
1370 | .vidioc_expbuf = vb2_ioctl_expbuf, | |
1371 | .vidioc_prepare_buf = vb2_ioctl_prepare_buf, | |
1372 | .vidioc_create_bufs = vb2_ioctl_create_bufs, | |
3b4c34aa | 1373 | |
5f3cc447 SN |
1374 | .vidioc_streamon = fimc_cap_streamon, |
1375 | .vidioc_streamoff = fimc_cap_streamoff, | |
1376 | ||
f9331d11 SN |
1377 | .vidioc_g_selection = fimc_cap_g_selection, |
1378 | .vidioc_s_selection = fimc_cap_s_selection, | |
5f3cc447 SN |
1379 | |
1380 | .vidioc_enum_input = fimc_cap_enum_input, | |
1381 | .vidioc_s_input = fimc_cap_s_input, | |
1382 | .vidioc_g_input = fimc_cap_g_input, | |
1383 | }; | |
1384 | ||
237e0265 | 1385 | /* Capture subdev media entity operations */ |
d09a7dc8 SN |
1386 | static int fimc_link_setup(struct media_entity *entity, |
1387 | const struct media_pad *local, | |
1388 | const struct media_pad *remote, u32 flags) | |
1389 | { | |
237e0265 SN |
1390 | struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); |
1391 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
4403106d SN |
1392 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
1393 | struct v4l2_subdev *sensor; | |
237e0265 | 1394 | |
3efdf62c | 1395 | if (!is_media_entity_v4l2_subdev(remote->entity)) |
237e0265 | 1396 | return -EINVAL; |
d09a7dc8 SN |
1397 | |
1398 | if (WARN_ON(fimc == NULL)) | |
1399 | return 0; | |
1400 | ||
1401 | dbg("%s --> %s, flags: 0x%x. input: 0x%x", | |
1402 | local->entity->name, remote->entity->name, flags, | |
1403 | fimc->vid_cap.input); | |
1404 | ||
4403106d SN |
1405 | if (!(flags & MEDIA_LNK_FL_ENABLED)) { |
1406 | fimc->vid_cap.input = 0; | |
d09a7dc8 SN |
1407 | return 0; |
1408 | } | |
1409 | ||
4403106d SN |
1410 | if (vc->input != 0) |
1411 | return -EBUSY; | |
1412 | ||
1413 | vc->input = sd->grp_id; | |
1414 | ||
1415 | if (vc->user_subdev_api || vc->inh_sensor_ctrls) | |
1416 | return 0; | |
1417 | ||
1418 | /* Inherit V4L2 controls from the image sensor subdev. */ | |
1419 | sensor = fimc_find_remote_sensor(&vc->subdev.entity); | |
1420 | if (sensor == NULL) | |
1421 | return 0; | |
1422 | ||
1423 | return v4l2_ctrl_add_handler(&vc->ctx->ctrls.handler, | |
1424 | sensor->ctrl_handler, NULL); | |
d09a7dc8 SN |
1425 | } |
1426 | ||
237e0265 | 1427 | static const struct media_entity_operations fimc_sd_media_ops = { |
d09a7dc8 SN |
1428 | .link_setup = fimc_link_setup, |
1429 | }; | |
1430 | ||
e1d72f4d SN |
1431 | /** |
1432 | * fimc_sensor_notify - v4l2_device notification from a sensor subdev | |
1433 | * @sd: pointer to a subdev generating the notification | |
1434 | * @notification: the notification type, must be S5P_FIMC_TX_END_NOTIFY | |
1435 | * @arg: pointer to an u32 type integer that stores the frame payload value | |
1436 | * | |
1437 | * The End Of Frame notification sent by sensor subdev in its still capture | |
1438 | * mode. If there is only a single VSYNC generated by the sensor at the | |
1439 | * beginning of a frame transmission, FIMC does not issue the LastIrq | |
1440 | * (end of frame) interrupt. And this notification is used to complete the | |
1441 | * frame capture and returning a buffer to user-space. Subdev drivers should | |
1442 | * call this notification from their last 'End of frame capture' interrupt. | |
1443 | */ | |
1444 | void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification, | |
1445 | void *arg) | |
1446 | { | |
4c8f0629 | 1447 | struct fimc_source_info *si; |
e1d72f4d SN |
1448 | struct fimc_vid_buffer *buf; |
1449 | struct fimc_md *fmd; | |
1450 | struct fimc_dev *fimc; | |
1451 | unsigned long flags; | |
1452 | ||
1453 | if (sd == NULL) | |
1454 | return; | |
1455 | ||
4c8f0629 | 1456 | si = v4l2_get_subdev_hostdata(sd); |
e1d72f4d SN |
1457 | fmd = entity_to_fimc_mdev(&sd->entity); |
1458 | ||
1459 | spin_lock_irqsave(&fmd->slock, flags); | |
4c8f0629 SN |
1460 | |
1461 | fimc = si ? source_to_sensor_info(si)->host : NULL; | |
e1d72f4d SN |
1462 | |
1463 | if (fimc && arg && notification == S5P_FIMC_TX_END_NOTIFY && | |
1464 | test_bit(ST_CAPT_PEND, &fimc->state)) { | |
1465 | unsigned long irq_flags; | |
1466 | spin_lock_irqsave(&fimc->slock, irq_flags); | |
1467 | if (!list_empty(&fimc->vid_cap.active_buf_q)) { | |
1468 | buf = list_entry(fimc->vid_cap.active_buf_q.next, | |
1469 | struct fimc_vid_buffer, list); | |
2d700715 JS |
1470 | vb2_set_plane_payload(&buf->vb.vb2_buf, 0, |
1471 | *((u32 *)arg)); | |
e1d72f4d | 1472 | } |
97d97422 | 1473 | fimc_capture_irq_handler(fimc, 1); |
e1d72f4d SN |
1474 | fimc_deactivate_capture(fimc); |
1475 | spin_unlock_irqrestore(&fimc->slock, irq_flags); | |
1476 | } | |
1477 | spin_unlock_irqrestore(&fmd->slock, flags); | |
1478 | } | |
1479 | ||
237e0265 | 1480 | static int fimc_subdev_enum_mbus_code(struct v4l2_subdev *sd, |
f7234138 | 1481 | struct v4l2_subdev_pad_config *cfg, |
237e0265 SN |
1482 | struct v4l2_subdev_mbus_code_enum *code) |
1483 | { | |
1484 | struct fimc_fmt *fmt; | |
1485 | ||
1486 | fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, code->index); | |
1487 | if (!fmt) | |
1488 | return -EINVAL; | |
1489 | code->code = fmt->mbus_code; | |
1490 | return 0; | |
1491 | } | |
1492 | ||
1493 | static int fimc_subdev_get_fmt(struct v4l2_subdev *sd, | |
f7234138 | 1494 | struct v4l2_subdev_pad_config *cfg, |
237e0265 SN |
1495 | struct v4l2_subdev_format *fmt) |
1496 | { | |
1497 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1498 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
88fa8311 | 1499 | struct fimc_frame *ff = &ctx->s_frame; |
237e0265 | 1500 | struct v4l2_mbus_framefmt *mf; |
237e0265 SN |
1501 | |
1502 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
f7234138 | 1503 | mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); |
237e0265 SN |
1504 | fmt->format = *mf; |
1505 | return 0; | |
1506 | } | |
237e0265 | 1507 | |
88fa8311 | 1508 | mf = &fmt->format; |
237e0265 | 1509 | mutex_lock(&fimc->lock); |
88fa8311 SN |
1510 | |
1511 | switch (fmt->pad) { | |
1512 | case FIMC_SD_PAD_SOURCE: | |
1513 | if (!WARN_ON(ff->fmt == NULL)) | |
1514 | mf->code = ff->fmt->mbus_code; | |
1515 | /* Sink pads crop rectangle size */ | |
1516 | mf->width = ff->width; | |
1517 | mf->height = ff->height; | |
1518 | break; | |
1519 | case FIMC_SD_PAD_SINK_FIFO: | |
1520 | *mf = fimc->vid_cap.wb_fmt; | |
1521 | break; | |
1522 | case FIMC_SD_PAD_SINK_CAM: | |
1523 | default: | |
1524 | *mf = fimc->vid_cap.ci_fmt; | |
1525 | break; | |
1526 | } | |
1527 | ||
237e0265 | 1528 | mutex_unlock(&fimc->lock); |
88fa8311 | 1529 | mf->colorspace = V4L2_COLORSPACE_JPEG; |
237e0265 SN |
1530 | |
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static int fimc_subdev_set_fmt(struct v4l2_subdev *sd, | |
f7234138 | 1535 | struct v4l2_subdev_pad_config *cfg, |
237e0265 SN |
1536 | struct v4l2_subdev_format *fmt) |
1537 | { | |
1538 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1539 | struct v4l2_mbus_framefmt *mf = &fmt->format; | |
88fa8311 SN |
1540 | struct fimc_vid_cap *vc = &fimc->vid_cap; |
1541 | struct fimc_ctx *ctx = vc->ctx; | |
237e0265 SN |
1542 | struct fimc_frame *ff; |
1543 | struct fimc_fmt *ffmt; | |
1544 | ||
1545 | dbg("pad%d: code: 0x%x, %dx%d", | |
1546 | fmt->pad, mf->code, mf->width, mf->height); | |
1547 | ||
88fa8311 | 1548 | if (fmt->pad == FIMC_SD_PAD_SOURCE && vb2_is_busy(&vc->vbq)) |
237e0265 SN |
1549 | return -EBUSY; |
1550 | ||
1551 | mutex_lock(&fimc->lock); | |
1552 | ffmt = fimc_capture_try_format(ctx, &mf->width, &mf->height, | |
1553 | &mf->code, NULL, fmt->pad); | |
1554 | mutex_unlock(&fimc->lock); | |
1555 | mf->colorspace = V4L2_COLORSPACE_JPEG; | |
1556 | ||
1557 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
f7234138 | 1558 | mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); |
237e0265 SN |
1559 | *mf = fmt->format; |
1560 | return 0; | |
1561 | } | |
6612545f SN |
1562 | /* There must be a bug in the driver if this happens */ |
1563 | if (WARN_ON(ffmt == NULL)) | |
1564 | return -EINVAL; | |
1565 | ||
dafb9c70 SN |
1566 | /* Update RGB Alpha control state and value range */ |
1567 | fimc_alpha_ctrl_update(ctx); | |
1568 | ||
14783d25 | 1569 | fimc_capture_mark_jpeg_xfer(ctx, ffmt->color); |
88fa8311 SN |
1570 | if (fmt->pad == FIMC_SD_PAD_SOURCE) { |
1571 | ff = &ctx->d_frame; | |
1572 | /* Sink pads crop rectangle size */ | |
1573 | mf->width = ctx->s_frame.width; | |
1574 | mf->height = ctx->s_frame.height; | |
1575 | } else { | |
1576 | ff = &ctx->s_frame; | |
1577 | } | |
237e0265 SN |
1578 | |
1579 | mutex_lock(&fimc->lock); | |
1580 | set_frame_bounds(ff, mf->width, mf->height); | |
88fa8311 SN |
1581 | |
1582 | if (fmt->pad == FIMC_SD_PAD_SINK_FIFO) | |
1583 | vc->wb_fmt = *mf; | |
1584 | else if (fmt->pad == FIMC_SD_PAD_SINK_CAM) | |
1585 | vc->ci_fmt = *mf; | |
1586 | ||
237e0265 SN |
1587 | ff->fmt = ffmt; |
1588 | ||
1589 | /* Reset the crop rectangle if required. */ | |
fed07f84 | 1590 | if (!(fmt->pad == FIMC_SD_PAD_SOURCE && (ctx->state & FIMC_COMPOSE))) |
237e0265 SN |
1591 | set_frame_crop(ff, 0, 0, mf->width, mf->height); |
1592 | ||
88fa8311 | 1593 | if (fmt->pad != FIMC_SD_PAD_SOURCE) |
fed07f84 | 1594 | ctx->state &= ~FIMC_COMPOSE; |
88fa8311 | 1595 | |
237e0265 SN |
1596 | mutex_unlock(&fimc->lock); |
1597 | return 0; | |
1598 | } | |
1599 | ||
fed07f84 | 1600 | static int fimc_subdev_get_selection(struct v4l2_subdev *sd, |
f7234138 | 1601 | struct v4l2_subdev_pad_config *cfg, |
fed07f84 | 1602 | struct v4l2_subdev_selection *sel) |
237e0265 SN |
1603 | { |
1604 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1605 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
fed07f84 SN |
1606 | struct fimc_frame *f = &ctx->s_frame; |
1607 | struct v4l2_rect *r = &sel->r; | |
1608 | struct v4l2_rect *try_sel; | |
1609 | ||
88fa8311 | 1610 | if (sel->pad == FIMC_SD_PAD_SOURCE) |
fed07f84 SN |
1611 | return -EINVAL; |
1612 | ||
1613 | mutex_lock(&fimc->lock); | |
237e0265 | 1614 | |
fed07f84 | 1615 | switch (sel->target) { |
5689b288 | 1616 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: |
fed07f84 | 1617 | f = &ctx->d_frame; |
06eeefe8 | 1618 | /* fall through */ |
5689b288 | 1619 | case V4L2_SEL_TGT_CROP_BOUNDS: |
fed07f84 SN |
1620 | r->width = f->o_width; |
1621 | r->height = f->o_height; | |
1622 | r->left = 0; | |
1623 | r->top = 0; | |
1624 | mutex_unlock(&fimc->lock); | |
237e0265 | 1625 | return 0; |
fed07f84 | 1626 | |
5689b288 | 1627 | case V4L2_SEL_TGT_CROP: |
f7234138 | 1628 | try_sel = v4l2_subdev_get_try_crop(sd, cfg, sel->pad); |
fed07f84 | 1629 | break; |
5689b288 | 1630 | case V4L2_SEL_TGT_COMPOSE: |
f7234138 | 1631 | try_sel = v4l2_subdev_get_try_compose(sd, cfg, sel->pad); |
fed07f84 SN |
1632 | f = &ctx->d_frame; |
1633 | break; | |
1634 | default: | |
1635 | mutex_unlock(&fimc->lock); | |
1636 | return -EINVAL; | |
237e0265 | 1637 | } |
237e0265 | 1638 | |
fed07f84 SN |
1639 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
1640 | sel->r = *try_sel; | |
1641 | } else { | |
1642 | r->left = f->offs_h; | |
1643 | r->top = f->offs_v; | |
1644 | r->width = f->width; | |
1645 | r->height = f->height; | |
1646 | } | |
237e0265 | 1647 | |
fed07f84 SN |
1648 | dbg("target %#x: l:%d, t:%d, %dx%d, f_w: %d, f_h: %d", |
1649 | sel->pad, r->left, r->top, r->width, r->height, | |
1650 | f->f_width, f->f_height); | |
237e0265 | 1651 | |
fed07f84 | 1652 | mutex_unlock(&fimc->lock); |
237e0265 SN |
1653 | return 0; |
1654 | } | |
1655 | ||
fed07f84 | 1656 | static int fimc_subdev_set_selection(struct v4l2_subdev *sd, |
f7234138 | 1657 | struct v4l2_subdev_pad_config *cfg, |
fed07f84 | 1658 | struct v4l2_subdev_selection *sel) |
237e0265 SN |
1659 | { |
1660 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
1661 | struct fimc_ctx *ctx = fimc->vid_cap.ctx; | |
fed07f84 SN |
1662 | struct fimc_frame *f = &ctx->s_frame; |
1663 | struct v4l2_rect *r = &sel->r; | |
1664 | struct v4l2_rect *try_sel; | |
237e0265 SN |
1665 | unsigned long flags; |
1666 | ||
88fa8311 | 1667 | if (sel->pad == FIMC_SD_PAD_SOURCE) |
fed07f84 | 1668 | return -EINVAL; |
237e0265 SN |
1669 | |
1670 | mutex_lock(&fimc->lock); | |
c1334823 | 1671 | fimc_capture_try_selection(ctx, r, V4L2_SEL_TGT_CROP); |
237e0265 | 1672 | |
fed07f84 | 1673 | switch (sel->target) { |
5689b288 | 1674 | case V4L2_SEL_TGT_CROP: |
f7234138 | 1675 | try_sel = v4l2_subdev_get_try_crop(sd, cfg, sel->pad); |
fed07f84 | 1676 | break; |
5689b288 | 1677 | case V4L2_SEL_TGT_COMPOSE: |
f7234138 | 1678 | try_sel = v4l2_subdev_get_try_compose(sd, cfg, sel->pad); |
fed07f84 SN |
1679 | f = &ctx->d_frame; |
1680 | break; | |
1681 | default: | |
1682 | mutex_unlock(&fimc->lock); | |
1683 | return -EINVAL; | |
237e0265 | 1684 | } |
237e0265 | 1685 | |
fed07f84 SN |
1686 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
1687 | *try_sel = sel->r; | |
1688 | } else { | |
1689 | spin_lock_irqsave(&fimc->slock, flags); | |
1690 | set_frame_crop(f, r->left, r->top, r->width, r->height); | |
1691 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
5689b288 | 1692 | if (sel->target == V4L2_SEL_TGT_COMPOSE) |
fed07f84 | 1693 | ctx->state |= FIMC_COMPOSE; |
8b164105 | 1694 | spin_unlock_irqrestore(&fimc->slock, flags); |
fed07f84 | 1695 | } |
237e0265 | 1696 | |
fed07f84 | 1697 | dbg("target %#x: (%d,%d)/%dx%d", sel->target, r->left, r->top, |
237e0265 SN |
1698 | r->width, r->height); |
1699 | ||
1700 | mutex_unlock(&fimc->lock); | |
1701 | return 0; | |
1702 | } | |
1703 | ||
a2fafda6 | 1704 | static const struct v4l2_subdev_pad_ops fimc_subdev_pad_ops = { |
237e0265 | 1705 | .enum_mbus_code = fimc_subdev_enum_mbus_code, |
fed07f84 SN |
1706 | .get_selection = fimc_subdev_get_selection, |
1707 | .set_selection = fimc_subdev_set_selection, | |
237e0265 SN |
1708 | .get_fmt = fimc_subdev_get_fmt, |
1709 | .set_fmt = fimc_subdev_set_fmt, | |
237e0265 SN |
1710 | }; |
1711 | ||
a2fafda6 | 1712 | static const struct v4l2_subdev_ops fimc_subdev_ops = { |
237e0265 SN |
1713 | .pad = &fimc_subdev_pad_ops, |
1714 | }; | |
1715 | ||
237e0265 SN |
1716 | /* Set default format at the sensor and host interface */ |
1717 | static int fimc_capture_set_default_format(struct fimc_dev *fimc) | |
1718 | { | |
1719 | struct v4l2_format fmt = { | |
1720 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, | |
1721 | .fmt.pix_mp = { | |
3ad86245 SN |
1722 | .width = FIMC_DEFAULT_WIDTH, |
1723 | .height = FIMC_DEFAULT_HEIGHT, | |
237e0265 SN |
1724 | .pixelformat = V4L2_PIX_FMT_YUYV, |
1725 | .field = V4L2_FIELD_NONE, | |
1726 | .colorspace = V4L2_COLORSPACE_JPEG, | |
1727 | }, | |
1728 | }; | |
1729 | ||
740ad921 | 1730 | return __fimc_capture_set_format(fimc, &fmt); |
237e0265 SN |
1731 | } |
1732 | ||
ef7af59b | 1733 | /* fimc->lock must be already initialized */ |
693f5c40 | 1734 | static int fimc_register_capture_device(struct fimc_dev *fimc, |
30c9939d | 1735 | struct v4l2_device *v4l2_dev) |
5f3cc447 | 1736 | { |
bc7584b0 | 1737 | struct video_device *vfd = &fimc->vid_cap.ve.vdev; |
c444914a | 1738 | struct vb2_queue *q = &fimc->vid_cap.vbq; |
5f3cc447 | 1739 | struct fimc_ctx *ctx; |
c444914a | 1740 | struct fimc_vid_cap *vid_cap; |
3ad86245 | 1741 | struct fimc_fmt *fmt; |
30c9939d | 1742 | int ret = -ENOMEM; |
5f3cc447 | 1743 | |
26ee7f47 | 1744 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
5f3cc447 SN |
1745 | if (!ctx) |
1746 | return -ENOMEM; | |
1747 | ||
1748 | ctx->fimc_dev = fimc; | |
3d112d9a SN |
1749 | ctx->in_path = FIMC_IO_CAMERA; |
1750 | ctx->out_path = FIMC_IO_DMA; | |
5f3cc447 | 1751 | ctx->state = FIMC_CTX_CAP; |
237e0265 | 1752 | ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0); |
693f5c40 | 1753 | ctx->d_frame.fmt = ctx->s_frame.fmt; |
5f3cc447 | 1754 | |
31d34d9b | 1755 | memset(vfd, 0, sizeof(*vfd)); |
693f5c40 | 1756 | snprintf(vfd->name, sizeof(vfd->name), "fimc.%d.capture", fimc->id); |
5f3cc447 SN |
1757 | |
1758 | vfd->fops = &fimc_capture_fops; | |
1759 | vfd->ioctl_ops = &fimc_capture_ioctl_ops; | |
574e1717 | 1760 | vfd->v4l2_dev = v4l2_dev; |
5f3cc447 | 1761 | vfd->minor = -1; |
31d34d9b | 1762 | vfd->release = video_device_release_empty; |
c444914a | 1763 | vfd->queue = q; |
8293ebfc | 1764 | vfd->lock = &fimc->lock; |
c2d430af | 1765 | |
5f3cc447 | 1766 | video_set_drvdata(vfd, fimc); |
5f3cc447 | 1767 | vid_cap = &fimc->vid_cap; |
5f3cc447 | 1768 | vid_cap->active_buf_cnt = 0; |
c444914a SN |
1769 | vid_cap->reqbufs_count = 0; |
1770 | vid_cap->ctx = ctx; | |
5f3cc447 SN |
1771 | |
1772 | INIT_LIST_HEAD(&vid_cap->pending_buf_q); | |
1773 | INIT_LIST_HEAD(&vid_cap->active_buf_q); | |
5f3cc447 | 1774 | |
2dab38e2 | 1775 | memset(q, 0, sizeof(*q)); |
ef7af59b | 1776 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; |
9bd09fd7 | 1777 | q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; |
c444914a | 1778 | q->drv_priv = ctx; |
2dab38e2 SN |
1779 | q->ops = &fimc_capture_qops; |
1780 | q->mem_ops = &vb2_dma_contig_memops; | |
1781 | q->buf_struct_size = sizeof(struct fimc_vid_buffer); | |
ade48681 | 1782 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; |
c444914a | 1783 | q->lock = &fimc->lock; |
2548fee6 | 1784 | q->dev = &fimc->pdev->dev; |
2dab38e2 | 1785 | |
41fd087f SN |
1786 | ret = vb2_queue_init(q); |
1787 | if (ret) | |
4403106d | 1788 | goto err_free_ctx; |
5f3cc447 | 1789 | |
3ad86245 SN |
1790 | /* Default format configuration */ |
1791 | fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0); | |
1792 | vid_cap->ci_fmt.width = FIMC_DEFAULT_WIDTH; | |
1793 | vid_cap->ci_fmt.height = FIMC_DEFAULT_HEIGHT; | |
1794 | vid_cap->ci_fmt.code = fmt->mbus_code; | |
1795 | ||
1796 | ctx->s_frame.width = FIMC_DEFAULT_WIDTH; | |
1797 | ctx->s_frame.height = FIMC_DEFAULT_HEIGHT; | |
1798 | ctx->s_frame.fmt = fmt; | |
1799 | ||
1800 | fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_WRITEBACK, 0); | |
1801 | vid_cap->wb_fmt = vid_cap->ci_fmt; | |
1802 | vid_cap->wb_fmt.code = fmt->mbus_code; | |
1803 | ||
693f5c40 | 1804 | vid_cap->vd_pad.flags = MEDIA_PAD_FL_SINK; |
bae45003 | 1805 | vfd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER; |
ab22e77c | 1806 | ret = media_entity_pads_init(&vfd->entity, 1, &vid_cap->vd_pad); |
574e1717 | 1807 | if (ret) |
4403106d SN |
1808 | goto err_free_ctx; |
1809 | ||
1810 | ret = fimc_ctrls_create(ctx); | |
1811 | if (ret) | |
1812 | goto err_me_cleanup; | |
693f5c40 SN |
1813 | |
1814 | ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1); | |
237e0265 | 1815 | if (ret) |
4403106d | 1816 | goto err_ctrl_free; |
693f5c40 SN |
1817 | |
1818 | v4l2_info(v4l2_dev, "Registered %s as /dev/%s\n", | |
1819 | vfd->name, video_device_node_name(vfd)); | |
574e1717 | 1820 | |
9448ab7d | 1821 | vfd->ctrl_handler = &ctx->ctrls.handler; |
5f3cc447 SN |
1822 | return 0; |
1823 | ||
4403106d SN |
1824 | err_ctrl_free: |
1825 | fimc_ctrls_delete(ctx); | |
1826 | err_me_cleanup: | |
237e0265 | 1827 | media_entity_cleanup(&vfd->entity); |
4403106d | 1828 | err_free_ctx: |
cfd77310 | 1829 | kfree(ctx); |
5f3cc447 SN |
1830 | return ret; |
1831 | } | |
1832 | ||
693f5c40 | 1833 | static int fimc_capture_subdev_registered(struct v4l2_subdev *sd) |
5f3cc447 | 1834 | { |
693f5c40 SN |
1835 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); |
1836 | int ret; | |
5f3cc447 | 1837 | |
bbc5296f SN |
1838 | if (fimc == NULL) |
1839 | return -ENXIO; | |
1840 | ||
693f5c40 SN |
1841 | ret = fimc_register_m2m_device(fimc, sd->v4l2_dev); |
1842 | if (ret) | |
1843 | return ret; | |
1844 | ||
403dfbec | 1845 | fimc->vid_cap.ve.pipe = v4l2_get_subdev_hostdata(sd); |
97d66c47 | 1846 | |
693f5c40 | 1847 | ret = fimc_register_capture_device(fimc, sd->v4l2_dev); |
97d66c47 | 1848 | if (ret) { |
693f5c40 | 1849 | fimc_unregister_m2m_device(fimc); |
403dfbec | 1850 | fimc->vid_cap.ve.pipe = NULL; |
97d66c47 | 1851 | } |
693f5c40 SN |
1852 | |
1853 | return ret; | |
1854 | } | |
1855 | ||
1856 | static void fimc_capture_subdev_unregistered(struct v4l2_subdev *sd) | |
1857 | { | |
1858 | struct fimc_dev *fimc = v4l2_get_subdevdata(sd); | |
bc7584b0 | 1859 | struct video_device *vdev; |
693f5c40 SN |
1860 | |
1861 | if (fimc == NULL) | |
1862 | return; | |
1863 | ||
26d63d13 SN |
1864 | mutex_lock(&fimc->lock); |
1865 | ||
693f5c40 | 1866 | fimc_unregister_m2m_device(fimc); |
bc7584b0 | 1867 | vdev = &fimc->vid_cap.ve.vdev; |
693f5c40 | 1868 | |
bc7584b0 SN |
1869 | if (video_is_registered(vdev)) { |
1870 | video_unregister_device(vdev); | |
1871 | media_entity_cleanup(&vdev->entity); | |
4403106d | 1872 | fimc_ctrls_delete(fimc->vid_cap.ctx); |
403dfbec | 1873 | fimc->vid_cap.ve.pipe = NULL; |
574e1717 SN |
1874 | } |
1875 | kfree(fimc->vid_cap.ctx); | |
96a85742 | 1876 | fimc->vid_cap.ctx = NULL; |
26d63d13 SN |
1877 | |
1878 | mutex_unlock(&fimc->lock); | |
5f3cc447 | 1879 | } |
693f5c40 SN |
1880 | |
1881 | static const struct v4l2_subdev_internal_ops fimc_capture_sd_internal_ops = { | |
1882 | .registered = fimc_capture_subdev_registered, | |
1883 | .unregistered = fimc_capture_subdev_unregistered, | |
1884 | }; | |
1885 | ||
1886 | int fimc_initialize_capture_subdev(struct fimc_dev *fimc) | |
1887 | { | |
1888 | struct v4l2_subdev *sd = &fimc->vid_cap.subdev; | |
1889 | int ret; | |
1890 | ||
1891 | v4l2_subdev_init(sd, &fimc_subdev_ops); | |
5a66561f | 1892 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
e80cb1fa | 1893 | snprintf(sd->name, sizeof(sd->name), "FIMC.%d", fimc->id); |
693f5c40 | 1894 | |
88fa8311 SN |
1895 | fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_CAM].flags = MEDIA_PAD_FL_SINK; |
1896 | fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_FIFO].flags = MEDIA_PAD_FL_SINK; | |
693f5c40 | 1897 | fimc->vid_cap.sd_pads[FIMC_SD_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; |
ab22e77c | 1898 | ret = media_entity_pads_init(&sd->entity, FIMC_SD_PADS_NUM, |
18095107 | 1899 | fimc->vid_cap.sd_pads); |
693f5c40 SN |
1900 | if (ret) |
1901 | return ret; | |
1902 | ||
1903 | sd->entity.ops = &fimc_sd_media_ops; | |
1904 | sd->internal_ops = &fimc_capture_sd_internal_ops; | |
1905 | v4l2_set_subdevdata(sd, fimc); | |
1906 | return 0; | |
1907 | } | |
1908 | ||
1909 | void fimc_unregister_capture_subdev(struct fimc_dev *fimc) | |
1910 | { | |
1911 | struct v4l2_subdev *sd = &fimc->vid_cap.subdev; | |
1912 | ||
1913 | v4l2_device_unregister_subdev(sd); | |
1914 | media_entity_cleanup(&sd->entity); | |
1915 | v4l2_set_subdevdata(sd, NULL); | |
1916 | } |