[media] exynos4-is: Do not use asynchronous runtime PM in release fop
[linux-2.6-block.git] / drivers / media / platform / exynos4-is / fimc-capture.c
CommitLineData
5f3cc447 1/*
3a3f9449 2 * Samsung S5P/EXYNOS4 SoC series camera interface (camera capture) driver
5f3cc447 3 *
0c9204d3
SN
4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
5f3cc447
SN
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
5f3cc447
SN
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/bug.h>
17#include <linux/interrupt.h>
18#include <linux/device.h>
e9e21083 19#include <linux/pm_runtime.h>
5f3cc447
SN
20#include <linux/list.h>
21#include <linux/slab.h>
5f3cc447
SN
22
23#include <linux/videodev2.h>
24#include <media/v4l2-device.h>
25#include <media/v4l2-ioctl.h>
26#include <media/v4l2-mem2mem.h>
2dab38e2
SN
27#include <media/videobuf2-core.h>
28#include <media/videobuf2-dma-contig.h>
5f3cc447 29
4403106d 30#include "common.h"
5f3cc447 31#include "fimc-core.h"
c83a1ff0 32#include "fimc-reg.h"
4403106d 33#include "media-dev.h"
5f3cc447 34
bb7c276e 35static int fimc_capture_hw_init(struct fimc_dev *fimc)
9e803a04 36{
88fa8311 37 struct fimc_source_info *si = &fimc->vid_cap.source_config;
9e803a04 38 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
88fa8311 39 int ret;
9e803a04 40 unsigned long flags;
9e803a04 41
88fa8311 42 if (ctx == NULL || ctx->s_frame.fmt == NULL)
9e803a04
SN
43 return -EINVAL;
44
88fa8311
SN
45 if (si->fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK) {
46 ret = fimc_hw_camblk_cfg_writeback(fimc);
47 if (ret < 0)
48 return ret;
49 }
9e803a04
SN
50
51 spin_lock_irqsave(&fimc->slock, flags);
52 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
53 fimc_set_yuv_order(ctx);
54
88fa8311
SN
55 fimc_hw_set_camera_polarity(fimc, si);
56 fimc_hw_set_camera_type(fimc, si);
57 fimc_hw_set_camera_source(fimc, si);
9e803a04
SN
58 fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
59
60 ret = fimc_set_scaler_info(ctx);
61 if (!ret) {
62 fimc_hw_set_input_path(ctx);
63 fimc_hw_set_prescaler(ctx);
64 fimc_hw_set_mainscaler(ctx);
65 fimc_hw_set_target_format(ctx);
66 fimc_hw_set_rotation(ctx);
9448ab7d 67 fimc_hw_set_effect(ctx);
9e803a04
SN
68 fimc_hw_set_output_path(ctx);
69 fimc_hw_set_out_dma(ctx);
e80cb1fa 70 if (fimc->drv_data->alpha_color)
dafb9c70 71 fimc_hw_set_rgb_alpha(ctx);
237e0265 72 clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
9e803a04
SN
73 }
74 spin_unlock_irqrestore(&fimc->slock, flags);
75 return ret;
76}
77
bb7c276e
SN
78/*
79 * Reinitialize the driver so it is ready to start the streaming again.
80 * Set fimc->state to indicate stream off and the hardware shut down state.
81 * If not suspending (@suspend is false), return any buffers to videobuf2.
82 * Otherwise put any owned buffers onto the pending buffers queue, so they
83 * can be re-spun when the device is being resumed. Also perform FIMC
84 * software reset and disable streaming on the whole pipeline if required.
85 */
3e4748d8 86static int fimc_capture_state_cleanup(struct fimc_dev *fimc, bool suspend)
5f3cc447 87{
bd323e28 88 struct fimc_vid_cap *cap = &fimc->vid_cap;
2dab38e2 89 struct fimc_vid_buffer *buf;
bd323e28 90 unsigned long flags;
3e4748d8 91 bool streaming;
5f3cc447
SN
92
93 spin_lock_irqsave(&fimc->slock, flags);
3e4748d8 94 streaming = fimc->state & (1 << ST_CAPT_ISP_STREAM);
5f3cc447 95
3e4748d8
SN
96 fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_SHUT |
97 1 << ST_CAPT_STREAM | 1 << ST_CAPT_ISP_STREAM);
aa333122
SN
98 if (suspend)
99 fimc->state |= (1 << ST_CAPT_SUSPENDED);
100 else
3e4748d8 101 fimc->state &= ~(1 << ST_CAPT_PEND | 1 << ST_CAPT_SUSPENDED);
2dab38e2 102
3e4748d8
SN
103 /* Release unused buffers */
104 while (!suspend && !list_empty(&cap->pending_buf_q)) {
0295202c 105 buf = fimc_pending_queue_pop(cap);
2dab38e2
SN
106 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
107 }
3e4748d8 108 /* If suspending put unused buffers onto pending queue */
2dab38e2 109 while (!list_empty(&cap->active_buf_q)) {
0295202c 110 buf = fimc_active_queue_pop(cap);
3e4748d8
SN
111 if (suspend)
112 fimc_pending_queue_add(cap, buf);
113 else
114 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
2dab38e2 115 }
2c1bb62e
SN
116
117 fimc_hw_reset(fimc);
118 cap->buf_index = 0;
119
5f3cc447 120 spin_unlock_irqrestore(&fimc->slock, flags);
4db5e27e 121
3e4748d8 122 if (streaming)
b9ee31e6
SN
123 return fimc_pipeline_call(fimc, set_stream,
124 &fimc->pipeline, 0);
4db5e27e
SN
125 else
126 return 0;
bd323e28
MS
127}
128
3e4748d8 129static int fimc_stop_capture(struct fimc_dev *fimc, bool suspend)
bd323e28 130{
bd323e28
MS
131 unsigned long flags;
132
133 if (!fimc_capture_active(fimc))
134 return 0;
135
136 spin_lock_irqsave(&fimc->slock, flags);
137 set_bit(ST_CAPT_SHUT, &fimc->state);
138 fimc_deactivate_capture(fimc);
139 spin_unlock_irqrestore(&fimc->slock, flags);
140
141 wait_event_timeout(fimc->irq_queue,
142 !test_bit(ST_CAPT_SHUT, &fimc->state),
3e4748d8 143 (2*HZ/10)); /* 200 ms */
5f3cc447 144
3e4748d8 145 return fimc_capture_state_cleanup(fimc, suspend);
5f3cc447
SN
146}
147
237e0265
SN
148/**
149 * fimc_capture_config_update - apply the camera interface configuration
150 *
151 * To be called from within the interrupt handler with fimc.slock
152 * spinlock held. It updates the camera pixel crop, rotation and
153 * image flip in H/W.
154 */
97d97422 155static int fimc_capture_config_update(struct fimc_ctx *ctx)
237e0265
SN
156{
157 struct fimc_dev *fimc = ctx->fimc_dev;
158 int ret;
159
237e0265 160 fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
efb13c3d 161
237e0265 162 ret = fimc_set_scaler_info(ctx);
efb13c3d
SN
163 if (ret)
164 return ret;
165
166 fimc_hw_set_prescaler(ctx);
167 fimc_hw_set_mainscaler(ctx);
168 fimc_hw_set_target_format(ctx);
169 fimc_hw_set_rotation(ctx);
9448ab7d 170 fimc_hw_set_effect(ctx);
efb13c3d
SN
171 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
172 fimc_hw_set_out_dma(ctx);
e80cb1fa 173 if (fimc->drv_data->alpha_color)
efb13c3d
SN
174 fimc_hw_set_rgb_alpha(ctx);
175
176 clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
237e0265
SN
177 return ret;
178}
bd323e28 179
97d97422
SN
180void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
181{
14783d25 182 struct v4l2_subdev *csis = fimc->pipeline.subdevs[IDX_CSIS];
97d97422 183 struct fimc_vid_cap *cap = &fimc->vid_cap;
14783d25 184 struct fimc_frame *f = &cap->ctx->d_frame;
97d97422
SN
185 struct fimc_vid_buffer *v_buf;
186 struct timeval *tv;
187 struct timespec ts;
188
189 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
190 wake_up(&fimc->irq_queue);
191 goto done;
192 }
193
194 if (!list_empty(&cap->active_buf_q) &&
195 test_bit(ST_CAPT_RUN, &fimc->state) && deq_buf) {
196 ktime_get_real_ts(&ts);
197
198 v_buf = fimc_active_queue_pop(cap);
199
200 tv = &v_buf->vb.v4l2_buf.timestamp;
201 tv->tv_sec = ts.tv_sec;
202 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
203 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
204
205 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
206 }
207
208 if (!list_empty(&cap->pending_buf_q)) {
209
210 v_buf = fimc_pending_queue_pop(cap);
211 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
212 v_buf->index = cap->buf_index;
213
214 /* Move the buffer to the capture active queue */
215 fimc_active_queue_add(cap, v_buf);
216
217 dbg("next frame: %d, done frame: %d",
218 fimc_hw_get_frame_index(fimc), v_buf->index);
219
220 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
221 cap->buf_index = 0;
222 }
14783d25
SN
223 /*
224 * Set up a buffer at MIPI-CSIS if current image format
225 * requires the frame embedded data capture.
226 */
227 if (f->fmt->mdataplanes && !list_empty(&cap->active_buf_q)) {
228 unsigned int plane = ffs(f->fmt->mdataplanes) - 1;
229 unsigned int size = f->payload[plane];
230 s32 index = fimc_hw_get_frame_index(fimc);
231 void *vaddr;
232
233 list_for_each_entry(v_buf, &cap->active_buf_q, list) {
234 if (v_buf->index != index)
235 continue;
236 vaddr = vb2_plane_vaddr(&v_buf->vb, plane);
237 v4l2_subdev_call(csis, video, s_rx_buffer,
238 vaddr, &size);
239 break;
240 }
241 }
97d97422
SN
242
243 if (cap->active_buf_cnt == 0) {
244 if (deq_buf)
245 clear_bit(ST_CAPT_RUN, &fimc->state);
246
247 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
248 cap->buf_index = 0;
249 } else {
250 set_bit(ST_CAPT_RUN, &fimc->state);
251 }
252
bb7c276e
SN
253 if (test_bit(ST_CAPT_APPLY_CFG, &fimc->state))
254 fimc_capture_config_update(cap->ctx);
97d97422
SN
255done:
256 if (cap->active_buf_cnt == 1) {
257 fimc_deactivate_capture(fimc);
258 clear_bit(ST_CAPT_STREAM, &fimc->state);
259 }
260
261 dbg("frame: %d, active_buf_cnt: %d",
262 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
263}
264
265
bd323e28 266static int start_streaming(struct vb2_queue *q, unsigned int count)
2dab38e2
SN
267{
268 struct fimc_ctx *ctx = q->drv_priv;
269 struct fimc_dev *fimc = ctx->fimc_dev;
9e803a04 270 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
bd323e28 271 int min_bufs;
2dab38e2
SN
272 int ret;
273
9e803a04 274 vid_cap->frame_count = 0;
8ec737ff 275
bb7c276e
SN
276 ret = fimc_capture_hw_init(fimc);
277 if (ret) {
278 fimc_capture_state_cleanup(fimc, false);
279 return ret;
280 }
2dab38e2 281
2dab38e2
SN
282 set_bit(ST_CAPT_PEND, &fimc->state);
283
bd323e28
MS
284 min_bufs = fimc->vid_cap.reqbufs_count > 1 ? 2 : 1;
285
4db5e27e
SN
286 if (vid_cap->active_buf_cnt >= min_bufs &&
287 !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
bd323e28
MS
288 fimc_activate_capture(ctx);
289
4db5e27e 290 if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
76323e50
AH
291 return fimc_pipeline_call(fimc, set_stream,
292 &fimc->pipeline, 1);
4db5e27e
SN
293 }
294
2dab38e2
SN
295 return 0;
296}
297
298static int stop_streaming(struct vb2_queue *q)
299{
300 struct fimc_ctx *ctx = q->drv_priv;
301 struct fimc_dev *fimc = ctx->fimc_dev;
2dab38e2 302
4ecbf5d1 303 if (!fimc_capture_active(fimc))
2dab38e2 304 return -EINVAL;
2dab38e2 305
3e4748d8 306 return fimc_stop_capture(fimc, false);
2dab38e2
SN
307}
308
e9e21083
SN
309int fimc_capture_suspend(struct fimc_dev *fimc)
310{
3e4748d8
SN
311 bool suspend = fimc_capture_busy(fimc);
312
313 int ret = fimc_stop_capture(fimc, suspend);
314 if (ret)
315 return ret;
b9ee31e6 316 return fimc_pipeline_call(fimc, close, &fimc->pipeline);
e9e21083
SN
317}
318
3e4748d8
SN
319static void buffer_queue(struct vb2_buffer *vb);
320
e9e21083
SN
321int fimc_capture_resume(struct fimc_dev *fimc)
322{
3e4748d8 323 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
bc7584b0 324 struct exynos_video_entity *ve = &vid_cap->ve;
3e4748d8
SN
325 struct fimc_vid_buffer *buf;
326 int i;
327
328 if (!test_and_clear_bit(ST_CAPT_SUSPENDED, &fimc->state))
329 return 0;
330
331 INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
332 vid_cap->buf_index = 0;
b9ee31e6 333 fimc_pipeline_call(fimc, open, &fimc->pipeline,
bc7584b0 334 &ve->vdev.entity, false);
bb7c276e 335 fimc_capture_hw_init(fimc);
3e4748d8
SN
336
337 clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
338
339 for (i = 0; i < vid_cap->reqbufs_count; i++) {
340 if (list_empty(&vid_cap->pending_buf_q))
341 break;
342 buf = fimc_pending_queue_pop(vid_cap);
343 buffer_queue(&buf->vb);
344 }
e9e21083 345 return 0;
3e4748d8 346
e9e21083
SN
347}
348
63746be5 349static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
fc714e70
GL
350 unsigned int *num_buffers, unsigned int *num_planes,
351 unsigned int sizes[], void *allocators[])
2dab38e2 352{
63746be5 353 const struct v4l2_pix_format_mplane *pixm = NULL;
2dab38e2 354 struct fimc_ctx *ctx = vq->drv_priv;
63746be5
SN
355 struct fimc_frame *frame = &ctx->d_frame;
356 struct fimc_fmt *fmt = frame->fmt;
357 unsigned long wh;
ef7af59b 358 int i;
2dab38e2 359
63746be5
SN
360 if (pfmt) {
361 pixm = &pfmt->fmt.pix_mp;
362 fmt = fimc_find_format(&pixm->pixelformat, NULL,
363 FMT_FLAGS_CAM | FMT_FLAGS_M2M, -1);
364 wh = pixm->width * pixm->height;
365 } else {
366 wh = frame->f_width * frame->f_height;
367 }
368
369 if (fmt == NULL)
2dab38e2
SN
370 return -EINVAL;
371
ef7af59b 372 *num_planes = fmt->memplanes;
2dab38e2 373
ef7af59b 374 for (i = 0; i < fmt->memplanes; i++) {
63746be5
SN
375 unsigned int size = (wh * fmt->depth[i]) / 8;
376 if (pixm)
377 sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
14783d25
SN
378 else if (fimc_fmt_is_user_defined(fmt->color))
379 sizes[i] = frame->payload[i];
63746be5 380 else
d547ab66
SN
381 sizes[i] = max_t(u32, size, frame->payload[i]);
382
ef7af59b
SN
383 allocators[i] = ctx->fimc_dev->alloc_ctx;
384 }
2dab38e2 385
ef7af59b 386 return 0;
2dab38e2
SN
387}
388
2dab38e2
SN
389static int buffer_prepare(struct vb2_buffer *vb)
390{
391 struct vb2_queue *vq = vb->vb2_queue;
392 struct fimc_ctx *ctx = vq->drv_priv;
2dab38e2
SN
393 int i;
394
4db5e27e 395 if (ctx->d_frame.fmt == NULL)
ef7af59b 396 return -EINVAL;
2dab38e2 397
ef7af59b 398 for (i = 0; i < ctx->d_frame.fmt->memplanes; i++) {
4db5e27e 399 unsigned long size = ctx->d_frame.payload[i];
2dab38e2
SN
400
401 if (vb2_plane_size(vb, i) < size) {
bc7584b0 402 v4l2_err(&ctx->fimc_dev->vid_cap.ve.vdev,
30c9939d 403 "User buffer too small (%ld < %ld)\n",
2dab38e2
SN
404 vb2_plane_size(vb, i), size);
405 return -EINVAL;
406 }
2dab38e2
SN
407 vb2_set_plane_payload(vb, i, size);
408 }
409
410 return 0;
411}
412
413static void buffer_queue(struct vb2_buffer *vb)
414{
2dab38e2
SN
415 struct fimc_vid_buffer *buf
416 = container_of(vb, struct fimc_vid_buffer, vb);
4db5e27e
SN
417 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
418 struct fimc_dev *fimc = ctx->fimc_dev;
2dab38e2 419 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
bc7584b0 420 struct exynos_video_entity *ve = &vid_cap->ve;
2dab38e2 421 unsigned long flags;
8ec737ff 422 int min_bufs;
2dab38e2
SN
423
424 spin_lock_irqsave(&fimc->slock, flags);
8ec737ff
SK
425 fimc_prepare_addr(ctx, &buf->vb, &ctx->d_frame, &buf->paddr);
426
3e4748d8
SN
427 if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) &&
428 !test_bit(ST_CAPT_STREAM, &fimc->state) &&
429 vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) {
8ec737ff
SK
430 /* Setup the buffer directly for processing. */
431 int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
432 vid_cap->buf_index;
2dab38e2 433
8ec737ff
SK
434 fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
435 buf->index = vid_cap->buf_index;
0295202c 436 fimc_active_queue_add(vid_cap, buf);
2dab38e2 437
8ec737ff
SK
438 if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS)
439 vid_cap->buf_index = 0;
440 } else {
441 fimc_pending_queue_add(vid_cap, buf);
2dab38e2 442 }
8ec737ff
SK
443
444 min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1;
445
4db5e27e 446
bd323e28
MS
447 if (vb2_is_streaming(&vid_cap->vbq) &&
448 vid_cap->active_buf_cnt >= min_bufs &&
4db5e27e 449 !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
76323e50
AH
450 int ret;
451
8ec737ff 452 fimc_activate_capture(ctx);
4db5e27e 453 spin_unlock_irqrestore(&fimc->slock, flags);
8ec737ff 454
76323e50
AH
455 if (test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
456 return;
457
458 ret = fimc_pipeline_call(fimc, set_stream, &fimc->pipeline, 1);
459 if (ret < 0)
bc7584b0 460 v4l2_err(&ve->vdev, "stream on failed: %d\n", ret);
4db5e27e
SN
461 return;
462 }
2dab38e2
SN
463 spin_unlock_irqrestore(&fimc->slock, flags);
464}
465
2dab38e2
SN
466static struct vb2_ops fimc_capture_qops = {
467 .queue_setup = queue_setup,
468 .buf_prepare = buffer_prepare,
469 .buf_queue = buffer_queue,
c444914a
SN
470 .wait_prepare = vb2_ops_wait_prepare,
471 .wait_finish = vb2_ops_wait_finish,
2dab38e2
SN
472 .start_streaming = start_streaming,
473 .stop_streaming = stop_streaming,
474};
475
237e0265
SN
476static int fimc_capture_set_default_format(struct fimc_dev *fimc);
477
5f3cc447
SN
478static int fimc_capture_open(struct file *file)
479{
480 struct fimc_dev *fimc = video_drvdata(file);
4403106d
SN
481 struct fimc_vid_cap *vc = &fimc->vid_cap;
482 struct exynos_video_entity *ve = &vc->ve;
c2d430af 483 int ret = -EBUSY;
5f3cc447
SN
484
485 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
486
740ad921 487 mutex_lock(&fimc->lock);
c2d430af 488
5f3cc447 489 if (fimc_m2m_active(fimc))
c2d430af 490 goto unlock;
5f3cc447 491
3e4748d8 492 set_bit(ST_CAPT_BUSY, &fimc->state);
e3fc82e8
SN
493 ret = pm_runtime_get_sync(&fimc->pdev->dev);
494 if (ret < 0)
c2d430af 495 goto unlock;
4db5e27e 496
e3fc82e8 497 ret = v4l2_fh_open(file);
c2d430af 498 if (ret) {
4bd728a1 499 pm_runtime_put_sync(&fimc->pdev->dev);
c2d430af
SN
500 goto unlock;
501 }
e3fc82e8 502
c444914a 503 if (v4l2_fh_is_singular_file(file)) {
42625fdf
SN
504 fimc_md_graph_lock(ve);
505
b9ee31e6 506 ret = fimc_pipeline_call(fimc, open, &fimc->pipeline,
bc7584b0 507 &fimc->vid_cap.ve.vdev.entity, true);
4403106d 508 if (ret == 0)
c2d430af
SN
509 ret = fimc_capture_set_default_format(fimc);
510
4403106d
SN
511 if (ret == 0 && vc->user_subdev_api && vc->inh_sensor_ctrls) {
512 /*
513 * Recreate controls of the the video node to drop
514 * any controls inherited from the sensor subdev.
515 */
516 fimc_ctrls_delete(vc->ctx);
517
518 ret = fimc_ctrls_create(vc->ctx);
519 if (ret == 0)
520 vc->inh_sensor_ctrls = false;
521 }
42625fdf
SN
522 if (ret == 0)
523 ve->vdev.entity.use_count++;
524
525 fimc_md_graph_unlock(ve);
e3fc82e8 526
c2d430af
SN
527 if (ret < 0) {
528 clear_bit(ST_CAPT_BUSY, &fimc->state);
529 pm_runtime_put_sync(&fimc->pdev->dev);
c2d430af
SN
530 v4l2_fh_release(file);
531 }
532 }
533unlock:
534 mutex_unlock(&fimc->lock);
131b6c61 535 return ret;
5f3cc447
SN
536}
537
c444914a 538static int fimc_capture_release(struct file *file)
5f3cc447
SN
539{
540 struct fimc_dev *fimc = video_drvdata(file);
9ea89e2b 541 struct fimc_vid_cap *vc = &fimc->vid_cap;
42625fdf 542 bool close = v4l2_fh_is_singular_file(file);
c2d430af 543 int ret;
5f3cc447 544
5f3cc447
SN
545 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
546
ba6b372c 547 mutex_lock(&fimc->lock);
c2d430af 548
42625fdf
SN
549 if (close && vc->streaming) {
550 media_entity_pipeline_stop(&vc->ve.vdev.entity);
551 vc->streaming = false;
552 }
553
554 ret = vb2_fop_release(file);
555
556 if (close) {
3e4748d8
SN
557 clear_bit(ST_CAPT_BUSY, &fimc->state);
558 fimc_stop_capture(fimc, false);
b9ee31e6 559 fimc_pipeline_call(fimc, close, &fimc->pipeline);
3e4748d8 560 clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
42625fdf
SN
561
562 fimc_md_graph_lock(&vc->ve);
563 vc->ve.vdev.entity.use_count--;
564 fimc_md_graph_unlock(&vc->ve);
5f3cc447
SN
565 }
566
4bd728a1 567 pm_runtime_put_sync(&fimc->pdev->dev);
c2d430af
SN
568 mutex_unlock(&fimc->lock);
569
570 return ret;
5f3cc447
SN
571}
572
5f3cc447
SN
573static const struct v4l2_file_operations fimc_capture_fops = {
574 .owner = THIS_MODULE,
575 .open = fimc_capture_open,
c444914a
SN
576 .release = fimc_capture_release,
577 .poll = vb2_fop_poll,
5f3cc447 578 .unlocked_ioctl = video_ioctl2,
c444914a 579 .mmap = vb2_fop_mmap,
5f3cc447
SN
580};
581
237e0265
SN
582/*
583 * Format and crop negotiation helpers
584 */
585
586static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx,
587 u32 *width, u32 *height,
588 u32 *code, u32 *fourcc, int pad)
589{
590 bool rotation = ctx->rotation == 90 || ctx->rotation == 270;
591 struct fimc_dev *fimc = ctx->fimc_dev;
405f230c
SN
592 const struct fimc_variant *var = fimc->variant;
593 const struct fimc_pix_limit *pl = var->pix_limit;
237e0265
SN
594 struct fimc_frame *dst = &ctx->d_frame;
595 u32 depth, min_w, max_w, min_h, align_h = 3;
596 u32 mask = FMT_FLAGS_CAM;
597 struct fimc_fmt *ffmt;
598
14783d25 599 /* Conversion from/to JPEG or User Defined format is not supported */
237e0265 600 if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE &&
14783d25
SN
601 fimc_fmt_is_user_defined(ctx->s_frame.fmt->color))
602 *code = ctx->s_frame.fmt->mbus_code;
237e0265 603
88fa8311 604 if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad == FIMC_SD_PAD_SOURCE)
237e0265
SN
605 mask |= FMT_FLAGS_M2M;
606
88fa8311
SN
607 if (pad == FIMC_SD_PAD_SINK_FIFO)
608 mask = FMT_FLAGS_WRITEBACK;
609
237e0265
SN
610 ffmt = fimc_find_format(fourcc, code, mask, 0);
611 if (WARN_ON(!ffmt))
612 return NULL;
88fa8311 613
237e0265
SN
614 if (code)
615 *code = ffmt->mbus_code;
616 if (fourcc)
617 *fourcc = ffmt->fourcc;
618
88fa8311 619 if (pad != FIMC_SD_PAD_SOURCE) {
14783d25 620 max_w = fimc_fmt_is_user_defined(ffmt->color) ?
237e0265
SN
621 pl->scaler_dis_w : pl->scaler_en_w;
622 /* Apply the camera input interface pixel constraints */
623 v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4,
624 height, max_t(u32, *height, 32),
625 FIMC_CAMIF_MAX_HEIGHT,
14783d25
SN
626 fimc_fmt_is_user_defined(ffmt->color) ?
627 3 : 1,
237e0265
SN
628 0);
629 return ffmt;
630 }
631 /* Can't scale or crop in transparent (JPEG) transfer mode */
14783d25 632 if (fimc_fmt_is_user_defined(ffmt->color)) {
237e0265
SN
633 *width = ctx->s_frame.f_width;
634 *height = ctx->s_frame.f_height;
635 return ffmt;
636 }
637 /* Apply the scaler and the output DMA constraints */
638 max_w = rotation ? pl->out_rot_en_w : pl->out_rot_dis_w;
fed07f84
SN
639 if (ctx->state & FIMC_COMPOSE) {
640 min_w = dst->offs_h + dst->width;
641 min_h = dst->offs_v + dst->height;
642 } else {
643 min_w = var->min_out_pixsize;
644 min_h = var->min_out_pixsize;
645 }
9c63afcb 646 if (var->min_vsize_align == 1 && !rotation)
237e0265
SN
647 align_h = fimc_fmt_is_rgb(ffmt->color) ? 0 : 1;
648
649 depth = fimc_get_format_depth(ffmt);
650 v4l_bound_align_image(width, min_w, max_w,
651 ffs(var->min_out_pixsize) - 1,
652 height, min_h, FIMC_CAMIF_MAX_HEIGHT,
653 align_h,
654 64/(ALIGN(depth, 8)));
655
656 dbg("pad%d: code: 0x%x, %dx%d. dst fmt: %dx%d",
657 pad, code ? *code : 0, *width, *height,
658 dst->f_width, dst->f_height);
659
660 return ffmt;
661}
662
fed07f84
SN
663static void fimc_capture_try_selection(struct fimc_ctx *ctx,
664 struct v4l2_rect *r,
665 int target)
237e0265
SN
666{
667 bool rotate = ctx->rotation == 90 || ctx->rotation == 270;
668 struct fimc_dev *fimc = ctx->fimc_dev;
405f230c
SN
669 const struct fimc_variant *var = fimc->variant;
670 const struct fimc_pix_limit *pl = var->pix_limit;
237e0265
SN
671 struct fimc_frame *sink = &ctx->s_frame;
672 u32 max_w, max_h, min_w = 0, min_h = 0, min_sz;
673 u32 align_sz = 0, align_h = 4;
674 u32 max_sc_h, max_sc_v;
675
676 /* In JPEG transparent transfer mode cropping is not supported */
14783d25 677 if (fimc_fmt_is_user_defined(ctx->d_frame.fmt->color)) {
237e0265
SN
678 r->width = sink->f_width;
679 r->height = sink->f_height;
680 r->left = r->top = 0;
681 return;
682 }
c1334823 683 if (target == V4L2_SEL_TGT_COMPOSE) {
237e0265
SN
684 if (ctx->rotation != 90 && ctx->rotation != 270)
685 align_h = 1;
686 max_sc_h = min(SCALER_MAX_HRATIO, 1 << (ffs(sink->width) - 3));
687 max_sc_v = min(SCALER_MAX_VRATIO, 1 << (ffs(sink->height) - 1));
688 min_sz = var->min_out_pixsize;
689 } else {
690 u32 depth = fimc_get_format_depth(sink->fmt);
691 align_sz = 64/ALIGN(depth, 8);
692 min_sz = var->min_inp_pixsize;
693 min_w = min_h = min_sz;
694 max_sc_h = max_sc_v = 1;
695 }
696 /*
fed07f84 697 * For the compose rectangle the following constraints must be met:
237e0265
SN
698 * - it must fit in the sink pad format rectangle (f_width/f_height);
699 * - maximum downscaling ratio is 64;
700 * - maximum crop size depends if the rotator is used or not;
701 * - the sink pad format width/height must be 4 multiple of the
702 * prescaler ratios determined by sink pad size and source pad crop,
703 * the prescaler ratio is returned by fimc_get_scaler_factor().
704 */
705 max_w = min_t(u32,
706 rotate ? pl->out_rot_en_w : pl->out_rot_dis_w,
707 rotate ? sink->f_height : sink->f_width);
708 max_h = min_t(u32, FIMC_CAMIF_MAX_HEIGHT, sink->f_height);
fed07f84 709
c1334823 710 if (target == V4L2_SEL_TGT_COMPOSE) {
237e0265
SN
711 min_w = min_t(u32, max_w, sink->f_width / max_sc_h);
712 min_h = min_t(u32, max_h, sink->f_height / max_sc_v);
713 if (rotate) {
714 swap(max_sc_h, max_sc_v);
715 swap(min_w, min_h);
716 }
717 }
718 v4l_bound_align_image(&r->width, min_w, max_w, ffs(min_sz) - 1,
719 &r->height, min_h, max_h, align_h,
720 align_sz);
fed07f84 721 /* Adjust left/top if crop/compose rectangle is out of bounds */
237e0265
SN
722 r->left = clamp_t(u32, r->left, 0, sink->f_width - r->width);
723 r->top = clamp_t(u32, r->top, 0, sink->f_height - r->height);
724 r->left = round_down(r->left, var->hor_offs_align);
725
fed07f84
SN
726 dbg("target %#x: (%d,%d)/%dx%d, sink fmt: %dx%d",
727 target, r->left, r->top, r->width, r->height,
237e0265
SN
728 sink->f_width, sink->f_height);
729}
730
731/*
732 * The video node ioctl operations
733 */
aceb59ed 734static int fimc_cap_querycap(struct file *file, void *priv,
5f3cc447
SN
735 struct v4l2_capability *cap)
736{
e578588e 737 struct fimc_dev *fimc = video_drvdata(file);
5f3cc447 738
aceb59ed
SN
739 __fimc_vidioc_querycap(&fimc->pdev->dev, cap, V4L2_CAP_STREAMING |
740 V4L2_CAP_VIDEO_CAPTURE_MPLANE);
5f3cc447
SN
741 return 0;
742}
743
cf52df8a
SN
744static int fimc_cap_enum_fmt_mplane(struct file *file, void *priv,
745 struct v4l2_fmtdesc *f)
746{
747 struct fimc_fmt *fmt;
748
749 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM | FMT_FLAGS_M2M,
750 f->index);
751 if (!fmt)
752 return -EINVAL;
753 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
754 f->pixelformat = fmt->fourcc;
755 if (fmt->fourcc == V4L2_MBUS_FMT_JPEG_1X8)
756 f->flags |= V4L2_FMT_FLAG_COMPRESSED;
757 return 0;
758}
759
47800bc4
SN
760static struct media_entity *fimc_pipeline_get_head(struct media_entity *me)
761{
762 struct media_pad *pad = &me->pads[0];
763
764 while (!(pad->flags & MEDIA_PAD_FL_SOURCE)) {
1bddf1b3 765 pad = media_entity_remote_pad(pad);
47800bc4
SN
766 if (!pad)
767 break;
768 me = pad->entity;
769 pad = &me->pads[0];
770 }
771
772 return me;
773}
774
237e0265
SN
775/**
776 * fimc_pipeline_try_format - negotiate and/or set formats at pipeline
777 * elements
778 * @ctx: FIMC capture context
779 * @tfmt: media bus format to try/set on subdevs
780 * @fmt_id: fimc pixel format id corresponding to returned @tfmt (output)
781 * @set: true to set format on subdevs, false to try only
782 */
783static int fimc_pipeline_try_format(struct fimc_ctx *ctx,
784 struct v4l2_mbus_framefmt *tfmt,
785 struct fimc_fmt **fmt_id,
786 bool set)
787{
788 struct fimc_dev *fimc = ctx->fimc_dev;
0f735f52 789 struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
237e0265
SN
790 struct v4l2_subdev_format sfmt;
791 struct v4l2_mbus_framefmt *mf = &sfmt.format;
47800bc4
SN
792 struct media_entity *me;
793 struct fimc_fmt *ffmt;
794 struct media_pad *pad;
795 int ret, i = 1;
796 u32 fcc;
237e0265
SN
797
798 if (WARN_ON(!sd || !tfmt))
799 return -EINVAL;
5f3cc447 800
237e0265
SN
801 memset(&sfmt, 0, sizeof(sfmt));
802 sfmt.format = *tfmt;
237e0265 803 sfmt.which = set ? V4L2_SUBDEV_FORMAT_ACTIVE : V4L2_SUBDEV_FORMAT_TRY;
47800bc4
SN
804
805 me = fimc_pipeline_get_head(&sd->entity);
806
237e0265
SN
807 while (1) {
808 ffmt = fimc_find_format(NULL, mf->code != 0 ? &mf->code : NULL,
809 FMT_FLAGS_CAM, i++);
810 if (ffmt == NULL) {
811 /*
812 * Notify user-space if common pixel code for
813 * host and sensor does not exist.
814 */
815 return -EINVAL;
816 }
817 mf->code = tfmt->code = ffmt->mbus_code;
5f3cc447 818
47800bc4
SN
819 /* set format on all pipeline subdevs */
820 while (me != &fimc->vid_cap.subdev.entity) {
821 sd = media_entity_to_v4l2_subdev(me);
822
823 sfmt.pad = 0;
824 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &sfmt);
825 if (ret)
826 return ret;
827
828 if (me->pads[0].flags & MEDIA_PAD_FL_SINK) {
829 sfmt.pad = me->num_pads - 1;
830 mf->code = tfmt->code;
831 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL,
832 &sfmt);
833 if (ret)
834 return ret;
835 }
836
1bddf1b3 837 pad = media_entity_remote_pad(&me->pads[sfmt.pad]);
47800bc4
SN
838 if (!pad)
839 return -EINVAL;
840 me = pad->entity;
237e0265 841 }
5f3cc447 842
47800bc4
SN
843 if (mf->code != tfmt->code)
844 continue;
845
846 fcc = ffmt->fourcc;
847 tfmt->width = mf->width;
848 tfmt->height = mf->height;
849 ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height,
88fa8311 850 NULL, &fcc, FIMC_SD_PAD_SINK_CAM);
47800bc4
SN
851 ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height,
852 NULL, &fcc, FIMC_SD_PAD_SOURCE);
853 if (ffmt && ffmt->mbus_code)
854 mf->code = ffmt->mbus_code;
855 if (mf->width != tfmt->width || mf->height != tfmt->height)
856 continue;
857 tfmt->code = mf->code;
858 break;
237e0265 859 }
5f3cc447 860
237e0265
SN
861 if (fmt_id && ffmt)
862 *fmt_id = ffmt;
863 *tfmt = *mf;
5f3cc447 864
237e0265
SN
865 return 0;
866}
5f3cc447 867
14783d25
SN
868/**
869 * fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters
870 * @sensor: pointer to the sensor subdev
871 * @plane_fmt: provides plane sizes corresponding to the frame layout entries
872 * @try: true to set the frame parameters, false to query only
873 *
874 * This function is used by this driver only for compressed/blob data formats.
875 */
876static int fimc_get_sensor_frame_desc(struct v4l2_subdev *sensor,
877 struct v4l2_plane_pix_format *plane_fmt,
878 unsigned int num_planes, bool try)
879{
880 struct v4l2_mbus_frame_desc fd;
881 int i, ret;
1c9f5bd7 882 int pad;
14783d25
SN
883
884 for (i = 0; i < num_planes; i++)
885 fd.entry[i].length = plane_fmt[i].sizeimage;
886
1c9f5bd7 887 pad = sensor->entity.num_pads - 1;
14783d25 888 if (try)
1c9f5bd7 889 ret = v4l2_subdev_call(sensor, pad, set_frame_desc, pad, &fd);
14783d25 890 else
1c9f5bd7 891 ret = v4l2_subdev_call(sensor, pad, get_frame_desc, pad, &fd);
14783d25
SN
892
893 if (ret < 0)
894 return ret;
895
896 if (num_planes != fd.num_entries)
897 return -EINVAL;
898
899 for (i = 0; i < num_planes; i++)
900 plane_fmt[i].sizeimage = fd.entry[i].length;
901
902 if (fd.entry[0].length > FIMC_MAX_JPEG_BUF_SIZE) {
903 v4l2_err(sensor->v4l2_dev, "Unsupported buffer size: %u\n",
904 fd.entry[0].length);
905
906 return -EINVAL;
907 }
908
909 return 0;
910}
911
e578588e
SN
912static int fimc_cap_g_fmt_mplane(struct file *file, void *fh,
913 struct v4l2_format *f)
914{
915 struct fimc_dev *fimc = video_drvdata(file);
e578588e 916
fa8880be
SN
917 __fimc_get_format(&fimc->vid_cap.ctx->d_frame, f);
918 return 0;
e578588e
SN
919}
920
921static int fimc_cap_try_fmt_mplane(struct file *file, void *fh,
922 struct v4l2_format *f)
923{
237e0265 924 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
e578588e
SN
925 struct fimc_dev *fimc = video_drvdata(file);
926 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
bc7584b0 927 struct exynos_video_entity *ve = &fimc->vid_cap.ve;
237e0265
SN
928 struct v4l2_mbus_framefmt mf;
929 struct fimc_fmt *ffmt = NULL;
740ad921
SN
930 int ret = 0;
931
14783d25 932 if (fimc_jpeg_fourcc(pix->pixelformat)) {
237e0265
SN
933 fimc_capture_try_format(ctx, &pix->width, &pix->height,
934 NULL, &pix->pixelformat,
88fa8311 935 FIMC_SD_PAD_SINK_CAM);
237e0265
SN
936 ctx->s_frame.f_width = pix->width;
937 ctx->s_frame.f_height = pix->height;
938 }
939 ffmt = fimc_capture_try_format(ctx, &pix->width, &pix->height,
940 NULL, &pix->pixelformat,
941 FIMC_SD_PAD_SOURCE);
42625fdf
SN
942 if (!ffmt)
943 return -EINVAL;
237e0265
SN
944
945 if (!fimc->vid_cap.user_subdev_api) {
14783d25 946 mf.width = pix->width;
237e0265 947 mf.height = pix->height;
14783d25 948 mf.code = ffmt->mbus_code;
42625fdf
SN
949
950 fimc_md_graph_lock(ve);
237e0265 951 fimc_pipeline_try_format(ctx, &mf, &ffmt, false);
42625fdf
SN
952 fimc_md_graph_unlock(ve);
953
14783d25
SN
954 pix->width = mf.width;
955 pix->height = mf.height;
237e0265
SN
956 if (ffmt)
957 pix->pixelformat = ffmt->fourcc;
958 }
e578588e 959
237e0265 960 fimc_adjust_mplane_format(ffmt, pix->width, pix->height, pix);
14783d25
SN
961
962 if (ffmt->flags & FMT_FLAGS_COMPRESSED)
963 fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
964 pix->plane_fmt, ffmt->memplanes, true);
965
740ad921 966 return ret;
e578588e
SN
967}
968
14783d25
SN
969static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx,
970 enum fimc_color_fmt color)
ee7160e5 971{
14783d25
SN
972 bool jpeg = fimc_fmt_is_user_defined(color);
973
ee7160e5
SN
974 ctx->scaler.enabled = !jpeg;
975 fimc_ctrls_activate(ctx, !jpeg);
976
977 if (jpeg)
978 set_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
979 else
980 clear_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
981}
982
740ad921
SN
983static int __fimc_capture_set_format(struct fimc_dev *fimc,
984 struct v4l2_format *f)
5f3cc447 985{
e578588e 986 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
237e0265 987 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
88fa8311 988 struct v4l2_mbus_framefmt *mf = &fimc->vid_cap.ci_fmt;
237e0265
SN
989 struct fimc_frame *ff = &ctx->d_frame;
990 struct fimc_fmt *s_fmt = NULL;
991 int ret, i;
5f3cc447 992
237e0265 993 if (vb2_is_busy(&fimc->vid_cap.vbq))
ef7af59b 994 return -EBUSY;
5f3cc447 995
237e0265 996 /* Pre-configure format at camera interface input, for JPEG only */
14783d25 997 if (fimc_jpeg_fourcc(pix->pixelformat)) {
237e0265
SN
998 fimc_capture_try_format(ctx, &pix->width, &pix->height,
999 NULL, &pix->pixelformat,
88fa8311 1000 FIMC_SD_PAD_SINK_CAM);
237e0265
SN
1001 ctx->s_frame.f_width = pix->width;
1002 ctx->s_frame.f_height = pix->height;
1003 }
1004 /* Try the format at the scaler and the DMA output */
1005 ff->fmt = fimc_capture_try_format(ctx, &pix->width, &pix->height,
1006 NULL, &pix->pixelformat,
1007 FIMC_SD_PAD_SOURCE);
1008 if (!ff->fmt)
8293ebfc 1009 return -EINVAL;
dafb9c70
SN
1010
1011 /* Update RGB Alpha control state and value range */
1012 fimc_alpha_ctrl_update(ctx);
1013
237e0265
SN
1014 /* Try to match format at the host and the sensor */
1015 if (!fimc->vid_cap.user_subdev_api) {
1016 mf->code = ff->fmt->mbus_code;
1017 mf->width = pix->width;
1018 mf->height = pix->height;
237e0265 1019 ret = fimc_pipeline_try_format(ctx, mf, &s_fmt, true);
237e0265
SN
1020 if (ret)
1021 return ret;
740ad921 1022
237e0265
SN
1023 pix->width = mf->width;
1024 pix->height = mf->height;
1025 }
d547ab66 1026
237e0265 1027 fimc_adjust_mplane_format(ff->fmt, pix->width, pix->height, pix);
14783d25
SN
1028
1029 if (ff->fmt->flags & FMT_FLAGS_COMPRESSED) {
1030 ret = fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
1031 pix->plane_fmt, ff->fmt->memplanes,
1032 true);
1033 if (ret < 0)
1034 return ret;
1035 }
1036
fa8880be
SN
1037 for (i = 0; i < ff->fmt->memplanes; i++) {
1038 ff->bytesperline[i] = pix->plane_fmt[i].bytesperline;
d547ab66 1039 ff->payload[i] = pix->plane_fmt[i].sizeimage;
fa8880be 1040 }
237e0265
SN
1041
1042 set_frame_bounds(ff, pix->width, pix->height);
1043 /* Reset the composition rectangle if not yet configured */
fed07f84 1044 if (!(ctx->state & FIMC_COMPOSE))
237e0265
SN
1045 set_frame_crop(ff, 0, 0, pix->width, pix->height);
1046
14783d25 1047 fimc_capture_mark_jpeg_xfer(ctx, ff->fmt->color);
ee7160e5 1048
237e0265
SN
1049 /* Reset cropping and set format at the camera interface input */
1050 if (!fimc->vid_cap.user_subdev_api) {
1051 ctx->s_frame.fmt = s_fmt;
1052 set_frame_bounds(&ctx->s_frame, pix->width, pix->height);
1053 set_frame_crop(&ctx->s_frame, 0, 0, pix->width, pix->height);
045030fa 1054 }
ef7af59b 1055
237e0265
SN
1056 return ret;
1057}
5f3cc447 1058
237e0265
SN
1059static int fimc_cap_s_fmt_mplane(struct file *file, void *priv,
1060 struct v4l2_format *f)
1061{
1062 struct fimc_dev *fimc = video_drvdata(file);
740ad921
SN
1063 int ret;
1064
bc7584b0 1065 fimc_md_graph_lock(&fimc->vid_cap.ve);
740ad921
SN
1066 /*
1067 * The graph is walked within __fimc_capture_set_format() to set
1068 * the format at subdevs thus the graph mutex needs to be held at
42625fdf 1069 * this point.
740ad921
SN
1070 */
1071 ret = __fimc_capture_set_format(fimc, f);
5f3cc447 1072
bc7584b0 1073 fimc_md_graph_unlock(&fimc->vid_cap.ve);
740ad921 1074 return ret;
5f3cc447
SN
1075}
1076
1077static int fimc_cap_enum_input(struct file *file, void *priv,
3e002182 1078 struct v4l2_input *i)
5f3cc447 1079{
e578588e 1080 struct fimc_dev *fimc = video_drvdata(file);
0f735f52 1081 struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
5f3cc447 1082
3e002182 1083 if (i->index != 0)
5f3cc447
SN
1084 return -EINVAL;
1085
5f3cc447 1086 i->type = V4L2_INPUT_TYPE_CAMERA;
4db5e27e
SN
1087 if (sd)
1088 strlcpy(i->name, sd->name, sizeof(i->name));
5f3cc447
SN
1089 return 0;
1090}
1091
3e002182 1092static int fimc_cap_s_input(struct file *file, void *priv, unsigned int i)
5f3cc447 1093{
3e002182 1094 return i == 0 ? i : -EINVAL;
5f3cc447
SN
1095}
1096
3e002182 1097static int fimc_cap_g_input(struct file *file, void *priv, unsigned int *i)
5f3cc447 1098{
3e002182 1099 *i = 0;
5f3cc447
SN
1100 return 0;
1101}
1102
237e0265
SN
1103/**
1104 * fimc_pipeline_validate - check for formats inconsistencies
1105 * between source and sink pad of each link
1106 *
1107 * Return 0 if all formats match or -EPIPE otherwise.
1108 */
1109static int fimc_pipeline_validate(struct fimc_dev *fimc)
1110{
1111 struct v4l2_subdev_format sink_fmt, src_fmt;
88fa8311
SN
1112 struct fimc_vid_cap *vc = &fimc->vid_cap;
1113 struct v4l2_subdev *sd = &vc->subdev;
1114 struct media_pad *sink_pad, *src_pad;
1115 int i, ret;
237e0265
SN
1116
1117 while (1) {
88fa8311
SN
1118 /*
1119 * Find current entity sink pad and any remote sink pad linked
1120 * to it. We stop if there is no sink pad in current entity or
1121 * it is not linked to any other remote entity.
1122 */
1123 src_pad = NULL;
1124
1125 for (i = 0; i < sd->entity.num_pads; i++) {
1126 struct media_pad *p = &sd->entity.pads[i];
1127
1128 if (p->flags & MEDIA_PAD_FL_SINK) {
1129 sink_pad = p;
1bddf1b3 1130 src_pad = media_entity_remote_pad(sink_pad);
88fa8311
SN
1131 if (src_pad)
1132 break;
1133 }
1134 }
1135
1136 if (src_pad == NULL ||
1137 media_entity_type(src_pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
237e0265 1138 break;
88fa8311 1139
237e0265 1140 /* Don't call FIMC subdev operation to avoid nested locking */
88fa8311
SN
1141 if (sd == &vc->subdev) {
1142 struct fimc_frame *ff = &vc->ctx->s_frame;
237e0265
SN
1143 sink_fmt.format.width = ff->f_width;
1144 sink_fmt.format.height = ff->f_height;
1145 sink_fmt.format.code = ff->fmt ? ff->fmt->mbus_code : 0;
1146 } else {
88fa8311 1147 sink_fmt.pad = sink_pad->index;
237e0265
SN
1148 sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1149 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt);
1150 if (ret < 0 && ret != -ENOIOCTLCMD)
1151 return -EPIPE;
1152 }
237e0265 1153
88fa8311
SN
1154 /* Retrieve format at the source pad */
1155 sd = media_entity_to_v4l2_subdev(src_pad->entity);
1156 src_fmt.pad = src_pad->index;
237e0265
SN
1157 src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1158 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
1159 if (ret < 0 && ret != -ENOIOCTLCMD)
1160 return -EPIPE;
1161
1162 if (src_fmt.format.width != sink_fmt.format.width ||
1163 src_fmt.format.height != sink_fmt.format.height ||
1164 src_fmt.format.code != sink_fmt.format.code)
1165 return -EPIPE;
14783d25
SN
1166
1167 if (sd == fimc->pipeline.subdevs[IDX_SENSOR] &&
1168 fimc_user_defined_mbus_fmt(src_fmt.format.code)) {
1169 struct v4l2_plane_pix_format plane_fmt[FIMC_MAX_PLANES];
88fa8311 1170 struct fimc_frame *frame = &vc->ctx->d_frame;
14783d25
SN
1171 unsigned int i;
1172
1173 ret = fimc_get_sensor_frame_desc(sd, plane_fmt,
1174 frame->fmt->memplanes,
1175 false);
1176 if (ret < 0)
1177 return -EPIPE;
1178
1179 for (i = 0; i < frame->fmt->memplanes; i++)
1180 if (frame->payload[i] < plane_fmt[i].sizeimage)
1181 return -EPIPE;
1182 }
237e0265
SN
1183 }
1184 return 0;
1185}
1186
5f3cc447 1187static int fimc_cap_streamon(struct file *file, void *priv,
2dab38e2 1188 enum v4l2_buf_type type)
5f3cc447 1189{
e578588e 1190 struct fimc_dev *fimc = video_drvdata(file);
4db5e27e 1191 struct fimc_pipeline *p = &fimc->pipeline;
95c4a17f 1192 struct fimc_vid_cap *vc = &fimc->vid_cap;
bc7584b0 1193 struct media_entity *entity = &vc->ve.vdev.entity;
88fa8311
SN
1194 struct fimc_source_info *si = NULL;
1195 struct v4l2_subdev *sd;
237e0265 1196 int ret;
5f3cc447 1197
4db5e27e 1198 if (fimc_capture_active(fimc))
8293ebfc 1199 return -EBUSY;
5f3cc447 1200
95c4a17f 1201 ret = media_entity_pipeline_start(entity, p->m_pipeline);
a60a2959
SA
1202 if (ret < 0)
1203 return ret;
5f3cc447 1204
88fa8311
SN
1205 sd = p->subdevs[IDX_SENSOR];
1206 if (sd)
1207 si = v4l2_get_subdev_hostdata(sd);
1208
1209 if (si == NULL) {
1210 ret = -EPIPE;
1211 goto err_p_stop;
1212 }
1213 /*
1214 * Save configuration data related to currently attached image
1215 * sensor or other data source, e.g. FIMC-IS.
1216 */
1217 vc->source_config = *si;
1218
1219 if (vc->input == GRP_ID_FIMC_IS)
1220 vc->source_config.fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK;
1221
95c4a17f 1222 if (vc->user_subdev_api) {
237e0265 1223 ret = fimc_pipeline_validate(fimc);
95c4a17f
SN
1224 if (ret < 0)
1225 goto err_p_stop;
237e0265 1226 }
95c4a17f 1227
c444914a 1228 ret = vb2_ioctl_streamon(file, priv, type);
9ea89e2b
SN
1229 if (!ret) {
1230 vc->streaming = true;
95c4a17f 1231 return ret;
9ea89e2b 1232 }
95c4a17f
SN
1233
1234err_p_stop:
1235 media_entity_pipeline_stop(entity);
1236 return ret;
5f3cc447
SN
1237}
1238
1239static int fimc_cap_streamoff(struct file *file, void *priv,
8293ebfc 1240 enum v4l2_buf_type type)
5f3cc447 1241{
e578588e 1242 struct fimc_dev *fimc = video_drvdata(file);
bc7584b0 1243 struct fimc_vid_cap *vc = &fimc->vid_cap;
4db5e27e 1244 int ret;
5f3cc447 1245
c444914a 1246 ret = vb2_ioctl_streamoff(file, priv, type);
9ea89e2b
SN
1247 if (ret < 0)
1248 return ret;
95c4a17f 1249
bc7584b0
SN
1250 media_entity_pipeline_stop(&vc->ve.vdev.entity);
1251 vc->streaming = false;
9ea89e2b 1252 return 0;
5f3cc447
SN
1253}
1254
1255static int fimc_cap_reqbufs(struct file *file, void *priv,
ef7af59b 1256 struct v4l2_requestbuffers *reqbufs)
5f3cc447 1257{
e578588e 1258 struct fimc_dev *fimc = video_drvdata(file);
c444914a
SN
1259 int ret;
1260
1261 ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
5f3cc447 1262
5f3cc447 1263 if (!ret)
e578588e 1264 fimc->vid_cap.reqbufs_count = reqbufs->count;
3b4c34aa 1265
c444914a 1266 return ret;
3b4c34aa
SN
1267}
1268
f9331d11
SN
1269static int fimc_cap_g_selection(struct file *file, void *fh,
1270 struct v4l2_selection *s)
e004e02f 1271{
e578588e 1272 struct fimc_dev *fimc = video_drvdata(file);
f9331d11
SN
1273 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
1274 struct fimc_frame *f = &ctx->s_frame;
e004e02f 1275
f9331d11 1276 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
e004e02f
SN
1277 return -EINVAL;
1278
f9331d11
SN
1279 switch (s->target) {
1280 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1281 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1282 f = &ctx->d_frame;
1283 case V4L2_SEL_TGT_CROP_BOUNDS:
1284 case V4L2_SEL_TGT_CROP_DEFAULT:
1285 s->r.left = 0;
1286 s->r.top = 0;
1287 s->r.width = f->o_width;
1288 s->r.height = f->o_height;
1289 return 0;
e004e02f 1290
c1334823 1291 case V4L2_SEL_TGT_COMPOSE:
f9331d11 1292 f = &ctx->d_frame;
c1334823 1293 case V4L2_SEL_TGT_CROP:
f9331d11
SN
1294 s->r.left = f->offs_h;
1295 s->r.top = f->offs_v;
1296 s->r.width = f->width;
1297 s->r.height = f->height;
1298 return 0;
1299 }
1300
1301 return -EINVAL;
e004e02f
SN
1302}
1303
f9331d11 1304/* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
7e566be2 1305static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
e004e02f 1306{
f9331d11
SN
1307 if (a->left < b->left || a->top < b->top)
1308 return 0;
1309 if (a->left + a->width > b->left + b->width)
1310 return 0;
1311 if (a->top + a->height > b->top + b->height)
1312 return 0;
e004e02f 1313
f9331d11 1314 return 1;
e004e02f
SN
1315}
1316
f9331d11
SN
1317static int fimc_cap_s_selection(struct file *file, void *fh,
1318 struct v4l2_selection *s)
5f3cc447 1319{
e578588e
SN
1320 struct fimc_dev *fimc = video_drvdata(file);
1321 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
f9331d11
SN
1322 struct v4l2_rect rect = s->r;
1323 struct fimc_frame *f;
237e0265 1324 unsigned long flags;
f9331d11
SN
1325
1326 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1327 return -EINVAL;
1328
c1334823 1329 if (s->target == V4L2_SEL_TGT_COMPOSE)
f9331d11 1330 f = &ctx->d_frame;
c1334823 1331 else if (s->target == V4L2_SEL_TGT_CROP)
f9331d11 1332 f = &ctx->s_frame;
fed07f84 1333 else
f9331d11 1334 return -EINVAL;
f9331d11 1335
fed07f84 1336 fimc_capture_try_selection(ctx, &rect, s->target);
f9331d11
SN
1337
1338 if (s->flags & V4L2_SEL_FLAG_LE &&
1339 !enclosed_rectangle(&rect, &s->r))
1340 return -ERANGE;
5f3cc447 1341
f9331d11
SN
1342 if (s->flags & V4L2_SEL_FLAG_GE &&
1343 !enclosed_rectangle(&s->r, &rect))
1344 return -ERANGE;
5f3cc447 1345
f9331d11 1346 s->r = rect;
237e0265 1347 spin_lock_irqsave(&fimc->slock, flags);
f9331d11
SN
1348 set_frame_crop(f, s->r.left, s->r.top, s->r.width,
1349 s->r.height);
237e0265 1350 spin_unlock_irqrestore(&fimc->slock, flags);
8293ebfc 1351
f9331d11 1352 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
8293ebfc 1353 return 0;
5f3cc447
SN
1354}
1355
5f3cc447 1356static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = {
aceb59ed 1357 .vidioc_querycap = fimc_cap_querycap,
5f3cc447 1358
cf52df8a 1359 .vidioc_enum_fmt_vid_cap_mplane = fimc_cap_enum_fmt_mplane,
e578588e 1360 .vidioc_try_fmt_vid_cap_mplane = fimc_cap_try_fmt_mplane,
ef7af59b 1361 .vidioc_s_fmt_vid_cap_mplane = fimc_cap_s_fmt_mplane,
e578588e 1362 .vidioc_g_fmt_vid_cap_mplane = fimc_cap_g_fmt_mplane,
5f3cc447
SN
1363
1364 .vidioc_reqbufs = fimc_cap_reqbufs,
c444914a
SN
1365 .vidioc_querybuf = vb2_ioctl_querybuf,
1366 .vidioc_qbuf = vb2_ioctl_qbuf,
1367 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1368 .vidioc_expbuf = vb2_ioctl_expbuf,
1369 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1370 .vidioc_create_bufs = vb2_ioctl_create_bufs,
3b4c34aa 1371
5f3cc447
SN
1372 .vidioc_streamon = fimc_cap_streamon,
1373 .vidioc_streamoff = fimc_cap_streamoff,
1374
f9331d11
SN
1375 .vidioc_g_selection = fimc_cap_g_selection,
1376 .vidioc_s_selection = fimc_cap_s_selection,
5f3cc447
SN
1377
1378 .vidioc_enum_input = fimc_cap_enum_input,
1379 .vidioc_s_input = fimc_cap_s_input,
1380 .vidioc_g_input = fimc_cap_g_input,
1381};
1382
237e0265 1383/* Capture subdev media entity operations */
d09a7dc8
SN
1384static int fimc_link_setup(struct media_entity *entity,
1385 const struct media_pad *local,
1386 const struct media_pad *remote, u32 flags)
1387{
237e0265
SN
1388 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1389 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
4403106d
SN
1390 struct fimc_vid_cap *vc = &fimc->vid_cap;
1391 struct v4l2_subdev *sensor;
237e0265
SN
1392
1393 if (media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
1394 return -EINVAL;
d09a7dc8
SN
1395
1396 if (WARN_ON(fimc == NULL))
1397 return 0;
1398
1399 dbg("%s --> %s, flags: 0x%x. input: 0x%x",
1400 local->entity->name, remote->entity->name, flags,
1401 fimc->vid_cap.input);
1402
4403106d
SN
1403 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
1404 fimc->vid_cap.input = 0;
d09a7dc8
SN
1405 return 0;
1406 }
1407
4403106d
SN
1408 if (vc->input != 0)
1409 return -EBUSY;
1410
1411 vc->input = sd->grp_id;
1412
1413 if (vc->user_subdev_api || vc->inh_sensor_ctrls)
1414 return 0;
1415
1416 /* Inherit V4L2 controls from the image sensor subdev. */
1417 sensor = fimc_find_remote_sensor(&vc->subdev.entity);
1418 if (sensor == NULL)
1419 return 0;
1420
1421 return v4l2_ctrl_add_handler(&vc->ctx->ctrls.handler,
1422 sensor->ctrl_handler, NULL);
d09a7dc8
SN
1423}
1424
237e0265 1425static const struct media_entity_operations fimc_sd_media_ops = {
d09a7dc8
SN
1426 .link_setup = fimc_link_setup,
1427};
1428
e1d72f4d
SN
1429/**
1430 * fimc_sensor_notify - v4l2_device notification from a sensor subdev
1431 * @sd: pointer to a subdev generating the notification
1432 * @notification: the notification type, must be S5P_FIMC_TX_END_NOTIFY
1433 * @arg: pointer to an u32 type integer that stores the frame payload value
1434 *
1435 * The End Of Frame notification sent by sensor subdev in its still capture
1436 * mode. If there is only a single VSYNC generated by the sensor at the
1437 * beginning of a frame transmission, FIMC does not issue the LastIrq
1438 * (end of frame) interrupt. And this notification is used to complete the
1439 * frame capture and returning a buffer to user-space. Subdev drivers should
1440 * call this notification from their last 'End of frame capture' interrupt.
1441 */
1442void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
1443 void *arg)
1444{
4c8f0629 1445 struct fimc_source_info *si;
e1d72f4d
SN
1446 struct fimc_vid_buffer *buf;
1447 struct fimc_md *fmd;
1448 struct fimc_dev *fimc;
1449 unsigned long flags;
1450
1451 if (sd == NULL)
1452 return;
1453
4c8f0629 1454 si = v4l2_get_subdev_hostdata(sd);
e1d72f4d
SN
1455 fmd = entity_to_fimc_mdev(&sd->entity);
1456
1457 spin_lock_irqsave(&fmd->slock, flags);
4c8f0629
SN
1458
1459 fimc = si ? source_to_sensor_info(si)->host : NULL;
e1d72f4d
SN
1460
1461 if (fimc && arg && notification == S5P_FIMC_TX_END_NOTIFY &&
1462 test_bit(ST_CAPT_PEND, &fimc->state)) {
1463 unsigned long irq_flags;
1464 spin_lock_irqsave(&fimc->slock, irq_flags);
1465 if (!list_empty(&fimc->vid_cap.active_buf_q)) {
1466 buf = list_entry(fimc->vid_cap.active_buf_q.next,
1467 struct fimc_vid_buffer, list);
1468 vb2_set_plane_payload(&buf->vb, 0, *((u32 *)arg));
1469 }
97d97422 1470 fimc_capture_irq_handler(fimc, 1);
e1d72f4d
SN
1471 fimc_deactivate_capture(fimc);
1472 spin_unlock_irqrestore(&fimc->slock, irq_flags);
1473 }
1474 spin_unlock_irqrestore(&fmd->slock, flags);
1475}
1476
237e0265
SN
1477static int fimc_subdev_enum_mbus_code(struct v4l2_subdev *sd,
1478 struct v4l2_subdev_fh *fh,
1479 struct v4l2_subdev_mbus_code_enum *code)
1480{
1481 struct fimc_fmt *fmt;
1482
1483 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, code->index);
1484 if (!fmt)
1485 return -EINVAL;
1486 code->code = fmt->mbus_code;
1487 return 0;
1488}
1489
1490static int fimc_subdev_get_fmt(struct v4l2_subdev *sd,
1491 struct v4l2_subdev_fh *fh,
1492 struct v4l2_subdev_format *fmt)
1493{
1494 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1495 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
88fa8311 1496 struct fimc_frame *ff = &ctx->s_frame;
237e0265 1497 struct v4l2_mbus_framefmt *mf;
237e0265
SN
1498
1499 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1500 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1501 fmt->format = *mf;
1502 return 0;
1503 }
237e0265 1504
88fa8311 1505 mf = &fmt->format;
237e0265 1506 mutex_lock(&fimc->lock);
88fa8311
SN
1507
1508 switch (fmt->pad) {
1509 case FIMC_SD_PAD_SOURCE:
1510 if (!WARN_ON(ff->fmt == NULL))
1511 mf->code = ff->fmt->mbus_code;
1512 /* Sink pads crop rectangle size */
1513 mf->width = ff->width;
1514 mf->height = ff->height;
1515 break;
1516 case FIMC_SD_PAD_SINK_FIFO:
1517 *mf = fimc->vid_cap.wb_fmt;
1518 break;
1519 case FIMC_SD_PAD_SINK_CAM:
1520 default:
1521 *mf = fimc->vid_cap.ci_fmt;
1522 break;
1523 }
1524
237e0265 1525 mutex_unlock(&fimc->lock);
88fa8311 1526 mf->colorspace = V4L2_COLORSPACE_JPEG;
237e0265
SN
1527
1528 return 0;
1529}
1530
1531static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,
1532 struct v4l2_subdev_fh *fh,
1533 struct v4l2_subdev_format *fmt)
1534{
1535 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1536 struct v4l2_mbus_framefmt *mf = &fmt->format;
88fa8311
SN
1537 struct fimc_vid_cap *vc = &fimc->vid_cap;
1538 struct fimc_ctx *ctx = vc->ctx;
237e0265
SN
1539 struct fimc_frame *ff;
1540 struct fimc_fmt *ffmt;
1541
1542 dbg("pad%d: code: 0x%x, %dx%d",
1543 fmt->pad, mf->code, mf->width, mf->height);
1544
88fa8311 1545 if (fmt->pad == FIMC_SD_PAD_SOURCE && vb2_is_busy(&vc->vbq))
237e0265
SN
1546 return -EBUSY;
1547
1548 mutex_lock(&fimc->lock);
1549 ffmt = fimc_capture_try_format(ctx, &mf->width, &mf->height,
1550 &mf->code, NULL, fmt->pad);
1551 mutex_unlock(&fimc->lock);
1552 mf->colorspace = V4L2_COLORSPACE_JPEG;
1553
1554 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1555 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1556 *mf = fmt->format;
1557 return 0;
1558 }
6612545f
SN
1559 /* There must be a bug in the driver if this happens */
1560 if (WARN_ON(ffmt == NULL))
1561 return -EINVAL;
1562
dafb9c70
SN
1563 /* Update RGB Alpha control state and value range */
1564 fimc_alpha_ctrl_update(ctx);
1565
14783d25 1566 fimc_capture_mark_jpeg_xfer(ctx, ffmt->color);
88fa8311
SN
1567 if (fmt->pad == FIMC_SD_PAD_SOURCE) {
1568 ff = &ctx->d_frame;
1569 /* Sink pads crop rectangle size */
1570 mf->width = ctx->s_frame.width;
1571 mf->height = ctx->s_frame.height;
1572 } else {
1573 ff = &ctx->s_frame;
1574 }
237e0265
SN
1575
1576 mutex_lock(&fimc->lock);
1577 set_frame_bounds(ff, mf->width, mf->height);
88fa8311
SN
1578
1579 if (fmt->pad == FIMC_SD_PAD_SINK_FIFO)
1580 vc->wb_fmt = *mf;
1581 else if (fmt->pad == FIMC_SD_PAD_SINK_CAM)
1582 vc->ci_fmt = *mf;
1583
237e0265
SN
1584 ff->fmt = ffmt;
1585
1586 /* Reset the crop rectangle if required. */
fed07f84 1587 if (!(fmt->pad == FIMC_SD_PAD_SOURCE && (ctx->state & FIMC_COMPOSE)))
237e0265
SN
1588 set_frame_crop(ff, 0, 0, mf->width, mf->height);
1589
88fa8311 1590 if (fmt->pad != FIMC_SD_PAD_SOURCE)
fed07f84 1591 ctx->state &= ~FIMC_COMPOSE;
88fa8311 1592
237e0265
SN
1593 mutex_unlock(&fimc->lock);
1594 return 0;
1595}
1596
fed07f84
SN
1597static int fimc_subdev_get_selection(struct v4l2_subdev *sd,
1598 struct v4l2_subdev_fh *fh,
1599 struct v4l2_subdev_selection *sel)
237e0265
SN
1600{
1601 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1602 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
fed07f84
SN
1603 struct fimc_frame *f = &ctx->s_frame;
1604 struct v4l2_rect *r = &sel->r;
1605 struct v4l2_rect *try_sel;
1606
88fa8311 1607 if (sel->pad == FIMC_SD_PAD_SOURCE)
fed07f84
SN
1608 return -EINVAL;
1609
1610 mutex_lock(&fimc->lock);
237e0265 1611
fed07f84 1612 switch (sel->target) {
5689b288 1613 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
fed07f84 1614 f = &ctx->d_frame;
5689b288 1615 case V4L2_SEL_TGT_CROP_BOUNDS:
fed07f84
SN
1616 r->width = f->o_width;
1617 r->height = f->o_height;
1618 r->left = 0;
1619 r->top = 0;
1620 mutex_unlock(&fimc->lock);
237e0265 1621 return 0;
fed07f84 1622
5689b288 1623 case V4L2_SEL_TGT_CROP:
fed07f84
SN
1624 try_sel = v4l2_subdev_get_try_crop(fh, sel->pad);
1625 break;
5689b288 1626 case V4L2_SEL_TGT_COMPOSE:
fed07f84
SN
1627 try_sel = v4l2_subdev_get_try_compose(fh, sel->pad);
1628 f = &ctx->d_frame;
1629 break;
1630 default:
1631 mutex_unlock(&fimc->lock);
1632 return -EINVAL;
237e0265 1633 }
237e0265 1634
fed07f84
SN
1635 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1636 sel->r = *try_sel;
1637 } else {
1638 r->left = f->offs_h;
1639 r->top = f->offs_v;
1640 r->width = f->width;
1641 r->height = f->height;
1642 }
237e0265 1643
fed07f84
SN
1644 dbg("target %#x: l:%d, t:%d, %dx%d, f_w: %d, f_h: %d",
1645 sel->pad, r->left, r->top, r->width, r->height,
1646 f->f_width, f->f_height);
237e0265 1647
fed07f84 1648 mutex_unlock(&fimc->lock);
237e0265
SN
1649 return 0;
1650}
1651
fed07f84
SN
1652static int fimc_subdev_set_selection(struct v4l2_subdev *sd,
1653 struct v4l2_subdev_fh *fh,
1654 struct v4l2_subdev_selection *sel)
237e0265
SN
1655{
1656 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1657 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
fed07f84
SN
1658 struct fimc_frame *f = &ctx->s_frame;
1659 struct v4l2_rect *r = &sel->r;
1660 struct v4l2_rect *try_sel;
237e0265
SN
1661 unsigned long flags;
1662
88fa8311 1663 if (sel->pad == FIMC_SD_PAD_SOURCE)
fed07f84 1664 return -EINVAL;
237e0265
SN
1665
1666 mutex_lock(&fimc->lock);
c1334823 1667 fimc_capture_try_selection(ctx, r, V4L2_SEL_TGT_CROP);
237e0265 1668
fed07f84 1669 switch (sel->target) {
5689b288 1670 case V4L2_SEL_TGT_CROP:
fed07f84
SN
1671 try_sel = v4l2_subdev_get_try_crop(fh, sel->pad);
1672 break;
5689b288 1673 case V4L2_SEL_TGT_COMPOSE:
fed07f84
SN
1674 try_sel = v4l2_subdev_get_try_compose(fh, sel->pad);
1675 f = &ctx->d_frame;
1676 break;
1677 default:
1678 mutex_unlock(&fimc->lock);
1679 return -EINVAL;
237e0265 1680 }
237e0265 1681
fed07f84
SN
1682 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1683 *try_sel = sel->r;
1684 } else {
1685 spin_lock_irqsave(&fimc->slock, flags);
1686 set_frame_crop(f, r->left, r->top, r->width, r->height);
1687 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
5689b288 1688 if (sel->target == V4L2_SEL_TGT_COMPOSE)
fed07f84 1689 ctx->state |= FIMC_COMPOSE;
8b164105 1690 spin_unlock_irqrestore(&fimc->slock, flags);
fed07f84 1691 }
237e0265 1692
fed07f84 1693 dbg("target %#x: (%d,%d)/%dx%d", sel->target, r->left, r->top,
237e0265
SN
1694 r->width, r->height);
1695
1696 mutex_unlock(&fimc->lock);
1697 return 0;
1698}
1699
1700static struct v4l2_subdev_pad_ops fimc_subdev_pad_ops = {
1701 .enum_mbus_code = fimc_subdev_enum_mbus_code,
fed07f84
SN
1702 .get_selection = fimc_subdev_get_selection,
1703 .set_selection = fimc_subdev_set_selection,
237e0265
SN
1704 .get_fmt = fimc_subdev_get_fmt,
1705 .set_fmt = fimc_subdev_set_fmt,
237e0265
SN
1706};
1707
1708static struct v4l2_subdev_ops fimc_subdev_ops = {
1709 .pad = &fimc_subdev_pad_ops,
1710};
1711
237e0265
SN
1712/* Set default format at the sensor and host interface */
1713static int fimc_capture_set_default_format(struct fimc_dev *fimc)
1714{
1715 struct v4l2_format fmt = {
1716 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
1717 .fmt.pix_mp = {
1718 .width = 640,
1719 .height = 480,
1720 .pixelformat = V4L2_PIX_FMT_YUYV,
1721 .field = V4L2_FIELD_NONE,
1722 .colorspace = V4L2_COLORSPACE_JPEG,
1723 },
1724 };
1725
740ad921 1726 return __fimc_capture_set_format(fimc, &fmt);
237e0265
SN
1727}
1728
ef7af59b 1729/* fimc->lock must be already initialized */
693f5c40 1730static int fimc_register_capture_device(struct fimc_dev *fimc,
30c9939d 1731 struct v4l2_device *v4l2_dev)
5f3cc447 1732{
bc7584b0 1733 struct video_device *vfd = &fimc->vid_cap.ve.vdev;
c444914a 1734 struct vb2_queue *q = &fimc->vid_cap.vbq;
5f3cc447 1735 struct fimc_ctx *ctx;
c444914a 1736 struct fimc_vid_cap *vid_cap;
30c9939d 1737 int ret = -ENOMEM;
5f3cc447 1738
26ee7f47 1739 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
5f3cc447
SN
1740 if (!ctx)
1741 return -ENOMEM;
1742
1743 ctx->fimc_dev = fimc;
3d112d9a
SN
1744 ctx->in_path = FIMC_IO_CAMERA;
1745 ctx->out_path = FIMC_IO_DMA;
5f3cc447 1746 ctx->state = FIMC_CTX_CAP;
237e0265 1747 ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0);
693f5c40 1748 ctx->d_frame.fmt = ctx->s_frame.fmt;
5f3cc447 1749
31d34d9b 1750 memset(vfd, 0, sizeof(*vfd));
693f5c40 1751 snprintf(vfd->name, sizeof(vfd->name), "fimc.%d.capture", fimc->id);
5f3cc447
SN
1752
1753 vfd->fops = &fimc_capture_fops;
1754 vfd->ioctl_ops = &fimc_capture_ioctl_ops;
574e1717 1755 vfd->v4l2_dev = v4l2_dev;
5f3cc447 1756 vfd->minor = -1;
31d34d9b 1757 vfd->release = video_device_release_empty;
c444914a 1758 vfd->queue = q;
8293ebfc 1759 vfd->lock = &fimc->lock;
c2d430af 1760
5f3cc447 1761 video_set_drvdata(vfd, fimc);
5f3cc447 1762 vid_cap = &fimc->vid_cap;
5f3cc447 1763 vid_cap->active_buf_cnt = 0;
c444914a
SN
1764 vid_cap->reqbufs_count = 0;
1765 vid_cap->ctx = ctx;
5f3cc447
SN
1766
1767 INIT_LIST_HEAD(&vid_cap->pending_buf_q);
1768 INIT_LIST_HEAD(&vid_cap->active_buf_q);
5f3cc447 1769
2dab38e2 1770 memset(q, 0, sizeof(*q));
ef7af59b 1771 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
9bd09fd7 1772 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
c444914a 1773 q->drv_priv = ctx;
2dab38e2
SN
1774 q->ops = &fimc_capture_qops;
1775 q->mem_ops = &vb2_dma_contig_memops;
1776 q->buf_struct_size = sizeof(struct fimc_vid_buffer);
6aa69f99 1777 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
c444914a 1778 q->lock = &fimc->lock;
2dab38e2 1779
41fd087f
SN
1780 ret = vb2_queue_init(q);
1781 if (ret)
4403106d 1782 goto err_free_ctx;
5f3cc447 1783
693f5c40
SN
1784 vid_cap->vd_pad.flags = MEDIA_PAD_FL_SINK;
1785 ret = media_entity_init(&vfd->entity, 1, &vid_cap->vd_pad, 0);
574e1717 1786 if (ret)
4403106d
SN
1787 goto err_free_ctx;
1788
1789 ret = fimc_ctrls_create(ctx);
1790 if (ret)
1791 goto err_me_cleanup;
693f5c40
SN
1792
1793 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
237e0265 1794 if (ret)
4403106d 1795 goto err_ctrl_free;
693f5c40
SN
1796
1797 v4l2_info(v4l2_dev, "Registered %s as /dev/%s\n",
1798 vfd->name, video_device_node_name(vfd));
574e1717 1799
9448ab7d 1800 vfd->ctrl_handler = &ctx->ctrls.handler;
5f3cc447
SN
1801 return 0;
1802
4403106d
SN
1803err_ctrl_free:
1804 fimc_ctrls_delete(ctx);
1805err_me_cleanup:
237e0265 1806 media_entity_cleanup(&vfd->entity);
4403106d 1807err_free_ctx:
cfd77310 1808 kfree(ctx);
5f3cc447
SN
1809 return ret;
1810}
1811
693f5c40 1812static int fimc_capture_subdev_registered(struct v4l2_subdev *sd)
5f3cc447 1813{
693f5c40
SN
1814 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1815 int ret;
5f3cc447 1816
bbc5296f
SN
1817 if (fimc == NULL)
1818 return -ENXIO;
1819
693f5c40
SN
1820 ret = fimc_register_m2m_device(fimc, sd->v4l2_dev);
1821 if (ret)
1822 return ret;
1823
97d66c47
SN
1824 fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd);
1825
693f5c40 1826 ret = fimc_register_capture_device(fimc, sd->v4l2_dev);
97d66c47 1827 if (ret) {
693f5c40 1828 fimc_unregister_m2m_device(fimc);
97d66c47
SN
1829 fimc->pipeline_ops = NULL;
1830 }
693f5c40
SN
1831
1832 return ret;
1833}
1834
1835static void fimc_capture_subdev_unregistered(struct v4l2_subdev *sd)
1836{
1837 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
bc7584b0 1838 struct video_device *vdev;
693f5c40
SN
1839
1840 if (fimc == NULL)
1841 return;
1842
1843 fimc_unregister_m2m_device(fimc);
bc7584b0 1844 vdev = &fimc->vid_cap.ve.vdev;
693f5c40 1845
bc7584b0
SN
1846 if (video_is_registered(vdev)) {
1847 video_unregister_device(vdev);
1848 media_entity_cleanup(&vdev->entity);
4403106d 1849 fimc_ctrls_delete(fimc->vid_cap.ctx);
97d66c47 1850 fimc->pipeline_ops = NULL;
574e1717
SN
1851 }
1852 kfree(fimc->vid_cap.ctx);
96a85742 1853 fimc->vid_cap.ctx = NULL;
5f3cc447 1854}
693f5c40
SN
1855
1856static const struct v4l2_subdev_internal_ops fimc_capture_sd_internal_ops = {
1857 .registered = fimc_capture_subdev_registered,
1858 .unregistered = fimc_capture_subdev_unregistered,
1859};
1860
1861int fimc_initialize_capture_subdev(struct fimc_dev *fimc)
1862{
1863 struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
1864 int ret;
1865
1866 v4l2_subdev_init(sd, &fimc_subdev_ops);
5a66561f 1867 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
e80cb1fa 1868 snprintf(sd->name, sizeof(sd->name), "FIMC.%d", fimc->id);
693f5c40 1869
88fa8311
SN
1870 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_CAM].flags = MEDIA_PAD_FL_SINK;
1871 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_FIFO].flags = MEDIA_PAD_FL_SINK;
693f5c40
SN
1872 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1873 ret = media_entity_init(&sd->entity, FIMC_SD_PADS_NUM,
1874 fimc->vid_cap.sd_pads, 0);
1875 if (ret)
1876 return ret;
1877
1878 sd->entity.ops = &fimc_sd_media_ops;
1879 sd->internal_ops = &fimc_capture_sd_internal_ops;
1880 v4l2_set_subdevdata(sd, fimc);
1881 return 0;
1882}
1883
1884void fimc_unregister_capture_subdev(struct fimc_dev *fimc)
1885{
1886 struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
1887
1888 v4l2_device_unregister_subdev(sd);
1889 media_entity_cleanup(&sd->entity);
1890 v4l2_set_subdevdata(sd, NULL);
1891}