[media] media: videobuf2: Restructure vb2_buffer
[linux-2.6-block.git] / drivers / media / platform / exynos4-is / fimc-capture.c
CommitLineData
5f3cc447 1/*
3a3f9449 2 * Samsung S5P/EXYNOS4 SoC series camera interface (camera capture) driver
5f3cc447 3 *
0c9204d3
SN
4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
5f3cc447
SN
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
5f3cc447
SN
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/bug.h>
17#include <linux/interrupt.h>
18#include <linux/device.h>
e9e21083 19#include <linux/pm_runtime.h>
5f3cc447
SN
20#include <linux/list.h>
21#include <linux/slab.h>
5f3cc447
SN
22
23#include <linux/videodev2.h>
24#include <media/v4l2-device.h>
25#include <media/v4l2-ioctl.h>
26#include <media/v4l2-mem2mem.h>
c139990e 27#include <media/videobuf2-v4l2.h>
2dab38e2 28#include <media/videobuf2-dma-contig.h>
5f3cc447 29
4403106d 30#include "common.h"
5f3cc447 31#include "fimc-core.h"
c83a1ff0 32#include "fimc-reg.h"
4403106d 33#include "media-dev.h"
5f3cc447 34
bb7c276e 35static int fimc_capture_hw_init(struct fimc_dev *fimc)
9e803a04 36{
88fa8311 37 struct fimc_source_info *si = &fimc->vid_cap.source_config;
9e803a04 38 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
88fa8311 39 int ret;
9e803a04 40 unsigned long flags;
9e803a04 41
88fa8311 42 if (ctx == NULL || ctx->s_frame.fmt == NULL)
9e803a04
SN
43 return -EINVAL;
44
88fa8311
SN
45 if (si->fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK) {
46 ret = fimc_hw_camblk_cfg_writeback(fimc);
47 if (ret < 0)
48 return ret;
49 }
9e803a04
SN
50
51 spin_lock_irqsave(&fimc->slock, flags);
52 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
53 fimc_set_yuv_order(ctx);
54
88fa8311
SN
55 fimc_hw_set_camera_polarity(fimc, si);
56 fimc_hw_set_camera_type(fimc, si);
57 fimc_hw_set_camera_source(fimc, si);
9e803a04
SN
58 fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
59
60 ret = fimc_set_scaler_info(ctx);
61 if (!ret) {
62 fimc_hw_set_input_path(ctx);
63 fimc_hw_set_prescaler(ctx);
64 fimc_hw_set_mainscaler(ctx);
65 fimc_hw_set_target_format(ctx);
66 fimc_hw_set_rotation(ctx);
9448ab7d 67 fimc_hw_set_effect(ctx);
9e803a04
SN
68 fimc_hw_set_output_path(ctx);
69 fimc_hw_set_out_dma(ctx);
e80cb1fa 70 if (fimc->drv_data->alpha_color)
dafb9c70 71 fimc_hw_set_rgb_alpha(ctx);
237e0265 72 clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
9e803a04
SN
73 }
74 spin_unlock_irqrestore(&fimc->slock, flags);
75 return ret;
76}
77
bb7c276e
SN
78/*
79 * Reinitialize the driver so it is ready to start the streaming again.
80 * Set fimc->state to indicate stream off and the hardware shut down state.
81 * If not suspending (@suspend is false), return any buffers to videobuf2.
82 * Otherwise put any owned buffers onto the pending buffers queue, so they
83 * can be re-spun when the device is being resumed. Also perform FIMC
84 * software reset and disable streaming on the whole pipeline if required.
85 */
3e4748d8 86static int fimc_capture_state_cleanup(struct fimc_dev *fimc, bool suspend)
5f3cc447 87{
bd323e28 88 struct fimc_vid_cap *cap = &fimc->vid_cap;
2dab38e2 89 struct fimc_vid_buffer *buf;
bd323e28 90 unsigned long flags;
3e4748d8 91 bool streaming;
5f3cc447
SN
92
93 spin_lock_irqsave(&fimc->slock, flags);
3e4748d8 94 streaming = fimc->state & (1 << ST_CAPT_ISP_STREAM);
5f3cc447 95
3e4748d8
SN
96 fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_SHUT |
97 1 << ST_CAPT_STREAM | 1 << ST_CAPT_ISP_STREAM);
aa333122
SN
98 if (suspend)
99 fimc->state |= (1 << ST_CAPT_SUSPENDED);
100 else
3e4748d8 101 fimc->state &= ~(1 << ST_CAPT_PEND | 1 << ST_CAPT_SUSPENDED);
2dab38e2 102
3e4748d8
SN
103 /* Release unused buffers */
104 while (!suspend && !list_empty(&cap->pending_buf_q)) {
0295202c 105 buf = fimc_pending_queue_pop(cap);
2d700715 106 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
2dab38e2 107 }
3e4748d8 108 /* If suspending put unused buffers onto pending queue */
2dab38e2 109 while (!list_empty(&cap->active_buf_q)) {
0295202c 110 buf = fimc_active_queue_pop(cap);
3e4748d8
SN
111 if (suspend)
112 fimc_pending_queue_add(cap, buf);
113 else
2d700715 114 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
2dab38e2 115 }
2c1bb62e
SN
116
117 fimc_hw_reset(fimc);
118 cap->buf_index = 0;
119
5f3cc447 120 spin_unlock_irqrestore(&fimc->slock, flags);
4db5e27e 121
3e4748d8 122 if (streaming)
403dfbec 123 return fimc_pipeline_call(&cap->ve, set_stream, 0);
4db5e27e
SN
124 else
125 return 0;
bd323e28
MS
126}
127
3e4748d8 128static int fimc_stop_capture(struct fimc_dev *fimc, bool suspend)
bd323e28 129{
bd323e28
MS
130 unsigned long flags;
131
132 if (!fimc_capture_active(fimc))
133 return 0;
134
135 spin_lock_irqsave(&fimc->slock, flags);
136 set_bit(ST_CAPT_SHUT, &fimc->state);
137 fimc_deactivate_capture(fimc);
138 spin_unlock_irqrestore(&fimc->slock, flags);
139
140 wait_event_timeout(fimc->irq_queue,
141 !test_bit(ST_CAPT_SHUT, &fimc->state),
3e4748d8 142 (2*HZ/10)); /* 200 ms */
5f3cc447 143
3e4748d8 144 return fimc_capture_state_cleanup(fimc, suspend);
5f3cc447
SN
145}
146
237e0265
SN
147/**
148 * fimc_capture_config_update - apply the camera interface configuration
149 *
150 * To be called from within the interrupt handler with fimc.slock
151 * spinlock held. It updates the camera pixel crop, rotation and
152 * image flip in H/W.
153 */
97d97422 154static int fimc_capture_config_update(struct fimc_ctx *ctx)
237e0265
SN
155{
156 struct fimc_dev *fimc = ctx->fimc_dev;
157 int ret;
158
237e0265 159 fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
efb13c3d 160
237e0265 161 ret = fimc_set_scaler_info(ctx);
efb13c3d
SN
162 if (ret)
163 return ret;
164
165 fimc_hw_set_prescaler(ctx);
166 fimc_hw_set_mainscaler(ctx);
167 fimc_hw_set_target_format(ctx);
168 fimc_hw_set_rotation(ctx);
9448ab7d 169 fimc_hw_set_effect(ctx);
efb13c3d
SN
170 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
171 fimc_hw_set_out_dma(ctx);
e80cb1fa 172 if (fimc->drv_data->alpha_color)
efb13c3d
SN
173 fimc_hw_set_rgb_alpha(ctx);
174
175 clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
237e0265
SN
176 return ret;
177}
bd323e28 178
97d97422
SN
179void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
180{
181 struct fimc_vid_cap *cap = &fimc->vid_cap;
403dfbec
SN
182 struct fimc_pipeline *p = to_fimc_pipeline(cap->ve.pipe);
183 struct v4l2_subdev *csis = p->subdevs[IDX_CSIS];
14783d25 184 struct fimc_frame *f = &cap->ctx->d_frame;
97d97422 185 struct fimc_vid_buffer *v_buf;
97d97422
SN
186
187 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
188 wake_up(&fimc->irq_queue);
189 goto done;
190 }
191
192 if (!list_empty(&cap->active_buf_q) &&
193 test_bit(ST_CAPT_RUN, &fimc->state) && deq_buf) {
97d97422
SN
194 v_buf = fimc_active_queue_pop(cap);
195
2d700715
JS
196 v4l2_get_timestamp(&v_buf->vb.timestamp);
197 v_buf->vb.sequence = cap->frame_count++;
97d97422 198
2d700715 199 vb2_buffer_done(&v_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
97d97422
SN
200 }
201
202 if (!list_empty(&cap->pending_buf_q)) {
203
204 v_buf = fimc_pending_queue_pop(cap);
205 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
206 v_buf->index = cap->buf_index;
207
208 /* Move the buffer to the capture active queue */
209 fimc_active_queue_add(cap, v_buf);
210
211 dbg("next frame: %d, done frame: %d",
212 fimc_hw_get_frame_index(fimc), v_buf->index);
213
214 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
215 cap->buf_index = 0;
216 }
14783d25
SN
217 /*
218 * Set up a buffer at MIPI-CSIS if current image format
219 * requires the frame embedded data capture.
220 */
221 if (f->fmt->mdataplanes && !list_empty(&cap->active_buf_q)) {
222 unsigned int plane = ffs(f->fmt->mdataplanes) - 1;
223 unsigned int size = f->payload[plane];
224 s32 index = fimc_hw_get_frame_index(fimc);
225 void *vaddr;
226
227 list_for_each_entry(v_buf, &cap->active_buf_q, list) {
228 if (v_buf->index != index)
229 continue;
2d700715 230 vaddr = vb2_plane_vaddr(&v_buf->vb.vb2_buf, plane);
14783d25
SN
231 v4l2_subdev_call(csis, video, s_rx_buffer,
232 vaddr, &size);
233 break;
234 }
235 }
97d97422
SN
236
237 if (cap->active_buf_cnt == 0) {
238 if (deq_buf)
239 clear_bit(ST_CAPT_RUN, &fimc->state);
240
241 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
242 cap->buf_index = 0;
243 } else {
244 set_bit(ST_CAPT_RUN, &fimc->state);
245 }
246
bb7c276e
SN
247 if (test_bit(ST_CAPT_APPLY_CFG, &fimc->state))
248 fimc_capture_config_update(cap->ctx);
97d97422
SN
249done:
250 if (cap->active_buf_cnt == 1) {
251 fimc_deactivate_capture(fimc);
252 clear_bit(ST_CAPT_STREAM, &fimc->state);
253 }
254
255 dbg("frame: %d, active_buf_cnt: %d",
256 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
257}
258
259
bd323e28 260static int start_streaming(struct vb2_queue *q, unsigned int count)
2dab38e2
SN
261{
262 struct fimc_ctx *ctx = q->drv_priv;
263 struct fimc_dev *fimc = ctx->fimc_dev;
9e803a04 264 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
bd323e28 265 int min_bufs;
2dab38e2
SN
266 int ret;
267
9e803a04 268 vid_cap->frame_count = 0;
8ec737ff 269
bb7c276e
SN
270 ret = fimc_capture_hw_init(fimc);
271 if (ret) {
272 fimc_capture_state_cleanup(fimc, false);
273 return ret;
274 }
2dab38e2 275
2dab38e2
SN
276 set_bit(ST_CAPT_PEND, &fimc->state);
277
bd323e28
MS
278 min_bufs = fimc->vid_cap.reqbufs_count > 1 ? 2 : 1;
279
4db5e27e
SN
280 if (vid_cap->active_buf_cnt >= min_bufs &&
281 !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
bd323e28
MS
282 fimc_activate_capture(ctx);
283
4db5e27e 284 if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
403dfbec 285 return fimc_pipeline_call(&vid_cap->ve, set_stream, 1);
4db5e27e
SN
286 }
287
2dab38e2
SN
288 return 0;
289}
290
e37559b2 291static void stop_streaming(struct vb2_queue *q)
2dab38e2
SN
292{
293 struct fimc_ctx *ctx = q->drv_priv;
294 struct fimc_dev *fimc = ctx->fimc_dev;
2dab38e2 295
4ecbf5d1 296 if (!fimc_capture_active(fimc))
e37559b2 297 return;
2dab38e2 298
e37559b2 299 fimc_stop_capture(fimc, false);
2dab38e2
SN
300}
301
e9e21083
SN
302int fimc_capture_suspend(struct fimc_dev *fimc)
303{
3e4748d8
SN
304 bool suspend = fimc_capture_busy(fimc);
305
306 int ret = fimc_stop_capture(fimc, suspend);
307 if (ret)
308 return ret;
403dfbec 309 return fimc_pipeline_call(&fimc->vid_cap.ve, close);
e9e21083
SN
310}
311
3e4748d8
SN
312static void buffer_queue(struct vb2_buffer *vb);
313
e9e21083
SN
314int fimc_capture_resume(struct fimc_dev *fimc)
315{
3e4748d8 316 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
bc7584b0 317 struct exynos_video_entity *ve = &vid_cap->ve;
3e4748d8
SN
318 struct fimc_vid_buffer *buf;
319 int i;
320
321 if (!test_and_clear_bit(ST_CAPT_SUSPENDED, &fimc->state))
322 return 0;
323
324 INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
325 vid_cap->buf_index = 0;
403dfbec 326 fimc_pipeline_call(ve, open, &ve->vdev.entity, false);
bb7c276e 327 fimc_capture_hw_init(fimc);
3e4748d8
SN
328
329 clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
330
331 for (i = 0; i < vid_cap->reqbufs_count; i++) {
332 if (list_empty(&vid_cap->pending_buf_q))
333 break;
334 buf = fimc_pending_queue_pop(vid_cap);
2d700715 335 buffer_queue(&buf->vb.vb2_buf);
3e4748d8 336 }
e9e21083 337 return 0;
3e4748d8 338
e9e21083
SN
339}
340
63746be5 341static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
fc714e70
GL
342 unsigned int *num_buffers, unsigned int *num_planes,
343 unsigned int sizes[], void *allocators[])
2dab38e2 344{
63746be5 345 const struct v4l2_pix_format_mplane *pixm = NULL;
2dab38e2 346 struct fimc_ctx *ctx = vq->drv_priv;
63746be5
SN
347 struct fimc_frame *frame = &ctx->d_frame;
348 struct fimc_fmt *fmt = frame->fmt;
349 unsigned long wh;
ef7af59b 350 int i;
2dab38e2 351
63746be5
SN
352 if (pfmt) {
353 pixm = &pfmt->fmt.pix_mp;
354 fmt = fimc_find_format(&pixm->pixelformat, NULL,
355 FMT_FLAGS_CAM | FMT_FLAGS_M2M, -1);
356 wh = pixm->width * pixm->height;
357 } else {
358 wh = frame->f_width * frame->f_height;
359 }
360
361 if (fmt == NULL)
2dab38e2
SN
362 return -EINVAL;
363
ef7af59b 364 *num_planes = fmt->memplanes;
2dab38e2 365
ef7af59b 366 for (i = 0; i < fmt->memplanes; i++) {
63746be5
SN
367 unsigned int size = (wh * fmt->depth[i]) / 8;
368 if (pixm)
369 sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
14783d25
SN
370 else if (fimc_fmt_is_user_defined(fmt->color))
371 sizes[i] = frame->payload[i];
63746be5 372 else
d547ab66
SN
373 sizes[i] = max_t(u32, size, frame->payload[i]);
374
ef7af59b
SN
375 allocators[i] = ctx->fimc_dev->alloc_ctx;
376 }
2dab38e2 377
ef7af59b 378 return 0;
2dab38e2
SN
379}
380
2dab38e2
SN
381static int buffer_prepare(struct vb2_buffer *vb)
382{
383 struct vb2_queue *vq = vb->vb2_queue;
384 struct fimc_ctx *ctx = vq->drv_priv;
2dab38e2
SN
385 int i;
386
4db5e27e 387 if (ctx->d_frame.fmt == NULL)
ef7af59b 388 return -EINVAL;
2dab38e2 389
ef7af59b 390 for (i = 0; i < ctx->d_frame.fmt->memplanes; i++) {
4db5e27e 391 unsigned long size = ctx->d_frame.payload[i];
2dab38e2
SN
392
393 if (vb2_plane_size(vb, i) < size) {
bc7584b0 394 v4l2_err(&ctx->fimc_dev->vid_cap.ve.vdev,
30c9939d 395 "User buffer too small (%ld < %ld)\n",
2dab38e2
SN
396 vb2_plane_size(vb, i), size);
397 return -EINVAL;
398 }
2dab38e2
SN
399 vb2_set_plane_payload(vb, i, size);
400 }
401
402 return 0;
403}
404
405static void buffer_queue(struct vb2_buffer *vb)
406{
2d700715 407 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2dab38e2 408 struct fimc_vid_buffer *buf
2d700715 409 = container_of(vbuf, struct fimc_vid_buffer, vb);
4db5e27e
SN
410 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
411 struct fimc_dev *fimc = ctx->fimc_dev;
2dab38e2 412 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
bc7584b0 413 struct exynos_video_entity *ve = &vid_cap->ve;
2dab38e2 414 unsigned long flags;
8ec737ff 415 int min_bufs;
2dab38e2
SN
416
417 spin_lock_irqsave(&fimc->slock, flags);
2d700715 418 fimc_prepare_addr(ctx, &buf->vb.vb2_buf, &ctx->d_frame, &buf->paddr);
8ec737ff 419
3e4748d8
SN
420 if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) &&
421 !test_bit(ST_CAPT_STREAM, &fimc->state) &&
422 vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) {
8ec737ff
SK
423 /* Setup the buffer directly for processing. */
424 int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
425 vid_cap->buf_index;
2dab38e2 426
8ec737ff
SK
427 fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
428 buf->index = vid_cap->buf_index;
0295202c 429 fimc_active_queue_add(vid_cap, buf);
2dab38e2 430
8ec737ff
SK
431 if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS)
432 vid_cap->buf_index = 0;
433 } else {
434 fimc_pending_queue_add(vid_cap, buf);
2dab38e2 435 }
8ec737ff
SK
436
437 min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1;
438
4db5e27e 439
bd323e28
MS
440 if (vb2_is_streaming(&vid_cap->vbq) &&
441 vid_cap->active_buf_cnt >= min_bufs &&
4db5e27e 442 !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
76323e50
AH
443 int ret;
444
8ec737ff 445 fimc_activate_capture(ctx);
4db5e27e 446 spin_unlock_irqrestore(&fimc->slock, flags);
8ec737ff 447
76323e50
AH
448 if (test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
449 return;
450
403dfbec 451 ret = fimc_pipeline_call(ve, set_stream, 1);
76323e50 452 if (ret < 0)
bc7584b0 453 v4l2_err(&ve->vdev, "stream on failed: %d\n", ret);
4db5e27e
SN
454 return;
455 }
2dab38e2
SN
456 spin_unlock_irqrestore(&fimc->slock, flags);
457}
458
2dab38e2
SN
459static struct vb2_ops fimc_capture_qops = {
460 .queue_setup = queue_setup,
461 .buf_prepare = buffer_prepare,
462 .buf_queue = buffer_queue,
c444914a
SN
463 .wait_prepare = vb2_ops_wait_prepare,
464 .wait_finish = vb2_ops_wait_finish,
2dab38e2
SN
465 .start_streaming = start_streaming,
466 .stop_streaming = stop_streaming,
467};
468
237e0265
SN
469static int fimc_capture_set_default_format(struct fimc_dev *fimc);
470
5f3cc447
SN
471static int fimc_capture_open(struct file *file)
472{
473 struct fimc_dev *fimc = video_drvdata(file);
4403106d
SN
474 struct fimc_vid_cap *vc = &fimc->vid_cap;
475 struct exynos_video_entity *ve = &vc->ve;
c2d430af 476 int ret = -EBUSY;
5f3cc447
SN
477
478 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
479
740ad921 480 mutex_lock(&fimc->lock);
c2d430af 481
5f3cc447 482 if (fimc_m2m_active(fimc))
c2d430af 483 goto unlock;
5f3cc447 484
3e4748d8 485 set_bit(ST_CAPT_BUSY, &fimc->state);
e3fc82e8
SN
486 ret = pm_runtime_get_sync(&fimc->pdev->dev);
487 if (ret < 0)
c2d430af 488 goto unlock;
4db5e27e 489
e3fc82e8 490 ret = v4l2_fh_open(file);
c2d430af 491 if (ret) {
4bd728a1 492 pm_runtime_put_sync(&fimc->pdev->dev);
c2d430af
SN
493 goto unlock;
494 }
e3fc82e8 495
c444914a 496 if (v4l2_fh_is_singular_file(file)) {
42625fdf
SN
497 fimc_md_graph_lock(ve);
498
403dfbec
SN
499 ret = fimc_pipeline_call(ve, open, &ve->vdev.entity, true);
500
4403106d
SN
501 if (ret == 0 && vc->user_subdev_api && vc->inh_sensor_ctrls) {
502 /*
503 * Recreate controls of the the video node to drop
504 * any controls inherited from the sensor subdev.
505 */
506 fimc_ctrls_delete(vc->ctx);
507
508 ret = fimc_ctrls_create(vc->ctx);
509 if (ret == 0)
510 vc->inh_sensor_ctrls = false;
511 }
42625fdf
SN
512 if (ret == 0)
513 ve->vdev.entity.use_count++;
514
515 fimc_md_graph_unlock(ve);
e3fc82e8 516
7536b424
SN
517 if (ret == 0)
518 ret = fimc_capture_set_default_format(fimc);
519
c2d430af
SN
520 if (ret < 0) {
521 clear_bit(ST_CAPT_BUSY, &fimc->state);
522 pm_runtime_put_sync(&fimc->pdev->dev);
c2d430af
SN
523 v4l2_fh_release(file);
524 }
525 }
526unlock:
527 mutex_unlock(&fimc->lock);
131b6c61 528 return ret;
5f3cc447
SN
529}
530
c444914a 531static int fimc_capture_release(struct file *file)
5f3cc447
SN
532{
533 struct fimc_dev *fimc = video_drvdata(file);
9ea89e2b 534 struct fimc_vid_cap *vc = &fimc->vid_cap;
42625fdf 535 bool close = v4l2_fh_is_singular_file(file);
c2d430af 536 int ret;
5f3cc447 537
5f3cc447
SN
538 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
539
ba6b372c 540 mutex_lock(&fimc->lock);
c2d430af 541
42625fdf
SN
542 if (close && vc->streaming) {
543 media_entity_pipeline_stop(&vc->ve.vdev.entity);
544 vc->streaming = false;
545 }
546
1380f575 547 ret = _vb2_fop_release(file, NULL);
42625fdf
SN
548
549 if (close) {
3e4748d8 550 clear_bit(ST_CAPT_BUSY, &fimc->state);
403dfbec 551 fimc_pipeline_call(&vc->ve, close);
3e4748d8 552 clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
42625fdf
SN
553
554 fimc_md_graph_lock(&vc->ve);
555 vc->ve.vdev.entity.use_count--;
556 fimc_md_graph_unlock(&vc->ve);
5f3cc447
SN
557 }
558
4bd728a1 559 pm_runtime_put_sync(&fimc->pdev->dev);
c2d430af
SN
560 mutex_unlock(&fimc->lock);
561
562 return ret;
5f3cc447
SN
563}
564
5f3cc447
SN
565static const struct v4l2_file_operations fimc_capture_fops = {
566 .owner = THIS_MODULE,
567 .open = fimc_capture_open,
c444914a
SN
568 .release = fimc_capture_release,
569 .poll = vb2_fop_poll,
5f3cc447 570 .unlocked_ioctl = video_ioctl2,
c444914a 571 .mmap = vb2_fop_mmap,
5f3cc447
SN
572};
573
237e0265
SN
574/*
575 * Format and crop negotiation helpers
576 */
577
578static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx,
579 u32 *width, u32 *height,
580 u32 *code, u32 *fourcc, int pad)
581{
582 bool rotation = ctx->rotation == 90 || ctx->rotation == 270;
583 struct fimc_dev *fimc = ctx->fimc_dev;
405f230c
SN
584 const struct fimc_variant *var = fimc->variant;
585 const struct fimc_pix_limit *pl = var->pix_limit;
237e0265
SN
586 struct fimc_frame *dst = &ctx->d_frame;
587 u32 depth, min_w, max_w, min_h, align_h = 3;
588 u32 mask = FMT_FLAGS_CAM;
589 struct fimc_fmt *ffmt;
590
14783d25 591 /* Conversion from/to JPEG or User Defined format is not supported */
237e0265 592 if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE &&
14783d25
SN
593 fimc_fmt_is_user_defined(ctx->s_frame.fmt->color))
594 *code = ctx->s_frame.fmt->mbus_code;
237e0265 595
88fa8311 596 if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad == FIMC_SD_PAD_SOURCE)
237e0265
SN
597 mask |= FMT_FLAGS_M2M;
598
88fa8311
SN
599 if (pad == FIMC_SD_PAD_SINK_FIFO)
600 mask = FMT_FLAGS_WRITEBACK;
601
237e0265
SN
602 ffmt = fimc_find_format(fourcc, code, mask, 0);
603 if (WARN_ON(!ffmt))
604 return NULL;
88fa8311 605
237e0265
SN
606 if (code)
607 *code = ffmt->mbus_code;
608 if (fourcc)
609 *fourcc = ffmt->fourcc;
610
88fa8311 611 if (pad != FIMC_SD_PAD_SOURCE) {
14783d25 612 max_w = fimc_fmt_is_user_defined(ffmt->color) ?
237e0265
SN
613 pl->scaler_dis_w : pl->scaler_en_w;
614 /* Apply the camera input interface pixel constraints */
615 v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4,
616 height, max_t(u32, *height, 32),
617 FIMC_CAMIF_MAX_HEIGHT,
14783d25
SN
618 fimc_fmt_is_user_defined(ffmt->color) ?
619 3 : 1,
237e0265
SN
620 0);
621 return ffmt;
622 }
623 /* Can't scale or crop in transparent (JPEG) transfer mode */
14783d25 624 if (fimc_fmt_is_user_defined(ffmt->color)) {
237e0265
SN
625 *width = ctx->s_frame.f_width;
626 *height = ctx->s_frame.f_height;
627 return ffmt;
628 }
629 /* Apply the scaler and the output DMA constraints */
630 max_w = rotation ? pl->out_rot_en_w : pl->out_rot_dis_w;
fed07f84
SN
631 if (ctx->state & FIMC_COMPOSE) {
632 min_w = dst->offs_h + dst->width;
633 min_h = dst->offs_v + dst->height;
634 } else {
635 min_w = var->min_out_pixsize;
636 min_h = var->min_out_pixsize;
637 }
9c63afcb 638 if (var->min_vsize_align == 1 && !rotation)
237e0265
SN
639 align_h = fimc_fmt_is_rgb(ffmt->color) ? 0 : 1;
640
641 depth = fimc_get_format_depth(ffmt);
642 v4l_bound_align_image(width, min_w, max_w,
643 ffs(var->min_out_pixsize) - 1,
644 height, min_h, FIMC_CAMIF_MAX_HEIGHT,
645 align_h,
646 64/(ALIGN(depth, 8)));
647
648 dbg("pad%d: code: 0x%x, %dx%d. dst fmt: %dx%d",
649 pad, code ? *code : 0, *width, *height,
650 dst->f_width, dst->f_height);
651
652 return ffmt;
653}
654
fed07f84
SN
655static void fimc_capture_try_selection(struct fimc_ctx *ctx,
656 struct v4l2_rect *r,
657 int target)
237e0265
SN
658{
659 bool rotate = ctx->rotation == 90 || ctx->rotation == 270;
660 struct fimc_dev *fimc = ctx->fimc_dev;
405f230c
SN
661 const struct fimc_variant *var = fimc->variant;
662 const struct fimc_pix_limit *pl = var->pix_limit;
237e0265
SN
663 struct fimc_frame *sink = &ctx->s_frame;
664 u32 max_w, max_h, min_w = 0, min_h = 0, min_sz;
665 u32 align_sz = 0, align_h = 4;
666 u32 max_sc_h, max_sc_v;
667
668 /* In JPEG transparent transfer mode cropping is not supported */
14783d25 669 if (fimc_fmt_is_user_defined(ctx->d_frame.fmt->color)) {
237e0265
SN
670 r->width = sink->f_width;
671 r->height = sink->f_height;
672 r->left = r->top = 0;
673 return;
674 }
c1334823 675 if (target == V4L2_SEL_TGT_COMPOSE) {
237e0265
SN
676 if (ctx->rotation != 90 && ctx->rotation != 270)
677 align_h = 1;
678 max_sc_h = min(SCALER_MAX_HRATIO, 1 << (ffs(sink->width) - 3));
679 max_sc_v = min(SCALER_MAX_VRATIO, 1 << (ffs(sink->height) - 1));
680 min_sz = var->min_out_pixsize;
681 } else {
682 u32 depth = fimc_get_format_depth(sink->fmt);
683 align_sz = 64/ALIGN(depth, 8);
684 min_sz = var->min_inp_pixsize;
685 min_w = min_h = min_sz;
686 max_sc_h = max_sc_v = 1;
687 }
688 /*
fed07f84 689 * For the compose rectangle the following constraints must be met:
237e0265
SN
690 * - it must fit in the sink pad format rectangle (f_width/f_height);
691 * - maximum downscaling ratio is 64;
692 * - maximum crop size depends if the rotator is used or not;
693 * - the sink pad format width/height must be 4 multiple of the
694 * prescaler ratios determined by sink pad size and source pad crop,
695 * the prescaler ratio is returned by fimc_get_scaler_factor().
696 */
697 max_w = min_t(u32,
698 rotate ? pl->out_rot_en_w : pl->out_rot_dis_w,
699 rotate ? sink->f_height : sink->f_width);
700 max_h = min_t(u32, FIMC_CAMIF_MAX_HEIGHT, sink->f_height);
fed07f84 701
c1334823 702 if (target == V4L2_SEL_TGT_COMPOSE) {
237e0265
SN
703 min_w = min_t(u32, max_w, sink->f_width / max_sc_h);
704 min_h = min_t(u32, max_h, sink->f_height / max_sc_v);
705 if (rotate) {
706 swap(max_sc_h, max_sc_v);
707 swap(min_w, min_h);
708 }
709 }
710 v4l_bound_align_image(&r->width, min_w, max_w, ffs(min_sz) - 1,
711 &r->height, min_h, max_h, align_h,
712 align_sz);
fed07f84 713 /* Adjust left/top if crop/compose rectangle is out of bounds */
237e0265
SN
714 r->left = clamp_t(u32, r->left, 0, sink->f_width - r->width);
715 r->top = clamp_t(u32, r->top, 0, sink->f_height - r->height);
716 r->left = round_down(r->left, var->hor_offs_align);
717
fed07f84
SN
718 dbg("target %#x: (%d,%d)/%dx%d, sink fmt: %dx%d",
719 target, r->left, r->top, r->width, r->height,
237e0265
SN
720 sink->f_width, sink->f_height);
721}
722
723/*
724 * The video node ioctl operations
725 */
aceb59ed 726static int fimc_cap_querycap(struct file *file, void *priv,
5f3cc447
SN
727 struct v4l2_capability *cap)
728{
e578588e 729 struct fimc_dev *fimc = video_drvdata(file);
5f3cc447 730
aceb59ed
SN
731 __fimc_vidioc_querycap(&fimc->pdev->dev, cap, V4L2_CAP_STREAMING |
732 V4L2_CAP_VIDEO_CAPTURE_MPLANE);
5f3cc447
SN
733 return 0;
734}
735
cf52df8a
SN
736static int fimc_cap_enum_fmt_mplane(struct file *file, void *priv,
737 struct v4l2_fmtdesc *f)
738{
739 struct fimc_fmt *fmt;
740
741 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM | FMT_FLAGS_M2M,
742 f->index);
743 if (!fmt)
744 return -EINVAL;
745 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
746 f->pixelformat = fmt->fourcc;
27ffaeb0 747 if (fmt->fourcc == MEDIA_BUS_FMT_JPEG_1X8)
cf52df8a
SN
748 f->flags |= V4L2_FMT_FLAG_COMPRESSED;
749 return 0;
750}
751
47800bc4
SN
752static struct media_entity *fimc_pipeline_get_head(struct media_entity *me)
753{
754 struct media_pad *pad = &me->pads[0];
755
756 while (!(pad->flags & MEDIA_PAD_FL_SOURCE)) {
1bddf1b3 757 pad = media_entity_remote_pad(pad);
47800bc4
SN
758 if (!pad)
759 break;
760 me = pad->entity;
761 pad = &me->pads[0];
762 }
763
764 return me;
765}
766
237e0265
SN
767/**
768 * fimc_pipeline_try_format - negotiate and/or set formats at pipeline
769 * elements
770 * @ctx: FIMC capture context
771 * @tfmt: media bus format to try/set on subdevs
772 * @fmt_id: fimc pixel format id corresponding to returned @tfmt (output)
773 * @set: true to set format on subdevs, false to try only
774 */
775static int fimc_pipeline_try_format(struct fimc_ctx *ctx,
776 struct v4l2_mbus_framefmt *tfmt,
777 struct fimc_fmt **fmt_id,
778 bool set)
779{
780 struct fimc_dev *fimc = ctx->fimc_dev;
403dfbec
SN
781 struct fimc_pipeline *p = to_fimc_pipeline(fimc->vid_cap.ve.pipe);
782 struct v4l2_subdev *sd = p->subdevs[IDX_SENSOR];
237e0265
SN
783 struct v4l2_subdev_format sfmt;
784 struct v4l2_mbus_framefmt *mf = &sfmt.format;
47800bc4
SN
785 struct media_entity *me;
786 struct fimc_fmt *ffmt;
787 struct media_pad *pad;
788 int ret, i = 1;
789 u32 fcc;
237e0265
SN
790
791 if (WARN_ON(!sd || !tfmt))
792 return -EINVAL;
5f3cc447 793
237e0265
SN
794 memset(&sfmt, 0, sizeof(sfmt));
795 sfmt.format = *tfmt;
237e0265 796 sfmt.which = set ? V4L2_SUBDEV_FORMAT_ACTIVE : V4L2_SUBDEV_FORMAT_TRY;
47800bc4
SN
797
798 me = fimc_pipeline_get_head(&sd->entity);
799
237e0265
SN
800 while (1) {
801 ffmt = fimc_find_format(NULL, mf->code != 0 ? &mf->code : NULL,
802 FMT_FLAGS_CAM, i++);
803 if (ffmt == NULL) {
804 /*
805 * Notify user-space if common pixel code for
806 * host and sensor does not exist.
807 */
808 return -EINVAL;
809 }
810 mf->code = tfmt->code = ffmt->mbus_code;
5f3cc447 811
47800bc4
SN
812 /* set format on all pipeline subdevs */
813 while (me != &fimc->vid_cap.subdev.entity) {
814 sd = media_entity_to_v4l2_subdev(me);
815
816 sfmt.pad = 0;
817 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &sfmt);
818 if (ret)
819 return ret;
820
821 if (me->pads[0].flags & MEDIA_PAD_FL_SINK) {
822 sfmt.pad = me->num_pads - 1;
823 mf->code = tfmt->code;
824 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL,
825 &sfmt);
826 if (ret)
827 return ret;
828 }
829
1bddf1b3 830 pad = media_entity_remote_pad(&me->pads[sfmt.pad]);
47800bc4
SN
831 if (!pad)
832 return -EINVAL;
833 me = pad->entity;
237e0265 834 }
5f3cc447 835
47800bc4
SN
836 if (mf->code != tfmt->code)
837 continue;
838
839 fcc = ffmt->fourcc;
840 tfmt->width = mf->width;
841 tfmt->height = mf->height;
842 ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height,
88fa8311 843 NULL, &fcc, FIMC_SD_PAD_SINK_CAM);
47800bc4
SN
844 ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height,
845 NULL, &fcc, FIMC_SD_PAD_SOURCE);
846 if (ffmt && ffmt->mbus_code)
847 mf->code = ffmt->mbus_code;
848 if (mf->width != tfmt->width || mf->height != tfmt->height)
849 continue;
850 tfmt->code = mf->code;
851 break;
237e0265 852 }
5f3cc447 853
237e0265
SN
854 if (fmt_id && ffmt)
855 *fmt_id = ffmt;
856 *tfmt = *mf;
5f3cc447 857
237e0265
SN
858 return 0;
859}
5f3cc447 860
14783d25
SN
861/**
862 * fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters
863 * @sensor: pointer to the sensor subdev
864 * @plane_fmt: provides plane sizes corresponding to the frame layout entries
865 * @try: true to set the frame parameters, false to query only
866 *
867 * This function is used by this driver only for compressed/blob data formats.
868 */
869static int fimc_get_sensor_frame_desc(struct v4l2_subdev *sensor,
870 struct v4l2_plane_pix_format *plane_fmt,
871 unsigned int num_planes, bool try)
872{
873 struct v4l2_mbus_frame_desc fd;
874 int i, ret;
1c9f5bd7 875 int pad;
14783d25
SN
876
877 for (i = 0; i < num_planes; i++)
878 fd.entry[i].length = plane_fmt[i].sizeimage;
879
1c9f5bd7 880 pad = sensor->entity.num_pads - 1;
14783d25 881 if (try)
1c9f5bd7 882 ret = v4l2_subdev_call(sensor, pad, set_frame_desc, pad, &fd);
14783d25 883 else
1c9f5bd7 884 ret = v4l2_subdev_call(sensor, pad, get_frame_desc, pad, &fd);
14783d25
SN
885
886 if (ret < 0)
887 return ret;
888
889 if (num_planes != fd.num_entries)
890 return -EINVAL;
891
892 for (i = 0; i < num_planes; i++)
893 plane_fmt[i].sizeimage = fd.entry[i].length;
894
895 if (fd.entry[0].length > FIMC_MAX_JPEG_BUF_SIZE) {
896 v4l2_err(sensor->v4l2_dev, "Unsupported buffer size: %u\n",
897 fd.entry[0].length);
898
899 return -EINVAL;
900 }
901
902 return 0;
903}
904
e578588e
SN
905static int fimc_cap_g_fmt_mplane(struct file *file, void *fh,
906 struct v4l2_format *f)
907{
908 struct fimc_dev *fimc = video_drvdata(file);
e578588e 909
fa8880be
SN
910 __fimc_get_format(&fimc->vid_cap.ctx->d_frame, f);
911 return 0;
e578588e
SN
912}
913
7536b424
SN
914/*
915 * Try or set format on the fimc.X.capture video node and additionally
916 * on the whole pipeline if @try is false.
917 * Locking: the caller must _not_ hold the graph mutex.
918 */
919static int __video_try_or_set_format(struct fimc_dev *fimc,
920 struct v4l2_format *f, bool try,
921 struct fimc_fmt **inp_fmt,
922 struct fimc_fmt **out_fmt)
e578588e 923{
237e0265 924 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
7536b424
SN
925 struct fimc_vid_cap *vc = &fimc->vid_cap;
926 struct exynos_video_entity *ve = &vc->ve;
927 struct fimc_ctx *ctx = vc->ctx;
928 unsigned int width = 0, height = 0;
740ad921
SN
929 int ret = 0;
930
7536b424 931 /* Pre-configure format at the camera input interface, for JPEG only */
14783d25 932 if (fimc_jpeg_fourcc(pix->pixelformat)) {
237e0265
SN
933 fimc_capture_try_format(ctx, &pix->width, &pix->height,
934 NULL, &pix->pixelformat,
88fa8311 935 FIMC_SD_PAD_SINK_CAM);
7536b424
SN
936 if (try) {
937 width = pix->width;
938 height = pix->height;
939 } else {
940 ctx->s_frame.f_width = pix->width;
941 ctx->s_frame.f_height = pix->height;
942 }
237e0265 943 }
7536b424
SN
944
945 /* Try the format at the scaler and the DMA output */
946 *out_fmt = fimc_capture_try_format(ctx, &pix->width, &pix->height,
947 NULL, &pix->pixelformat,
948 FIMC_SD_PAD_SOURCE);
949 if (*out_fmt == NULL)
42625fdf 950 return -EINVAL;
237e0265 951
7536b424
SN
952 /* Restore image width/height for JPEG (no resizing supported). */
953 if (try && fimc_jpeg_fourcc(pix->pixelformat)) {
954 pix->width = width;
955 pix->height = height;
956 }
957
958 /* Try to match format at the host and the sensor */
959 if (!vc->user_subdev_api) {
960 struct v4l2_mbus_framefmt mbus_fmt;
961 struct v4l2_mbus_framefmt *mf;
962
963 mf = try ? &mbus_fmt : &fimc->vid_cap.ci_fmt;
964
965 mf->code = (*out_fmt)->mbus_code;
966 mf->width = pix->width;
967 mf->height = pix->height;
42625fdf
SN
968
969 fimc_md_graph_lock(ve);
7536b424 970 ret = fimc_pipeline_try_format(ctx, mf, inp_fmt, try);
42625fdf
SN
971 fimc_md_graph_unlock(ve);
972
7536b424
SN
973 if (ret < 0)
974 return ret;
975
976 pix->width = mf->width;
977 pix->height = mf->height;
237e0265 978 }
e578588e 979
7536b424
SN
980 fimc_adjust_mplane_format(*out_fmt, pix->width, pix->height, pix);
981
982 if ((*out_fmt)->flags & FMT_FLAGS_COMPRESSED) {
983 struct v4l2_subdev *sensor;
14783d25 984
403dfbec
SN
985 fimc_md_graph_lock(ve);
986
987 sensor = __fimc_md_get_subdev(ve->pipe, IDX_SENSOR);
988 if (sensor)
989 fimc_get_sensor_frame_desc(sensor, pix->plane_fmt,
7536b424 990 (*out_fmt)->memplanes, try);
403dfbec
SN
991 else
992 ret = -EPIPE;
993
994 fimc_md_graph_unlock(ve);
995 }
14783d25 996
740ad921 997 return ret;
e578588e
SN
998}
999
7536b424
SN
1000static int fimc_cap_try_fmt_mplane(struct file *file, void *fh,
1001 struct v4l2_format *f)
1002{
1003 struct fimc_dev *fimc = video_drvdata(file);
1004 struct fimc_fmt *out_fmt = NULL, *inp_fmt = NULL;
1005
1006 return __video_try_or_set_format(fimc, f, true, &inp_fmt, &out_fmt);
1007}
1008
14783d25
SN
1009static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx,
1010 enum fimc_color_fmt color)
ee7160e5 1011{
14783d25
SN
1012 bool jpeg = fimc_fmt_is_user_defined(color);
1013
ee7160e5
SN
1014 ctx->scaler.enabled = !jpeg;
1015 fimc_ctrls_activate(ctx, !jpeg);
1016
1017 if (jpeg)
1018 set_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
1019 else
1020 clear_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
1021}
1022
740ad921
SN
1023static int __fimc_capture_set_format(struct fimc_dev *fimc,
1024 struct v4l2_format *f)
5f3cc447 1025{
7536b424
SN
1026 struct fimc_vid_cap *vc = &fimc->vid_cap;
1027 struct fimc_ctx *ctx = vc->ctx;
237e0265 1028 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
237e0265 1029 struct fimc_frame *ff = &ctx->d_frame;
7536b424 1030 struct fimc_fmt *inp_fmt = NULL;
237e0265 1031 int ret, i;
5f3cc447 1032
237e0265 1033 if (vb2_is_busy(&fimc->vid_cap.vbq))
ef7af59b 1034 return -EBUSY;
5f3cc447 1035
7536b424
SN
1036 ret = __video_try_or_set_format(fimc, f, false, &inp_fmt, &ff->fmt);
1037 if (ret < 0)
1038 return ret;
dafb9c70
SN
1039
1040 /* Update RGB Alpha control state and value range */
1041 fimc_alpha_ctrl_update(ctx);
1042
fa8880be
SN
1043 for (i = 0; i < ff->fmt->memplanes; i++) {
1044 ff->bytesperline[i] = pix->plane_fmt[i].bytesperline;
d547ab66 1045 ff->payload[i] = pix->plane_fmt[i].sizeimage;
fa8880be 1046 }
237e0265
SN
1047
1048 set_frame_bounds(ff, pix->width, pix->height);
1049 /* Reset the composition rectangle if not yet configured */
fed07f84 1050 if (!(ctx->state & FIMC_COMPOSE))
237e0265
SN
1051 set_frame_crop(ff, 0, 0, pix->width, pix->height);
1052
14783d25 1053 fimc_capture_mark_jpeg_xfer(ctx, ff->fmt->color);
ee7160e5 1054
237e0265 1055 /* Reset cropping and set format at the camera interface input */
7536b424
SN
1056 if (!vc->user_subdev_api) {
1057 ctx->s_frame.fmt = inp_fmt;
237e0265
SN
1058 set_frame_bounds(&ctx->s_frame, pix->width, pix->height);
1059 set_frame_crop(&ctx->s_frame, 0, 0, pix->width, pix->height);
045030fa 1060 }
ef7af59b 1061
237e0265
SN
1062 return ret;
1063}
5f3cc447 1064
237e0265
SN
1065static int fimc_cap_s_fmt_mplane(struct file *file, void *priv,
1066 struct v4l2_format *f)
1067{
1068 struct fimc_dev *fimc = video_drvdata(file);
740ad921 1069
7536b424 1070 return __fimc_capture_set_format(fimc, f);
5f3cc447
SN
1071}
1072
1073static int fimc_cap_enum_input(struct file *file, void *priv,
3e002182 1074 struct v4l2_input *i)
5f3cc447 1075{
e578588e 1076 struct fimc_dev *fimc = video_drvdata(file);
403dfbec
SN
1077 struct exynos_video_entity *ve = &fimc->vid_cap.ve;
1078 struct v4l2_subdev *sd;
5f3cc447 1079
3e002182 1080 if (i->index != 0)
5f3cc447
SN
1081 return -EINVAL;
1082
5f3cc447 1083 i->type = V4L2_INPUT_TYPE_CAMERA;
403dfbec
SN
1084 fimc_md_graph_lock(ve);
1085 sd = __fimc_md_get_subdev(ve->pipe, IDX_SENSOR);
1086 fimc_md_graph_unlock(ve);
1087
4db5e27e
SN
1088 if (sd)
1089 strlcpy(i->name, sd->name, sizeof(i->name));
403dfbec 1090
5f3cc447
SN
1091 return 0;
1092}
1093
3e002182 1094static int fimc_cap_s_input(struct file *file, void *priv, unsigned int i)
5f3cc447 1095{
3e002182 1096 return i == 0 ? i : -EINVAL;
5f3cc447
SN
1097}
1098
3e002182 1099static int fimc_cap_g_input(struct file *file, void *priv, unsigned int *i)
5f3cc447 1100{
3e002182 1101 *i = 0;
5f3cc447
SN
1102 return 0;
1103}
1104
237e0265
SN
1105/**
1106 * fimc_pipeline_validate - check for formats inconsistencies
1107 * between source and sink pad of each link
1108 *
1109 * Return 0 if all formats match or -EPIPE otherwise.
1110 */
1111static int fimc_pipeline_validate(struct fimc_dev *fimc)
1112{
1113 struct v4l2_subdev_format sink_fmt, src_fmt;
88fa8311
SN
1114 struct fimc_vid_cap *vc = &fimc->vid_cap;
1115 struct v4l2_subdev *sd = &vc->subdev;
403dfbec 1116 struct fimc_pipeline *p = to_fimc_pipeline(vc->ve.pipe);
88fa8311
SN
1117 struct media_pad *sink_pad, *src_pad;
1118 int i, ret;
237e0265
SN
1119
1120 while (1) {
88fa8311
SN
1121 /*
1122 * Find current entity sink pad and any remote sink pad linked
1123 * to it. We stop if there is no sink pad in current entity or
1124 * it is not linked to any other remote entity.
1125 */
1126 src_pad = NULL;
1127
1128 for (i = 0; i < sd->entity.num_pads; i++) {
1129 struct media_pad *p = &sd->entity.pads[i];
1130
1131 if (p->flags & MEDIA_PAD_FL_SINK) {
1132 sink_pad = p;
1bddf1b3 1133 src_pad = media_entity_remote_pad(sink_pad);
88fa8311
SN
1134 if (src_pad)
1135 break;
1136 }
1137 }
1138
1139 if (src_pad == NULL ||
1140 media_entity_type(src_pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
237e0265 1141 break;
88fa8311 1142
237e0265 1143 /* Don't call FIMC subdev operation to avoid nested locking */
88fa8311
SN
1144 if (sd == &vc->subdev) {
1145 struct fimc_frame *ff = &vc->ctx->s_frame;
237e0265
SN
1146 sink_fmt.format.width = ff->f_width;
1147 sink_fmt.format.height = ff->f_height;
1148 sink_fmt.format.code = ff->fmt ? ff->fmt->mbus_code : 0;
1149 } else {
88fa8311 1150 sink_fmt.pad = sink_pad->index;
237e0265
SN
1151 sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1152 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt);
1153 if (ret < 0 && ret != -ENOIOCTLCMD)
1154 return -EPIPE;
1155 }
237e0265 1156
88fa8311
SN
1157 /* Retrieve format at the source pad */
1158 sd = media_entity_to_v4l2_subdev(src_pad->entity);
1159 src_fmt.pad = src_pad->index;
237e0265
SN
1160 src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1161 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
1162 if (ret < 0 && ret != -ENOIOCTLCMD)
1163 return -EPIPE;
1164
1165 if (src_fmt.format.width != sink_fmt.format.width ||
1166 src_fmt.format.height != sink_fmt.format.height ||
1167 src_fmt.format.code != sink_fmt.format.code)
1168 return -EPIPE;
14783d25 1169
403dfbec 1170 if (sd == p->subdevs[IDX_SENSOR] &&
14783d25
SN
1171 fimc_user_defined_mbus_fmt(src_fmt.format.code)) {
1172 struct v4l2_plane_pix_format plane_fmt[FIMC_MAX_PLANES];
88fa8311 1173 struct fimc_frame *frame = &vc->ctx->d_frame;
14783d25
SN
1174 unsigned int i;
1175
1176 ret = fimc_get_sensor_frame_desc(sd, plane_fmt,
1177 frame->fmt->memplanes,
1178 false);
1179 if (ret < 0)
1180 return -EPIPE;
1181
1182 for (i = 0; i < frame->fmt->memplanes; i++)
1183 if (frame->payload[i] < plane_fmt[i].sizeimage)
1184 return -EPIPE;
1185 }
237e0265
SN
1186 }
1187 return 0;
1188}
1189
5f3cc447 1190static int fimc_cap_streamon(struct file *file, void *priv,
2dab38e2 1191 enum v4l2_buf_type type)
5f3cc447 1192{
e578588e 1193 struct fimc_dev *fimc = video_drvdata(file);
95c4a17f 1194 struct fimc_vid_cap *vc = &fimc->vid_cap;
bc7584b0 1195 struct media_entity *entity = &vc->ve.vdev.entity;
88fa8311
SN
1196 struct fimc_source_info *si = NULL;
1197 struct v4l2_subdev *sd;
237e0265 1198 int ret;
5f3cc447 1199
4db5e27e 1200 if (fimc_capture_active(fimc))
8293ebfc 1201 return -EBUSY;
5f3cc447 1202
403dfbec 1203 ret = media_entity_pipeline_start(entity, &vc->ve.pipe->mp);
a60a2959
SA
1204 if (ret < 0)
1205 return ret;
5f3cc447 1206
403dfbec 1207 sd = __fimc_md_get_subdev(vc->ve.pipe, IDX_SENSOR);
88fa8311
SN
1208 if (sd)
1209 si = v4l2_get_subdev_hostdata(sd);
1210
1211 if (si == NULL) {
1212 ret = -EPIPE;
1213 goto err_p_stop;
1214 }
1215 /*
1216 * Save configuration data related to currently attached image
1217 * sensor or other data source, e.g. FIMC-IS.
1218 */
1219 vc->source_config = *si;
1220
1221 if (vc->input == GRP_ID_FIMC_IS)
1222 vc->source_config.fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK;
1223
95c4a17f 1224 if (vc->user_subdev_api) {
237e0265 1225 ret = fimc_pipeline_validate(fimc);
95c4a17f
SN
1226 if (ret < 0)
1227 goto err_p_stop;
237e0265 1228 }
95c4a17f 1229
c444914a 1230 ret = vb2_ioctl_streamon(file, priv, type);
9ea89e2b
SN
1231 if (!ret) {
1232 vc->streaming = true;
95c4a17f 1233 return ret;
9ea89e2b 1234 }
95c4a17f
SN
1235
1236err_p_stop:
1237 media_entity_pipeline_stop(entity);
1238 return ret;
5f3cc447
SN
1239}
1240
1241static int fimc_cap_streamoff(struct file *file, void *priv,
8293ebfc 1242 enum v4l2_buf_type type)
5f3cc447 1243{
e578588e 1244 struct fimc_dev *fimc = video_drvdata(file);
bc7584b0 1245 struct fimc_vid_cap *vc = &fimc->vid_cap;
4db5e27e 1246 int ret;
5f3cc447 1247
c444914a 1248 ret = vb2_ioctl_streamoff(file, priv, type);
9ea89e2b
SN
1249 if (ret < 0)
1250 return ret;
95c4a17f 1251
bc7584b0
SN
1252 media_entity_pipeline_stop(&vc->ve.vdev.entity);
1253 vc->streaming = false;
9ea89e2b 1254 return 0;
5f3cc447
SN
1255}
1256
1257static int fimc_cap_reqbufs(struct file *file, void *priv,
ef7af59b 1258 struct v4l2_requestbuffers *reqbufs)
5f3cc447 1259{
e578588e 1260 struct fimc_dev *fimc = video_drvdata(file);
c444914a
SN
1261 int ret;
1262
1263 ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
5f3cc447 1264
5f3cc447 1265 if (!ret)
e578588e 1266 fimc->vid_cap.reqbufs_count = reqbufs->count;
3b4c34aa 1267
c444914a 1268 return ret;
3b4c34aa
SN
1269}
1270
f9331d11
SN
1271static int fimc_cap_g_selection(struct file *file, void *fh,
1272 struct v4l2_selection *s)
e004e02f 1273{
e578588e 1274 struct fimc_dev *fimc = video_drvdata(file);
f9331d11
SN
1275 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
1276 struct fimc_frame *f = &ctx->s_frame;
e004e02f 1277
f9331d11 1278 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
e004e02f
SN
1279 return -EINVAL;
1280
f9331d11
SN
1281 switch (s->target) {
1282 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1283 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1284 f = &ctx->d_frame;
1285 case V4L2_SEL_TGT_CROP_BOUNDS:
1286 case V4L2_SEL_TGT_CROP_DEFAULT:
1287 s->r.left = 0;
1288 s->r.top = 0;
1289 s->r.width = f->o_width;
1290 s->r.height = f->o_height;
1291 return 0;
e004e02f 1292
c1334823 1293 case V4L2_SEL_TGT_COMPOSE:
f9331d11 1294 f = &ctx->d_frame;
c1334823 1295 case V4L2_SEL_TGT_CROP:
f9331d11
SN
1296 s->r.left = f->offs_h;
1297 s->r.top = f->offs_v;
1298 s->r.width = f->width;
1299 s->r.height = f->height;
1300 return 0;
1301 }
1302
1303 return -EINVAL;
e004e02f
SN
1304}
1305
f9331d11 1306/* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
7e566be2 1307static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
e004e02f 1308{
f9331d11
SN
1309 if (a->left < b->left || a->top < b->top)
1310 return 0;
1311 if (a->left + a->width > b->left + b->width)
1312 return 0;
1313 if (a->top + a->height > b->top + b->height)
1314 return 0;
e004e02f 1315
f9331d11 1316 return 1;
e004e02f
SN
1317}
1318
f9331d11
SN
1319static int fimc_cap_s_selection(struct file *file, void *fh,
1320 struct v4l2_selection *s)
5f3cc447 1321{
e578588e
SN
1322 struct fimc_dev *fimc = video_drvdata(file);
1323 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
f9331d11
SN
1324 struct v4l2_rect rect = s->r;
1325 struct fimc_frame *f;
237e0265 1326 unsigned long flags;
f9331d11
SN
1327
1328 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1329 return -EINVAL;
1330
c1334823 1331 if (s->target == V4L2_SEL_TGT_COMPOSE)
f9331d11 1332 f = &ctx->d_frame;
c1334823 1333 else if (s->target == V4L2_SEL_TGT_CROP)
f9331d11 1334 f = &ctx->s_frame;
fed07f84 1335 else
f9331d11 1336 return -EINVAL;
f9331d11 1337
fed07f84 1338 fimc_capture_try_selection(ctx, &rect, s->target);
f9331d11
SN
1339
1340 if (s->flags & V4L2_SEL_FLAG_LE &&
1341 !enclosed_rectangle(&rect, &s->r))
1342 return -ERANGE;
5f3cc447 1343
f9331d11
SN
1344 if (s->flags & V4L2_SEL_FLAG_GE &&
1345 !enclosed_rectangle(&s->r, &rect))
1346 return -ERANGE;
5f3cc447 1347
f9331d11 1348 s->r = rect;
237e0265 1349 spin_lock_irqsave(&fimc->slock, flags);
f9331d11
SN
1350 set_frame_crop(f, s->r.left, s->r.top, s->r.width,
1351 s->r.height);
237e0265 1352 spin_unlock_irqrestore(&fimc->slock, flags);
8293ebfc 1353
f9331d11 1354 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
8293ebfc 1355 return 0;
5f3cc447
SN
1356}
1357
5f3cc447 1358static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = {
aceb59ed 1359 .vidioc_querycap = fimc_cap_querycap,
5f3cc447 1360
cf52df8a 1361 .vidioc_enum_fmt_vid_cap_mplane = fimc_cap_enum_fmt_mplane,
e578588e 1362 .vidioc_try_fmt_vid_cap_mplane = fimc_cap_try_fmt_mplane,
ef7af59b 1363 .vidioc_s_fmt_vid_cap_mplane = fimc_cap_s_fmt_mplane,
e578588e 1364 .vidioc_g_fmt_vid_cap_mplane = fimc_cap_g_fmt_mplane,
5f3cc447
SN
1365
1366 .vidioc_reqbufs = fimc_cap_reqbufs,
c444914a
SN
1367 .vidioc_querybuf = vb2_ioctl_querybuf,
1368 .vidioc_qbuf = vb2_ioctl_qbuf,
1369 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1370 .vidioc_expbuf = vb2_ioctl_expbuf,
1371 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1372 .vidioc_create_bufs = vb2_ioctl_create_bufs,
3b4c34aa 1373
5f3cc447
SN
1374 .vidioc_streamon = fimc_cap_streamon,
1375 .vidioc_streamoff = fimc_cap_streamoff,
1376
f9331d11
SN
1377 .vidioc_g_selection = fimc_cap_g_selection,
1378 .vidioc_s_selection = fimc_cap_s_selection,
5f3cc447
SN
1379
1380 .vidioc_enum_input = fimc_cap_enum_input,
1381 .vidioc_s_input = fimc_cap_s_input,
1382 .vidioc_g_input = fimc_cap_g_input,
1383};
1384
237e0265 1385/* Capture subdev media entity operations */
d09a7dc8
SN
1386static int fimc_link_setup(struct media_entity *entity,
1387 const struct media_pad *local,
1388 const struct media_pad *remote, u32 flags)
1389{
237e0265
SN
1390 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1391 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
4403106d
SN
1392 struct fimc_vid_cap *vc = &fimc->vid_cap;
1393 struct v4l2_subdev *sensor;
237e0265
SN
1394
1395 if (media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
1396 return -EINVAL;
d09a7dc8
SN
1397
1398 if (WARN_ON(fimc == NULL))
1399 return 0;
1400
1401 dbg("%s --> %s, flags: 0x%x. input: 0x%x",
1402 local->entity->name, remote->entity->name, flags,
1403 fimc->vid_cap.input);
1404
4403106d
SN
1405 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
1406 fimc->vid_cap.input = 0;
d09a7dc8
SN
1407 return 0;
1408 }
1409
4403106d
SN
1410 if (vc->input != 0)
1411 return -EBUSY;
1412
1413 vc->input = sd->grp_id;
1414
1415 if (vc->user_subdev_api || vc->inh_sensor_ctrls)
1416 return 0;
1417
1418 /* Inherit V4L2 controls from the image sensor subdev. */
1419 sensor = fimc_find_remote_sensor(&vc->subdev.entity);
1420 if (sensor == NULL)
1421 return 0;
1422
1423 return v4l2_ctrl_add_handler(&vc->ctx->ctrls.handler,
1424 sensor->ctrl_handler, NULL);
d09a7dc8
SN
1425}
1426
237e0265 1427static const struct media_entity_operations fimc_sd_media_ops = {
d09a7dc8
SN
1428 .link_setup = fimc_link_setup,
1429};
1430
e1d72f4d
SN
1431/**
1432 * fimc_sensor_notify - v4l2_device notification from a sensor subdev
1433 * @sd: pointer to a subdev generating the notification
1434 * @notification: the notification type, must be S5P_FIMC_TX_END_NOTIFY
1435 * @arg: pointer to an u32 type integer that stores the frame payload value
1436 *
1437 * The End Of Frame notification sent by sensor subdev in its still capture
1438 * mode. If there is only a single VSYNC generated by the sensor at the
1439 * beginning of a frame transmission, FIMC does not issue the LastIrq
1440 * (end of frame) interrupt. And this notification is used to complete the
1441 * frame capture and returning a buffer to user-space. Subdev drivers should
1442 * call this notification from their last 'End of frame capture' interrupt.
1443 */
1444void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
1445 void *arg)
1446{
4c8f0629 1447 struct fimc_source_info *si;
e1d72f4d
SN
1448 struct fimc_vid_buffer *buf;
1449 struct fimc_md *fmd;
1450 struct fimc_dev *fimc;
1451 unsigned long flags;
1452
1453 if (sd == NULL)
1454 return;
1455
4c8f0629 1456 si = v4l2_get_subdev_hostdata(sd);
e1d72f4d
SN
1457 fmd = entity_to_fimc_mdev(&sd->entity);
1458
1459 spin_lock_irqsave(&fmd->slock, flags);
4c8f0629
SN
1460
1461 fimc = si ? source_to_sensor_info(si)->host : NULL;
e1d72f4d
SN
1462
1463 if (fimc && arg && notification == S5P_FIMC_TX_END_NOTIFY &&
1464 test_bit(ST_CAPT_PEND, &fimc->state)) {
1465 unsigned long irq_flags;
1466 spin_lock_irqsave(&fimc->slock, irq_flags);
1467 if (!list_empty(&fimc->vid_cap.active_buf_q)) {
1468 buf = list_entry(fimc->vid_cap.active_buf_q.next,
1469 struct fimc_vid_buffer, list);
2d700715
JS
1470 vb2_set_plane_payload(&buf->vb.vb2_buf, 0,
1471 *((u32 *)arg));
e1d72f4d 1472 }
97d97422 1473 fimc_capture_irq_handler(fimc, 1);
e1d72f4d
SN
1474 fimc_deactivate_capture(fimc);
1475 spin_unlock_irqrestore(&fimc->slock, irq_flags);
1476 }
1477 spin_unlock_irqrestore(&fmd->slock, flags);
1478}
1479
237e0265 1480static int fimc_subdev_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1481 struct v4l2_subdev_pad_config *cfg,
237e0265
SN
1482 struct v4l2_subdev_mbus_code_enum *code)
1483{
1484 struct fimc_fmt *fmt;
1485
1486 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, code->index);
1487 if (!fmt)
1488 return -EINVAL;
1489 code->code = fmt->mbus_code;
1490 return 0;
1491}
1492
1493static int fimc_subdev_get_fmt(struct v4l2_subdev *sd,
f7234138 1494 struct v4l2_subdev_pad_config *cfg,
237e0265
SN
1495 struct v4l2_subdev_format *fmt)
1496{
1497 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1498 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
88fa8311 1499 struct fimc_frame *ff = &ctx->s_frame;
237e0265 1500 struct v4l2_mbus_framefmt *mf;
237e0265
SN
1501
1502 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
f7234138 1503 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
237e0265
SN
1504 fmt->format = *mf;
1505 return 0;
1506 }
237e0265 1507
88fa8311 1508 mf = &fmt->format;
237e0265 1509 mutex_lock(&fimc->lock);
88fa8311
SN
1510
1511 switch (fmt->pad) {
1512 case FIMC_SD_PAD_SOURCE:
1513 if (!WARN_ON(ff->fmt == NULL))
1514 mf->code = ff->fmt->mbus_code;
1515 /* Sink pads crop rectangle size */
1516 mf->width = ff->width;
1517 mf->height = ff->height;
1518 break;
1519 case FIMC_SD_PAD_SINK_FIFO:
1520 *mf = fimc->vid_cap.wb_fmt;
1521 break;
1522 case FIMC_SD_PAD_SINK_CAM:
1523 default:
1524 *mf = fimc->vid_cap.ci_fmt;
1525 break;
1526 }
1527
237e0265 1528 mutex_unlock(&fimc->lock);
88fa8311 1529 mf->colorspace = V4L2_COLORSPACE_JPEG;
237e0265
SN
1530
1531 return 0;
1532}
1533
1534static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,
f7234138 1535 struct v4l2_subdev_pad_config *cfg,
237e0265
SN
1536 struct v4l2_subdev_format *fmt)
1537{
1538 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1539 struct v4l2_mbus_framefmt *mf = &fmt->format;
88fa8311
SN
1540 struct fimc_vid_cap *vc = &fimc->vid_cap;
1541 struct fimc_ctx *ctx = vc->ctx;
237e0265
SN
1542 struct fimc_frame *ff;
1543 struct fimc_fmt *ffmt;
1544
1545 dbg("pad%d: code: 0x%x, %dx%d",
1546 fmt->pad, mf->code, mf->width, mf->height);
1547
88fa8311 1548 if (fmt->pad == FIMC_SD_PAD_SOURCE && vb2_is_busy(&vc->vbq))
237e0265
SN
1549 return -EBUSY;
1550
1551 mutex_lock(&fimc->lock);
1552 ffmt = fimc_capture_try_format(ctx, &mf->width, &mf->height,
1553 &mf->code, NULL, fmt->pad);
1554 mutex_unlock(&fimc->lock);
1555 mf->colorspace = V4L2_COLORSPACE_JPEG;
1556
1557 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
f7234138 1558 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
237e0265
SN
1559 *mf = fmt->format;
1560 return 0;
1561 }
6612545f
SN
1562 /* There must be a bug in the driver if this happens */
1563 if (WARN_ON(ffmt == NULL))
1564 return -EINVAL;
1565
dafb9c70
SN
1566 /* Update RGB Alpha control state and value range */
1567 fimc_alpha_ctrl_update(ctx);
1568
14783d25 1569 fimc_capture_mark_jpeg_xfer(ctx, ffmt->color);
88fa8311
SN
1570 if (fmt->pad == FIMC_SD_PAD_SOURCE) {
1571 ff = &ctx->d_frame;
1572 /* Sink pads crop rectangle size */
1573 mf->width = ctx->s_frame.width;
1574 mf->height = ctx->s_frame.height;
1575 } else {
1576 ff = &ctx->s_frame;
1577 }
237e0265
SN
1578
1579 mutex_lock(&fimc->lock);
1580 set_frame_bounds(ff, mf->width, mf->height);
88fa8311
SN
1581
1582 if (fmt->pad == FIMC_SD_PAD_SINK_FIFO)
1583 vc->wb_fmt = *mf;
1584 else if (fmt->pad == FIMC_SD_PAD_SINK_CAM)
1585 vc->ci_fmt = *mf;
1586
237e0265
SN
1587 ff->fmt = ffmt;
1588
1589 /* Reset the crop rectangle if required. */
fed07f84 1590 if (!(fmt->pad == FIMC_SD_PAD_SOURCE && (ctx->state & FIMC_COMPOSE)))
237e0265
SN
1591 set_frame_crop(ff, 0, 0, mf->width, mf->height);
1592
88fa8311 1593 if (fmt->pad != FIMC_SD_PAD_SOURCE)
fed07f84 1594 ctx->state &= ~FIMC_COMPOSE;
88fa8311 1595
237e0265
SN
1596 mutex_unlock(&fimc->lock);
1597 return 0;
1598}
1599
fed07f84 1600static int fimc_subdev_get_selection(struct v4l2_subdev *sd,
f7234138 1601 struct v4l2_subdev_pad_config *cfg,
fed07f84 1602 struct v4l2_subdev_selection *sel)
237e0265
SN
1603{
1604 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1605 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
fed07f84
SN
1606 struct fimc_frame *f = &ctx->s_frame;
1607 struct v4l2_rect *r = &sel->r;
1608 struct v4l2_rect *try_sel;
1609
88fa8311 1610 if (sel->pad == FIMC_SD_PAD_SOURCE)
fed07f84
SN
1611 return -EINVAL;
1612
1613 mutex_lock(&fimc->lock);
237e0265 1614
fed07f84 1615 switch (sel->target) {
5689b288 1616 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
fed07f84 1617 f = &ctx->d_frame;
5689b288 1618 case V4L2_SEL_TGT_CROP_BOUNDS:
fed07f84
SN
1619 r->width = f->o_width;
1620 r->height = f->o_height;
1621 r->left = 0;
1622 r->top = 0;
1623 mutex_unlock(&fimc->lock);
237e0265 1624 return 0;
fed07f84 1625
5689b288 1626 case V4L2_SEL_TGT_CROP:
f7234138 1627 try_sel = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
fed07f84 1628 break;
5689b288 1629 case V4L2_SEL_TGT_COMPOSE:
f7234138 1630 try_sel = v4l2_subdev_get_try_compose(sd, cfg, sel->pad);
fed07f84
SN
1631 f = &ctx->d_frame;
1632 break;
1633 default:
1634 mutex_unlock(&fimc->lock);
1635 return -EINVAL;
237e0265 1636 }
237e0265 1637
fed07f84
SN
1638 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1639 sel->r = *try_sel;
1640 } else {
1641 r->left = f->offs_h;
1642 r->top = f->offs_v;
1643 r->width = f->width;
1644 r->height = f->height;
1645 }
237e0265 1646
fed07f84
SN
1647 dbg("target %#x: l:%d, t:%d, %dx%d, f_w: %d, f_h: %d",
1648 sel->pad, r->left, r->top, r->width, r->height,
1649 f->f_width, f->f_height);
237e0265 1650
fed07f84 1651 mutex_unlock(&fimc->lock);
237e0265
SN
1652 return 0;
1653}
1654
fed07f84 1655static int fimc_subdev_set_selection(struct v4l2_subdev *sd,
f7234138 1656 struct v4l2_subdev_pad_config *cfg,
fed07f84 1657 struct v4l2_subdev_selection *sel)
237e0265
SN
1658{
1659 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1660 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
fed07f84
SN
1661 struct fimc_frame *f = &ctx->s_frame;
1662 struct v4l2_rect *r = &sel->r;
1663 struct v4l2_rect *try_sel;
237e0265
SN
1664 unsigned long flags;
1665
88fa8311 1666 if (sel->pad == FIMC_SD_PAD_SOURCE)
fed07f84 1667 return -EINVAL;
237e0265
SN
1668
1669 mutex_lock(&fimc->lock);
c1334823 1670 fimc_capture_try_selection(ctx, r, V4L2_SEL_TGT_CROP);
237e0265 1671
fed07f84 1672 switch (sel->target) {
5689b288 1673 case V4L2_SEL_TGT_CROP:
f7234138 1674 try_sel = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
fed07f84 1675 break;
5689b288 1676 case V4L2_SEL_TGT_COMPOSE:
f7234138 1677 try_sel = v4l2_subdev_get_try_compose(sd, cfg, sel->pad);
fed07f84
SN
1678 f = &ctx->d_frame;
1679 break;
1680 default:
1681 mutex_unlock(&fimc->lock);
1682 return -EINVAL;
237e0265 1683 }
237e0265 1684
fed07f84
SN
1685 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1686 *try_sel = sel->r;
1687 } else {
1688 spin_lock_irqsave(&fimc->slock, flags);
1689 set_frame_crop(f, r->left, r->top, r->width, r->height);
1690 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
5689b288 1691 if (sel->target == V4L2_SEL_TGT_COMPOSE)
fed07f84 1692 ctx->state |= FIMC_COMPOSE;
8b164105 1693 spin_unlock_irqrestore(&fimc->slock, flags);
fed07f84 1694 }
237e0265 1695
fed07f84 1696 dbg("target %#x: (%d,%d)/%dx%d", sel->target, r->left, r->top,
237e0265
SN
1697 r->width, r->height);
1698
1699 mutex_unlock(&fimc->lock);
1700 return 0;
1701}
1702
1703static struct v4l2_subdev_pad_ops fimc_subdev_pad_ops = {
1704 .enum_mbus_code = fimc_subdev_enum_mbus_code,
fed07f84
SN
1705 .get_selection = fimc_subdev_get_selection,
1706 .set_selection = fimc_subdev_set_selection,
237e0265
SN
1707 .get_fmt = fimc_subdev_get_fmt,
1708 .set_fmt = fimc_subdev_set_fmt,
237e0265
SN
1709};
1710
1711static struct v4l2_subdev_ops fimc_subdev_ops = {
1712 .pad = &fimc_subdev_pad_ops,
1713};
1714
237e0265
SN
1715/* Set default format at the sensor and host interface */
1716static int fimc_capture_set_default_format(struct fimc_dev *fimc)
1717{
1718 struct v4l2_format fmt = {
1719 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
1720 .fmt.pix_mp = {
3ad86245
SN
1721 .width = FIMC_DEFAULT_WIDTH,
1722 .height = FIMC_DEFAULT_HEIGHT,
237e0265
SN
1723 .pixelformat = V4L2_PIX_FMT_YUYV,
1724 .field = V4L2_FIELD_NONE,
1725 .colorspace = V4L2_COLORSPACE_JPEG,
1726 },
1727 };
1728
740ad921 1729 return __fimc_capture_set_format(fimc, &fmt);
237e0265
SN
1730}
1731
ef7af59b 1732/* fimc->lock must be already initialized */
693f5c40 1733static int fimc_register_capture_device(struct fimc_dev *fimc,
30c9939d 1734 struct v4l2_device *v4l2_dev)
5f3cc447 1735{
bc7584b0 1736 struct video_device *vfd = &fimc->vid_cap.ve.vdev;
c444914a 1737 struct vb2_queue *q = &fimc->vid_cap.vbq;
5f3cc447 1738 struct fimc_ctx *ctx;
c444914a 1739 struct fimc_vid_cap *vid_cap;
3ad86245 1740 struct fimc_fmt *fmt;
30c9939d 1741 int ret = -ENOMEM;
5f3cc447 1742
26ee7f47 1743 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
5f3cc447
SN
1744 if (!ctx)
1745 return -ENOMEM;
1746
1747 ctx->fimc_dev = fimc;
3d112d9a
SN
1748 ctx->in_path = FIMC_IO_CAMERA;
1749 ctx->out_path = FIMC_IO_DMA;
5f3cc447 1750 ctx->state = FIMC_CTX_CAP;
237e0265 1751 ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0);
693f5c40 1752 ctx->d_frame.fmt = ctx->s_frame.fmt;
5f3cc447 1753
31d34d9b 1754 memset(vfd, 0, sizeof(*vfd));
693f5c40 1755 snprintf(vfd->name, sizeof(vfd->name), "fimc.%d.capture", fimc->id);
5f3cc447
SN
1756
1757 vfd->fops = &fimc_capture_fops;
1758 vfd->ioctl_ops = &fimc_capture_ioctl_ops;
574e1717 1759 vfd->v4l2_dev = v4l2_dev;
5f3cc447 1760 vfd->minor = -1;
31d34d9b 1761 vfd->release = video_device_release_empty;
c444914a 1762 vfd->queue = q;
8293ebfc 1763 vfd->lock = &fimc->lock;
c2d430af 1764
5f3cc447 1765 video_set_drvdata(vfd, fimc);
5f3cc447 1766 vid_cap = &fimc->vid_cap;
5f3cc447 1767 vid_cap->active_buf_cnt = 0;
c444914a
SN
1768 vid_cap->reqbufs_count = 0;
1769 vid_cap->ctx = ctx;
5f3cc447
SN
1770
1771 INIT_LIST_HEAD(&vid_cap->pending_buf_q);
1772 INIT_LIST_HEAD(&vid_cap->active_buf_q);
5f3cc447 1773
2dab38e2 1774 memset(q, 0, sizeof(*q));
ef7af59b 1775 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
9bd09fd7 1776 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
c444914a 1777 q->drv_priv = ctx;
2dab38e2
SN
1778 q->ops = &fimc_capture_qops;
1779 q->mem_ops = &vb2_dma_contig_memops;
1780 q->buf_struct_size = sizeof(struct fimc_vid_buffer);
ade48681 1781 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
c444914a 1782 q->lock = &fimc->lock;
2dab38e2 1783
41fd087f
SN
1784 ret = vb2_queue_init(q);
1785 if (ret)
4403106d 1786 goto err_free_ctx;
5f3cc447 1787
3ad86245
SN
1788 /* Default format configuration */
1789 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0);
1790 vid_cap->ci_fmt.width = FIMC_DEFAULT_WIDTH;
1791 vid_cap->ci_fmt.height = FIMC_DEFAULT_HEIGHT;
1792 vid_cap->ci_fmt.code = fmt->mbus_code;
1793
1794 ctx->s_frame.width = FIMC_DEFAULT_WIDTH;
1795 ctx->s_frame.height = FIMC_DEFAULT_HEIGHT;
1796 ctx->s_frame.fmt = fmt;
1797
1798 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_WRITEBACK, 0);
1799 vid_cap->wb_fmt = vid_cap->ci_fmt;
1800 vid_cap->wb_fmt.code = fmt->mbus_code;
1801
693f5c40
SN
1802 vid_cap->vd_pad.flags = MEDIA_PAD_FL_SINK;
1803 ret = media_entity_init(&vfd->entity, 1, &vid_cap->vd_pad, 0);
574e1717 1804 if (ret)
4403106d
SN
1805 goto err_free_ctx;
1806
1807 ret = fimc_ctrls_create(ctx);
1808 if (ret)
1809 goto err_me_cleanup;
693f5c40
SN
1810
1811 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
237e0265 1812 if (ret)
4403106d 1813 goto err_ctrl_free;
693f5c40
SN
1814
1815 v4l2_info(v4l2_dev, "Registered %s as /dev/%s\n",
1816 vfd->name, video_device_node_name(vfd));
574e1717 1817
9448ab7d 1818 vfd->ctrl_handler = &ctx->ctrls.handler;
5f3cc447
SN
1819 return 0;
1820
4403106d
SN
1821err_ctrl_free:
1822 fimc_ctrls_delete(ctx);
1823err_me_cleanup:
237e0265 1824 media_entity_cleanup(&vfd->entity);
4403106d 1825err_free_ctx:
cfd77310 1826 kfree(ctx);
5f3cc447
SN
1827 return ret;
1828}
1829
693f5c40 1830static int fimc_capture_subdev_registered(struct v4l2_subdev *sd)
5f3cc447 1831{
693f5c40
SN
1832 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1833 int ret;
5f3cc447 1834
bbc5296f
SN
1835 if (fimc == NULL)
1836 return -ENXIO;
1837
693f5c40
SN
1838 ret = fimc_register_m2m_device(fimc, sd->v4l2_dev);
1839 if (ret)
1840 return ret;
1841
403dfbec 1842 fimc->vid_cap.ve.pipe = v4l2_get_subdev_hostdata(sd);
97d66c47 1843
693f5c40 1844 ret = fimc_register_capture_device(fimc, sd->v4l2_dev);
97d66c47 1845 if (ret) {
693f5c40 1846 fimc_unregister_m2m_device(fimc);
403dfbec 1847 fimc->vid_cap.ve.pipe = NULL;
97d66c47 1848 }
693f5c40
SN
1849
1850 return ret;
1851}
1852
1853static void fimc_capture_subdev_unregistered(struct v4l2_subdev *sd)
1854{
1855 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
bc7584b0 1856 struct video_device *vdev;
693f5c40
SN
1857
1858 if (fimc == NULL)
1859 return;
1860
26d63d13
SN
1861 mutex_lock(&fimc->lock);
1862
693f5c40 1863 fimc_unregister_m2m_device(fimc);
bc7584b0 1864 vdev = &fimc->vid_cap.ve.vdev;
693f5c40 1865
bc7584b0
SN
1866 if (video_is_registered(vdev)) {
1867 video_unregister_device(vdev);
1868 media_entity_cleanup(&vdev->entity);
4403106d 1869 fimc_ctrls_delete(fimc->vid_cap.ctx);
403dfbec 1870 fimc->vid_cap.ve.pipe = NULL;
574e1717
SN
1871 }
1872 kfree(fimc->vid_cap.ctx);
96a85742 1873 fimc->vid_cap.ctx = NULL;
26d63d13
SN
1874
1875 mutex_unlock(&fimc->lock);
5f3cc447 1876}
693f5c40
SN
1877
1878static const struct v4l2_subdev_internal_ops fimc_capture_sd_internal_ops = {
1879 .registered = fimc_capture_subdev_registered,
1880 .unregistered = fimc_capture_subdev_unregistered,
1881};
1882
1883int fimc_initialize_capture_subdev(struct fimc_dev *fimc)
1884{
1885 struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
1886 int ret;
1887
1888 v4l2_subdev_init(sd, &fimc_subdev_ops);
5a66561f 1889 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
e80cb1fa 1890 snprintf(sd->name, sizeof(sd->name), "FIMC.%d", fimc->id);
693f5c40 1891
88fa8311
SN
1892 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_CAM].flags = MEDIA_PAD_FL_SINK;
1893 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_FIFO].flags = MEDIA_PAD_FL_SINK;
693f5c40
SN
1894 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1895 ret = media_entity_init(&sd->entity, FIMC_SD_PADS_NUM,
1896 fimc->vid_cap.sd_pads, 0);
1897 if (ret)
1898 return ret;
1899
1900 sd->entity.ops = &fimc_sd_media_ops;
1901 sd->internal_ops = &fimc_capture_sd_internal_ops;
1902 v4l2_set_subdevdata(sd, fimc);
1903 return 0;
1904}
1905
1906void fimc_unregister_capture_subdev(struct fimc_dev *fimc)
1907{
1908 struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
1909
1910 v4l2_device_unregister_subdev(sd);
1911 media_entity_cleanup(&sd->entity);
1912 v4l2_set_subdevdata(sd, NULL);
1913}