Commit | Line | Data |
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5740f4e7 HV |
1 | /* |
2 | * tw68 functions to handle video data | |
3 | * | |
4 | * Much of this code is derived from the cx88 and sa7134 drivers, which | |
5 | * were in turn derived from the bt87x driver. The original work was by | |
6 | * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab, | |
7 | * Hans Verkuil, Andy Walls and many others. Their work is gratefully | |
8 | * acknowledged. Full credit goes to them - any problems within this code | |
9 | * are mine. | |
10 | * | |
e15d1c12 HV |
11 | * Copyright (C) 2009 William M. Brack |
12 | * | |
13 | * Refactored and updated to the latest v4l core frameworks: | |
14 | * | |
15 | * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl> | |
5740f4e7 HV |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2 of the License, or | |
20 | * (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
5740f4e7 HV |
26 | */ |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <media/v4l2-common.h> | |
e15d1c12 HV |
30 | #include <media/v4l2-event.h> |
31 | #include <media/videobuf2-dma-sg.h> | |
5740f4e7 HV |
32 | |
33 | #include "tw68.h" | |
34 | #include "tw68-reg.h" | |
35 | ||
5740f4e7 HV |
36 | /* ------------------------------------------------------------------ */ |
37 | /* data structs for video */ | |
38 | /* | |
39 | * FIXME - | |
40 | * Note that the saa7134 has formats, e.g. YUV420, which are classified | |
41 | * as "planar". These affect overlay mode, and are flagged with a field | |
42 | * ".planar" in the format. Do we need to implement this in this driver? | |
43 | */ | |
e15d1c12 | 44 | static const struct tw68_format formats[] = { |
5740f4e7 HV |
45 | { |
46 | .name = "15 bpp RGB, le", | |
47 | .fourcc = V4L2_PIX_FMT_RGB555, | |
48 | .depth = 16, | |
49 | .twformat = ColorFormatRGB15, | |
50 | }, { | |
51 | .name = "15 bpp RGB, be", | |
52 | .fourcc = V4L2_PIX_FMT_RGB555X, | |
53 | .depth = 16, | |
54 | .twformat = ColorFormatRGB15 | ColorFormatBSWAP, | |
55 | }, { | |
56 | .name = "16 bpp RGB, le", | |
57 | .fourcc = V4L2_PIX_FMT_RGB565, | |
58 | .depth = 16, | |
59 | .twformat = ColorFormatRGB16, | |
60 | }, { | |
61 | .name = "16 bpp RGB, be", | |
62 | .fourcc = V4L2_PIX_FMT_RGB565X, | |
63 | .depth = 16, | |
64 | .twformat = ColorFormatRGB16 | ColorFormatBSWAP, | |
65 | }, { | |
66 | .name = "24 bpp RGB, le", | |
67 | .fourcc = V4L2_PIX_FMT_BGR24, | |
68 | .depth = 24, | |
69 | .twformat = ColorFormatRGB24, | |
70 | }, { | |
71 | .name = "24 bpp RGB, be", | |
72 | .fourcc = V4L2_PIX_FMT_RGB24, | |
73 | .depth = 24, | |
74 | .twformat = ColorFormatRGB24 | ColorFormatBSWAP, | |
75 | }, { | |
76 | .name = "32 bpp RGB, le", | |
77 | .fourcc = V4L2_PIX_FMT_BGR32, | |
78 | .depth = 32, | |
79 | .twformat = ColorFormatRGB32, | |
80 | }, { | |
81 | .name = "32 bpp RGB, be", | |
82 | .fourcc = V4L2_PIX_FMT_RGB32, | |
83 | .depth = 32, | |
84 | .twformat = ColorFormatRGB32 | ColorFormatBSWAP | | |
85 | ColorFormatWSWAP, | |
86 | }, { | |
87 | .name = "4:2:2 packed, YUYV", | |
88 | .fourcc = V4L2_PIX_FMT_YUYV, | |
89 | .depth = 16, | |
90 | .twformat = ColorFormatYUY2, | |
91 | }, { | |
92 | .name = "4:2:2 packed, UYVY", | |
93 | .fourcc = V4L2_PIX_FMT_UYVY, | |
94 | .depth = 16, | |
95 | .twformat = ColorFormatYUY2 | ColorFormatBSWAP, | |
96 | } | |
97 | }; | |
98 | #define FORMATS ARRAY_SIZE(formats) | |
99 | ||
100 | #define NORM_625_50 \ | |
101 | .h_delay = 3, \ | |
102 | .h_delay0 = 133, \ | |
103 | .h_start = 0, \ | |
104 | .h_stop = 719, \ | |
105 | .v_delay = 24, \ | |
106 | .vbi_v_start_0 = 7, \ | |
107 | .vbi_v_stop_0 = 22, \ | |
108 | .video_v_start = 24, \ | |
109 | .video_v_stop = 311, \ | |
110 | .vbi_v_start_1 = 319 | |
111 | ||
112 | #define NORM_525_60 \ | |
113 | .h_delay = 8, \ | |
114 | .h_delay0 = 138, \ | |
115 | .h_start = 0, \ | |
116 | .h_stop = 719, \ | |
117 | .v_delay = 22, \ | |
118 | .vbi_v_start_0 = 10, \ | |
119 | .vbi_v_stop_0 = 21, \ | |
120 | .video_v_start = 22, \ | |
121 | .video_v_stop = 262, \ | |
122 | .vbi_v_start_1 = 273 | |
123 | ||
124 | /* | |
125 | * The following table is searched by tw68_s_std, first for a specific | |
126 | * match, then for an entry which contains the desired id. The table | |
127 | * entries should therefore be ordered in ascending order of specificity. | |
128 | */ | |
e15d1c12 | 129 | static const struct tw68_tvnorm tvnorms[] = { |
5740f4e7 | 130 | { |
5740f4e7 HV |
131 | .name = "PAL", /* autodetect */ |
132 | .id = V4L2_STD_PAL, | |
133 | NORM_625_50, | |
134 | ||
135 | .sync_control = 0x18, | |
136 | .luma_control = 0x40, | |
137 | .chroma_ctrl1 = 0x81, | |
138 | .chroma_gain = 0x2a, | |
139 | .chroma_ctrl2 = 0x06, | |
140 | .vgate_misc = 0x1c, | |
141 | .format = VideoFormatPALBDGHI, | |
5740f4e7 HV |
142 | }, { |
143 | .name = "NTSC", | |
144 | .id = V4L2_STD_NTSC, | |
145 | NORM_525_60, | |
146 | ||
147 | .sync_control = 0x59, | |
148 | .luma_control = 0x40, | |
149 | .chroma_ctrl1 = 0x89, | |
150 | .chroma_gain = 0x2a, | |
151 | .chroma_ctrl2 = 0x0e, | |
152 | .vgate_misc = 0x18, | |
153 | .format = VideoFormatNTSC, | |
5740f4e7 HV |
154 | }, { |
155 | .name = "SECAM", | |
156 | .id = V4L2_STD_SECAM, | |
157 | NORM_625_50, | |
158 | ||
159 | .sync_control = 0x18, | |
160 | .luma_control = 0x1b, | |
161 | .chroma_ctrl1 = 0xd1, | |
162 | .chroma_gain = 0x80, | |
163 | .chroma_ctrl2 = 0x00, | |
164 | .vgate_misc = 0x1c, | |
165 | .format = VideoFormatSECAM, | |
5740f4e7 HV |
166 | }, { |
167 | .name = "PAL-M", | |
168 | .id = V4L2_STD_PAL_M, | |
169 | NORM_525_60, | |
170 | ||
171 | .sync_control = 0x59, | |
172 | .luma_control = 0x40, | |
173 | .chroma_ctrl1 = 0xb9, | |
174 | .chroma_gain = 0x2a, | |
175 | .chroma_ctrl2 = 0x0e, | |
176 | .vgate_misc = 0x18, | |
177 | .format = VideoFormatPALM, | |
5740f4e7 HV |
178 | }, { |
179 | .name = "PAL-Nc", | |
180 | .id = V4L2_STD_PAL_Nc, | |
181 | NORM_625_50, | |
182 | ||
183 | .sync_control = 0x18, | |
184 | .luma_control = 0x40, | |
185 | .chroma_ctrl1 = 0xa1, | |
186 | .chroma_gain = 0x2a, | |
187 | .chroma_ctrl2 = 0x06, | |
188 | .vgate_misc = 0x1c, | |
189 | .format = VideoFormatPALNC, | |
5740f4e7 HV |
190 | }, { |
191 | .name = "PAL-60", | |
192 | .id = V4L2_STD_PAL_60, | |
193 | .h_delay = 186, | |
194 | .h_start = 0, | |
195 | .h_stop = 719, | |
196 | .v_delay = 26, | |
197 | .video_v_start = 23, | |
198 | .video_v_stop = 262, | |
199 | .vbi_v_start_0 = 10, | |
200 | .vbi_v_stop_0 = 21, | |
201 | .vbi_v_start_1 = 273, | |
202 | ||
203 | .sync_control = 0x18, | |
204 | .luma_control = 0x40, | |
205 | .chroma_ctrl1 = 0x81, | |
206 | .chroma_gain = 0x2a, | |
207 | .chroma_ctrl2 = 0x06, | |
208 | .vgate_misc = 0x1c, | |
209 | .format = VideoFormatPAL60, | |
5740f4e7 HV |
210 | } |
211 | }; | |
212 | #define TVNORMS ARRAY_SIZE(tvnorms) | |
213 | ||
e15d1c12 | 214 | static const struct tw68_format *format_by_fourcc(unsigned int fourcc) |
5740f4e7 HV |
215 | { |
216 | unsigned int i; | |
217 | ||
218 | for (i = 0; i < FORMATS; i++) | |
219 | if (formats[i].fourcc == fourcc) | |
220 | return formats+i; | |
221 | return NULL; | |
222 | } | |
223 | ||
5740f4e7 HV |
224 | |
225 | /* ------------------------------------------------------------------ */ | |
226 | /* | |
227 | * Note that the cropping rectangles are described in terms of a single | |
228 | * frame, i.e. line positions are only 1/2 the interlaced equivalent | |
229 | */ | |
e15d1c12 | 230 | static void set_tvnorm(struct tw68_dev *dev, const struct tw68_tvnorm *norm) |
5740f4e7 | 231 | { |
5740f4e7 | 232 | if (norm != dev->tvnorm) { |
e15d1c12 HV |
233 | dev->width = 720; |
234 | dev->height = (norm->id & V4L2_STD_525_60) ? 480 : 576; | |
5740f4e7 HV |
235 | dev->tvnorm = norm; |
236 | tw68_set_tvnorm_hw(dev); | |
237 | } | |
238 | } | |
239 | ||
5740f4e7 HV |
240 | /* |
241 | * tw68_set_scale | |
242 | * | |
243 | * Scaling and Cropping for video decoding | |
244 | * | |
245 | * We are working with 3 values for horizontal and vertical - scale, | |
246 | * delay and active. | |
247 | * | |
248 | * HACTIVE represent the actual number of pixels in the "usable" image, | |
249 | * before scaling. HDELAY represents the number of pixels skipped | |
250 | * between the start of the horizontal sync and the start of the image. | |
251 | * HSCALE is calculated using the formula | |
e15d1c12 | 252 | * HSCALE = (HACTIVE / (#pixels desired)) * 256 |
5740f4e7 HV |
253 | * |
254 | * The vertical registers are similar, except based upon the total number | |
255 | * of lines in the image, and the first line of the image (i.e. ignoring | |
256 | * vertical sync and VBI). | |
257 | * | |
258 | * Note that the number of bytes reaching the FIFO (and hence needing | |
259 | * to be processed by the DMAP program) is completely dependent upon | |
260 | * these values, especially HSCALE. | |
261 | * | |
262 | * Parameters: | |
e15d1c12 HV |
263 | * @dev pointer to the device structure, needed for |
264 | * getting current norm (as well as debug print) | |
265 | * @width actual image width (from user buffer) | |
266 | * @height actual image height | |
267 | * @field indicates Top, Bottom or Interlaced | |
5740f4e7 HV |
268 | */ |
269 | static int tw68_set_scale(struct tw68_dev *dev, unsigned int width, | |
270 | unsigned int height, enum v4l2_field field) | |
271 | { | |
e15d1c12 | 272 | const struct tw68_tvnorm *norm = dev->tvnorm; |
5740f4e7 HV |
273 | /* set individually for debugging clarity */ |
274 | int hactive, hdelay, hscale; | |
275 | int vactive, vdelay, vscale; | |
276 | int comb; | |
277 | ||
278 | if (V4L2_FIELD_HAS_BOTH(field)) /* if field is interlaced */ | |
279 | height /= 2; /* we must set for 1-frame */ | |
280 | ||
e15d1c12 HV |
281 | pr_debug("%s: width=%d, height=%d, both=%d\n" |
282 | " tvnorm h_delay=%d, h_start=%d, h_stop=%d, " | |
283 | "v_delay=%d, v_start=%d, v_stop=%d\n" , __func__, | |
5740f4e7 | 284 | width, height, V4L2_FIELD_HAS_BOTH(field), |
e15d1c12 HV |
285 | norm->h_delay, norm->h_start, norm->h_stop, |
286 | norm->v_delay, norm->video_v_start, | |
287 | norm->video_v_stop); | |
5740f4e7 HV |
288 | |
289 | switch (dev->vdecoder) { | |
290 | case TW6800: | |
e15d1c12 | 291 | hdelay = norm->h_delay0; |
5740f4e7 HV |
292 | break; |
293 | default: | |
e15d1c12 | 294 | hdelay = norm->h_delay; |
5740f4e7 HV |
295 | break; |
296 | } | |
e15d1c12 HV |
297 | |
298 | hdelay += norm->h_start; | |
299 | hactive = norm->h_stop - norm->h_start + 1; | |
5740f4e7 HV |
300 | |
301 | hscale = (hactive * 256) / (width); | |
302 | ||
e15d1c12 HV |
303 | vdelay = norm->v_delay; |
304 | vactive = ((norm->id & V4L2_STD_525_60) ? 524 : 624) / 2 - norm->video_v_start; | |
5740f4e7 HV |
305 | vscale = (vactive * 256) / height; |
306 | ||
e15d1c12 | 307 | pr_debug("%s: %dx%d [%s%s,%s]\n", __func__, |
5740f4e7 HV |
308 | width, height, |
309 | V4L2_FIELD_HAS_TOP(field) ? "T" : "", | |
310 | V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "", | |
311 | v4l2_norm_to_name(dev->tvnorm->id)); | |
e15d1c12 | 312 | pr_debug("%s: hactive=%d, hdelay=%d, hscale=%d; " |
5740f4e7 HV |
313 | "vactive=%d, vdelay=%d, vscale=%d\n", __func__, |
314 | hactive, hdelay, hscale, vactive, vdelay, vscale); | |
315 | ||
316 | comb = ((vdelay & 0x300) >> 2) | | |
317 | ((vactive & 0x300) >> 4) | | |
318 | ((hdelay & 0x300) >> 6) | | |
319 | ((hactive & 0x300) >> 8); | |
e15d1c12 | 320 | pr_debug("%s: setting CROP_HI=%02x, VDELAY_LO=%02x, " |
5740f4e7 HV |
321 | "VACTIVE_LO=%02x, HDELAY_LO=%02x, HACTIVE_LO=%02x\n", |
322 | __func__, comb, vdelay, vactive, hdelay, hactive); | |
323 | tw_writeb(TW68_CROP_HI, comb); | |
324 | tw_writeb(TW68_VDELAY_LO, vdelay & 0xff); | |
325 | tw_writeb(TW68_VACTIVE_LO, vactive & 0xff); | |
326 | tw_writeb(TW68_HDELAY_LO, hdelay & 0xff); | |
327 | tw_writeb(TW68_HACTIVE_LO, hactive & 0xff); | |
328 | ||
329 | comb = ((vscale & 0xf00) >> 4) | ((hscale & 0xf00) >> 8); | |
e15d1c12 | 330 | pr_debug("%s: setting SCALE_HI=%02x, VSCALE_LO=%02x, " |
5740f4e7 HV |
331 | "HSCALE_LO=%02x\n", __func__, comb, vscale, hscale); |
332 | tw_writeb(TW68_SCALE_HI, comb); | |
333 | tw_writeb(TW68_VSCALE_LO, vscale); | |
334 | tw_writeb(TW68_HSCALE_LO, hscale); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | /* ------------------------------------------------------------------ */ | |
340 | ||
e15d1c12 HV |
341 | int tw68_video_start_dma(struct tw68_dev *dev, struct tw68_buf *buf) |
342 | { | |
5740f4e7 | 343 | /* Set cropping and scaling */ |
e15d1c12 | 344 | tw68_set_scale(dev, dev->width, dev->height, dev->field); |
5740f4e7 HV |
345 | /* |
346 | * Set start address for RISC program. Note that if the DMAP | |
347 | * processor is currently running, it must be stopped before | |
348 | * a new address can be set. | |
349 | */ | |
350 | tw_clearl(TW68_DMAC, TW68_DMAP_EN); | |
91f96e8b | 351 | tw_writel(TW68_DMAP_SA, buf->dma); |
5740f4e7 HV |
352 | /* Clear any pending interrupts */ |
353 | tw_writel(TW68_INTSTAT, dev->board_virqmask); | |
354 | /* Enable the risc engine and the fifo */ | |
e15d1c12 | 355 | tw_andorl(TW68_DMAC, 0xff, dev->fmt->twformat | |
5740f4e7 HV |
356 | ColorFormatGamma | TW68_DMAP_EN | TW68_FIFO_EN); |
357 | dev->pci_irqmask |= dev->board_virqmask; | |
358 | tw_setl(TW68_INTMASK, dev->pci_irqmask); | |
359 | return 0; | |
360 | } | |
361 | ||
362 | /* ------------------------------------------------------------------ */ | |
5740f4e7 | 363 | |
e15d1c12 HV |
364 | /* calc max # of buffers from size (must not exceed the 4MB virtual |
365 | * address space per DMA channel) */ | |
366 | static int tw68_buffer_count(unsigned int size, unsigned int count) | |
5740f4e7 | 367 | { |
e15d1c12 | 368 | unsigned int maxcount; |
5740f4e7 | 369 | |
947b38bb | 370 | maxcount = (4 * 1024 * 1024) / roundup(size, PAGE_SIZE); |
e15d1c12 HV |
371 | if (count > maxcount) |
372 | count = maxcount; | |
373 | return count; | |
5740f4e7 HV |
374 | } |
375 | ||
e15d1c12 HV |
376 | /* ------------------------------------------------------------- */ |
377 | /* vb2 queue operations */ | |
5740f4e7 | 378 | |
e15d1c12 HV |
379 | static int tw68_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, |
380 | unsigned int *num_buffers, unsigned int *num_planes, | |
381 | unsigned int sizes[], void *alloc_ctxs[]) | |
5740f4e7 | 382 | { |
e15d1c12 HV |
383 | struct tw68_dev *dev = vb2_get_drv_priv(q); |
384 | unsigned tot_bufs = q->num_buffers + *num_buffers; | |
5740f4e7 | 385 | |
e15d1c12 | 386 | sizes[0] = (dev->fmt->depth * dev->width * dev->height) >> 3; |
0c3a14c1 | 387 | alloc_ctxs[0] = dev->alloc_ctx; |
e15d1c12 HV |
388 | /* |
389 | * We allow create_bufs, but only if the sizeimage is the same as the | |
390 | * current sizeimage. The tw68_buffer_count calculation becomes quite | |
391 | * difficult otherwise. | |
392 | */ | |
393 | if (fmt && fmt->fmt.pix.sizeimage < sizes[0]) | |
394 | return -EINVAL; | |
395 | *num_planes = 1; | |
396 | if (tot_bufs < 2) | |
397 | tot_bufs = 2; | |
398 | tot_bufs = tw68_buffer_count(sizes[0], tot_bufs); | |
399 | *num_buffers = tot_bufs - q->num_buffers; | |
5740f4e7 | 400 | |
5740f4e7 | 401 | return 0; |
5740f4e7 HV |
402 | } |
403 | ||
404 | /* | |
e15d1c12 HV |
405 | * The risc program for each buffers works as follows: it starts with a simple |
406 | * 'JUMP to addr + 8', which is effectively a NOP. Then the program to DMA the | |
407 | * buffer follows and at the end we have a JUMP back to the start + 8 (skipping | |
408 | * the initial JUMP). | |
409 | * | |
410 | * This is the program of the first buffer to be queued if the active list is | |
411 | * empty and it just keeps DMAing this buffer without generating any interrupts. | |
412 | * | |
413 | * If a new buffer is added then the initial JUMP in the program generates an | |
414 | * interrupt as well which signals that the previous buffer has been DMAed | |
415 | * successfully and that it can be returned to userspace. | |
416 | * | |
417 | * It also sets the final jump of the previous buffer to the start of the new | |
418 | * buffer, thus chaining the new buffer into the DMA chain. This is a single | |
419 | * atomic u32 write, so there is no race condition. | |
5740f4e7 | 420 | * |
e15d1c12 HV |
421 | * The end-result of all this that you only get an interrupt when a buffer |
422 | * is ready, so the control flow is very easy. | |
5740f4e7 | 423 | */ |
e15d1c12 | 424 | static void tw68_buf_queue(struct vb2_buffer *vb) |
5740f4e7 | 425 | { |
e15d1c12 HV |
426 | struct vb2_queue *vq = vb->vb2_queue; |
427 | struct tw68_dev *dev = vb2_get_drv_priv(vq); | |
428 | struct tw68_buf *buf = container_of(vb, struct tw68_buf, vb); | |
429 | struct tw68_buf *prev; | |
430 | unsigned long flags; | |
431 | ||
432 | spin_lock_irqsave(&dev->slock, flags); | |
5740f4e7 | 433 | |
e15d1c12 HV |
434 | /* append a 'JUMP to start of buffer' to the buffer risc program */ |
435 | buf->jmp[0] = cpu_to_le32(RISC_JUMP); | |
436 | buf->jmp[1] = cpu_to_le32(buf->dma + 8); | |
437 | ||
438 | if (!list_empty(&dev->active)) { | |
439 | prev = list_entry(dev->active.prev, struct tw68_buf, list); | |
440 | buf->cpu[0] |= cpu_to_le32(RISC_INT_BIT); | |
441 | prev->jmp[1] = cpu_to_le32(buf->dma); | |
442 | } | |
443 | list_add_tail(&buf->list, &dev->active); | |
444 | spin_unlock_irqrestore(&dev->slock, flags); | |
5740f4e7 HV |
445 | } |
446 | ||
447 | /* | |
e15d1c12 | 448 | * buffer_prepare |
5740f4e7 | 449 | * |
e15d1c12 HV |
450 | * Set the ancilliary information into the buffer structure. This |
451 | * includes generating the necessary risc program if it hasn't already | |
452 | * been done for the current buffer format. | |
453 | * The structure fh contains the details of the format requested by the | |
454 | * user - type, width, height and #fields. This is compared with the | |
455 | * last format set for the current buffer. If they differ, the risc | |
456 | * code (which controls the filling of the buffer) is (re-)generated. | |
5740f4e7 | 457 | */ |
e15d1c12 | 458 | static int tw68_buf_prepare(struct vb2_buffer *vb) |
5740f4e7 | 459 | { |
e15d1c12 HV |
460 | struct vb2_queue *vq = vb->vb2_queue; |
461 | struct tw68_dev *dev = vb2_get_drv_priv(vq); | |
5740f4e7 | 462 | struct tw68_buf *buf = container_of(vb, struct tw68_buf, vb); |
e15d1c12 HV |
463 | struct sg_table *dma = vb2_dma_sg_plane_desc(vb, 0); |
464 | unsigned size, bpl; | |
5740f4e7 | 465 | |
e15d1c12 HV |
466 | size = (dev->width * dev->height * dev->fmt->depth) >> 3; |
467 | if (vb2_plane_size(vb, 0) < size) | |
468 | return -EINVAL; | |
469 | vb2_set_plane_payload(vb, 0, size); | |
5740f4e7 | 470 | |
e15d1c12 HV |
471 | bpl = (dev->width * dev->fmt->depth) >> 3; |
472 | switch (dev->field) { | |
473 | case V4L2_FIELD_TOP: | |
474 | tw68_risc_buffer(dev->pci, buf, dma->sgl, | |
475 | 0, UNSET, bpl, 0, dev->height); | |
5740f4e7 | 476 | break; |
e15d1c12 HV |
477 | case V4L2_FIELD_BOTTOM: |
478 | tw68_risc_buffer(dev->pci, buf, dma->sgl, | |
479 | UNSET, 0, bpl, 0, dev->height); | |
5740f4e7 | 480 | break; |
e15d1c12 HV |
481 | case V4L2_FIELD_SEQ_TB: |
482 | tw68_risc_buffer(dev->pci, buf, dma->sgl, | |
483 | 0, bpl * (dev->height >> 1), | |
484 | bpl, 0, dev->height >> 1); | |
5740f4e7 | 485 | break; |
e15d1c12 HV |
486 | case V4L2_FIELD_SEQ_BT: |
487 | tw68_risc_buffer(dev->pci, buf, dma->sgl, | |
488 | bpl * (dev->height >> 1), 0, | |
489 | bpl, 0, dev->height >> 1); | |
5740f4e7 | 490 | break; |
e15d1c12 | 491 | case V4L2_FIELD_INTERLACED: |
5740f4e7 | 492 | default: |
e15d1c12 HV |
493 | tw68_risc_buffer(dev->pci, buf, dma->sgl, |
494 | 0, bpl, bpl, bpl, dev->height >> 1); | |
495 | break; | |
5740f4e7 HV |
496 | } |
497 | return 0; | |
498 | } | |
499 | ||
e15d1c12 HV |
500 | static void tw68_buf_finish(struct vb2_buffer *vb) |
501 | { | |
502 | struct vb2_queue *vq = vb->vb2_queue; | |
503 | struct tw68_dev *dev = vb2_get_drv_priv(vq); | |
e15d1c12 HV |
504 | struct tw68_buf *buf = container_of(vb, struct tw68_buf, vb); |
505 | ||
e15d1c12 HV |
506 | pci_free_consistent(dev->pci, buf->size, buf->cpu, buf->dma); |
507 | } | |
508 | ||
509 | static int tw68_start_streaming(struct vb2_queue *q, unsigned int count) | |
510 | { | |
511 | struct tw68_dev *dev = vb2_get_drv_priv(q); | |
512 | struct tw68_buf *buf = | |
513 | container_of(dev->active.next, struct tw68_buf, list); | |
514 | ||
515 | dev->seqnr = 0; | |
516 | tw68_video_start_dma(dev, buf); | |
517 | return 0; | |
518 | } | |
519 | ||
520 | static void tw68_stop_streaming(struct vb2_queue *q) | |
5740f4e7 | 521 | { |
e15d1c12 HV |
522 | struct tw68_dev *dev = vb2_get_drv_priv(q); |
523 | ||
524 | /* Stop risc & fifo */ | |
525 | tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN); | |
526 | while (!list_empty(&dev->active)) { | |
527 | struct tw68_buf *buf = | |
528 | container_of(dev->active.next, struct tw68_buf, list); | |
5740f4e7 | 529 | |
e15d1c12 HV |
530 | list_del(&buf->list); |
531 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); | |
532 | } | |
5740f4e7 HV |
533 | } |
534 | ||
e15d1c12 HV |
535 | static struct vb2_ops tw68_video_qops = { |
536 | .queue_setup = tw68_queue_setup, | |
537 | .buf_queue = tw68_buf_queue, | |
538 | .buf_prepare = tw68_buf_prepare, | |
539 | .buf_finish = tw68_buf_finish, | |
540 | .start_streaming = tw68_start_streaming, | |
541 | .stop_streaming = tw68_stop_streaming, | |
542 | .wait_prepare = vb2_ops_wait_prepare, | |
543 | .wait_finish = vb2_ops_wait_finish, | |
544 | }; | |
545 | ||
546 | /* ------------------------------------------------------------------ */ | |
547 | ||
548 | static int tw68_s_ctrl(struct v4l2_ctrl *ctrl) | |
5740f4e7 | 549 | { |
e15d1c12 HV |
550 | struct tw68_dev *dev = |
551 | container_of(ctrl->handler, struct tw68_dev, hdl); | |
5740f4e7 | 552 | |
e15d1c12 | 553 | switch (ctrl->id) { |
5740f4e7 | 554 | case V4L2_CID_BRIGHTNESS: |
e15d1c12 | 555 | tw_writeb(TW68_BRIGHT, ctrl->val); |
5740f4e7 HV |
556 | break; |
557 | case V4L2_CID_HUE: | |
e15d1c12 | 558 | tw_writeb(TW68_HUE, ctrl->val); |
5740f4e7 HV |
559 | break; |
560 | case V4L2_CID_CONTRAST: | |
e15d1c12 | 561 | tw_writeb(TW68_CONTRAST, ctrl->val); |
5740f4e7 HV |
562 | break; |
563 | case V4L2_CID_SATURATION: | |
e15d1c12 HV |
564 | tw_writeb(TW68_SAT_U, ctrl->val); |
565 | tw_writeb(TW68_SAT_V, ctrl->val); | |
5740f4e7 HV |
566 | break; |
567 | case V4L2_CID_COLOR_KILLER: | |
e15d1c12 | 568 | if (ctrl->val) |
5740f4e7 HV |
569 | tw_andorb(TW68_MISC2, 0xe0, 0xe0); |
570 | else | |
571 | tw_andorb(TW68_MISC2, 0xe0, 0x00); | |
572 | break; | |
573 | case V4L2_CID_CHROMA_AGC: | |
e15d1c12 | 574 | if (ctrl->val) |
5740f4e7 HV |
575 | tw_andorb(TW68_LOOP, 0x30, 0x20); |
576 | else | |
577 | tw_andorb(TW68_LOOP, 0x30, 0x00); | |
578 | break; | |
5740f4e7 | 579 | } |
e15d1c12 | 580 | return 0; |
5740f4e7 HV |
581 | } |
582 | ||
e15d1c12 | 583 | /* ------------------------------------------------------------------ */ |
5740f4e7 | 584 | |
e15d1c12 HV |
585 | /* |
586 | * Note that this routine returns what is stored in the fh structure, and | |
587 | * does not interrogate any of the device registers. | |
588 | */ | |
589 | static int tw68_g_fmt_vid_cap(struct file *file, void *priv, | |
590 | struct v4l2_format *f) | |
591 | { | |
592 | struct tw68_dev *dev = video_drvdata(file); | |
5740f4e7 | 593 | |
e15d1c12 HV |
594 | f->fmt.pix.width = dev->width; |
595 | f->fmt.pix.height = dev->height; | |
596 | f->fmt.pix.field = dev->field; | |
597 | f->fmt.pix.pixelformat = dev->fmt->fourcc; | |
5740f4e7 | 598 | f->fmt.pix.bytesperline = |
e15d1c12 | 599 | (f->fmt.pix.width * (dev->fmt->depth)) >> 3; |
5740f4e7 HV |
600 | f->fmt.pix.sizeimage = |
601 | f->fmt.pix.height * f->fmt.pix.bytesperline; | |
602 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
e15d1c12 | 603 | f->fmt.pix.priv = 0; |
5740f4e7 HV |
604 | return 0; |
605 | } | |
606 | ||
607 | static int tw68_try_fmt_vid_cap(struct file *file, void *priv, | |
608 | struct v4l2_format *f) | |
609 | { | |
e15d1c12 HV |
610 | struct tw68_dev *dev = video_drvdata(file); |
611 | const struct tw68_format *fmt; | |
5740f4e7 | 612 | enum v4l2_field field; |
e15d1c12 | 613 | unsigned int maxh; |
5740f4e7 | 614 | |
5740f4e7 HV |
615 | fmt = format_by_fourcc(f->fmt.pix.pixelformat); |
616 | if (NULL == fmt) | |
617 | return -EINVAL; | |
618 | ||
619 | field = f->fmt.pix.field; | |
e15d1c12 | 620 | maxh = (dev->tvnorm->id & V4L2_STD_525_60) ? 480 : 576; |
5740f4e7 | 621 | |
5740f4e7 HV |
622 | switch (field) { |
623 | case V4L2_FIELD_TOP: | |
624 | case V4L2_FIELD_BOTTOM: | |
625 | break; | |
626 | case V4L2_FIELD_INTERLACED: | |
e15d1c12 HV |
627 | case V4L2_FIELD_SEQ_BT: |
628 | case V4L2_FIELD_SEQ_TB: | |
5740f4e7 HV |
629 | maxh = maxh * 2; |
630 | break; | |
631 | default: | |
e15d1c12 HV |
632 | field = (f->fmt.pix.height > maxh / 2) |
633 | ? V4L2_FIELD_INTERLACED | |
634 | : V4L2_FIELD_BOTTOM; | |
635 | break; | |
5740f4e7 HV |
636 | } |
637 | ||
638 | f->fmt.pix.field = field; | |
639 | if (f->fmt.pix.width < 48) | |
640 | f->fmt.pix.width = 48; | |
641 | if (f->fmt.pix.height < 32) | |
642 | f->fmt.pix.height = 32; | |
e15d1c12 HV |
643 | if (f->fmt.pix.width > 720) |
644 | f->fmt.pix.width = 720; | |
5740f4e7 HV |
645 | if (f->fmt.pix.height > maxh) |
646 | f->fmt.pix.height = maxh; | |
647 | f->fmt.pix.width &= ~0x03; | |
648 | f->fmt.pix.bytesperline = | |
649 | (f->fmt.pix.width * (fmt->depth)) >> 3; | |
650 | f->fmt.pix.sizeimage = | |
651 | f->fmt.pix.height * f->fmt.pix.bytesperline; | |
e15d1c12 | 652 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; |
5740f4e7 HV |
653 | return 0; |
654 | } | |
655 | ||
656 | /* | |
657 | * Note that tw68_s_fmt_vid_cap sets the information into the fh structure, | |
658 | * and it will be used for all future new buffers. However, there could be | |
659 | * some number of buffers on the "active" chain which will be filled before | |
660 | * the change takes place. | |
661 | */ | |
662 | static int tw68_s_fmt_vid_cap(struct file *file, void *priv, | |
663 | struct v4l2_format *f) | |
664 | { | |
e15d1c12 | 665 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 HV |
666 | int err; |
667 | ||
5740f4e7 HV |
668 | err = tw68_try_fmt_vid_cap(file, priv, f); |
669 | if (0 != err) | |
670 | return err; | |
671 | ||
e15d1c12 HV |
672 | dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat); |
673 | dev->width = f->fmt.pix.width; | |
674 | dev->height = f->fmt.pix.height; | |
675 | dev->field = f->fmt.pix.field; | |
5740f4e7 HV |
676 | return 0; |
677 | } | |
678 | ||
679 | static int tw68_enum_input(struct file *file, void *priv, | |
680 | struct v4l2_input *i) | |
681 | { | |
e15d1c12 | 682 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 HV |
683 | unsigned int n; |
684 | ||
685 | n = i->index; | |
e15d1c12 | 686 | if (n >= TW68_INPUT_MAX) |
5740f4e7 | 687 | return -EINVAL; |
5740f4e7 | 688 | i->index = n; |
e15d1c12 HV |
689 | i->type = V4L2_INPUT_TYPE_CAMERA; |
690 | snprintf(i->name, sizeof(i->name), "Composite %d", n); | |
691 | ||
5740f4e7 | 692 | /* If the query is for the current input, get live data */ |
e15d1c12 | 693 | if (n == dev->input) { |
5740f4e7 HV |
694 | int v1 = tw_readb(TW68_STATUS1); |
695 | int v2 = tw_readb(TW68_MVSN); | |
696 | ||
697 | if (0 != (v1 & (1 << 7))) | |
698 | i->status |= V4L2_IN_ST_NO_SYNC; | |
699 | if (0 != (v1 & (1 << 6))) | |
700 | i->status |= V4L2_IN_ST_NO_H_LOCK; | |
701 | if (0 != (v1 & (1 << 2))) | |
702 | i->status |= V4L2_IN_ST_NO_SIGNAL; | |
703 | if (0 != (v1 & 1 << 1)) | |
704 | i->status |= V4L2_IN_ST_NO_COLOR; | |
705 | if (0 != (v2 & (1 << 2))) | |
706 | i->status |= V4L2_IN_ST_MACROVISION; | |
707 | } | |
e15d1c12 | 708 | i->std = video_devdata(file)->tvnorms; |
5740f4e7 HV |
709 | return 0; |
710 | } | |
711 | ||
712 | static int tw68_g_input(struct file *file, void *priv, unsigned int *i) | |
713 | { | |
e15d1c12 | 714 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 | 715 | |
e15d1c12 | 716 | *i = dev->input; |
5740f4e7 HV |
717 | return 0; |
718 | } | |
719 | ||
720 | static int tw68_s_input(struct file *file, void *priv, unsigned int i) | |
721 | { | |
e15d1c12 | 722 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 | 723 | |
e15d1c12 | 724 | if (i >= TW68_INPUT_MAX) |
5740f4e7 | 725 | return -EINVAL; |
e15d1c12 HV |
726 | dev->input = i; |
727 | tw_andorb(TW68_INFORM, 0x03 << 2, dev->input << 2); | |
5740f4e7 HV |
728 | return 0; |
729 | } | |
730 | ||
731 | static int tw68_querycap(struct file *file, void *priv, | |
732 | struct v4l2_capability *cap) | |
733 | { | |
e15d1c12 | 734 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 | 735 | |
5740f4e7 | 736 | strcpy(cap->driver, "tw68"); |
e15d1c12 | 737 | strlcpy(cap->card, "Techwell Capture Card", |
5740f4e7 HV |
738 | sizeof(cap->card)); |
739 | sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); | |
e15d1c12 | 740 | cap->device_caps = |
5740f4e7 | 741 | V4L2_CAP_VIDEO_CAPTURE | |
5740f4e7 | 742 | V4L2_CAP_READWRITE | |
e15d1c12 | 743 | V4L2_CAP_STREAMING; |
5740f4e7 | 744 | |
e15d1c12 | 745 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; |
5740f4e7 HV |
746 | return 0; |
747 | } | |
748 | ||
e15d1c12 | 749 | static int tw68_s_std(struct file *file, void *priv, v4l2_std_id id) |
5740f4e7 | 750 | { |
e15d1c12 | 751 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 | 752 | unsigned int i; |
5740f4e7 | 753 | |
e15d1c12 HV |
754 | if (vb2_is_busy(&dev->vidq)) |
755 | return -EBUSY; | |
5740f4e7 HV |
756 | |
757 | /* Look for match on complete norm id (may have mult bits) */ | |
758 | for (i = 0; i < TVNORMS; i++) { | |
e15d1c12 | 759 | if (id == tvnorms[i].id) |
5740f4e7 HV |
760 | break; |
761 | } | |
762 | ||
763 | /* If no exact match, look for norm which contains this one */ | |
e15d1c12 HV |
764 | if (i == TVNORMS) { |
765 | for (i = 0; i < TVNORMS; i++) | |
766 | if (id & tvnorms[i].id) | |
5740f4e7 | 767 | break; |
e15d1c12 | 768 | } |
5740f4e7 HV |
769 | /* If still not matched, give up */ |
770 | if (i == TVNORMS) | |
771 | return -EINVAL; | |
772 | ||
5740f4e7 | 773 | set_tvnorm(dev, &tvnorms[i]); /* do the actual setting */ |
5740f4e7 HV |
774 | return 0; |
775 | } | |
776 | ||
5740f4e7 HV |
777 | static int tw68_g_std(struct file *file, void *priv, v4l2_std_id *id) |
778 | { | |
e15d1c12 | 779 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 | 780 | |
5740f4e7 HV |
781 | *id = dev->tvnorm->id; |
782 | return 0; | |
783 | } | |
784 | ||
5740f4e7 HV |
785 | static int tw68_enum_fmt_vid_cap(struct file *file, void *priv, |
786 | struct v4l2_fmtdesc *f) | |
787 | { | |
5740f4e7 HV |
788 | if (f->index >= FORMATS) |
789 | return -EINVAL; | |
790 | ||
791 | strlcpy(f->description, formats[f->index].name, | |
792 | sizeof(f->description)); | |
793 | ||
794 | f->pixelformat = formats[f->index].fourcc; | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
5740f4e7 HV |
799 | /* |
800 | * Used strictly for internal development and debugging, this routine | |
801 | * prints out the current register contents for the tw68xx device. | |
802 | */ | |
803 | static void tw68_dump_regs(struct tw68_dev *dev) | |
804 | { | |
805 | unsigned char line[80]; | |
806 | int i, j, k; | |
807 | unsigned char *cptr; | |
808 | ||
e15d1c12 | 809 | pr_info("Full dump of TW68 registers:\n"); |
5740f4e7 HV |
810 | /* First we do the PCI regs, 8 4-byte regs per line */ |
811 | for (i = 0; i < 0x100; i += 32) { | |
812 | cptr = line; | |
813 | cptr += sprintf(cptr, "%03x ", i); | |
814 | /* j steps through the next 4 words */ | |
815 | for (j = i; j < i + 16; j += 4) | |
816 | cptr += sprintf(cptr, "%08x ", tw_readl(j)); | |
817 | *cptr++ = ' '; | |
818 | for (; j < i + 32; j += 4) | |
819 | cptr += sprintf(cptr, "%08x ", tw_readl(j)); | |
820 | *cptr++ = '\n'; | |
821 | *cptr = 0; | |
e15d1c12 | 822 | pr_info("%s", line); |
5740f4e7 HV |
823 | } |
824 | /* Next the control regs, which are single-byte, address mod 4 */ | |
825 | while (i < 0x400) { | |
826 | cptr = line; | |
827 | cptr += sprintf(cptr, "%03x ", i); | |
828 | /* Print out 4 groups of 4 bytes */ | |
829 | for (j = 0; j < 4; j++) { | |
830 | for (k = 0; k < 4; k++) { | |
831 | cptr += sprintf(cptr, "%02x ", | |
832 | tw_readb(i)); | |
833 | i += 4; | |
834 | } | |
835 | *cptr++ = ' '; | |
836 | } | |
837 | *cptr++ = '\n'; | |
838 | *cptr = 0; | |
e15d1c12 | 839 | pr_info("%s", line); |
5740f4e7 HV |
840 | } |
841 | } | |
842 | ||
843 | static int vidioc_log_status(struct file *file, void *priv) | |
844 | { | |
e15d1c12 | 845 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 HV |
846 | |
847 | tw68_dump_regs(dev); | |
e15d1c12 | 848 | return v4l2_ctrl_log_status(file, priv); |
5740f4e7 HV |
849 | } |
850 | ||
e15d1c12 | 851 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
5740f4e7 HV |
852 | static int vidioc_g_register(struct file *file, void *priv, |
853 | struct v4l2_dbg_register *reg) | |
854 | { | |
e15d1c12 | 855 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 | 856 | |
5740f4e7 HV |
857 | if (reg->size == 1) |
858 | reg->val = tw_readb(reg->reg); | |
859 | else | |
860 | reg->val = tw_readl(reg->reg); | |
861 | return 0; | |
862 | } | |
863 | ||
864 | static int vidioc_s_register(struct file *file, void *priv, | |
e15d1c12 | 865 | const struct v4l2_dbg_register *reg) |
5740f4e7 | 866 | { |
e15d1c12 | 867 | struct tw68_dev *dev = video_drvdata(file); |
5740f4e7 | 868 | |
5740f4e7 HV |
869 | if (reg->size == 1) |
870 | tw_writeb(reg->reg, reg->val); | |
871 | else | |
872 | tw_writel(reg->reg & 0xffff, reg->val); | |
873 | return 0; | |
874 | } | |
875 | #endif | |
876 | ||
e15d1c12 HV |
877 | static const struct v4l2_ctrl_ops tw68_ctrl_ops = { |
878 | .s_ctrl = tw68_s_ctrl, | |
879 | }; | |
880 | ||
5740f4e7 HV |
881 | static const struct v4l2_file_operations video_fops = { |
882 | .owner = THIS_MODULE, | |
e15d1c12 HV |
883 | .open = v4l2_fh_open, |
884 | .release = vb2_fop_release, | |
885 | .read = vb2_fop_read, | |
886 | .poll = vb2_fop_poll, | |
887 | .mmap = vb2_fop_mmap, | |
888 | .unlocked_ioctl = video_ioctl2, | |
5740f4e7 HV |
889 | }; |
890 | ||
891 | static const struct v4l2_ioctl_ops video_ioctl_ops = { | |
892 | .vidioc_querycap = tw68_querycap, | |
893 | .vidioc_enum_fmt_vid_cap = tw68_enum_fmt_vid_cap, | |
e15d1c12 HV |
894 | .vidioc_reqbufs = vb2_ioctl_reqbufs, |
895 | .vidioc_create_bufs = vb2_ioctl_create_bufs, | |
896 | .vidioc_querybuf = vb2_ioctl_querybuf, | |
897 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
898 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
5740f4e7 HV |
899 | .vidioc_s_std = tw68_s_std, |
900 | .vidioc_g_std = tw68_g_std, | |
901 | .vidioc_enum_input = tw68_enum_input, | |
902 | .vidioc_g_input = tw68_g_input, | |
903 | .vidioc_s_input = tw68_s_input, | |
e15d1c12 HV |
904 | .vidioc_streamon = vb2_ioctl_streamon, |
905 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
5740f4e7 HV |
906 | .vidioc_g_fmt_vid_cap = tw68_g_fmt_vid_cap, |
907 | .vidioc_try_fmt_vid_cap = tw68_try_fmt_vid_cap, | |
908 | .vidioc_s_fmt_vid_cap = tw68_s_fmt_vid_cap, | |
5740f4e7 | 909 | .vidioc_log_status = vidioc_log_status, |
e15d1c12 HV |
910 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
911 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
912 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
5740f4e7 HV |
913 | .vidioc_g_register = vidioc_g_register, |
914 | .vidioc_s_register = vidioc_s_register, | |
915 | #endif | |
916 | }; | |
917 | ||
e15d1c12 | 918 | static struct video_device tw68_video_template = { |
5740f4e7 HV |
919 | .name = "tw68_video", |
920 | .fops = &video_fops, | |
921 | .ioctl_ops = &video_ioctl_ops, | |
e15d1c12 | 922 | .release = video_device_release_empty, |
5740f4e7 | 923 | .tvnorms = TW68_NORMS, |
5740f4e7 HV |
924 | }; |
925 | ||
e15d1c12 HV |
926 | /* ------------------------------------------------------------------ */ |
927 | /* exported stuff */ | |
5740f4e7 HV |
928 | void tw68_set_tvnorm_hw(struct tw68_dev *dev) |
929 | { | |
930 | tw_andorb(TW68_SDT, 0x07, dev->tvnorm->format); | |
5740f4e7 HV |
931 | } |
932 | ||
933 | int tw68_video_init1(struct tw68_dev *dev) | |
934 | { | |
e15d1c12 HV |
935 | struct v4l2_ctrl_handler *hdl = &dev->hdl; |
936 | ||
937 | v4l2_ctrl_handler_init(hdl, 6); | |
938 | v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, | |
939 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 20); | |
940 | v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, | |
941 | V4L2_CID_CONTRAST, 0, 255, 1, 100); | |
942 | v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, | |
943 | V4L2_CID_SATURATION, 0, 255, 1, 128); | |
944 | /* NTSC only */ | |
945 | v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, | |
946 | V4L2_CID_HUE, -128, 127, 1, 0); | |
947 | v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, | |
948 | V4L2_CID_COLOR_KILLER, 0, 1, 1, 0); | |
949 | v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops, | |
950 | V4L2_CID_CHROMA_AGC, 0, 1, 1, 1); | |
951 | if (hdl->error) { | |
952 | v4l2_ctrl_handler_free(hdl); | |
953 | return hdl->error; | |
954 | } | |
955 | dev->v4l2_dev.ctrl_handler = hdl; | |
956 | v4l2_ctrl_handler_setup(hdl); | |
5740f4e7 HV |
957 | return 0; |
958 | } | |
959 | ||
e15d1c12 | 960 | int tw68_video_init2(struct tw68_dev *dev, int video_nr) |
5740f4e7 | 961 | { |
e15d1c12 HV |
962 | int ret; |
963 | ||
5740f4e7 | 964 | set_tvnorm(dev, &tvnorms[0]); |
5740f4e7 | 965 | |
e15d1c12 HV |
966 | dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24); |
967 | dev->width = 720; | |
968 | dev->height = 576; | |
969 | dev->field = V4L2_FIELD_INTERLACED; | |
970 | ||
971 | INIT_LIST_HEAD(&dev->active); | |
972 | dev->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
973 | dev->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
974 | dev->vidq.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ | VB2_DMABUF; | |
975 | dev->vidq.ops = &tw68_video_qops; | |
976 | dev->vidq.mem_ops = &vb2_dma_sg_memops; | |
977 | dev->vidq.drv_priv = dev; | |
978 | dev->vidq.gfp_flags = __GFP_DMA32; | |
979 | dev->vidq.buf_struct_size = sizeof(struct tw68_buf); | |
980 | dev->vidq.lock = &dev->lock; | |
981 | dev->vidq.min_buffers_needed = 2; | |
982 | ret = vb2_queue_init(&dev->vidq); | |
983 | if (ret) | |
984 | return ret; | |
985 | dev->vdev = tw68_video_template; | |
986 | dev->vdev.v4l2_dev = &dev->v4l2_dev; | |
987 | dev->vdev.lock = &dev->lock; | |
988 | dev->vdev.queue = &dev->vidq; | |
989 | video_set_drvdata(&dev->vdev, dev); | |
990 | return video_register_device(&dev->vdev, VFL_TYPE_GRABBER, video_nr); | |
5740f4e7 HV |
991 | } |
992 | ||
993 | /* | |
994 | * tw68_irq_video_done | |
995 | */ | |
996 | void tw68_irq_video_done(struct tw68_dev *dev, unsigned long status) | |
997 | { | |
998 | __u32 reg; | |
999 | ||
1000 | /* reset interrupts handled by this routine */ | |
1001 | tw_writel(TW68_INTSTAT, status); | |
1002 | /* | |
1003 | * Check most likely first | |
1004 | * | |
1005 | * DMAPI shows we have reached the end of the risc code | |
1006 | * for the current buffer. | |
1007 | */ | |
1008 | if (status & TW68_DMAPI) { | |
e15d1c12 HV |
1009 | struct tw68_buf *buf; |
1010 | ||
5740f4e7 | 1011 | spin_lock(&dev->slock); |
e15d1c12 HV |
1012 | buf = list_entry(dev->active.next, struct tw68_buf, list); |
1013 | list_del(&buf->list); | |
5740f4e7 | 1014 | spin_unlock(&dev->slock); |
e15d1c12 HV |
1015 | v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); |
1016 | buf->vb.v4l2_buf.field = dev->field; | |
1017 | buf->vb.v4l2_buf.sequence = dev->seqnr++; | |
1018 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); | |
5740f4e7 HV |
1019 | status &= ~(TW68_DMAPI); |
1020 | if (0 == status) | |
1021 | return; | |
1022 | } | |
e15d1c12 HV |
1023 | if (status & (TW68_VLOCK | TW68_HLOCK)) |
1024 | dev_dbg(&dev->pci->dev, "Lost sync\n"); | |
1025 | if (status & TW68_PABORT) | |
1026 | dev_err(&dev->pci->dev, "PABORT interrupt\n"); | |
1027 | if (status & TW68_DMAPERR) | |
1028 | dev_err(&dev->pci->dev, "DMAPERR interrupt\n"); | |
5740f4e7 HV |
1029 | /* |
1030 | * On TW6800, FDMIS is apparently generated if video input is switched | |
1031 | * during operation. Therefore, it is not enabled for that chip. | |
1032 | */ | |
e15d1c12 HV |
1033 | if (status & TW68_FDMIS) |
1034 | dev_dbg(&dev->pci->dev, "FDMIS interrupt\n"); | |
1035 | if (status & TW68_FFOF) { | |
1036 | /* probably a logic error */ | |
5740f4e7 HV |
1037 | reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN; |
1038 | tw_clearl(TW68_DMAC, TW68_FIFO_EN); | |
e15d1c12 | 1039 | dev_dbg(&dev->pci->dev, "FFOF interrupt\n"); |
5740f4e7 HV |
1040 | tw_setl(TW68_DMAC, reg); |
1041 | } | |
1042 | if (status & TW68_FFERR) | |
e15d1c12 | 1043 | dev_dbg(&dev->pci->dev, "FFERR interrupt\n"); |
5740f4e7 | 1044 | } |