[linux-2.6-block.git] / drivers / media / pci / solo6x10 / solo6x10-enc.c

/*
 * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
 *
 * Original author:
 * Ben Collins <bcollins@ubuntu.com>
 *
 * Additional work by:
 * John Brooks <john.brooks@bluecherry.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/font.h>
#include <linux/bitrev.h>
#include <linux/slab.h>

#include "solo6x10.h"

#define VI_PROG_HSIZE			(1280 - 16)
#define VI_PROG_VSIZE			(1024 - 16)

#define IRQ_LEVEL			2

static void solo_capture_config(struct solo_dev *solo_dev)
{
	unsigned long height;
	unsigned long width;
	void *buf;
	int i;

	solo_reg_write(solo_dev, SOLO_CAP_BASE,
		       SOLO_CAP_MAX_PAGE((SOLO_CAP_EXT_SIZE(solo_dev)
					  - SOLO_CAP_PAGE_SIZE) >> 16)
		       | SOLO_CAP_BASE_ADDR(SOLO_CAP_EXT_ADDR(solo_dev) >> 16));

	/* XXX: Undocumented bits at b17 and b24 */
	if (solo_dev->type == SOLO_DEV_6110) {
		/* NOTE: Ref driver has (62 << 24) here as well, but it causes
		 * wacked out frame timing on 4-port 6110. */
		solo_reg_write(solo_dev, SOLO_CAP_BTW,
			       (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
			       SOLO_CAP_MAX_BANDWIDTH(36));
	} else {
		solo_reg_write(solo_dev, SOLO_CAP_BTW,
			       (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
			       SOLO_CAP_MAX_BANDWIDTH(32));
	}

	/* Set scale 1, 9 dimension */
	width = solo_dev->video_hsize;
	height = solo_dev->video_vsize;
	solo_reg_write(solo_dev, SOLO_DIM_SCALE1,
		       SOLO_DIM_H_MB_NUM(width / 16) |
		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));

	/* Set scale 2, 10 dimension */
	width = solo_dev->video_hsize / 2;
	height = solo_dev->video_vsize;
	solo_reg_write(solo_dev, SOLO_DIM_SCALE2,
		       SOLO_DIM_H_MB_NUM(width / 16) |
		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));

	/* Set scale 3, 11 dimension */
	width = solo_dev->video_hsize / 2;
	height = solo_dev->video_vsize / 2;
	solo_reg_write(solo_dev, SOLO_DIM_SCALE3,
		       SOLO_DIM_H_MB_NUM(width / 16) |
		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));

	/* Set scale 4, 12 dimension */
	width = solo_dev->video_hsize / 3;
	height = solo_dev->video_vsize / 3;
	solo_reg_write(solo_dev, SOLO_DIM_SCALE4,
		       SOLO_DIM_H_MB_NUM(width / 16) |
		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));

	/* Set scale 5, 13 dimension */
	width = solo_dev->video_hsize / 4;
	height = solo_dev->video_vsize / 2;
	solo_reg_write(solo_dev, SOLO_DIM_SCALE5,
		       SOLO_DIM_H_MB_NUM(width / 16) |
		       SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));

	/* Progressive */
	width = VI_PROG_HSIZE;
	height = VI_PROG_VSIZE;
	solo_reg_write(solo_dev, SOLO_DIM_PROG,
		       SOLO_DIM_H_MB_NUM(width / 16) |
		       SOLO_DIM_V_MB_NUM_FRAME(height / 16) |
		       SOLO_DIM_V_MB_NUM_FIELD(height / 16));

	/* Clear OSD */
	solo_reg_write(solo_dev, SOLO_VE_OSD_CH, 0);
	solo_reg_write(solo_dev, SOLO_VE_OSD_BASE, SOLO_EOSD_EXT_ADDR >> 16);
	solo_reg_write(solo_dev, SOLO_VE_OSD_CLR,
		       0xF0 << 16 | 0x80 << 8 | 0x80);

	if (solo_dev->type == SOLO_DEV_6010)
		solo_reg_write(solo_dev, SOLO_VE_OSD_OPT,
			       SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
	else
		solo_reg_write(solo_dev, SOLO_VE_OSD_OPT, SOLO_VE_OSD_V_DOUBLE
			       | SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);

	/* Clear OSG buffer */
	buf = kzalloc(SOLO_EOSD_EXT_SIZE(solo_dev), GFP_KERNEL);
	if (!buf)
		return;

	for (i = 0; i < solo_dev->nr_chans; i++) {
		solo_p2m_dma(solo_dev, 1, buf,
			     SOLO_EOSD_EXT_ADDR +
			     (SOLO_EOSD_EXT_SIZE(solo_dev) * i),
			     SOLO_EOSD_EXT_SIZE(solo_dev), 0, 0);
	}
	kfree(buf);
}

#define SOLO_OSD_WRITE_SIZE (16 * OSD_TEXT_MAX)

/* Should be called with enable_lock held */
int solo_osd_print(struct solo_enc_dev *solo_enc)
{
	struct solo_dev *solo_dev = solo_enc->solo_dev;
	u8 *str = solo_enc->osd_text;
	u8 *buf = solo_enc->osd_buf;
	u32 reg;
	const struct font_desc *vga = find_font("VGA8x16");
	const u8 *vga_data;
	int i, j;

	if (WARN_ON_ONCE(!vga))
		return -ENODEV;

	reg = solo_reg_read(solo_dev, SOLO_VE_OSD_CH);
	if (!*str) {
		/* Disable OSD on this channel */
		reg &= ~(1 << solo_enc->ch);
		goto out;
	}

	memset(buf, 0, SOLO_OSD_WRITE_SIZE);
	vga_data = (const u8 *)vga->data;

	for (i = 0; *str; i++, str++) {
		for (j = 0; j < 16; j++) {
			buf[(j << 1) | (i & 1) | ((i & ~1) << 4)] =
			    bitrev8(vga_data[(*str << 4) | j]);
		}
	}

	solo_p2m_dma(solo_dev, 1, buf,
		     SOLO_EOSD_EXT_ADDR_CHAN(solo_dev, solo_enc->ch),
		     SOLO_OSD_WRITE_SIZE, 0, 0);

	/* Enable OSD on this channel */
	reg |= (1 << solo_enc->ch);

out:
	solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg);
	return 0;
}

/*
 * Set channel Quality Profile (0-3).
 */
void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
		    unsigned int qp)
{
	unsigned long flags;
	unsigned int idx, reg;

	if ((ch > 31) || (qp > 3))
		return;

	if (solo_dev->type == SOLO_DEV_6010)
		return;

	if (ch < 16) {
		idx = 0;
		reg = SOLO_VE_JPEG_QP_CH_L;
	} else {
		ch -= 16;
		idx = 1;
		reg = SOLO_VE_JPEG_QP_CH_H;
	}
	ch *= 2;

	spin_lock_irqsave(&solo_dev->jpeg_qp_lock, flags);

	solo_dev->jpeg_qp[idx] &= ~(3 << ch);
	solo_dev->jpeg_qp[idx] |= (qp & 3) << ch;

	solo_reg_write(solo_dev, reg, solo_dev->jpeg_qp[idx]);

	spin_unlock_irqrestore(&solo_dev->jpeg_qp_lock, flags);
}

int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch)
{
	int idx;

	if (solo_dev->type == SOLO_DEV_6010)
		return 2;

	if (WARN_ON_ONCE(ch > 31))
		return 2;

	if (ch < 16) {
		idx = 0;
	} else {
		ch -= 16;
		idx = 1;
	}
	ch *= 2;

	return (solo_dev->jpeg_qp[idx] >> ch) & 3;
}

#define SOLO_QP_INIT 0xaaaaaaaa

static void solo_jpeg_config(struct solo_dev *solo_dev)
{
	if (solo_dev->type == SOLO_DEV_6010) {
		solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
			       (2 << 24) | (2 << 16) | (2 << 8) | 2);
	} else {
		solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
			       (4 << 24) | (3 << 16) | (2 << 8) | 1);
	}

	spin_lock_init(&solo_dev->jpeg_qp_lock);

	/* Initialize Quality Profile for all channels */
	solo_dev->jpeg_qp[0] = solo_dev->jpeg_qp[1] = SOLO_QP_INIT;
	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_L, SOLO_QP_INIT);
	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_H, SOLO_QP_INIT);

	solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG,
		(SOLO_JPEG_EXT_SIZE(solo_dev) & 0xffff0000) |
		((SOLO_JPEG_EXT_ADDR(solo_dev) >> 16) & 0x0000ffff));
	solo_reg_write(solo_dev, SOLO_VE_JPEG_CTRL, 0xffffffff);
	if (solo_dev->type == SOLO_DEV_6110) {
		solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG1,
			       (0 << 16) | (30 << 8) | 60);
	}
}

static void solo_mp4e_config(struct solo_dev *solo_dev)
{
	int i;
	u32 cfg;

	solo_reg_write(solo_dev, SOLO_VE_CFG0,
		       SOLO_VE_INTR_CTRL(IRQ_LEVEL) |
		       SOLO_VE_BLOCK_SIZE(SOLO_MP4E_EXT_SIZE(solo_dev) >> 16) |
		       SOLO_VE_BLOCK_BASE(SOLO_MP4E_EXT_ADDR(solo_dev) >> 16));


	cfg = SOLO_VE_BYTE_ALIGN(2) | SOLO_VE_INSERT_INDEX
		| SOLO_VE_MOTION_MODE(0);
	if (solo_dev->type != SOLO_DEV_6010) {
		cfg |= SOLO_VE_MPEG_SIZE_H(
			(SOLO_MP4E_EXT_SIZE(solo_dev) >> 24) & 0x0f);
		cfg |= SOLO_VE_JPEG_SIZE_H(
			(SOLO_JPEG_EXT_SIZE(solo_dev) >> 24) & 0x0f);
	}
	solo_reg_write(solo_dev, SOLO_VE_CFG1, cfg);

	solo_reg_write(solo_dev, SOLO_VE_WMRK_POLY, 0);
	solo_reg_write(solo_dev, SOLO_VE_VMRK_INIT_KEY, 0);
	solo_reg_write(solo_dev, SOLO_VE_WMRK_STRL, 0);
	if (solo_dev->type == SOLO_DEV_6110)
		solo_reg_write(solo_dev, SOLO_VE_WMRK_ENABLE, 0);
	solo_reg_write(solo_dev, SOLO_VE_ENCRYP_POLY, 0);
	solo_reg_write(solo_dev, SOLO_VE_ENCRYP_INIT, 0);

	solo_reg_write(solo_dev, SOLO_VE_ATTR,
		       SOLO_VE_LITTLE_ENDIAN |
		       SOLO_COMP_ATTR_FCODE(1) |
		       SOLO_COMP_TIME_INC(0) |
		       SOLO_COMP_TIME_WIDTH(15) |
		       SOLO_DCT_INTERVAL(solo_dev->type == SOLO_DEV_6010 ? 9 : 10));

	for (i = 0; i < solo_dev->nr_chans; i++) {
		solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE(i),
			       (SOLO_EREF_EXT_ADDR(solo_dev) +
			       (i * SOLO_EREF_EXT_SIZE)) >> 16);
		solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE_E(i),
			       (SOLO_EREF_EXT_ADDR(solo_dev) +
			       ((i + 16) * SOLO_EREF_EXT_SIZE)) >> 16);
	}

	if (solo_dev->type == SOLO_DEV_6110) {
		solo_reg_write(solo_dev, SOLO_VE_COMPT_MOT, 0x00040008);
	} else {
		for (i = 0; i < solo_dev->nr_chans; i++)
			solo_reg_write(solo_dev, SOLO_VE_CH_MOT(i), 0x100);
	}
}

int solo_enc_init(struct solo_dev *solo_dev)
{
	int i;

	solo_capture_config(solo_dev);
	solo_mp4e_config(solo_dev);
	solo_jpeg_config(solo_dev);

	for (i = 0; i < solo_dev->nr_chans; i++) {
		solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
		solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
	}

	return 0;
}

void solo_enc_exit(struct solo_dev *solo_dev)
{
	int i;

	for (i = 0; i < solo_dev->nr_chans; i++) {
		solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
		solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
	}
}
Commit	Line	Data
faa4fd2a	1	/*
dcae5dac HV	2	* Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
	3	*
	4	* Original author:
	5	* Ben Collins <bcollins@ubuntu.com>
	6	*
	7	* Additional work by:
	8	* John Brooks <john.brooks@bluecherry.net>
faa4fd2a BC	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
faa4fd2a BC	19	*/
	20
	21	#include <linux/kernel.h>
dcae5dac HV	22	#include <linux/font.h>
dcae5dac HV	23	#include <linux/bitrev.h>
e72be3fc	24	#include <linux/slab.h>
faa4fd2a	25
dcae5dac	26	#include "solo6x10.h"
faa4fd2a BC	27
	28	#define VI_PROG_HSIZE (1280 - 16)
	29	#define VI_PROG_VSIZE (1024 - 16)
	30
dcae5dac HV	31	#define IRQ_LEVEL 2
dcae5dac HV	32
decebabf	33	static void solo_capture_config(struct solo_dev *solo_dev)
faa4fd2a	34	{
faa4fd2a BC	35	unsigned long height;
faa4fd2a BC	36	unsigned long width;
dcae5dac HV	37	void *buf;
dcae5dac HV	38	int i;
faa4fd2a BC	39
faa4fd2a BC	40	solo_reg_write(solo_dev, SOLO_CAP_BASE,
dcae5dac HV	41	SOLO_CAP_MAX_PAGE((SOLO_CAP_EXT_SIZE(solo_dev)
	42	- SOLO_CAP_PAGE_SIZE) >> 16)
	43	\| SOLO_CAP_BASE_ADDR(SOLO_CAP_EXT_ADDR(solo_dev) >> 16));
	44
	45	/* XXX: Undocumented bits at b17 and b24 */
	46	if (solo_dev->type == SOLO_DEV_6110) {
	47	/* NOTE: Ref driver has (62 << 24) here as well, but it causes
	48	* wacked out frame timing on 4-port 6110. */
	49	solo_reg_write(solo_dev, SOLO_CAP_BTW,
	50	(1 << 17) \| SOLO_CAP_PROG_BANDWIDTH(2) \|
	51	SOLO_CAP_MAX_BANDWIDTH(36));
	52	} else {
	53	solo_reg_write(solo_dev, SOLO_CAP_BTW,
	54	(1 << 17) \| SOLO_CAP_PROG_BANDWIDTH(2) \|
	55	SOLO_CAP_MAX_BANDWIDTH(32));
	56	}
faa4fd2a BC	57
	58	/* Set scale 1, 9 dimension */
	59	width = solo_dev->video_hsize;
	60	height = solo_dev->video_vsize;
	61	solo_reg_write(solo_dev, SOLO_DIM_SCALE1,
	62	SOLO_DIM_H_MB_NUM(width / 16) \|
	63	SOLO_DIM_V_MB_NUM_FRAME(height / 8) \|
	64	SOLO_DIM_V_MB_NUM_FIELD(height / 16));
	65
	66	/* Set scale 2, 10 dimension */
	67	width = solo_dev->video_hsize / 2;
	68	height = solo_dev->video_vsize;
	69	solo_reg_write(solo_dev, SOLO_DIM_SCALE2,
	70	SOLO_DIM_H_MB_NUM(width / 16) \|
	71	SOLO_DIM_V_MB_NUM_FRAME(height / 8) \|
	72	SOLO_DIM_V_MB_NUM_FIELD(height / 16));
	73
	74	/* Set scale 3, 11 dimension */
	75	width = solo_dev->video_hsize / 2;
	76	height = solo_dev->video_vsize / 2;
	77	solo_reg_write(solo_dev, SOLO_DIM_SCALE3,
	78	SOLO_DIM_H_MB_NUM(width / 16) \|
	79	SOLO_DIM_V_MB_NUM_FRAME(height / 8) \|
	80	SOLO_DIM_V_MB_NUM_FIELD(height / 16));
	81
	82	/* Set scale 4, 12 dimension */
	83	width = solo_dev->video_hsize / 3;
	84	height = solo_dev->video_vsize / 3;
	85	solo_reg_write(solo_dev, SOLO_DIM_SCALE4,
	86	SOLO_DIM_H_MB_NUM(width / 16) \|
	87	SOLO_DIM_V_MB_NUM_FRAME(height / 8) \|
	88	SOLO_DIM_V_MB_NUM_FIELD(height / 16));
	89
	90	/* Set scale 5, 13 dimension */
	91	width = solo_dev->video_hsize / 4;
	92	height = solo_dev->video_vsize / 2;
	93	solo_reg_write(solo_dev, SOLO_DIM_SCALE5,
	94	SOLO_DIM_H_MB_NUM(width / 16) \|
	95	SOLO_DIM_V_MB_NUM_FRAME(height / 8) \|
	96	SOLO_DIM_V_MB_NUM_FIELD(height / 16));
	97
	98	/* Progressive */
	99	width = VI_PROG_HSIZE;
	100	height = VI_PROG_VSIZE;
	101	solo_reg_write(solo_dev, SOLO_DIM_PROG,
	102	SOLO_DIM_H_MB_NUM(width / 16) \|
	103	SOLO_DIM_V_MB_NUM_FRAME(height / 16) \|
	104	SOLO_DIM_V_MB_NUM_FIELD(height / 16));
	105
	106	/* Clear OSD */
	107	solo_reg_write(solo_dev, SOLO_VE_OSD_CH, 0);
43d1136d	108	solo_reg_write(solo_dev, SOLO_VE_OSD_BASE, SOLO_EOSD_EXT_ADDR >> 16);
faa4fd2a BC	109	solo_reg_write(solo_dev, SOLO_VE_OSD_CLR,
faa4fd2a BC	110	0xF0 << 16 \| 0x80 << 8 \| 0x80);
dcae5dac HV	111
	112	if (solo_dev->type == SOLO_DEV_6010)
	113	solo_reg_write(solo_dev, SOLO_VE_OSD_OPT,
	114	SOLO_VE_OSD_H_SHADOW \| SOLO_VE_OSD_V_SHADOW);
	115	else
	116	solo_reg_write(solo_dev, SOLO_VE_OSD_OPT, SOLO_VE_OSD_V_DOUBLE
	117	\| SOLO_VE_OSD_H_SHADOW \| SOLO_VE_OSD_V_SHADOW);
faa4fd2a BC	118
faa4fd2a BC	119	/* Clear OSG buffer */
dcae5dac	120	buf = kzalloc(SOLO_EOSD_EXT_SIZE(solo_dev), GFP_KERNEL);
faa4fd2a BC	121	if (!buf)
	122	return;
	123
	124	for (i = 0; i < solo_dev->nr_chans; i++) {
dcae5dac HV	125	solo_p2m_dma(solo_dev, 1, buf,
	126	SOLO_EOSD_EXT_ADDR +
	127	(SOLO_EOSD_EXT_SIZE(solo_dev) * i),
	128	SOLO_EOSD_EXT_SIZE(solo_dev), 0, 0);
faa4fd2a BC	129	}
	130	kfree(buf);
	131	}
	132
3a4d339f IL	133	#define SOLO_OSD_WRITE_SIZE (16 * OSD_TEXT_MAX)
3a4d339f IL	134
dcae5dac	135	/* Should be called with enable_lock held */
faa4fd2a BC	136	int solo_osd_print(struct solo_enc_dev *solo_enc)
faa4fd2a BC	137	{
decebabf	138	struct solo_dev *solo_dev = solo_enc->solo_dev;
8a4d9a9c	139	u8 *str = solo_enc->osd_text;
dcae5dac	140	u8 *buf = solo_enc->osd_buf;
3a4d339f	141	u32 reg;
dcae5dac	142	const struct font_desc *vga = find_font("VGA8x16");
8a4d9a9c	143	const u8 *vga_data;
faa4fd2a	144	int i, j;
dcae5dac HV	145
	146	if (WARN_ON_ONCE(!vga))
	147	return -ENODEV;
	148
3a4d339f IL	149	reg = solo_reg_read(solo_dev, SOLO_VE_OSD_CH);
3a4d339f IL	150	if (!*str) {
dcae5dac	151	/* Disable OSD on this channel */
faa4fd2a	152	reg &= ~(1 << solo_enc->ch);
3a4d339f	153	goto out;
faa4fd2a BC	154	}
faa4fd2a BC	155
3a4d339f	156	memset(buf, 0, SOLO_OSD_WRITE_SIZE);
8a4d9a9c	157	vga_data = (const u8 *)vga->data;
faa4fd2a	158
3a4d339f	159	for (i = 0; *str; i++, str++) {
faa4fd2a	160	for (j = 0; j < 16; j++) {
3a4d339f IL	161	buf[(j << 1) \| (i & 1) \| ((i & ~1) << 4)] =
3a4d339f IL	162	bitrev8(vga_data[(*str << 4) \| j]);
faa4fd2a BC	163	}
	164	}
	165
dcae5dac	166	solo_p2m_dma(solo_dev, 1, buf,
3a4d339f IL	167	SOLO_EOSD_EXT_ADDR_CHAN(solo_dev, solo_enc->ch),
3a4d339f IL	168	SOLO_OSD_WRITE_SIZE, 0, 0);
dcae5dac HV	169
dcae5dac HV	170	/* Enable OSD on this channel */
98e2d5a8	171	reg \|= (1 << solo_enc->ch);
faa4fd2a	172
3a4d339f IL	173	out:
3a4d339f IL	174	solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg);
faa4fd2a BC	175	return 0;
	176	}
	177
cba862dc	178	/*
dcae5dac HV	179	* Set channel Quality Profile (0-3).
	180	*/
	181	void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
	182	unsigned int qp)
	183	{
	184	unsigned long flags;
	185	unsigned int idx, reg;
	186
	187	if ((ch > 31) \|\| (qp > 3))
	188	return;
	189
	190	if (solo_dev->type == SOLO_DEV_6010)
	191	return;
	192
	193	if (ch < 16) {
	194	idx = 0;
	195	reg = SOLO_VE_JPEG_QP_CH_L;
	196	} else {
	197	ch -= 16;
	198	idx = 1;
	199	reg = SOLO_VE_JPEG_QP_CH_H;
	200	}
	201	ch *= 2;
	202
	203	spin_lock_irqsave(&solo_dev->jpeg_qp_lock, flags);
	204
	205	solo_dev->jpeg_qp[idx] &= ~(3 << ch);
	206	solo_dev->jpeg_qp[idx] \|= (qp & 3) << ch;
	207
	208	solo_reg_write(solo_dev, reg, solo_dev->jpeg_qp[idx]);
	209
	210	spin_unlock_irqrestore(&solo_dev->jpeg_qp_lock, flags);
	211	}
	212
	213	int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch)
	214	{
	215	int idx;
	216
	217	if (solo_dev->type == SOLO_DEV_6010)
	218	return 2;
	219
	220	if (WARN_ON_ONCE(ch > 31))
	221	return 2;
	222
	223	if (ch < 16) {
	224	idx = 0;
	225	} else {
	226	ch -= 16;
	227	idx = 1;
	228	}
	229	ch *= 2;
	230
	231	return (solo_dev->jpeg_qp[idx] >> ch) & 3;
	232	}
	233
	234	#define SOLO_QP_INIT 0xaaaaaaaa
	235
decebabf	236	static void solo_jpeg_config(struct solo_dev *solo_dev)
faa4fd2a	237	{
dcae5dac HV	238	if (solo_dev->type == SOLO_DEV_6010) {
	239	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
	240	(2 << 24) \| (2 << 16) \| (2 << 8) \| 2);
	241	} else {
	242	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
	243	(4 << 24) \| (3 << 16) \| (2 << 8) \| 1);
	244	}
	245
	246	spin_lock_init(&solo_dev->jpeg_qp_lock);
	247
	248	/* Initialize Quality Profile for all channels */
	249	solo_dev->jpeg_qp[0] = solo_dev->jpeg_qp[1] = SOLO_QP_INIT;
	250	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_L, SOLO_QP_INIT);
	251	solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_H, SOLO_QP_INIT);
	252
faa4fd2a BC	253	solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG,
	254	(SOLO_JPEG_EXT_SIZE(solo_dev) & 0xffff0000) \|
	255	((SOLO_JPEG_EXT_ADDR(solo_dev) >> 16) & 0x0000ffff));
	256	solo_reg_write(solo_dev, SOLO_VE_JPEG_CTRL, 0xffffffff);
dcae5dac HV	257	if (solo_dev->type == SOLO_DEV_6110) {
	258	solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG1,
	259	(0 << 16) \| (30 << 8) \| 60);
	260	}
faa4fd2a BC	261	}
faa4fd2a BC	262
decebabf	263	static void solo_mp4e_config(struct solo_dev *solo_dev)
faa4fd2a BC	264	{
faa4fd2a BC	265	int i;
dcae5dac	266	u32 cfg;
faa4fd2a	267
faa4fd2a	268	solo_reg_write(solo_dev, SOLO_VE_CFG0,
dcae5dac	269	SOLO_VE_INTR_CTRL(IRQ_LEVEL) \|
faa4fd2a BC	270	SOLO_VE_BLOCK_SIZE(SOLO_MP4E_EXT_SIZE(solo_dev) >> 16) \|
	271	SOLO_VE_BLOCK_BASE(SOLO_MP4E_EXT_ADDR(solo_dev) >> 16));
	272
dcae5dac HV	273
	274	cfg = SOLO_VE_BYTE_ALIGN(2) \| SOLO_VE_INSERT_INDEX
	275	\| SOLO_VE_MOTION_MODE(0);
	276	if (solo_dev->type != SOLO_DEV_6010) {
	277	cfg \|= SOLO_VE_MPEG_SIZE_H(
	278	(SOLO_MP4E_EXT_SIZE(solo_dev) >> 24) & 0x0f);
	279	cfg \|= SOLO_VE_JPEG_SIZE_H(
	280	(SOLO_JPEG_EXT_SIZE(solo_dev) >> 24) & 0x0f);
	281	}
	282	solo_reg_write(solo_dev, SOLO_VE_CFG1, cfg);
faa4fd2a BC	283
	284	solo_reg_write(solo_dev, SOLO_VE_WMRK_POLY, 0);
	285	solo_reg_write(solo_dev, SOLO_VE_VMRK_INIT_KEY, 0);
	286	solo_reg_write(solo_dev, SOLO_VE_WMRK_STRL, 0);
dcae5dac HV	287	if (solo_dev->type == SOLO_DEV_6110)
dcae5dac HV	288	solo_reg_write(solo_dev, SOLO_VE_WMRK_ENABLE, 0);
faa4fd2a BC	289	solo_reg_write(solo_dev, SOLO_VE_ENCRYP_POLY, 0);
	290	solo_reg_write(solo_dev, SOLO_VE_ENCRYP_INIT, 0);
	291
dcae5dac HV	292	solo_reg_write(solo_dev, SOLO_VE_ATTR,
	293	SOLO_VE_LITTLE_ENDIAN \|
	294	SOLO_COMP_ATTR_FCODE(1) \|
	295	SOLO_COMP_TIME_INC(0) \|
	296	SOLO_COMP_TIME_WIDTH(15) \|
	297	SOLO_DCT_INTERVAL(solo_dev->type == SOLO_DEV_6010 ? 9 : 10));
faa4fd2a	298
dcae5dac	299	for (i = 0; i < solo_dev->nr_chans; i++) {
faa4fd2a BC	300	solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE(i),
	301	(SOLO_EREF_EXT_ADDR(solo_dev) +
	302	(i * SOLO_EREF_EXT_SIZE)) >> 16);
dcae5dac HV	303	solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE_E(i),
	304	(SOLO_EREF_EXT_ADDR(solo_dev) +
	305	((i + 16) * SOLO_EREF_EXT_SIZE)) >> 16);
	306	}
908113d8	307
dcae5dac HV	308	if (solo_dev->type == SOLO_DEV_6110) {
	309	solo_reg_write(solo_dev, SOLO_VE_COMPT_MOT, 0x00040008);
	310	} else {
	311	for (i = 0; i < solo_dev->nr_chans; i++)
	312	solo_reg_write(solo_dev, SOLO_VE_CH_MOT(i), 0x100);
	313	}
faa4fd2a BC	314	}
faa4fd2a BC	315
decebabf	316	int solo_enc_init(struct solo_dev *solo_dev)
faa4fd2a BC	317	{
	318	int i;
	319
	320	solo_capture_config(solo_dev);
	321	solo_mp4e_config(solo_dev);
	322	solo_jpeg_config(solo_dev);
	323
	324	for (i = 0; i < solo_dev->nr_chans; i++) {
	325	solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
	326	solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
	327	}
	328
faa4fd2a BC	329	return 0;
	330	}
	331
decebabf	332	void solo_enc_exit(struct solo_dev *solo_dev)
faa4fd2a BC	333	{
	334	int i;
	335
faa4fd2a BC	336	for (i = 0; i < solo_dev->nr_chans; i++) {
	337	solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
	338	solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
	339	}
	340	}