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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1a0adaf3 HV |
2 | /* |
3 | interrupt handling | |
4 | Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com> | |
5 | Copyright (C) 2004 Chris Kennedy <c@groovy.org> | |
6 | Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl> | |
7 | ||
1a0adaf3 HV |
8 | */ |
9 | ||
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10 | #ifndef IVTV_IRQ_H |
11 | #define IVTV_IRQ_H | |
12 | ||
33c0fcad HV |
13 | #define IVTV_IRQ_ENC_START_CAP (0x1 << 31) |
14 | #define IVTV_IRQ_ENC_EOS (0x1 << 30) | |
15 | #define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) | |
16 | #define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) | |
17 | #define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) | |
18 | #define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) | |
19 | #define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) | |
20 | #define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) | |
21 | #define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) | |
22 | #define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19) | |
23 | #define IVTV_IRQ_DMA_ERR (0x1 << 18) | |
24 | #define IVTV_IRQ_DMA_WRITE (0x1 << 17) | |
25 | #define IVTV_IRQ_DMA_READ (0x1 << 16) | |
26 | #define IVTV_IRQ_DEC_VSYNC (0x1 << 10) | |
27 | ||
28 | /* IRQ Masks */ | |
29 | #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ | |
30 | IVTV_IRQ_DMA_READ|IVTV_IRQ_ENC_PIO_COMPLETE) | |
31 | ||
32 | #define IVTV_IRQ_MASK_CAPTURE (IVTV_IRQ_ENC_START_CAP | IVTV_IRQ_ENC_EOS) | |
33 | #define IVTV_IRQ_MASK_DECODE (IVTV_IRQ_DEC_DATA_REQ|IVTV_IRQ_DEC_AUD_MODE_CHG) | |
34 | ||
1a0adaf3 | 35 | irqreturn_t ivtv_irq_handler(int irq, void *dev_id); |
1e13f9e3 | 36 | |
7bc46560 | 37 | void ivtv_irq_work_handler(struct kthread_work *work); |
1a0adaf3 | 38 | void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock); |
162e6376 | 39 | void ivtv_unfinished_dma(struct timer_list *t); |
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40 | |
41 | #endif |