Commit | Line | Data |
---|---|---|
1a0adaf3 HV |
1 | /* |
2 | ivtv driver internal defines and structures | |
3 | Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com> | |
4 | Copyright (C) 2004 Chris Kennedy <c@groovy.org> | |
5 | Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef IVTV_DRIVER_H | |
23 | #define IVTV_DRIVER_H | |
24 | ||
bbdba43f MCC |
25 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
26 | ||
1a0adaf3 HV |
27 | /* Internal header for ivtv project: |
28 | * Driver for the cx23415/6 chip. | |
29 | * Author: Kevin Thayer (nufan_wfk at yahoo.com) | |
30 | * License: GPL | |
1a0adaf3 HV |
31 | * |
32 | * ----- | |
33 | * MPG600/MPG160 support by T.Adachi <tadachi@tadachi-net.com> | |
34 | * and Takeru KOMORIYA<komoriya@paken.org> | |
35 | * | |
36 | * AVerMedia M179 GPIO info by Chris Pinkham <cpinkham@bc2va.org> | |
37 | * using information provided by Jiun-Kuei Jung @ AVerMedia. | |
38 | */ | |
39 | ||
174cd4b1 IM |
40 | #include <linux/module.h> |
41 | #include <linux/init.h> | |
1a0adaf3 | 42 | #include <linux/delay.h> |
174cd4b1 | 43 | #include <linux/sched/signal.h> |
1a0adaf3 | 44 | #include <linux/fs.h> |
174cd4b1 IM |
45 | #include <linux/pci.h> |
46 | #include <linux/interrupt.h> | |
47 | #include <linux/spinlock.h> | |
1a0adaf3 HV |
48 | #include <linux/i2c.h> |
49 | #include <linux/i2c-algo-bit.h> | |
50 | #include <linux/list.h> | |
174cd4b1 | 51 | #include <linux/unistd.h> |
1a0adaf3 | 52 | #include <linux/pagemap.h> |
11763609 | 53 | #include <linux/scatterlist.h> |
174cd4b1 IM |
54 | #include <linux/kthread.h> |
55 | #include <linux/mutex.h> | |
5a0e3ad6 | 56 | #include <linux/slab.h> |
7c0f6ba6 | 57 | #include <linux/uaccess.h> |
174cd4b1 | 58 | #include <asm/byteorder.h> |
1a0adaf3 | 59 | |
1a0adaf3 | 60 | #include <media/v4l2-common.h> |
174cd4b1 | 61 | #include <media/v4l2-ioctl.h> |
f7b80e69 | 62 | #include <media/v4l2-ctrls.h> |
67ec09fd | 63 | #include <media/v4l2-device.h> |
09250193 | 64 | #include <media/v4l2-fh.h> |
174cd4b1 IM |
65 | #include <media/tuner.h> |
66 | #include <media/drv-intf/cx2341x.h> | |
67 | #include <media/i2c/ir-kbd-i2c.h> | |
68 | ||
69 | #include <linux/ivtv.h> | |
1a0adaf3 | 70 | |
33c0fcad | 71 | /* Memory layout */ |
1a0adaf3 | 72 | #define IVTV_ENCODER_OFFSET 0x00000000 |
33c0fcad | 73 | #define IVTV_ENCODER_SIZE 0x00800000 /* Total size is 0x01000000, but only first half is used */ |
1a0adaf3 | 74 | #define IVTV_DECODER_OFFSET 0x01000000 |
33c0fcad | 75 | #define IVTV_DECODER_SIZE 0x00800000 /* Total size is 0x01000000, but only first half is used */ |
6e6a8b5a | 76 | #define IVTV_REG_OFFSET 0x02000000 |
1a0adaf3 HV |
77 | #define IVTV_REG_SIZE 0x00010000 |
78 | ||
32db7754 HV |
79 | /* Maximum ivtv driver instances. Some people have a huge number of |
80 | capture cards, so set this to a high value. */ | |
81 | #define IVTV_MAX_CARDS 32 | |
1a0adaf3 | 82 | |
1a0adaf3 HV |
83 | #define IVTV_ENC_STREAM_TYPE_MPG 0 |
84 | #define IVTV_ENC_STREAM_TYPE_YUV 1 | |
85 | #define IVTV_ENC_STREAM_TYPE_VBI 2 | |
86 | #define IVTV_ENC_STREAM_TYPE_PCM 3 | |
87 | #define IVTV_ENC_STREAM_TYPE_RAD 4 | |
88 | #define IVTV_DEC_STREAM_TYPE_MPG 5 | |
89 | #define IVTV_DEC_STREAM_TYPE_VBI 6 | |
90 | #define IVTV_DEC_STREAM_TYPE_VOUT 7 | |
91 | #define IVTV_DEC_STREAM_TYPE_YUV 8 | |
92 | #define IVTV_MAX_STREAMS 9 | |
93 | ||
1a0adaf3 HV |
94 | #define IVTV_DMA_SG_OSD_ENT (2883584/PAGE_SIZE) /* sg entities */ |
95 | ||
1a0adaf3 | 96 | /* DMA Registers */ |
6e6a8b5a MCC |
97 | #define IVTV_REG_DMAXFER (0x0000) |
98 | #define IVTV_REG_DMASTATUS (0x0004) | |
99 | #define IVTV_REG_DECDMAADDR (0x0008) | |
100 | #define IVTV_REG_ENCDMAADDR (0x000c) | |
101 | #define IVTV_REG_DMACONTROL (0x0010) | |
102 | #define IVTV_REG_IRQSTATUS (0x0040) | |
103 | #define IVTV_REG_IRQMASK (0x0048) | |
1a0adaf3 HV |
104 | |
105 | /* Setup Registers */ | |
6e6a8b5a MCC |
106 | #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) |
107 | #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) | |
108 | #define IVTV_REG_DEC_SDRAM_REFRESH (0x08F8) | |
109 | #define IVTV_REG_DEC_SDRAM_PRECHARGE (0x08FC) | |
110 | #define IVTV_REG_VDM (0x2800) | |
111 | #define IVTV_REG_AO (0x2D00) | |
112 | #define IVTV_REG_BYTEFLUSH (0x2D24) | |
113 | #define IVTV_REG_SPU (0x9050) | |
114 | #define IVTV_REG_HW_BLOCKS (0x9054) | |
115 | #define IVTV_REG_VPU (0x9058) | |
116 | #define IVTV_REG_APU (0xA064) | |
1a0adaf3 | 117 | |
4e1af31a AW |
118 | /* Other registers */ |
119 | #define IVTV_REG_DEC_LINE_FIELD (0x28C0) | |
120 | ||
1a0adaf3 | 121 | /* debugging */ |
33c0fcad | 122 | extern int ivtv_debug; |
914610e8 IA |
123 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
124 | extern int ivtv_fw_debug; | |
125 | #endif | |
1a0adaf3 | 126 | |
1aa32c2f HV |
127 | #define IVTV_DBGFLG_WARN (1 << 0) |
128 | #define IVTV_DBGFLG_INFO (1 << 1) | |
129 | #define IVTV_DBGFLG_MB (1 << 2) | |
130 | #define IVTV_DBGFLG_IOCTL (1 << 3) | |
131 | #define IVTV_DBGFLG_FILE (1 << 4) | |
132 | #define IVTV_DBGFLG_DMA (1 << 5) | |
133 | #define IVTV_DBGFLG_IRQ (1 << 6) | |
134 | #define IVTV_DBGFLG_DEC (1 << 7) | |
135 | #define IVTV_DBGFLG_YUV (1 << 8) | |
136 | #define IVTV_DBGFLG_I2C (1 << 9) | |
bd58df6d | 137 | /* Flag to turn on high volume debugging */ |
1aa32c2f | 138 | #define IVTV_DBGFLG_HIGHVOL (1 << 10) |
1a0adaf3 | 139 | |
1a0adaf3 HV |
140 | #define IVTV_DEBUG(x, type, fmt, args...) \ |
141 | do { \ | |
142 | if ((x) & ivtv_debug) \ | |
8ac05ae3 | 143 | v4l2_info(&itv->v4l2_dev, " " type ": " fmt , ##args); \ |
1a0adaf3 | 144 | } while (0) |
1aa32c2f HV |
145 | #define IVTV_DEBUG_WARN(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_WARN, "warn", fmt , ## args) |
146 | #define IVTV_DEBUG_INFO(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_INFO, "info", fmt , ## args) | |
147 | #define IVTV_DEBUG_MB(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_MB, "mb", fmt , ## args) | |
148 | #define IVTV_DEBUG_DMA(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DMA, "dma", fmt , ## args) | |
1a0adaf3 | 149 | #define IVTV_DEBUG_IOCTL(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args) |
1aa32c2f HV |
150 | #define IVTV_DEBUG_FILE(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_FILE, "file", fmt , ## args) |
151 | #define IVTV_DEBUG_I2C(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_I2C, "i2c", fmt , ## args) | |
152 | #define IVTV_DEBUG_IRQ(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IRQ, "irq", fmt , ## args) | |
153 | #define IVTV_DEBUG_DEC(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DEC, "dec", fmt , ## args) | |
154 | #define IVTV_DEBUG_YUV(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_YUV, "yuv", fmt , ## args) | |
1a0adaf3 | 155 | |
bd58df6d HV |
156 | #define IVTV_DEBUG_HIGH_VOL(x, type, fmt, args...) \ |
157 | do { \ | |
6e6a8b5a | 158 | if (((x) & ivtv_debug) && (ivtv_debug & IVTV_DBGFLG_HIGHVOL)) \ |
8ac05ae3 | 159 | v4l2_info(&itv->v4l2_dev, " " type ": " fmt , ##args); \ |
bd58df6d | 160 | } while (0) |
1aa32c2f HV |
161 | #define IVTV_DEBUG_HI_WARN(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_WARN, "warn", fmt , ## args) |
162 | #define IVTV_DEBUG_HI_INFO(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_INFO, "info", fmt , ## args) | |
163 | #define IVTV_DEBUG_HI_MB(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_MB, "mb", fmt , ## args) | |
164 | #define IVTV_DEBUG_HI_DMA(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DMA, "dma", fmt , ## args) | |
bd58df6d | 165 | #define IVTV_DEBUG_HI_IOCTL(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args) |
1aa32c2f HV |
166 | #define IVTV_DEBUG_HI_FILE(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_FILE, "file", fmt , ## args) |
167 | #define IVTV_DEBUG_HI_I2C(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_I2C, "i2c", fmt , ## args) | |
168 | #define IVTV_DEBUG_HI_IRQ(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IRQ, "irq", fmt , ## args) | |
169 | #define IVTV_DEBUG_HI_DEC(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DEC, "dec", fmt , ## args) | |
170 | #define IVTV_DEBUG_HI_YUV(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_YUV, "yuv", fmt , ## args) | |
bd58df6d | 171 | |
1a0adaf3 | 172 | /* Standard kernel messages */ |
8ac05ae3 HV |
173 | #define IVTV_ERR(fmt, args...) v4l2_err(&itv->v4l2_dev, fmt , ## args) |
174 | #define IVTV_WARN(fmt, args...) v4l2_warn(&itv->v4l2_dev, fmt , ## args) | |
175 | #define IVTV_INFO(fmt, args...) v4l2_info(&itv->v4l2_dev, fmt , ## args) | |
1a0adaf3 | 176 | |
1a0adaf3 HV |
177 | /* output modes (cx23415 only) */ |
178 | #define OUT_NONE 0 | |
179 | #define OUT_MPG 1 | |
180 | #define OUT_YUV 2 | |
181 | #define OUT_UDMA_YUV 3 | |
182 | #define OUT_PASSTHROUGH 4 | |
183 | ||
184 | #define IVTV_MAX_PGM_INDEX (400) | |
185 | ||
f412d36a AW |
186 | /* Default I2C SCL period in microseconds */ |
187 | #define IVTV_DEFAULT_I2C_CLOCK_PERIOD 20 | |
188 | ||
1a0adaf3 | 189 | struct ivtv_options { |
a158f355 HV |
190 | int kilobytes[IVTV_MAX_STREAMS]; /* size in kilobytes of each stream */ |
191 | int cardtype; /* force card type on load */ | |
192 | int tuner; /* set tuner on load */ | |
193 | int radio; /* enable/disable radio */ | |
194 | int newi2c; /* new I2C algorithm */ | |
f412d36a | 195 | int i2c_clock_period; /* period of SCL for I2C bus */ |
1a0adaf3 HV |
196 | }; |
197 | ||
1a0adaf3 HV |
198 | /* ivtv-specific mailbox template */ |
199 | struct ivtv_mailbox { | |
200 | u32 flags; | |
201 | u32 cmd; | |
202 | u32 retval; | |
203 | u32 timeout; | |
204 | u32 data[CX2341X_MBOX_MAX_DATA]; | |
205 | }; | |
206 | ||
207 | struct ivtv_api_cache { | |
208 | unsigned long last_jiffies; /* when last command was issued */ | |
209 | u32 data[CX2341X_MBOX_MAX_DATA]; /* last sent api data */ | |
210 | }; | |
211 | ||
212 | struct ivtv_mailbox_data { | |
213 | volatile struct ivtv_mailbox __iomem *mbox; | |
214 | /* Bits 0-2 are for the encoder mailboxes, 0-1 are for the decoder mailboxes. | |
215 | If the bit is set, then the corresponding mailbox is in use by the driver. */ | |
216 | unsigned long busy; | |
217 | u8 max_mbox; | |
218 | }; | |
219 | ||
220 | /* per-buffer bit flags */ | |
f4071b85 | 221 | #define IVTV_F_B_NEED_BUF_SWAP (1 << 0) /* this buffer should be byte swapped */ |
1a0adaf3 HV |
222 | |
223 | /* per-stream, s_flags */ | |
224 | #define IVTV_F_S_DMA_PENDING 0 /* this stream has pending DMA */ | |
225 | #define IVTV_F_S_DMA_HAS_VBI 1 /* the current DMA request also requests VBI data */ | |
6e6a8b5a | 226 | #define IVTV_F_S_NEEDS_DATA 2 /* this decoding stream needs more data */ |
1a0adaf3 | 227 | |
6e6a8b5a | 228 | #define IVTV_F_S_CLAIMED 3 /* this stream is claimed */ |
1a0adaf3 HV |
229 | #define IVTV_F_S_STREAMING 4 /* the fw is decoding/encoding this stream */ |
230 | #define IVTV_F_S_INTERNAL_USE 5 /* this stream is used internally (sliced VBI processing) */ | |
231 | #define IVTV_F_S_PASSTHROUGH 6 /* this stream is in passthrough mode */ | |
232 | #define IVTV_F_S_STREAMOFF 7 /* signal end of stream EOS */ | |
233 | #define IVTV_F_S_APPL_IO 8 /* this stream is used read/written by an application */ | |
234 | ||
dc02d50a HV |
235 | #define IVTV_F_S_PIO_PENDING 9 /* this stream has pending PIO */ |
236 | #define IVTV_F_S_PIO_HAS_VBI 1 /* the current PIO request also requests VBI data */ | |
237 | ||
1a0adaf3 | 238 | /* per-ivtv, i_flags */ |
6e6a8b5a MCC |
239 | #define IVTV_F_I_DMA 0 /* DMA in progress */ |
240 | #define IVTV_F_I_UDMA 1 /* UDMA in progress */ | |
241 | #define IVTV_F_I_UDMA_PENDING 2 /* UDMA pending */ | |
242 | #define IVTV_F_I_SPEED_CHANGE 3 /* a speed change is in progress */ | |
243 | #define IVTV_F_I_EOS 4 /* end of encoder stream reached */ | |
244 | #define IVTV_F_I_RADIO_USER 5 /* the radio tuner is selected */ | |
245 | #define IVTV_F_I_DIG_RST 6 /* reset digitizer */ | |
246 | #define IVTV_F_I_DEC_YUV 7 /* YUV instead of MPG is being decoded */ | |
247 | #define IVTV_F_I_UPDATE_CC 9 /* CC should be updated */ | |
248 | #define IVTV_F_I_UPDATE_WSS 10 /* WSS should be updated */ | |
249 | #define IVTV_F_I_UPDATE_VPS 11 /* VPS should be updated */ | |
250 | #define IVTV_F_I_DECODING_YUV 12 /* this stream is YUV frame decoding */ | |
251 | #define IVTV_F_I_ENC_PAUSED 13 /* the encoder is paused */ | |
252 | #define IVTV_F_I_VALID_DEC_TIMINGS 14 /* last_dec_timing is valid */ | |
253 | #define IVTV_F_I_HAVE_WORK 15 /* used in the interrupt handler: there is work to be done */ | |
dc02d50a HV |
254 | #define IVTV_F_I_WORK_HANDLER_VBI 16 /* there is work to be done for VBI */ |
255 | #define IVTV_F_I_WORK_HANDLER_YUV 17 /* there is work to be done for YUV */ | |
256 | #define IVTV_F_I_WORK_HANDLER_PIO 18 /* there is work to be done for PIO */ | |
257 | #define IVTV_F_I_PIO 19 /* PIO in progress */ | |
6e6a8b5a MCC |
258 | #define IVTV_F_I_DEC_PAUSED 20 /* the decoder is paused */ |
259 | #define IVTV_F_I_INITED 21 /* set after first open */ | |
260 | #define IVTV_F_I_FAILED 22 /* set if first open failed */ | |
4313902e | 261 | #define IVTV_F_I_WORK_HANDLER_PCM 23 /* there is work to be done for PCM */ |
1a0adaf3 HV |
262 | |
263 | /* Event notifications */ | |
1e13f9e3 | 264 | #define IVTV_F_I_EV_DEC_STOPPED 28 /* decoder stopped event */ |
6e6a8b5a MCC |
265 | #define IVTV_F_I_EV_VSYNC 29 /* VSYNC event */ |
266 | #define IVTV_F_I_EV_VSYNC_FIELD 30 /* VSYNC event field (0 = first, 1 = second field) */ | |
267 | #define IVTV_F_I_EV_VSYNC_ENABLED 31 /* VSYNC event enabled */ | |
1a0adaf3 HV |
268 | |
269 | /* Scatter-Gather array element, used in DMA transfers */ | |
37093b1e | 270 | struct ivtv_sg_element { |
b0510f8d AV |
271 | __le32 src; |
272 | __le32 dst; | |
273 | __le32 size; | |
274 | }; | |
275 | ||
276 | struct ivtv_sg_host_element { | |
1a0adaf3 HV |
277 | u32 src; |
278 | u32 dst; | |
279 | u32 size; | |
280 | }; | |
281 | ||
282 | struct ivtv_user_dma { | |
283 | struct mutex lock; | |
284 | int page_count; | |
285 | struct page *map[IVTV_DMA_SG_OSD_ENT]; | |
0989fd2c HV |
286 | /* Needed when dealing with highmem userspace buffers */ |
287 | struct page *bouncemap[IVTV_DMA_SG_OSD_ENT]; | |
1a0adaf3 HV |
288 | |
289 | /* Base Dev SG Array for cx23415/6 */ | |
37093b1e | 290 | struct ivtv_sg_element SGarray[IVTV_DMA_SG_OSD_ENT]; |
1a0adaf3 HV |
291 | dma_addr_t SG_handle; |
292 | int SG_length; | |
293 | ||
294 | /* SG List of Buffers */ | |
295 | struct scatterlist SGlist[IVTV_DMA_SG_OSD_ENT]; | |
296 | }; | |
297 | ||
298 | struct ivtv_dma_page_info { | |
299 | unsigned long uaddr; | |
300 | unsigned long first; | |
301 | unsigned long last; | |
302 | unsigned int offset; | |
303 | unsigned int tail; | |
304 | int page_count; | |
305 | }; | |
306 | ||
307 | struct ivtv_buffer { | |
308 | struct list_head list; | |
309 | dma_addr_t dma_handle; | |
f4071b85 HV |
310 | unsigned short b_flags; |
311 | unsigned short dma_xfer_cnt; | |
1a0adaf3 | 312 | char *buf; |
1a0adaf3 HV |
313 | u32 bytesused; |
314 | u32 readpos; | |
315 | }; | |
316 | ||
317 | struct ivtv_queue { | |
a158f355 HV |
318 | struct list_head list; /* the list of buffers in this queue */ |
319 | u32 buffers; /* number of buffers in this queue */ | |
320 | u32 length; /* total number of bytes of available buffer space */ | |
321 | u32 bytesused; /* total number of bytes used in this queue */ | |
1a0adaf3 HV |
322 | }; |
323 | ||
a158f355 | 324 | struct ivtv; /* forward reference */ |
1a0adaf3 HV |
325 | |
326 | struct ivtv_stream { | |
327 | /* These first four fields are always set, even if the stream | |
328 | is not actually created. */ | |
635d62f0 | 329 | struct video_device vdev; /* vdev.v4l2_dev is NULL if there is no device */ |
6e6a8b5a | 330 | struct ivtv *itv; /* for ease of use */ |
1a0adaf3 HV |
331 | const char *name; /* name of the stream */ |
332 | int type; /* stream type */ | |
333 | ||
61bb725e | 334 | struct v4l2_fh *fh; /* pointer to the streaming filehandle */ |
6e6a8b5a | 335 | spinlock_t qlock; /* locks access to the queues */ |
a158f355 HV |
336 | unsigned long s_flags; /* status flags, see above */ |
337 | int dma; /* can be PCI_DMA_TODEVICE, PCI_DMA_FROMDEVICE or PCI_DMA_NONE */ | |
37093b1e HV |
338 | u32 pending_offset; |
339 | u32 pending_backup; | |
340 | u64 pending_pts; | |
341 | ||
1a0adaf3 HV |
342 | u32 dma_offset; |
343 | u32 dma_backup; | |
344 | u64 dma_pts; | |
345 | ||
346 | int subtype; | |
347 | wait_queue_head_t waitq; | |
348 | u32 dma_last_offset; | |
349 | ||
350 | /* Buffer Stats */ | |
351 | u32 buffers; | |
352 | u32 buf_size; | |
353 | u32 buffers_stolen; | |
354 | ||
355 | /* Buffer Queues */ | |
356 | struct ivtv_queue q_free; /* free buffers */ | |
357 | struct ivtv_queue q_full; /* full buffers */ | |
358 | struct ivtv_queue q_io; /* waiting for I/O */ | |
359 | struct ivtv_queue q_dma; /* waiting for DMA */ | |
360 | struct ivtv_queue q_predma; /* waiting for DMA */ | |
361 | ||
f4071b85 HV |
362 | /* DMA xfer counter, buffers belonging to the same DMA |
363 | xfer will have the same dma_xfer_cnt. */ | |
364 | u16 dma_xfer_cnt; | |
365 | ||
1a0adaf3 | 366 | /* Base Dev SG Array for cx23415/6 */ |
b0510f8d AV |
367 | struct ivtv_sg_host_element *sg_pending; |
368 | struct ivtv_sg_host_element *sg_processing; | |
37093b1e HV |
369 | struct ivtv_sg_element *sg_dma; |
370 | dma_addr_t sg_handle; | |
371 | int sg_pending_size; | |
372 | int sg_processing_size; | |
373 | int sg_processed; | |
1a0adaf3 HV |
374 | |
375 | /* SG List of Buffers */ | |
376 | struct scatterlist *SGlist; | |
377 | }; | |
378 | ||
379 | struct ivtv_open_id { | |
09250193 | 380 | struct v4l2_fh fh; |
a158f355 HV |
381 | int type; /* stream type */ |
382 | int yuv_frames; /* 1: started OUT_UDMA_YUV output mode */ | |
1a0adaf3 HV |
383 | struct ivtv *itv; |
384 | }; | |
385 | ||
09250193 HV |
386 | static inline struct ivtv_open_id *fh2id(struct v4l2_fh *fh) |
387 | { | |
388 | return container_of(fh, struct ivtv_open_id, fh); | |
389 | } | |
390 | ||
1a0adaf3 HV |
391 | struct yuv_frame_info |
392 | { | |
393 | u32 update; | |
33c0fcad HV |
394 | s32 src_x; |
395 | s32 src_y; | |
396 | u32 src_w; | |
397 | u32 src_h; | |
398 | s32 dst_x; | |
399 | s32 dst_y; | |
400 | u32 dst_w; | |
401 | u32 dst_h; | |
402 | s32 pan_x; | |
403 | s32 pan_y; | |
1a0adaf3 HV |
404 | u32 vis_w; |
405 | u32 vis_h; | |
406 | u32 interlaced_y; | |
407 | u32 interlaced_uv; | |
33c0fcad | 408 | s32 tru_x; |
1a0adaf3 HV |
409 | u32 tru_w; |
410 | u32 tru_h; | |
411 | u32 offset_y; | |
33c0fcad | 412 | s32 lace_mode; |
3b5c1c8e IA |
413 | u32 sync_field; |
414 | u32 delay; | |
415 | u32 interlaced; | |
1a0adaf3 HV |
416 | }; |
417 | ||
418 | #define IVTV_YUV_MODE_INTERLACED 0x00 | |
419 | #define IVTV_YUV_MODE_PROGRESSIVE 0x01 | |
420 | #define IVTV_YUV_MODE_AUTO 0x02 | |
421 | #define IVTV_YUV_MODE_MASK 0x03 | |
422 | ||
423 | #define IVTV_YUV_SYNC_EVEN 0x00 | |
424 | #define IVTV_YUV_SYNC_ODD 0x04 | |
425 | #define IVTV_YUV_SYNC_MASK 0x04 | |
426 | ||
a3e5f5e2 IA |
427 | #define IVTV_YUV_BUFFERS 8 |
428 | ||
1a0adaf3 HV |
429 | struct yuv_playback_info |
430 | { | |
431 | u32 reg_2834; | |
432 | u32 reg_2838; | |
433 | u32 reg_283c; | |
434 | u32 reg_2840; | |
435 | u32 reg_2844; | |
436 | u32 reg_2848; | |
437 | u32 reg_2854; | |
438 | u32 reg_285c; | |
439 | u32 reg_2864; | |
440 | ||
441 | u32 reg_2870; | |
442 | u32 reg_2874; | |
443 | u32 reg_2890; | |
444 | u32 reg_2898; | |
445 | u32 reg_289c; | |
446 | ||
447 | u32 reg_2918; | |
448 | u32 reg_291c; | |
449 | u32 reg_2920; | |
450 | u32 reg_2924; | |
451 | u32 reg_2928; | |
452 | u32 reg_292c; | |
453 | u32 reg_2930; | |
454 | ||
455 | u32 reg_2934; | |
456 | ||
457 | u32 reg_2938; | |
458 | u32 reg_293c; | |
459 | u32 reg_2940; | |
460 | u32 reg_2944; | |
461 | u32 reg_2948; | |
462 | u32 reg_294c; | |
463 | u32 reg_2950; | |
464 | u32 reg_2954; | |
465 | u32 reg_2958; | |
466 | u32 reg_295c; | |
467 | u32 reg_2960; | |
468 | u32 reg_2964; | |
469 | u32 reg_2968; | |
470 | u32 reg_296c; | |
471 | ||
472 | u32 reg_2970; | |
473 | ||
474 | int v_filter_1; | |
475 | int v_filter_2; | |
476 | int h_filter; | |
477 | ||
88ab075a IA |
478 | u8 track_osd; /* Should yuv output track the OSD size & position */ |
479 | ||
1a0adaf3 HV |
480 | u32 osd_x_offset; |
481 | u32 osd_y_offset; | |
482 | ||
483 | u32 osd_x_pan; | |
484 | u32 osd_y_pan; | |
485 | ||
486 | u32 osd_vis_w; | |
487 | u32 osd_vis_h; | |
488 | ||
77aded6b IA |
489 | u32 osd_full_w; |
490 | u32 osd_full_h; | |
491 | ||
1a0adaf3 HV |
492 | int decode_height; |
493 | ||
1a0adaf3 HV |
494 | int lace_mode; |
495 | int lace_threshold; | |
1a0adaf3 HV |
496 | int lace_sync_field; |
497 | ||
498 | atomic_t next_dma_frame; | |
499 | atomic_t next_fill_frame; | |
500 | ||
501 | u32 yuv_forced_update; | |
502 | int update_frame; | |
bfd7beac | 503 | |
bfd7beac IA |
504 | u8 fields_lapsed; /* Counter used when delaying a frame */ |
505 | ||
a3e5f5e2 | 506 | struct yuv_frame_info new_frame_info[IVTV_YUV_BUFFERS]; |
1a0adaf3 HV |
507 | struct yuv_frame_info old_frame_info; |
508 | struct yuv_frame_info old_frame_info_args; | |
509 | ||
510 | void *blanking_ptr; | |
511 | dma_addr_t blanking_dmaptr; | |
c240ad00 IA |
512 | |
513 | int stream_size; | |
a3e5f5e2 IA |
514 | |
515 | u8 draw_frame; /* PVR350 buffer to draw into */ | |
516 | u8 max_frames_buffered; /* Maximum number of frames to buffer */ | |
77aded6b IA |
517 | |
518 | struct v4l2_rect main_rect; | |
519 | u32 v4l2_src_w; | |
520 | u32 v4l2_src_h; | |
2bd7ac55 IA |
521 | |
522 | u8 running; /* Have any frames been displayed */ | |
1a0adaf3 HV |
523 | }; |
524 | ||
525 | #define IVTV_VBI_FRAMES 32 | |
526 | ||
527 | /* VBI data */ | |
2f3a9893 HV |
528 | struct vbi_cc { |
529 | u8 odd[2]; /* two-byte payload of odd field */ | |
530 | u8 even[2]; /* two-byte payload of even field */; | |
531 | }; | |
532 | ||
533 | struct vbi_vps { | |
534 | u8 data[5]; /* five-byte VPS payload */ | |
535 | }; | |
536 | ||
1a0adaf3 | 537 | struct vbi_info { |
effa0b08 HV |
538 | /* VBI general data, does not change during streaming */ |
539 | ||
a158f355 HV |
540 | u32 raw_decoder_line_size; /* raw VBI line size from digitizer */ |
541 | u8 raw_decoder_sav_odd_field; /* raw VBI Start Active Video digitizer code of odd field */ | |
542 | u8 raw_decoder_sav_even_field; /* raw VBI Start Active Video digitizer code of even field */ | |
543 | u32 sliced_decoder_line_size; /* sliced VBI line size from digitizer */ | |
544 | u8 sliced_decoder_sav_odd_field; /* sliced VBI Start Active Video digitizer code of odd field */ | |
545 | u8 sliced_decoder_sav_even_field; /* sliced VBI Start Active Video digitizer code of even field */ | |
546 | ||
effa0b08 HV |
547 | u32 start[2]; /* start of first VBI line in the odd/even fields */ |
548 | u32 count; /* number of VBI lines per field */ | |
549 | u32 raw_size; /* size of raw VBI line from the digitizer */ | |
550 | u32 sliced_size; /* size of sliced VBI line from the digitizer */ | |
551 | ||
552 | u32 dec_start; /* start in decoder memory of VBI re-insertion buffers */ | |
553 | u32 enc_start; /* start in encoder memory of VBI capture buffers */ | |
554 | u32 enc_size; /* size of VBI capture area */ | |
555 | int fpi; /* number of VBI frames per interrupt */ | |
556 | ||
557 | struct v4l2_format in; /* current VBI capture format */ | |
558 | struct v4l2_sliced_vbi_format *sliced_in; /* convenience pointer to sliced struct in vbi.in union */ | |
559 | int insert_mpeg; /* if non-zero, then embed VBI data in MPEG stream */ | |
560 | ||
561 | /* Raw VBI compatibility hack */ | |
562 | ||
6e6a8b5a | 563 | u32 frame; /* frame counter hack needed for backwards compatibility |
effa0b08 HV |
564 | of old VBI software */ |
565 | ||
566 | /* Sliced VBI output data */ | |
567 | ||
568 | struct vbi_cc cc_payload[256]; /* sliced VBI CC payload array: it is an array to | |
2f3a9893 | 569 | prevent dropping CC data if they couldn't be |
effa0b08 HV |
570 | processed fast enough */ |
571 | int cc_payload_idx; /* index in cc_payload */ | |
572 | u8 cc_missing_cnt; /* counts number of frames without CC for passthrough mode */ | |
573 | int wss_payload; /* sliced VBI WSS payload */ | |
574 | u8 wss_missing_cnt; /* counts number of frames without WSS for passthrough mode */ | |
575 | struct vbi_vps vps_payload; /* sliced VBI VPS payload */ | |
576 | ||
577 | /* Sliced VBI capture data */ | |
578 | ||
579 | struct v4l2_sliced_vbi_data sliced_data[36]; /* sliced VBI storage for VBI encoder stream */ | |
580 | struct v4l2_sliced_vbi_data sliced_dec_data[36];/* sliced VBI storage for VBI decoder stream */ | |
581 | ||
582 | /* VBI Embedding data */ | |
1a0adaf3 HV |
583 | |
584 | /* Buffer for VBI data inserted into MPEG stream. | |
585 | The first byte is a dummy byte that's never used. | |
586 | The next 16 bytes contain the MPEG header for the VBI data, | |
587 | the remainder is the actual VBI data. | |
588 | The max size accepted by the MPEG VBI reinsertion turns out | |
589 | to be 1552 bytes, which happens to be 4 + (1 + 42) * (2 * 18) bytes, | |
590 | where 4 is a four byte header, 42 is the max sliced VBI payload, 1 is | |
591 | a single line header byte and 2 * 18 is the number of VBI lines per frame. | |
592 | ||
593 | However, it seems that the data must be 1K aligned, so we have to | |
594 | pad the data until the 1 or 2 K boundary. | |
595 | ||
596 | This pointer array will allocate 2049 bytes to store each VBI frame. */ | |
597 | u8 *sliced_mpeg_data[IVTV_VBI_FRAMES]; | |
598 | u32 sliced_mpeg_size[IVTV_VBI_FRAMES]; | |
effa0b08 HV |
599 | struct ivtv_buffer sliced_mpeg_buf; /* temporary buffer holding data from sliced_mpeg_data */ |
600 | u32 inserted_frame; /* index in sliced_mpeg_size of next sliced data | |
601 | to be inserted in the MPEG stream */ | |
1a0adaf3 HV |
602 | }; |
603 | ||
604 | /* forward declaration of struct defined in ivtv-cards.h */ | |
605 | struct ivtv_card; | |
606 | ||
607 | /* Struct to hold info about ivtv cards */ | |
608 | struct ivtv { | |
fd8b281a | 609 | /* General fixed card data */ |
8ac05ae3 | 610 | struct pci_dev *pdev; /* PCI device */ |
1a0adaf3 | 611 | const struct ivtv_card *card; /* card information */ |
fd8b281a | 612 | const char *card_name; /* full name of the card */ |
d9009201 | 613 | const struct ivtv_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */ |
fd8b281a HV |
614 | u8 has_cx23415; /* 1 if it is a cx23415 based card, 0 for cx23416 */ |
615 | u8 pvr150_workaround; /* 1 if the cx25840 needs to workaround a PVR150 bug */ | |
616 | u8 nof_inputs; /* number of video inputs */ | |
617 | u8 nof_audio_inputs; /* number of audio inputs */ | |
618 | u32 v4l2_cap; /* V4L2 capabilities of card */ | |
6e6a8b5a | 619 | u32 hw_flags; /* hardware description of the board */ |
fd8b281a | 620 | v4l2_std_id tuner_std; /* the norm of the card's tuner (fixed) */ |
67ec09fd | 621 | struct v4l2_subdev *sd_video; /* controlling video decoder subdev */ |
c411b39d | 622 | bool sd_video_is_streaming; /* is video already streaming? */ |
67ec09fd HV |
623 | struct v4l2_subdev *sd_audio; /* controlling audio subdev */ |
624 | struct v4l2_subdev *sd_muxer; /* controlling audio muxer subdev */ | |
1c36dfc5 | 625 | resource_size_t base_addr; /* PCI resource base address */ |
fd8b281a HV |
626 | volatile void __iomem *enc_mem; /* pointer to mapped encoder memory */ |
627 | volatile void __iomem *dec_mem; /* pointer to mapped decoder memory */ | |
628 | volatile void __iomem *reg_mem; /* pointer to mapped registers */ | |
6e6a8b5a | 629 | struct ivtv_options options; /* user options */ |
fd8b281a | 630 | |
8ac05ae3 | 631 | struct v4l2_device v4l2_dev; |
f7b80e69 | 632 | struct cx2341x_handler cxhdl; |
debf8001 HV |
633 | struct { |
634 | /* PTS/Frame count control cluster */ | |
635 | struct v4l2_ctrl *ctrl_pts; | |
636 | struct v4l2_ctrl *ctrl_frame; | |
637 | }; | |
638 | struct { | |
639 | /* Audio Playback control cluster */ | |
640 | struct v4l2_ctrl *ctrl_audio_playback; | |
641 | struct v4l2_ctrl *ctrl_audio_multilingual_playback; | |
642 | }; | |
2fd78144 | 643 | struct v4l2_ctrl_handler hdl_gpio; |
f7b80e69 | 644 | struct v4l2_subdev sd_gpio; /* GPIO sub-device */ |
67ec09fd | 645 | u16 instance; |
fd8b281a HV |
646 | |
647 | /* High-level state info */ | |
648 | unsigned long i_flags; /* global ivtv flags */ | |
649 | u8 is_50hz; /* 1 if the current capture standard is 50 Hz */ | |
650 | u8 is_60hz /* 1 if the current capture standard is 60 Hz */; | |
651 | u8 is_out_50hz /* 1 if the current TV output standard is 50 Hz */; | |
652 | u8 is_out_60hz /* 1 if the current TV output standard is 60 Hz */; | |
653 | int output_mode; /* decoder output mode: NONE, MPG, YUV, UDMA YUV, passthrough */ | |
654 | u32 audio_input; /* current audio input */ | |
655 | u32 active_input; /* current video input */ | |
656 | u32 active_output; /* current video output */ | |
657 | v4l2_std_id std; /* current capture TV standard */ | |
658 | v4l2_std_id std_out; /* current TV output standard */ | |
659 | u8 audio_stereo_mode; /* decoder setting how to handle stereo MPEG audio */ | |
660 | u8 audio_bilingual_mode; /* decoder setting how to handle bilingual MPEG audio */ | |
fd8b281a | 661 | |
fd8b281a HV |
662 | /* Locking */ |
663 | spinlock_t lock; /* lock access to this struct */ | |
a158f355 | 664 | struct mutex serialize_lock; /* mutex used to serialize open/close/start/stop/ioctl operations */ |
fd8b281a | 665 | |
fd8b281a HV |
666 | /* Streams */ |
667 | int stream_buf_size[IVTV_MAX_STREAMS]; /* stream buffer size */ | |
6e6a8b5a | 668 | struct ivtv_stream streams[IVTV_MAX_STREAMS]; /* stream data */ |
fd8b281a HV |
669 | atomic_t capturing; /* count number of active capture streams */ |
670 | atomic_t decoding; /* count number of active decoding streams */ | |
671 | ||
269c11fb AW |
672 | /* ALSA interface for PCM capture stream */ |
673 | struct snd_ivtv_card *alsa; | |
674 | void (*pcm_announce_callback)(struct snd_ivtv_card *card, u8 *pcm_data, | |
675 | size_t num_bytes); | |
676 | ||
677 | /* Used for ivtv-alsa module loading */ | |
678 | struct work_struct request_module_wk; | |
fd8b281a HV |
679 | |
680 | /* Interrupts & DMA */ | |
681 | u32 irqmask; /* active interrupts */ | |
682 | u32 irq_rr_idx; /* round-robin stream index */ | |
7bc46560 TH |
683 | struct kthread_worker irq_worker; /* kthread worker for PIO/YUV/VBI actions */ |
684 | struct task_struct *irq_worker_task; /* task for irq_worker */ | |
685 | struct kthread_work irq_work; /* kthread work entry */ | |
fd8b281a HV |
686 | spinlock_t dma_reg_lock; /* lock access to DMA engine registers */ |
687 | int cur_dma_stream; /* index of current stream doing DMA (-1 if none) */ | |
688 | int cur_pio_stream; /* index of current stream doing PIO (-1 if none) */ | |
689 | u32 dma_data_req_offset; /* store offset in decoder memory of current DMA request */ | |
690 | u32 dma_data_req_size; /* store size of current DMA request */ | |
691 | int dma_retries; /* current DMA retry attempt */ | |
692 | struct ivtv_user_dma udma; /* user based DMA for OSD */ | |
693 | struct timer_list dma_timer; /* timer used to catch unfinished DMAs */ | |
a158f355 | 694 | u32 last_vsync_field; /* last seen vsync field */ |
fd8b281a HV |
695 | wait_queue_head_t dma_waitq; /* wake up when the current DMA is finished */ |
696 | wait_queue_head_t eos_waitq; /* wake up when EOS arrives */ | |
697 | wait_queue_head_t event_waitq; /* wake up when the next decoder event arrives */ | |
698 | wait_queue_head_t vsync_waitq; /* wake up when the next decoder vsync arrives */ | |
699 | ||
700 | ||
701 | /* Mailbox */ | |
702 | struct ivtv_mailbox_data enc_mbox; /* encoder mailboxes */ | |
703 | struct ivtv_mailbox_data dec_mbox; /* decoder mailboxes */ | |
6e6a8b5a | 704 | struct ivtv_api_cache api_cache[256]; /* cached API commands */ |
fd8b281a HV |
705 | |
706 | ||
707 | /* I2C */ | |
708 | struct i2c_adapter i2c_adap; | |
709 | struct i2c_algo_bit_data i2c_algo; | |
710 | struct i2c_client i2c_client; | |
fd8b281a HV |
711 | int i2c_state; /* i2c bit state */ |
712 | struct mutex i2c_bus_lock; /* lock i2c bus */ | |
713 | ||
ad2fe2d4 | 714 | struct IR_i2c_init_data ir_i2c_init_data; |
fd8b281a HV |
715 | |
716 | /* Program Index information */ | |
717 | u32 pgm_info_offset; /* start of pgm info in encoder memory */ | |
718 | u32 pgm_info_num; /* number of elements in the pgm cyclic buffer in encoder memory */ | |
719 | u32 pgm_info_write_idx; /* last index written by the card that was transferred to pgm_info[] */ | |
720 | u32 pgm_info_read_idx; /* last index in pgm_info read by the application */ | |
721 | struct v4l2_enc_idx_entry pgm_info[IVTV_MAX_PGM_INDEX]; /* filled from the pgm cyclic buffer on the card */ | |
722 | ||
723 | ||
724 | /* Miscellaneous */ | |
725 | u32 open_id; /* incremented each time an open occurs, is >= 1 */ | |
fd8b281a HV |
726 | int search_pack_header; /* 1 if ivtv_copy_buf_to_user() is scanning for a pack header (0xba) */ |
727 | int speed; /* current playback speed setting */ | |
728 | u8 speed_mute_audio; /* 1 if audio should be muted when fast forward */ | |
729 | u64 mpg_data_received; /* number of bytes received from the MPEG stream */ | |
730 | u64 vbi_data_inserted; /* number of VBI bytes inserted into the MPEG stream */ | |
731 | u32 last_dec_timing[3]; /* cache last retrieved pts/scr/frame values */ | |
732 | unsigned long dualwatch_jiffies;/* jiffies value of the previous dualwatch check */ | |
0d82fe80 | 733 | u32 dualwatch_stereo_mode; /* current detected dualwatch stereo mode */ |
fd8b281a HV |
734 | |
735 | ||
736 | /* VBI state info */ | |
737 | struct vbi_info vbi; /* VBI-specific data */ | |
738 | ||
739 | ||
740 | /* YUV playback */ | |
741 | struct yuv_playback_info yuv_info; /* YUV playback data */ | |
1a0adaf3 | 742 | |
1a0adaf3 HV |
743 | |
744 | /* OSD support */ | |
745 | unsigned long osd_video_pbase; | |
fd8b281a HV |
746 | int osd_global_alpha_state; /* 1 = global alpha is on */ |
747 | int osd_local_alpha_state; /* 1 = local alpha is on */ | |
748 | int osd_chroma_key_state; /* 1 = chroma-keying is on */ | |
749 | u8 osd_global_alpha; /* current global alpha */ | |
750 | u32 osd_chroma_key; /* current chroma key */ | |
fd8b281a HV |
751 | struct v4l2_rect osd_rect; /* current OSD position and size */ |
752 | struct v4l2_rect main_rect; /* current Main window position and size */ | |
7b3a0d49 | 753 | struct osd_info *osd_info; /* ivtvfb private OSD info */ |
215659d1 | 754 | void (*ivtvfb_restore)(struct ivtv *itv); /* Used for a warm start */ |
1a0adaf3 HV |
755 | }; |
756 | ||
8ac05ae3 | 757 | static inline struct ivtv *to_ivtv(struct v4l2_device *v4l2_dev) |
67ec09fd | 758 | { |
8ac05ae3 | 759 | return container_of(v4l2_dev, struct ivtv, v4l2_dev); |
67ec09fd HV |
760 | } |
761 | ||
269c11fb AW |
762 | /* ivtv extensions to be loaded */ |
763 | extern int (*ivtv_ext_init)(struct ivtv *); | |
764 | ||
1a0adaf3 | 765 | /* Globals */ |
1a0adaf3 | 766 | extern int ivtv_first_minor; |
1a0adaf3 HV |
767 | |
768 | /*==============Prototypes==================*/ | |
769 | ||
770 | /* Hardware/IRQ */ | |
771 | void ivtv_set_irq_mask(struct ivtv *itv, u32 mask); | |
772 | void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask); | |
773 | ||
774 | /* try to set output mode, return current mode. */ | |
775 | int ivtv_set_output_mode(struct ivtv *itv, int mode); | |
776 | ||
777 | /* return current output stream based on current mode */ | |
778 | struct ivtv_stream *ivtv_get_output_stream(struct ivtv *itv); | |
779 | ||
780 | /* Return non-zero if a signal is pending */ | |
201700d3 | 781 | int ivtv_msleep_timeout(unsigned int msecs, int intr); |
1a0adaf3 HV |
782 | |
783 | /* Wait on queue, returns -EINTR if interrupted */ | |
784 | int ivtv_waitq(wait_queue_head_t *waitq); | |
785 | ||
786 | /* Read Hauppauge eeprom */ | |
787 | struct tveeprom; /* forward reference */ | |
788 | void ivtv_read_eeprom(struct ivtv *itv, struct tveeprom *tv); | |
789 | ||
c976bc82 HV |
790 | /* First-open initialization: load firmware, init cx25840, etc. */ |
791 | int ivtv_init_on_first_open(struct ivtv *itv); | |
792 | ||
a8b86435 HV |
793 | /* Test if the current VBI mode is raw (1) or sliced (0) */ |
794 | static inline int ivtv_raw_vbi(const struct ivtv *itv) | |
795 | { | |
796 | return itv->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE; | |
797 | } | |
798 | ||
1a0adaf3 HV |
799 | /* This is a PCI post thing, where if the pci register is not read, then |
800 | the write doesn't always take effect right away. By reading back the | |
801 | register any pending PCI writes will be performed (in order), and so | |
802 | you can be sure that the writes are guaranteed to be done. | |
803 | ||
804 | Rarely needed, only in some timing sensitive cases. | |
805 | Apparently if this is not done some motherboards seem | |
806 | to kill the firmware and get into the broken state until computer is | |
807 | rebooted. */ | |
808 | #define write_sync(val, reg) \ | |
809 | do { writel(val, reg); readl(reg); } while (0) | |
810 | ||
811 | #define read_reg(reg) readl(itv->reg_mem + (reg)) | |
812 | #define write_reg(val, reg) writel(val, itv->reg_mem + (reg)) | |
813 | #define write_reg_sync(val, reg) \ | |
814 | do { write_reg(val, reg); read_reg(reg); } while (0) | |
815 | ||
816 | #define read_enc(addr) readl(itv->enc_mem + (u32)(addr)) | |
817 | #define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr)) | |
818 | #define write_enc_sync(val, addr) \ | |
819 | do { write_enc(val, addr); read_enc(addr); } while (0) | |
820 | ||
821 | #define read_dec(addr) readl(itv->dec_mem + (u32)(addr)) | |
822 | #define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr)) | |
823 | #define write_dec_sync(val, addr) \ | |
824 | do { write_dec(val, addr); read_dec(addr); } while (0) | |
825 | ||
67ec09fd HV |
826 | /* Call the specified callback for all subdevs matching hw (if 0, then |
827 | match them all). Ignore any errors. */ | |
6e6a8b5a | 828 | #define ivtv_call_hw(itv, hw, o, f, args...) \ |
fe293011 | 829 | v4l2_device_mask_call_all(&(itv)->v4l2_dev, hw, o, f, ##args) |
67ec09fd HV |
830 | |
831 | #define ivtv_call_all(itv, o, f, args...) ivtv_call_hw(itv, 0, o, f , ##args) | |
832 | ||
833 | /* Call the specified callback for all subdevs matching hw (if 0, then | |
834 | match them all). If the callback returns an error other than 0 or | |
835 | -ENOIOCTLCMD, then return with that error code. */ | |
6c2d4dd1 | 836 | #define ivtv_call_hw_err(itv, hw, o, f, args...) \ |
fe293011 | 837 | v4l2_device_mask_call_until_err(&(itv)->v4l2_dev, hw, o, f, ##args) |
67ec09fd HV |
838 | |
839 | #define ivtv_call_all_err(itv, o, f, args...) ivtv_call_hw_err(itv, 0, o, f , ##args) | |
840 | ||
612570f2 | 841 | #endif |