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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
a611d0ca IL |
2 | /* |
3 | * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip | |
4 | * | |
5 | * Copyright (C) 2008 Igor M. Liplianin <liplianin@me.by> | |
a611d0ca IL |
6 | */ |
7 | ||
a611d0ca | 8 | #include <linux/i2c.h> |
0017505d | 9 | #include <linux/i2c-algo-bit.h> |
a611d0ca | 10 | #include <linux/init.h> |
a6b7a407 | 11 | #include <linux/interrupt.h> |
a611d0ca IL |
12 | #include <linux/kernel.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/proc_fs.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 17 | #include <linux/slab.h> |
6bda9644 | 18 | #include <media/rc-core.h> |
a611d0ca | 19 | |
fada1935 MCC |
20 | #include <media/demux.h> |
21 | #include <media/dmxdev.h> | |
22 | #include <media/dvb_demux.h> | |
23 | #include <media/dvb_frontend.h> | |
24 | #include <media/dvb_net.h> | |
25 | #include <media/dvbdev.h> | |
a611d0ca IL |
26 | #include "dvb-pll.h" |
27 | ||
28 | #include "stv0299.h" | |
e4aab64c IL |
29 | #include "stv0288.h" |
30 | #include "stb6000.h" | |
04ad28c9 | 31 | #include "si21xx.h" |
35d9c427 | 32 | #include "cx24116.h" |
a611d0ca | 33 | #include "z0194a.h" |
73f0af44 | 34 | #include "ts2020.h" |
b4a0e816 | 35 | #include "ds3000.h" |
a611d0ca | 36 | |
727e625c MCC |
37 | #define MODULE_NAME "dm1105" |
38 | ||
d8300df9 IL |
39 | #define UNSET (-1U) |
40 | ||
0017505d IL |
41 | #define DM1105_BOARD_NOAUTO UNSET |
42 | #define DM1105_BOARD_UNKNOWN 0 | |
43 | #define DM1105_BOARD_DVBWORLD_2002 1 | |
44 | #define DM1105_BOARD_DVBWORLD_2004 2 | |
45 | #define DM1105_BOARD_AXESS_DM05 3 | |
46 | #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO 4 | |
d8300df9 | 47 | |
a611d0ca IL |
48 | /* ----------------------------------------------- */ |
49 | /* | |
50 | * PCI ID's | |
51 | */ | |
52 | #ifndef PCI_VENDOR_ID_TRIGEM | |
53 | #define PCI_VENDOR_ID_TRIGEM 0x109f | |
54 | #endif | |
519a4bdc IL |
55 | #ifndef PCI_VENDOR_ID_AXESS |
56 | #define PCI_VENDOR_ID_AXESS 0x195d | |
57 | #endif | |
a611d0ca IL |
58 | #ifndef PCI_DEVICE_ID_DM1105 |
59 | #define PCI_DEVICE_ID_DM1105 0x036f | |
60 | #endif | |
61 | #ifndef PCI_DEVICE_ID_DW2002 | |
62 | #define PCI_DEVICE_ID_DW2002 0x2002 | |
63 | #endif | |
64 | #ifndef PCI_DEVICE_ID_DW2004 | |
65 | #define PCI_DEVICE_ID_DW2004 0x2004 | |
66 | #endif | |
519a4bdc IL |
67 | #ifndef PCI_DEVICE_ID_DM05 |
68 | #define PCI_DEVICE_ID_DM05 0x1105 | |
69 | #endif | |
a611d0ca IL |
70 | /* ----------------------------------------------- */ |
71 | /* sdmc dm1105 registers */ | |
72 | ||
73 | /* TS Control */ | |
74 | #define DM1105_TSCTR 0x00 | |
75 | #define DM1105_DTALENTH 0x04 | |
76 | ||
77 | /* GPIO Interface */ | |
78 | #define DM1105_GPIOVAL 0x08 | |
79 | #define DM1105_GPIOCTR 0x0c | |
80 | ||
81 | /* PID serial number */ | |
82 | #define DM1105_PIDN 0x10 | |
83 | ||
84 | /* Odd-even secret key select */ | |
85 | #define DM1105_CWSEL 0x14 | |
86 | ||
87 | /* Host Command Interface */ | |
88 | #define DM1105_HOST_CTR 0x18 | |
89 | #define DM1105_HOST_AD 0x1c | |
90 | ||
91 | /* PCI Interface */ | |
92 | #define DM1105_CR 0x30 | |
93 | #define DM1105_RST 0x34 | |
94 | #define DM1105_STADR 0x38 | |
95 | #define DM1105_RLEN 0x3c | |
96 | #define DM1105_WRP 0x40 | |
97 | #define DM1105_INTCNT 0x44 | |
98 | #define DM1105_INTMAK 0x48 | |
99 | #define DM1105_INTSTS 0x4c | |
100 | ||
101 | /* CW Value */ | |
102 | #define DM1105_ODD 0x50 | |
103 | #define DM1105_EVEN 0x58 | |
104 | ||
105 | /* PID Value */ | |
106 | #define DM1105_PID 0x60 | |
107 | ||
108 | /* IR Control */ | |
109 | #define DM1105_IRCTR 0x64 | |
110 | #define DM1105_IRMODE 0x68 | |
111 | #define DM1105_SYSTEMCODE 0x6c | |
112 | #define DM1105_IRCODE 0x70 | |
113 | ||
114 | /* Unknown Values */ | |
115 | #define DM1105_ENCRYPT 0x74 | |
116 | #define DM1105_VER 0x7c | |
117 | ||
118 | /* I2C Interface */ | |
119 | #define DM1105_I2CCTR 0x80 | |
120 | #define DM1105_I2CSTS 0x81 | |
121 | #define DM1105_I2CDAT 0x82 | |
122 | #define DM1105_I2C_RA 0x83 | |
123 | /* ----------------------------------------------- */ | |
124 | /* Interrupt Mask Bits */ | |
125 | ||
126 | #define INTMAK_TSIRQM 0x01 | |
127 | #define INTMAK_HIRQM 0x04 | |
128 | #define INTMAK_IRM 0x08 | |
129 | #define INTMAK_ALLMASK (INTMAK_TSIRQM | \ | |
130 | INTMAK_HIRQM | \ | |
131 | INTMAK_IRM) | |
132 | #define INTMAK_NONEMASK 0x00 | |
133 | ||
134 | /* Interrupt Status Bits */ | |
135 | #define INTSTS_TSIRQ 0x01 | |
136 | #define INTSTS_HIRQ 0x04 | |
137 | #define INTSTS_IR 0x08 | |
138 | ||
139 | /* IR Control Bits */ | |
140 | #define DM1105_IR_EN 0x01 | |
141 | #define DM1105_SYS_CHK 0x02 | |
142 | #define DM1105_REP_FLG 0x08 | |
143 | ||
144 | /* EEPROM addr */ | |
145 | #define IIC_24C01_addr 0xa0 | |
146 | /* Max board count */ | |
147 | #define DM1105_MAX 0x04 | |
148 | ||
149 | #define DRIVER_NAME "dm1105" | |
0017505d | 150 | #define DM1105_I2C_GPIO_NAME "dm1105-gpio" |
a611d0ca IL |
151 | |
152 | #define DM1105_DMA_PACKETS 47 | |
153 | #define DM1105_DMA_PACKET_LENGTH (128*4) | |
154 | #define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS) | |
155 | ||
0017505d IL |
156 | /* */ |
157 | #define GPIO08 (1 << 8) | |
158 | #define GPIO13 (1 << 13) | |
159 | #define GPIO14 (1 << 14) | |
160 | #define GPIO15 (1 << 15) | |
161 | #define GPIO16 (1 << 16) | |
162 | #define GPIO17 (1 << 17) | |
163 | #define GPIO_ALL 0x03ffff | |
164 | ||
a611d0ca | 165 | /* GPIO's for LNB power control */ |
0017505d IL |
166 | #define DM1105_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13)) |
167 | #define DM1105_LNB_OFF GPIO17 | |
168 | #define DM1105_LNB_13V (GPIO16 | GPIO08) | |
169 | #define DM1105_LNB_18V GPIO08 | |
a611d0ca | 170 | |
519a4bdc | 171 | /* GPIO's for LNB power control for Axess DM05 */ |
0017505d IL |
172 | #define DM05_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13)) |
173 | #define DM05_LNB_OFF GPIO17/* actually 13v */ | |
174 | #define DM05_LNB_13V GPIO17 | |
175 | #define DM05_LNB_18V (GPIO17 | GPIO16) | |
176 | ||
177 | /* GPIO's for LNB power control for unbranded with I2C on GPIO */ | |
178 | #define UNBR_LNB_MASK (GPIO17 | GPIO16) | |
179 | #define UNBR_LNB_OFF 0 | |
180 | #define UNBR_LNB_13V GPIO17 | |
181 | #define UNBR_LNB_18V (GPIO17 | GPIO16) | |
519a4bdc | 182 | |
d8300df9 IL |
183 | static unsigned int card[] = {[0 ... 3] = UNSET }; |
184 | module_param_array(card, int, NULL, 0444); | |
185 | MODULE_PARM_DESC(card, "card type"); | |
186 | ||
a611d0ca IL |
187 | static int ir_debug; |
188 | module_param(ir_debug, int, 0644); | |
189 | MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding"); | |
190 | ||
d8300df9 IL |
191 | static unsigned int dm1105_devcount; |
192 | ||
a611d0ca IL |
193 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
194 | ||
d8300df9 | 195 | struct dm1105_board { |
0017505d IL |
196 | char *name; |
197 | struct { | |
198 | u32 mask, off, v13, v18; | |
199 | } lnb; | |
200 | u32 gpio_scl, gpio_sda; | |
d8300df9 IL |
201 | }; |
202 | ||
203 | struct dm1105_subid { | |
204 | u16 subvendor; | |
205 | u16 subdevice; | |
206 | u32 card; | |
207 | }; | |
208 | ||
209 | static const struct dm1105_board dm1105_boards[] = { | |
210 | [DM1105_BOARD_UNKNOWN] = { | |
211 | .name = "UNKNOWN/GENERIC", | |
0017505d IL |
212 | .lnb = { |
213 | .mask = DM1105_LNB_MASK, | |
214 | .off = DM1105_LNB_OFF, | |
215 | .v13 = DM1105_LNB_13V, | |
216 | .v18 = DM1105_LNB_18V, | |
217 | }, | |
d8300df9 IL |
218 | }, |
219 | [DM1105_BOARD_DVBWORLD_2002] = { | |
220 | .name = "DVBWorld PCI 2002", | |
0017505d IL |
221 | .lnb = { |
222 | .mask = DM1105_LNB_MASK, | |
223 | .off = DM1105_LNB_OFF, | |
224 | .v13 = DM1105_LNB_13V, | |
225 | .v18 = DM1105_LNB_18V, | |
226 | }, | |
d8300df9 IL |
227 | }, |
228 | [DM1105_BOARD_DVBWORLD_2004] = { | |
229 | .name = "DVBWorld PCI 2004", | |
0017505d IL |
230 | .lnb = { |
231 | .mask = DM1105_LNB_MASK, | |
232 | .off = DM1105_LNB_OFF, | |
233 | .v13 = DM1105_LNB_13V, | |
234 | .v18 = DM1105_LNB_18V, | |
235 | }, | |
d8300df9 IL |
236 | }, |
237 | [DM1105_BOARD_AXESS_DM05] = { | |
238 | .name = "Axess/EasyTv DM05", | |
0017505d IL |
239 | .lnb = { |
240 | .mask = DM05_LNB_MASK, | |
241 | .off = DM05_LNB_OFF, | |
242 | .v13 = DM05_LNB_13V, | |
243 | .v18 = DM05_LNB_18V, | |
244 | }, | |
245 | }, | |
246 | [DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = { | |
247 | .name = "Unbranded DM1105 with i2c on GPIOs", | |
248 | .lnb = { | |
249 | .mask = UNBR_LNB_MASK, | |
250 | .off = UNBR_LNB_OFF, | |
251 | .v13 = UNBR_LNB_13V, | |
252 | .v18 = UNBR_LNB_18V, | |
253 | }, | |
254 | .gpio_scl = GPIO14, | |
255 | .gpio_sda = GPIO13, | |
d8300df9 IL |
256 | }, |
257 | }; | |
258 | ||
259 | static const struct dm1105_subid dm1105_subids[] = { | |
260 | { | |
261 | .subvendor = 0x0000, | |
262 | .subdevice = 0x2002, | |
263 | .card = DM1105_BOARD_DVBWORLD_2002, | |
264 | }, { | |
265 | .subvendor = 0x0001, | |
266 | .subdevice = 0x2002, | |
267 | .card = DM1105_BOARD_DVBWORLD_2002, | |
268 | }, { | |
269 | .subvendor = 0x0000, | |
270 | .subdevice = 0x2004, | |
271 | .card = DM1105_BOARD_DVBWORLD_2004, | |
272 | }, { | |
273 | .subvendor = 0x0001, | |
274 | .subdevice = 0x2004, | |
275 | .card = DM1105_BOARD_DVBWORLD_2004, | |
276 | }, { | |
277 | .subvendor = 0x195d, | |
278 | .subdevice = 0x1105, | |
279 | .card = DM1105_BOARD_AXESS_DM05, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static void dm1105_card_list(struct pci_dev *pci) | |
284 | { | |
285 | int i; | |
286 | ||
287 | if (0 == pci->subsystem_vendor && | |
288 | 0 == pci->subsystem_device) { | |
289 | printk(KERN_ERR | |
290 | "dm1105: Your board has no valid PCI Subsystem ID\n" | |
291 | "dm1105: and thus can't be autodetected\n" | |
292 | "dm1105: Please pass card=<n> insmod option to\n" | |
293 | "dm1105: workaround that. Redirect complaints to\n" | |
294 | "dm1105: the vendor of the TV card. Best regards,\n" | |
295 | "dm1105: -- tux\n"); | |
296 | } else { | |
297 | printk(KERN_ERR | |
298 | "dm1105: Your board isn't known (yet) to the driver.\n" | |
299 | "dm1105: You can try to pick one of the existing\n" | |
300 | "dm1105: card configs via card=<n> insmod option.\n" | |
301 | "dm1105: Updating to the latest version might help\n" | |
302 | "dm1105: as well.\n"); | |
303 | } | |
0e8aebb5 | 304 | printk(KERN_ERR "Here is a list of valid choices for the card=<n> insmod option:\n"); |
d8300df9 IL |
305 | for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++) |
306 | printk(KERN_ERR "dm1105: card=%d -> %s\n", | |
307 | i, dm1105_boards[i].name); | |
308 | } | |
309 | ||
a611d0ca IL |
310 | /* infrared remote control */ |
311 | struct infrared { | |
d8b4b582 | 312 | struct rc_dev *dev; |
a611d0ca | 313 | char input_phys[32]; |
b72857dd | 314 | struct work_struct work; |
a611d0ca IL |
315 | u32 ir_command; |
316 | }; | |
317 | ||
34d2f9bf | 318 | struct dm1105_dev { |
a611d0ca IL |
319 | /* pci */ |
320 | struct pci_dev *pdev; | |
321 | u8 __iomem *io_mem; | |
322 | ||
323 | /* ir */ | |
324 | struct infrared ir; | |
325 | ||
326 | /* dvb */ | |
327 | struct dmx_frontend hw_frontend; | |
328 | struct dmx_frontend mem_frontend; | |
329 | struct dmxdev dmxdev; | |
330 | struct dvb_adapter dvb_adapter; | |
331 | struct dvb_demux demux; | |
332 | struct dvb_frontend *fe; | |
333 | struct dvb_net dvbnet; | |
334 | unsigned int full_ts_users; | |
d8300df9 IL |
335 | unsigned int boardnr; |
336 | int nr; | |
a611d0ca IL |
337 | |
338 | /* i2c */ | |
339 | struct i2c_adapter i2c_adap; | |
0017505d IL |
340 | struct i2c_adapter i2c_bb_adap; |
341 | struct i2c_algo_bit_data i2c_bit; | |
a611d0ca | 342 | |
d1498ffc IL |
343 | /* irq */ |
344 | struct work_struct work; | |
519a4bdc IL |
345 | struct workqueue_struct *wq; |
346 | char wqn[16]; | |
d1498ffc | 347 | |
a611d0ca IL |
348 | /* dma */ |
349 | dma_addr_t dma_addr; | |
350 | unsigned char *ts_buf; | |
351 | u32 wrp; | |
d1498ffc | 352 | u32 nextwrp; |
a611d0ca IL |
353 | u32 buffer_size; |
354 | unsigned int PacketErrorCount; | |
355 | unsigned int dmarst; | |
356 | spinlock_t lock; | |
a611d0ca IL |
357 | }; |
358 | ||
34d2f9bf | 359 | #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg])) |
a611d0ca | 360 | |
5eb3291f IL |
361 | #define dm_readb(reg) inb(dm_io_mem(reg)) |
362 | #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg))) | |
363 | ||
364 | #define dm_readw(reg) inw(dm_io_mem(reg)) | |
365 | #define dm_writew(reg, value) outw((value), (dm_io_mem(reg))) | |
366 | ||
367 | #define dm_readl(reg) inl(dm_io_mem(reg)) | |
368 | #define dm_writel(reg, value) outl((value), (dm_io_mem(reg))) | |
369 | ||
370 | #define dm_andorl(reg, mask, value) \ | |
371 | outl((inl(dm_io_mem(reg)) & ~(mask)) |\ | |
372 | ((value) & (mask)), (dm_io_mem(reg))) | |
373 | ||
374 | #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit)) | |
375 | #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0) | |
376 | ||
0017505d IL |
377 | /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines, |
378 | so we can use only 3 GPIO's from GPIO15 to GPIO17. | |
379 | Here I don't check whether HOST is enebled as it is not implemented yet. | |
380 | */ | |
381 | static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask) | |
382 | { | |
383 | if (mask & 0xfffc0000) | |
384 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
385 | ||
386 | if (mask & 0x0003ffff) | |
387 | dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff); | |
388 | ||
389 | } | |
390 | ||
391 | static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask) | |
392 | { | |
393 | if (mask & 0xfffc0000) | |
394 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
395 | ||
396 | if (mask & 0x0003ffff) | |
397 | dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff); | |
398 | ||
399 | } | |
400 | ||
401 | static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val) | |
402 | { | |
403 | if (mask & 0xfffc0000) | |
404 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
405 | ||
406 | if (mask & 0x0003ffff) | |
407 | dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val); | |
408 | ||
409 | } | |
410 | ||
411 | static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask) | |
412 | { | |
413 | if (mask & 0xfffc0000) | |
414 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
415 | ||
416 | if (mask & 0x0003ffff) | |
417 | return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff; | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput) | |
423 | { | |
424 | if (mask & 0xfffc0000) | |
425 | printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__); | |
426 | ||
427 | if ((mask & 0x0003ffff) && asoutput) | |
428 | dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff); | |
429 | else if ((mask & 0x0003ffff) && !asoutput) | |
430 | dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff); | |
431 | ||
432 | } | |
433 | ||
434 | static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state) | |
435 | { | |
436 | if (state) | |
437 | dm1105_gpio_enable(dev, line, 0); | |
438 | else { | |
439 | dm1105_gpio_enable(dev, line, 1); | |
440 | dm1105_gpio_clear(dev, line); | |
441 | } | |
442 | } | |
443 | ||
444 | static void dm1105_setsda(void *data, int state) | |
445 | { | |
446 | struct dm1105_dev *dev = data; | |
447 | ||
448 | dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state); | |
449 | } | |
450 | ||
451 | static void dm1105_setscl(void *data, int state) | |
452 | { | |
453 | struct dm1105_dev *dev = data; | |
454 | ||
455 | dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state); | |
456 | } | |
457 | ||
458 | static int dm1105_getsda(void *data) | |
459 | { | |
460 | struct dm1105_dev *dev = data; | |
461 | ||
462 | return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda) | |
463 | ? 1 : 0; | |
464 | } | |
465 | ||
466 | static int dm1105_getscl(void *data) | |
467 | { | |
468 | struct dm1105_dev *dev = data; | |
469 | ||
470 | return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl) | |
471 | ? 1 : 0; | |
472 | } | |
473 | ||
a611d0ca IL |
474 | static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap, |
475 | struct i2c_msg *msgs, int num) | |
476 | { | |
34d2f9bf | 477 | struct dm1105_dev *dev ; |
a611d0ca IL |
478 | |
479 | int addr, rc, i, j, k, len, byte, data; | |
480 | u8 status; | |
481 | ||
34d2f9bf | 482 | dev = i2c_adap->algo_data; |
a611d0ca | 483 | for (i = 0; i < num; i++) { |
5eb3291f | 484 | dm_writeb(DM1105_I2CCTR, 0x00); |
a611d0ca IL |
485 | if (msgs[i].flags & I2C_M_RD) { |
486 | /* read bytes */ | |
487 | addr = msgs[i].addr << 1; | |
488 | addr |= 1; | |
5eb3291f | 489 | dm_writeb(DM1105_I2CDAT, addr); |
a611d0ca | 490 | for (byte = 0; byte < msgs[i].len; byte++) |
5eb3291f | 491 | dm_writeb(DM1105_I2CDAT + byte + 1, 0); |
a611d0ca | 492 | |
5eb3291f | 493 | dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len); |
a611d0ca IL |
494 | for (j = 0; j < 55; j++) { |
495 | mdelay(10); | |
5eb3291f | 496 | status = dm_readb(DM1105_I2CSTS); |
a611d0ca IL |
497 | if ((status & 0xc0) == 0x40) |
498 | break; | |
499 | } | |
500 | if (j >= 55) | |
501 | return -1; | |
502 | ||
503 | for (byte = 0; byte < msgs[i].len; byte++) { | |
5eb3291f | 504 | rc = dm_readb(DM1105_I2CDAT + byte + 1); |
a611d0ca IL |
505 | if (rc < 0) |
506 | goto err; | |
507 | msgs[i].buf[byte] = rc; | |
508 | } | |
ed7c847a | 509 | } else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) { |
16790554 | 510 | /* prepared for cx24116 firmware */ |
ed7c847a IL |
511 | /* Write in small blocks */ |
512 | len = msgs[i].len - 1; | |
513 | k = 1; | |
514 | do { | |
5eb3291f IL |
515 | dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1); |
516 | dm_writeb(DM1105_I2CDAT + 1, 0xf7); | |
ed7c847a IL |
517 | for (byte = 0; byte < (len > 48 ? 48 : len); byte++) { |
518 | data = msgs[i].buf[k + byte]; | |
5eb3291f | 519 | dm_writeb(DM1105_I2CDAT + byte + 2, data); |
a611d0ca | 520 | } |
5eb3291f | 521 | dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len)); |
a611d0ca IL |
522 | for (j = 0; j < 25; j++) { |
523 | mdelay(10); | |
5eb3291f | 524 | status = dm_readb(DM1105_I2CSTS); |
a611d0ca IL |
525 | if ((status & 0xc0) == 0x40) |
526 | break; | |
527 | } | |
528 | ||
529 | if (j >= 25) | |
530 | return -1; | |
ed7c847a IL |
531 | |
532 | k += 48; | |
533 | len -= 48; | |
534 | } while (len > 0); | |
535 | } else { | |
536 | /* write bytes */ | |
5eb3291f | 537 | dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1); |
ed7c847a IL |
538 | for (byte = 0; byte < msgs[i].len; byte++) { |
539 | data = msgs[i].buf[byte]; | |
5eb3291f | 540 | dm_writeb(DM1105_I2CDAT + byte + 1, data); |
ed7c847a | 541 | } |
5eb3291f | 542 | dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len); |
ed7c847a IL |
543 | for (j = 0; j < 25; j++) { |
544 | mdelay(10); | |
5eb3291f | 545 | status = dm_readb(DM1105_I2CSTS); |
ed7c847a IL |
546 | if ((status & 0xc0) == 0x40) |
547 | break; | |
a611d0ca | 548 | } |
ed7c847a IL |
549 | |
550 | if (j >= 25) | |
551 | return -1; | |
a611d0ca IL |
552 | } |
553 | } | |
554 | return num; | |
555 | err: | |
556 | return rc; | |
557 | } | |
558 | ||
559 | static u32 functionality(struct i2c_adapter *adap) | |
560 | { | |
561 | return I2C_FUNC_I2C; | |
562 | } | |
563 | ||
3c13978e | 564 | static const struct i2c_algorithm dm1105_algo = { |
a611d0ca IL |
565 | .master_xfer = dm1105_i2c_xfer, |
566 | .functionality = functionality, | |
567 | }; | |
568 | ||
34d2f9bf | 569 | static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed) |
a611d0ca | 570 | { |
34d2f9bf | 571 | return container_of(feed->demux, struct dm1105_dev, demux); |
a611d0ca IL |
572 | } |
573 | ||
34d2f9bf | 574 | static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe) |
a611d0ca | 575 | { |
34d2f9bf | 576 | return container_of(fe->dvb, struct dm1105_dev, dvb_adapter); |
a611d0ca IL |
577 | } |
578 | ||
0df289a2 MCC |
579 | static int dm1105_set_voltage(struct dvb_frontend *fe, |
580 | enum fe_sec_voltage voltage) | |
a611d0ca | 581 | { |
34d2f9bf | 582 | struct dm1105_dev *dev = frontend_to_dm1105_dev(fe); |
a611d0ca | 583 | |
0017505d | 584 | dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1); |
519a4bdc | 585 | if (voltage == SEC_VOLTAGE_18) |
0017505d IL |
586 | dm1105_gpio_andor(dev, |
587 | dm1105_boards[dev->boardnr].lnb.mask, | |
588 | dm1105_boards[dev->boardnr].lnb.v18); | |
d8300df9 | 589 | else if (voltage == SEC_VOLTAGE_13) |
0017505d IL |
590 | dm1105_gpio_andor(dev, |
591 | dm1105_boards[dev->boardnr].lnb.mask, | |
592 | dm1105_boards[dev->boardnr].lnb.v13); | |
d8300df9 | 593 | else |
0017505d IL |
594 | dm1105_gpio_andor(dev, |
595 | dm1105_boards[dev->boardnr].lnb.mask, | |
596 | dm1105_boards[dev->boardnr].lnb.off); | |
a611d0ca IL |
597 | |
598 | return 0; | |
599 | } | |
600 | ||
34d2f9bf | 601 | static void dm1105_set_dma_addr(struct dm1105_dev *dev) |
a611d0ca | 602 | { |
888bd5dc | 603 | dm_writel(DM1105_STADR, (__force u32)cpu_to_le32(dev->dma_addr)); |
a611d0ca IL |
604 | } |
605 | ||
4c62e976 | 606 | static int dm1105_dma_map(struct dm1105_dev *dev) |
a611d0ca | 607 | { |
34d2f9bf IL |
608 | dev->ts_buf = pci_alloc_consistent(dev->pdev, |
609 | 6 * DM1105_DMA_BYTES, | |
610 | &dev->dma_addr); | |
a611d0ca | 611 | |
34d2f9bf | 612 | return !dev->ts_buf; |
a611d0ca IL |
613 | } |
614 | ||
34d2f9bf | 615 | static void dm1105_dma_unmap(struct dm1105_dev *dev) |
a611d0ca | 616 | { |
34d2f9bf IL |
617 | pci_free_consistent(dev->pdev, |
618 | 6 * DM1105_DMA_BYTES, | |
619 | dev->ts_buf, | |
620 | dev->dma_addr); | |
a611d0ca IL |
621 | } |
622 | ||
34d2f9bf | 623 | static void dm1105_enable_irqs(struct dm1105_dev *dev) |
a611d0ca | 624 | { |
5eb3291f IL |
625 | dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK); |
626 | dm_writeb(DM1105_CR, 1); | |
a611d0ca IL |
627 | } |
628 | ||
34d2f9bf | 629 | static void dm1105_disable_irqs(struct dm1105_dev *dev) |
a611d0ca | 630 | { |
5eb3291f IL |
631 | dm_writeb(DM1105_INTMAK, INTMAK_IRM); |
632 | dm_writeb(DM1105_CR, 0); | |
a611d0ca IL |
633 | } |
634 | ||
34d2f9bf | 635 | static int dm1105_start_feed(struct dvb_demux_feed *f) |
a611d0ca | 636 | { |
34d2f9bf | 637 | struct dm1105_dev *dev = feed_to_dm1105_dev(f); |
a611d0ca | 638 | |
34d2f9bf IL |
639 | if (dev->full_ts_users++ == 0) |
640 | dm1105_enable_irqs(dev); | |
a611d0ca IL |
641 | |
642 | return 0; | |
643 | } | |
644 | ||
34d2f9bf | 645 | static int dm1105_stop_feed(struct dvb_demux_feed *f) |
a611d0ca | 646 | { |
34d2f9bf | 647 | struct dm1105_dev *dev = feed_to_dm1105_dev(f); |
a611d0ca | 648 | |
34d2f9bf IL |
649 | if (--dev->full_ts_users == 0) |
650 | dm1105_disable_irqs(dev); | |
a611d0ca IL |
651 | |
652 | return 0; | |
653 | } | |
654 | ||
b72857dd IL |
655 | /* ir work handler */ |
656 | static void dm1105_emit_key(struct work_struct *work) | |
a611d0ca | 657 | { |
b72857dd | 658 | struct infrared *ir = container_of(work, struct infrared, work); |
a611d0ca IL |
659 | u32 ircom = ir->ir_command; |
660 | u8 data; | |
a611d0ca | 661 | |
d1498ffc IL |
662 | if (ir_debug) |
663 | printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom); | |
664 | ||
a611d0ca IL |
665 | data = (ircom >> 8) & 0x7f; |
666 | ||
120703f9 | 667 | /* FIXME: UNKNOWN because we don't generate a full NEC scancode (yet?) */ |
6d741bfe | 668 | rc_keydown(ir->dev, RC_PROTO_UNKNOWN, data, 0); |
a611d0ca IL |
669 | } |
670 | ||
d1498ffc IL |
671 | /* work handler */ |
672 | static void dm1105_dmx_buffer(struct work_struct *work) | |
673 | { | |
34d2f9bf | 674 | struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work); |
d1498ffc | 675 | unsigned int nbpackets; |
34d2f9bf IL |
676 | u32 oldwrp = dev->wrp; |
677 | u32 nextwrp = dev->nextwrp; | |
d1498ffc | 678 | |
34d2f9bf IL |
679 | if (!((dev->ts_buf[oldwrp] == 0x47) && |
680 | (dev->ts_buf[oldwrp + 188] == 0x47) && | |
681 | (dev->ts_buf[oldwrp + 188 * 2] == 0x47))) { | |
682 | dev->PacketErrorCount++; | |
d1498ffc | 683 | /* bad packet found */ |
34d2f9bf IL |
684 | if ((dev->PacketErrorCount >= 2) && |
685 | (dev->dmarst == 0)) { | |
5eb3291f | 686 | dm_writeb(DM1105_RST, 1); |
34d2f9bf IL |
687 | dev->wrp = 0; |
688 | dev->PacketErrorCount = 0; | |
689 | dev->dmarst = 0; | |
d1498ffc IL |
690 | return; |
691 | } | |
692 | } | |
693 | ||
694 | if (nextwrp < oldwrp) { | |
34d2f9bf IL |
695 | memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp); |
696 | nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188; | |
d1498ffc IL |
697 | } else |
698 | nbpackets = (nextwrp - oldwrp) / 188; | |
699 | ||
34d2f9bf IL |
700 | dev->wrp = nextwrp; |
701 | dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets); | |
d1498ffc IL |
702 | } |
703 | ||
34d2f9bf | 704 | static irqreturn_t dm1105_irq(int irq, void *dev_id) |
a611d0ca | 705 | { |
34d2f9bf | 706 | struct dm1105_dev *dev = dev_id; |
a611d0ca IL |
707 | |
708 | /* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */ | |
5eb3291f IL |
709 | unsigned int intsts = dm_readb(DM1105_INTSTS); |
710 | dm_writeb(DM1105_INTSTS, intsts); | |
a611d0ca IL |
711 | |
712 | switch (intsts) { | |
713 | case INTSTS_TSIRQ: | |
714 | case (INTSTS_TSIRQ | INTSTS_IR): | |
5eb3291f | 715 | dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR); |
34d2f9bf | 716 | queue_work(dev->wq, &dev->work); |
a611d0ca IL |
717 | break; |
718 | case INTSTS_IR: | |
5eb3291f | 719 | dev->ir.ir_command = dm_readl(DM1105_IRCODE); |
34d2f9bf | 720 | schedule_work(&dev->ir.work); |
a611d0ca IL |
721 | break; |
722 | } | |
a611d0ca | 723 | |
d1498ffc | 724 | return IRQ_HANDLED; |
a611d0ca IL |
725 | } |
726 | ||
4c62e976 | 727 | static int dm1105_ir_init(struct dm1105_dev *dm1105) |
a611d0ca | 728 | { |
d8b4b582 | 729 | struct rc_dev *dev; |
b72857dd | 730 | int err = -ENOMEM; |
a611d0ca | 731 | |
0f7499fd | 732 | dev = rc_allocate_device(RC_DRIVER_SCANCODE); |
d8b4b582 | 733 | if (!dev) |
a611d0ca IL |
734 | return -ENOMEM; |
735 | ||
a611d0ca IL |
736 | snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys), |
737 | "pci-%s/ir0", pci_name(dm1105->pdev)); | |
738 | ||
d8b4b582 DH |
739 | dev->driver_name = MODULE_NAME; |
740 | dev->map_name = RC_MAP_DM1105_NEC; | |
518f4b26 | 741 | dev->device_name = "DVB on-card IR receiver"; |
d8b4b582 DH |
742 | dev->input_phys = dm1105->ir.input_phys; |
743 | dev->input_id.bustype = BUS_PCI; | |
744 | dev->input_id.version = 1; | |
a611d0ca | 745 | if (dm1105->pdev->subsystem_vendor) { |
d8b4b582 DH |
746 | dev->input_id.vendor = dm1105->pdev->subsystem_vendor; |
747 | dev->input_id.product = dm1105->pdev->subsystem_device; | |
a611d0ca | 748 | } else { |
d8b4b582 DH |
749 | dev->input_id.vendor = dm1105->pdev->vendor; |
750 | dev->input_id.product = dm1105->pdev->device; | |
a611d0ca | 751 | } |
d8b4b582 | 752 | dev->dev.parent = &dm1105->pdev->dev; |
b72857dd IL |
753 | |
754 | INIT_WORK(&dm1105->ir.work, dm1105_emit_key); | |
755 | ||
d8b4b582 | 756 | err = rc_register_device(dev); |
15100d89 | 757 | if (err < 0) { |
d8b4b582 | 758 | rc_free_device(dev); |
15100d89 DH |
759 | return err; |
760 | } | |
a611d0ca | 761 | |
d8b4b582 | 762 | dm1105->ir.dev = dev; |
15100d89 | 763 | return 0; |
a611d0ca IL |
764 | } |
765 | ||
4c62e976 | 766 | static void dm1105_ir_exit(struct dm1105_dev *dm1105) |
a611d0ca | 767 | { |
d8b4b582 | 768 | rc_unregister_device(dm1105->ir.dev); |
a611d0ca IL |
769 | } |
770 | ||
4c62e976 | 771 | static int dm1105_hw_init(struct dm1105_dev *dev) |
a611d0ca | 772 | { |
34d2f9bf | 773 | dm1105_disable_irqs(dev); |
a611d0ca | 774 | |
5eb3291f | 775 | dm_writeb(DM1105_HOST_CTR, 0); |
a611d0ca IL |
776 | |
777 | /*DATALEN 188,*/ | |
5eb3291f | 778 | dm_writeb(DM1105_DTALENTH, 188); |
a611d0ca | 779 | /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/ |
5eb3291f | 780 | dm_writew(DM1105_TSCTR, 0xc10a); |
a611d0ca IL |
781 | |
782 | /* map DMA and set address */ | |
34d2f9bf IL |
783 | dm1105_dma_map(dev); |
784 | dm1105_set_dma_addr(dev); | |
a611d0ca | 785 | /* big buffer */ |
5eb3291f IL |
786 | dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES); |
787 | dm_writeb(DM1105_INTCNT, 47); | |
a611d0ca IL |
788 | |
789 | /* IR NEC mode enable */ | |
5eb3291f IL |
790 | dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK)); |
791 | dm_writeb(DM1105_IRMODE, 0); | |
792 | dm_writew(DM1105_SYSTEMCODE, 0); | |
a611d0ca IL |
793 | |
794 | return 0; | |
795 | } | |
796 | ||
34d2f9bf | 797 | static void dm1105_hw_exit(struct dm1105_dev *dev) |
a611d0ca | 798 | { |
34d2f9bf | 799 | dm1105_disable_irqs(dev); |
a611d0ca IL |
800 | |
801 | /* IR disable */ | |
5eb3291f IL |
802 | dm_writeb(DM1105_IRCTR, 0); |
803 | dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK); | |
a611d0ca | 804 | |
34d2f9bf | 805 | dm1105_dma_unmap(dev); |
a611d0ca | 806 | } |
e4aab64c | 807 | |
650497f1 | 808 | static const struct stv0299_config sharp_z0194a_config = { |
d4305c68 IL |
809 | .demod_address = 0x68, |
810 | .inittab = sharp_z0194a_inittab, | |
811 | .mclk = 88000000UL, | |
812 | .invert = 1, | |
813 | .skip_reinit = 0, | |
814 | .lock_output = STV0299_LOCKOUTPUT_1, | |
815 | .volt13_op0_op1 = STV0299_VOLT13_OP1, | |
816 | .min_delay_ms = 100, | |
817 | .set_symbol_rate = sharp_z0194a_set_symbol_rate, | |
818 | }; | |
819 | ||
a611d0ca IL |
820 | static struct stv0288_config earda_config = { |
821 | .demod_address = 0x68, | |
822 | .min_delay_ms = 100, | |
823 | }; | |
824 | ||
825 | static struct si21xx_config serit_config = { | |
826 | .demod_address = 0x68, | |
827 | .min_delay_ms = 100, | |
828 | ||
829 | }; | |
830 | ||
831 | static struct cx24116_config serit_sp2633_config = { | |
832 | .demod_address = 0x55, | |
833 | }; | |
a611d0ca | 834 | |
b4a0e816 IL |
835 | static struct ds3000_config dvbworld_ds3000_config = { |
836 | .demod_address = 0x68, | |
837 | }; | |
838 | ||
73f0af44 KD |
839 | static struct ts2020_config dvbworld_ts2020_config = { |
840 | .tuner_address = 0x60, | |
b858c331 | 841 | .clk_out_div = 1, |
73f0af44 KD |
842 | }; |
843 | ||
4c62e976 | 844 | static int frontend_init(struct dm1105_dev *dev) |
a611d0ca IL |
845 | { |
846 | int ret; | |
847 | ||
34d2f9bf | 848 | switch (dev->boardnr) { |
0017505d IL |
849 | case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO: |
850 | dm1105_gpio_enable(dev, GPIO15, 1); | |
851 | dm1105_gpio_clear(dev, GPIO15); | |
852 | msleep(100); | |
853 | dm1105_gpio_set(dev, GPIO15); | |
854 | msleep(200); | |
855 | dev->fe = dvb_attach( | |
856 | stv0299_attach, &sharp_z0194a_config, | |
857 | &dev->i2c_bb_adap); | |
858 | if (dev->fe) { | |
859 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
860 | dvb_attach(dvb_pll_attach, dev->fe, 0x60, | |
861 | &dev->i2c_bb_adap, DVB_PLL_OPERA1); | |
862 | break; | |
863 | } | |
864 | ||
865 | dev->fe = dvb_attach( | |
866 | stv0288_attach, &earda_config, | |
867 | &dev->i2c_bb_adap); | |
868 | if (dev->fe) { | |
869 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
870 | dvb_attach(stb6000_attach, dev->fe, 0x61, | |
871 | &dev->i2c_bb_adap); | |
872 | break; | |
873 | } | |
874 | ||
875 | dev->fe = dvb_attach( | |
876 | si21xx_attach, &serit_config, | |
877 | &dev->i2c_bb_adap); | |
878 | if (dev->fe) | |
879 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
880 | break; | |
d8300df9 | 881 | case DM1105_BOARD_DVBWORLD_2004: |
34d2f9bf | 882 | dev->fe = dvb_attach( |
519a4bdc | 883 | cx24116_attach, &serit_sp2633_config, |
34d2f9bf IL |
884 | &dev->i2c_adap); |
885 | if (dev->fe) { | |
886 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
b4a0e816 IL |
887 | break; |
888 | } | |
889 | ||
34d2f9bf | 890 | dev->fe = dvb_attach( |
b4a0e816 | 891 | ds3000_attach, &dvbworld_ds3000_config, |
34d2f9bf | 892 | &dev->i2c_adap); |
73f0af44 KD |
893 | if (dev->fe) { |
894 | dvb_attach(ts2020_attach, dev->fe, | |
895 | &dvbworld_ts2020_config, &dev->i2c_adap); | |
34d2f9bf | 896 | dev->fe->ops.set_voltage = dm1105_set_voltage; |
73f0af44 | 897 | } |
a611d0ca | 898 | |
519a4bdc | 899 | break; |
d8300df9 IL |
900 | case DM1105_BOARD_DVBWORLD_2002: |
901 | case DM1105_BOARD_AXESS_DM05: | |
519a4bdc | 902 | default: |
34d2f9bf | 903 | dev->fe = dvb_attach( |
519a4bdc | 904 | stv0299_attach, &sharp_z0194a_config, |
34d2f9bf IL |
905 | &dev->i2c_adap); |
906 | if (dev->fe) { | |
907 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
908 | dvb_attach(dvb_pll_attach, dev->fe, 0x60, | |
909 | &dev->i2c_adap, DVB_PLL_OPERA1); | |
519a4bdc | 910 | break; |
a611d0ca | 911 | } |
e4aab64c | 912 | |
34d2f9bf | 913 | dev->fe = dvb_attach( |
519a4bdc | 914 | stv0288_attach, &earda_config, |
34d2f9bf IL |
915 | &dev->i2c_adap); |
916 | if (dev->fe) { | |
917 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
918 | dvb_attach(stb6000_attach, dev->fe, 0x61, | |
919 | &dev->i2c_adap); | |
519a4bdc | 920 | break; |
a611d0ca | 921 | } |
e4aab64c | 922 | |
34d2f9bf | 923 | dev->fe = dvb_attach( |
519a4bdc | 924 | si21xx_attach, &serit_config, |
34d2f9bf IL |
925 | &dev->i2c_adap); |
926 | if (dev->fe) | |
927 | dev->fe->ops.set_voltage = dm1105_set_voltage; | |
519a4bdc | 928 | |
a611d0ca IL |
929 | } |
930 | ||
34d2f9bf IL |
931 | if (!dev->fe) { |
932 | dev_err(&dev->pdev->dev, "could not attach frontend\n"); | |
a611d0ca IL |
933 | return -ENODEV; |
934 | } | |
935 | ||
34d2f9bf | 936 | ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe); |
a611d0ca | 937 | if (ret < 0) { |
34d2f9bf IL |
938 | if (dev->fe->ops.release) |
939 | dev->fe->ops.release(dev->fe); | |
940 | dev->fe = NULL; | |
a611d0ca IL |
941 | return ret; |
942 | } | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
4c62e976 | 947 | static void dm1105_read_mac(struct dm1105_dev *dev, u8 *mac) |
a611d0ca IL |
948 | { |
949 | static u8 command[1] = { 0x28 }; | |
950 | ||
951 | struct i2c_msg msg[] = { | |
519a4bdc IL |
952 | { |
953 | .addr = IIC_24C01_addr >> 1, | |
954 | .flags = 0, | |
955 | .buf = command, | |
956 | .len = 1 | |
957 | }, { | |
958 | .addr = IIC_24C01_addr >> 1, | |
959 | .flags = I2C_M_RD, | |
960 | .buf = mac, | |
961 | .len = 6 | |
962 | }, | |
a611d0ca IL |
963 | }; |
964 | ||
34d2f9bf IL |
965 | dm1105_i2c_xfer(&dev->i2c_adap, msg , 2); |
966 | dev_info(&dev->pdev->dev, "MAC %pM\n", mac); | |
a611d0ca IL |
967 | } |
968 | ||
4c62e976 | 969 | static int dm1105_probe(struct pci_dev *pdev, |
a611d0ca IL |
970 | const struct pci_device_id *ent) |
971 | { | |
34d2f9bf | 972 | struct dm1105_dev *dev; |
a611d0ca IL |
973 | struct dvb_adapter *dvb_adapter; |
974 | struct dvb_demux *dvbdemux; | |
975 | struct dmx_demux *dmx; | |
976 | int ret = -ENOMEM; | |
d8300df9 | 977 | int i; |
a611d0ca | 978 | |
65b40a98 AV |
979 | if (dm1105_devcount >= ARRAY_SIZE(card)) |
980 | return -ENODEV; | |
981 | ||
34d2f9bf IL |
982 | dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL); |
983 | if (!dev) | |
d1498ffc | 984 | return -ENOMEM; |
a611d0ca | 985 | |
d8300df9 | 986 | /* board config */ |
34d2f9bf IL |
987 | dev->nr = dm1105_devcount; |
988 | dev->boardnr = UNSET; | |
989 | if (card[dev->nr] < ARRAY_SIZE(dm1105_boards)) | |
990 | dev->boardnr = card[dev->nr]; | |
991 | for (i = 0; UNSET == dev->boardnr && | |
d8300df9 IL |
992 | i < ARRAY_SIZE(dm1105_subids); i++) |
993 | if (pdev->subsystem_vendor == | |
994 | dm1105_subids[i].subvendor && | |
995 | pdev->subsystem_device == | |
996 | dm1105_subids[i].subdevice) | |
34d2f9bf | 997 | dev->boardnr = dm1105_subids[i].card; |
d8300df9 | 998 | |
34d2f9bf IL |
999 | if (UNSET == dev->boardnr) { |
1000 | dev->boardnr = DM1105_BOARD_UNKNOWN; | |
d8300df9 IL |
1001 | dm1105_card_list(pdev); |
1002 | } | |
1003 | ||
1004 | dm1105_devcount++; | |
34d2f9bf IL |
1005 | dev->pdev = pdev; |
1006 | dev->buffer_size = 5 * DM1105_DMA_BYTES; | |
1007 | dev->PacketErrorCount = 0; | |
1008 | dev->dmarst = 0; | |
a611d0ca IL |
1009 | |
1010 | ret = pci_enable_device(pdev); | |
1011 | if (ret < 0) | |
1012 | goto err_kfree; | |
1013 | ||
284901a9 | 1014 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
a611d0ca IL |
1015 | if (ret < 0) |
1016 | goto err_pci_disable_device; | |
1017 | ||
1018 | pci_set_master(pdev); | |
1019 | ||
1020 | ret = pci_request_regions(pdev, DRIVER_NAME); | |
1021 | if (ret < 0) | |
1022 | goto err_pci_disable_device; | |
1023 | ||
34d2f9bf IL |
1024 | dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); |
1025 | if (!dev->io_mem) { | |
a611d0ca IL |
1026 | ret = -EIO; |
1027 | goto err_pci_release_regions; | |
1028 | } | |
1029 | ||
34d2f9bf IL |
1030 | spin_lock_init(&dev->lock); |
1031 | pci_set_drvdata(pdev, dev); | |
a611d0ca | 1032 | |
34d2f9bf | 1033 | ret = dm1105_hw_init(dev); |
a611d0ca | 1034 | if (ret < 0) |
d1498ffc | 1035 | goto err_pci_iounmap; |
a611d0ca IL |
1036 | |
1037 | /* i2c */ | |
34d2f9bf | 1038 | i2c_set_adapdata(&dev->i2c_adap, dev); |
cc1e6315 | 1039 | strscpy(dev->i2c_adap.name, DRIVER_NAME, sizeof(dev->i2c_adap.name)); |
34d2f9bf | 1040 | dev->i2c_adap.owner = THIS_MODULE; |
34d2f9bf IL |
1041 | dev->i2c_adap.dev.parent = &pdev->dev; |
1042 | dev->i2c_adap.algo = &dm1105_algo; | |
1043 | dev->i2c_adap.algo_data = dev; | |
1044 | ret = i2c_add_adapter(&dev->i2c_adap); | |
a611d0ca IL |
1045 | |
1046 | if (ret < 0) | |
34d2f9bf | 1047 | goto err_dm1105_hw_exit; |
a611d0ca | 1048 | |
0017505d | 1049 | i2c_set_adapdata(&dev->i2c_bb_adap, dev); |
cc1e6315 MCC |
1050 | strscpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME, |
1051 | sizeof(dev->i2c_bb_adap.name)); | |
0017505d IL |
1052 | dev->i2c_bb_adap.owner = THIS_MODULE; |
1053 | dev->i2c_bb_adap.dev.parent = &pdev->dev; | |
1054 | dev->i2c_bb_adap.algo_data = &dev->i2c_bit; | |
1055 | dev->i2c_bit.data = dev; | |
1056 | dev->i2c_bit.setsda = dm1105_setsda; | |
1057 | dev->i2c_bit.setscl = dm1105_setscl; | |
1058 | dev->i2c_bit.getsda = dm1105_getsda; | |
1059 | dev->i2c_bit.getscl = dm1105_getscl; | |
1060 | dev->i2c_bit.udelay = 10; | |
1061 | dev->i2c_bit.timeout = 10; | |
1062 | ||
1063 | /* Raise SCL and SDA */ | |
1064 | dm1105_setsda(dev, 1); | |
1065 | dm1105_setscl(dev, 1); | |
1066 | ||
1067 | ret = i2c_bit_add_bus(&dev->i2c_bb_adap); | |
1068 | if (ret < 0) | |
1069 | goto err_i2c_del_adapter; | |
1070 | ||
a611d0ca | 1071 | /* dvb */ |
34d2f9bf | 1072 | ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME, |
a611d0ca IL |
1073 | THIS_MODULE, &pdev->dev, adapter_nr); |
1074 | if (ret < 0) | |
0017505d | 1075 | goto err_i2c_del_adapters; |
a611d0ca | 1076 | |
34d2f9bf | 1077 | dvb_adapter = &dev->dvb_adapter; |
a611d0ca | 1078 | |
34d2f9bf | 1079 | dm1105_read_mac(dev, dvb_adapter->proposed_mac); |
a611d0ca | 1080 | |
34d2f9bf | 1081 | dvbdemux = &dev->demux; |
a611d0ca IL |
1082 | dvbdemux->filternum = 256; |
1083 | dvbdemux->feednum = 256; | |
34d2f9bf IL |
1084 | dvbdemux->start_feed = dm1105_start_feed; |
1085 | dvbdemux->stop_feed = dm1105_stop_feed; | |
a611d0ca IL |
1086 | dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | |
1087 | DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING); | |
1088 | ret = dvb_dmx_init(dvbdemux); | |
1089 | if (ret < 0) | |
1090 | goto err_dvb_unregister_adapter; | |
1091 | ||
1092 | dmx = &dvbdemux->dmx; | |
34d2f9bf IL |
1093 | dev->dmxdev.filternum = 256; |
1094 | dev->dmxdev.demux = dmx; | |
1095 | dev->dmxdev.capabilities = 0; | |
a611d0ca | 1096 | |
34d2f9bf | 1097 | ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter); |
a611d0ca IL |
1098 | if (ret < 0) |
1099 | goto err_dvb_dmx_release; | |
1100 | ||
34d2f9bf | 1101 | dev->hw_frontend.source = DMX_FRONTEND_0; |
a611d0ca | 1102 | |
34d2f9bf | 1103 | ret = dmx->add_frontend(dmx, &dev->hw_frontend); |
a611d0ca IL |
1104 | if (ret < 0) |
1105 | goto err_dvb_dmxdev_release; | |
1106 | ||
34d2f9bf | 1107 | dev->mem_frontend.source = DMX_MEMORY_FE; |
a611d0ca | 1108 | |
34d2f9bf | 1109 | ret = dmx->add_frontend(dmx, &dev->mem_frontend); |
a611d0ca IL |
1110 | if (ret < 0) |
1111 | goto err_remove_hw_frontend; | |
1112 | ||
34d2f9bf | 1113 | ret = dmx->connect_frontend(dmx, &dev->hw_frontend); |
a611d0ca IL |
1114 | if (ret < 0) |
1115 | goto err_remove_mem_frontend; | |
1116 | ||
5584c641 JN |
1117 | ret = dvb_net_init(dvb_adapter, &dev->dvbnet, dmx); |
1118 | if (ret < 0) | |
1119 | goto err_disconnect_frontend; | |
1120 | ||
34d2f9bf | 1121 | ret = frontend_init(dev); |
a611d0ca | 1122 | if (ret < 0) |
e9966341 | 1123 | goto err_dvb_net; |
a611d0ca | 1124 | |
34d2f9bf | 1125 | dm1105_ir_init(dev); |
d1498ffc | 1126 | |
34d2f9bf IL |
1127 | INIT_WORK(&dev->work, dm1105_dmx_buffer); |
1128 | sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num); | |
1129 | dev->wq = create_singlethread_workqueue(dev->wqn); | |
95d08126 PST |
1130 | if (!dev->wq) { |
1131 | ret = -ENOMEM; | |
519a4bdc | 1132 | goto err_dvb_net; |
95d08126 | 1133 | } |
d1498ffc | 1134 | |
34d2f9bf IL |
1135 | ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED, |
1136 | DRIVER_NAME, dev); | |
d1498ffc | 1137 | if (ret < 0) |
519a4bdc | 1138 | goto err_workqueue; |
d1498ffc IL |
1139 | |
1140 | return 0; | |
a611d0ca | 1141 | |
519a4bdc | 1142 | err_workqueue: |
34d2f9bf | 1143 | destroy_workqueue(dev->wq); |
519a4bdc | 1144 | err_dvb_net: |
34d2f9bf | 1145 | dvb_net_release(&dev->dvbnet); |
a611d0ca IL |
1146 | err_disconnect_frontend: |
1147 | dmx->disconnect_frontend(dmx); | |
1148 | err_remove_mem_frontend: | |
34d2f9bf | 1149 | dmx->remove_frontend(dmx, &dev->mem_frontend); |
a611d0ca | 1150 | err_remove_hw_frontend: |
34d2f9bf | 1151 | dmx->remove_frontend(dmx, &dev->hw_frontend); |
a611d0ca | 1152 | err_dvb_dmxdev_release: |
34d2f9bf | 1153 | dvb_dmxdev_release(&dev->dmxdev); |
a611d0ca IL |
1154 | err_dvb_dmx_release: |
1155 | dvb_dmx_release(dvbdemux); | |
1156 | err_dvb_unregister_adapter: | |
1157 | dvb_unregister_adapter(dvb_adapter); | |
0017505d IL |
1158 | err_i2c_del_adapters: |
1159 | i2c_del_adapter(&dev->i2c_bb_adap); | |
a611d0ca | 1160 | err_i2c_del_adapter: |
34d2f9bf IL |
1161 | i2c_del_adapter(&dev->i2c_adap); |
1162 | err_dm1105_hw_exit: | |
1163 | dm1105_hw_exit(dev); | |
a611d0ca | 1164 | err_pci_iounmap: |
34d2f9bf | 1165 | pci_iounmap(pdev, dev->io_mem); |
a611d0ca IL |
1166 | err_pci_release_regions: |
1167 | pci_release_regions(pdev); | |
1168 | err_pci_disable_device: | |
1169 | pci_disable_device(pdev); | |
1170 | err_kfree: | |
34d2f9bf | 1171 | kfree(dev); |
d1498ffc | 1172 | return ret; |
a611d0ca IL |
1173 | } |
1174 | ||
4c62e976 | 1175 | static void dm1105_remove(struct pci_dev *pdev) |
a611d0ca | 1176 | { |
34d2f9bf IL |
1177 | struct dm1105_dev *dev = pci_get_drvdata(pdev); |
1178 | struct dvb_adapter *dvb_adapter = &dev->dvb_adapter; | |
1179 | struct dvb_demux *dvbdemux = &dev->demux; | |
a611d0ca IL |
1180 | struct dmx_demux *dmx = &dvbdemux->dmx; |
1181 | ||
34d2f9bf | 1182 | dm1105_ir_exit(dev); |
a611d0ca | 1183 | dmx->close(dmx); |
34d2f9bf IL |
1184 | dvb_net_release(&dev->dvbnet); |
1185 | if (dev->fe) | |
1186 | dvb_unregister_frontend(dev->fe); | |
a611d0ca IL |
1187 | |
1188 | dmx->disconnect_frontend(dmx); | |
34d2f9bf IL |
1189 | dmx->remove_frontend(dmx, &dev->mem_frontend); |
1190 | dmx->remove_frontend(dmx, &dev->hw_frontend); | |
1191 | dvb_dmxdev_release(&dev->dmxdev); | |
a611d0ca IL |
1192 | dvb_dmx_release(dvbdemux); |
1193 | dvb_unregister_adapter(dvb_adapter); | |
0e48a3e8 | 1194 | i2c_del_adapter(&dev->i2c_adap); |
a611d0ca | 1195 | |
34d2f9bf | 1196 | dm1105_hw_exit(dev); |
34d2f9bf IL |
1197 | free_irq(pdev->irq, dev); |
1198 | pci_iounmap(pdev, dev->io_mem); | |
a611d0ca IL |
1199 | pci_release_regions(pdev); |
1200 | pci_disable_device(pdev); | |
d8300df9 | 1201 | dm1105_devcount--; |
34d2f9bf | 1202 | kfree(dev); |
a611d0ca IL |
1203 | } |
1204 | ||
82c055cd | 1205 | static const struct pci_device_id dm1105_id_table[] = { |
a611d0ca IL |
1206 | { |
1207 | .vendor = PCI_VENDOR_ID_TRIGEM, | |
1208 | .device = PCI_DEVICE_ID_DM1105, | |
1209 | .subvendor = PCI_ANY_ID, | |
d8300df9 | 1210 | .subdevice = PCI_ANY_ID, |
519a4bdc IL |
1211 | }, { |
1212 | .vendor = PCI_VENDOR_ID_AXESS, | |
1213 | .device = PCI_DEVICE_ID_DM05, | |
d8300df9 IL |
1214 | .subvendor = PCI_ANY_ID, |
1215 | .subdevice = PCI_ANY_ID, | |
a611d0ca IL |
1216 | }, { |
1217 | /* empty */ | |
1218 | }, | |
1219 | }; | |
1220 | ||
1221 | MODULE_DEVICE_TABLE(pci, dm1105_id_table); | |
1222 | ||
1223 | static struct pci_driver dm1105_driver = { | |
1224 | .name = DRIVER_NAME, | |
1225 | .id_table = dm1105_id_table, | |
1226 | .probe = dm1105_probe, | |
4c62e976 | 1227 | .remove = dm1105_remove, |
a611d0ca IL |
1228 | }; |
1229 | ||
548006ce | 1230 | module_pci_driver(dm1105_driver); |
a611d0ca IL |
1231 | |
1232 | MODULE_AUTHOR("Igor M. Liplianin <liplianin@me.by>"); | |
1233 | MODULE_DESCRIPTION("SDMC DM1105 DVB driver"); | |
1234 | MODULE_LICENSE("GPL"); |