Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * device driver for Conexant 2388x based TV cards | |
4 | * MPEG Transport Stream (DVB) routines | |
5 | * | |
fc40b261 | 6 | * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au> |
1da177e4 LT |
7 | * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/fs.h> | |
28 | #include <linux/kthread.h> | |
29 | #include <linux/file.h> | |
30 | #include <linux/suspend.h> | |
31 | ||
1da177e4 LT |
32 | #include "cx88.h" |
33 | #include "dvb-pll.h" | |
5e453dc7 | 34 | #include <media/v4l2-common.h> |
41ef7c1e | 35 | |
1f10c7af AQ |
36 | #include "mt352.h" |
37 | #include "mt352_priv.h" | |
ecf854df | 38 | #include "cx88-vp3054-i2c.h" |
1f10c7af AQ |
39 | #include "zl10353.h" |
40 | #include "cx22702.h" | |
41 | #include "or51132.h" | |
42 | #include "lgdt330x.h" | |
60464da8 | 43 | #include "s5h1409.h" |
c21973e8 | 44 | #include "xc4000.h" |
60464da8 | 45 | #include "xc5000.h" |
1f10c7af AQ |
46 | #include "nxt200x.h" |
47 | #include "cx24123.h" | |
cd20ca9f | 48 | #include "isl6421.h" |
0df31f83 | 49 | #include "tuner-simple.h" |
827855d3 | 50 | #include "tda9887.h" |
d893d5dc | 51 | #include "s5h1411.h" |
e4aab64c IL |
52 | #include "stv0299.h" |
53 | #include "z0194a.h" | |
54 | #include "stv0288.h" | |
55 | #include "stb6000.h" | |
5bd1b663 | 56 | #include "cx24116.h" |
b699c271 IL |
57 | #include "stv0900.h" |
58 | #include "stb6100.h" | |
59 | #include "stb6100_proc.h" | |
111ac84a | 60 | #include "mb86a16.h" |
73f0af44 | 61 | #include "ts2020.h" |
0cb73639 | 62 | #include "ds3000.h" |
1da177e4 LT |
63 | |
64 | MODULE_DESCRIPTION("driver for cx2388x based DVB cards"); | |
65 | MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>"); | |
66 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); | |
67 | MODULE_LICENSE("GPL"); | |
1990d50b | 68 | MODULE_VERSION(CX88_VERSION); |
1da177e4 | 69 | |
ff699e6b | 70 | static unsigned int debug; |
1da177e4 LT |
71 | module_param(debug, int, 0644); |
72 | MODULE_PARM_DESC(debug,"enable debug messages [dvb]"); | |
73 | ||
44c6e2a7 AWC |
74 | static unsigned int dvb_buf_tscnt = 32; |
75 | module_param(dvb_buf_tscnt, int, 0644); | |
76 | MODULE_PARM_DESC(dvb_buf_tscnt, "DVB Buffer TS count [dvb]"); | |
77 | ||
78e92006 JG |
78 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
79 | ||
1da177e4 | 80 | #define dprintk(level,fmt, arg...) if (debug >= level) \ |
6c5be74c | 81 | printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg) |
1da177e4 LT |
82 | |
83 | /* ------------------------------------------------------------------ */ | |
84 | ||
0b6b6302 HV |
85 | static int queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, |
86 | unsigned int *num_buffers, unsigned int *num_planes, | |
87 | unsigned int sizes[], void *alloc_ctxs[]) | |
1da177e4 | 88 | { |
0b6b6302 | 89 | struct cx8802_dev *dev = q->drv_priv; |
1da177e4 | 90 | |
0b6b6302 | 91 | *num_planes = 1; |
1da177e4 | 92 | dev->ts_packet_size = 188 * 4; |
44c6e2a7 | 93 | dev->ts_packet_count = dvb_buf_tscnt; |
0b6b6302 | 94 | sizes[0] = dev->ts_packet_size * dev->ts_packet_count; |
165d0043 | 95 | alloc_ctxs[0] = dev->alloc_ctx; |
0b6b6302 | 96 | *num_buffers = dvb_buf_tscnt; |
1da177e4 LT |
97 | return 0; |
98 | } | |
99 | ||
0b6b6302 HV |
100 | static int buffer_prepare(struct vb2_buffer *vb) |
101 | { | |
102 | struct cx8802_dev *dev = vb->vb2_queue->drv_priv; | |
103 | struct cx88_buffer *buf = container_of(vb, struct cx88_buffer, vb); | |
104 | ||
ccd6f1d4 | 105 | return cx8802_buf_prepare(vb->vb2_queue, dev, buf); |
0b6b6302 HV |
106 | } |
107 | ||
108 | static void buffer_finish(struct vb2_buffer *vb) | |
109 | { | |
110 | struct cx8802_dev *dev = vb->vb2_queue->drv_priv; | |
111 | struct cx88_buffer *buf = container_of(vb, struct cx88_buffer, vb); | |
5e7045e3 | 112 | struct cx88_riscmem *risc = &buf->risc; |
0b6b6302 | 113 | |
5e7045e3 HV |
114 | if (risc->cpu) |
115 | pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma); | |
116 | memset(risc, 0, sizeof(*risc)); | |
0b6b6302 HV |
117 | } |
118 | ||
119 | static void buffer_queue(struct vb2_buffer *vb) | |
1da177e4 | 120 | { |
0b6b6302 HV |
121 | struct cx8802_dev *dev = vb->vb2_queue->drv_priv; |
122 | struct cx88_buffer *buf = container_of(vb, struct cx88_buffer, vb); | |
123 | ||
124 | cx8802_buf_queue(dev, buf); | |
1da177e4 LT |
125 | } |
126 | ||
0b6b6302 | 127 | static int start_streaming(struct vb2_queue *q, unsigned int count) |
1da177e4 | 128 | { |
0b6b6302 HV |
129 | struct cx8802_dev *dev = q->drv_priv; |
130 | struct cx88_dmaqueue *dmaq = &dev->mpegq; | |
131 | struct cx88_buffer *buf; | |
132 | ||
133 | buf = list_entry(dmaq->active.next, struct cx88_buffer, list); | |
134 | cx8802_start_dma(dev, dmaq, buf); | |
135 | return 0; | |
1da177e4 LT |
136 | } |
137 | ||
0b6b6302 | 138 | static void stop_streaming(struct vb2_queue *q) |
1da177e4 | 139 | { |
0b6b6302 HV |
140 | struct cx8802_dev *dev = q->drv_priv; |
141 | struct cx88_dmaqueue *dmaq = &dev->mpegq; | |
142 | unsigned long flags; | |
143 | ||
144 | cx8802_cancel_buffers(dev); | |
145 | ||
146 | spin_lock_irqsave(&dev->slock, flags); | |
147 | while (!list_empty(&dmaq->active)) { | |
148 | struct cx88_buffer *buf = list_entry(dmaq->active.next, | |
149 | struct cx88_buffer, list); | |
150 | ||
151 | list_del(&buf->list); | |
152 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); | |
153 | } | |
154 | spin_unlock_irqrestore(&dev->slock, flags); | |
1da177e4 LT |
155 | } |
156 | ||
0b6b6302 HV |
157 | static struct vb2_ops dvb_qops = { |
158 | .queue_setup = queue_setup, | |
159 | .buf_prepare = buffer_prepare, | |
160 | .buf_finish = buffer_finish, | |
161 | .buf_queue = buffer_queue, | |
162 | .wait_prepare = vb2_ops_wait_prepare, | |
163 | .wait_finish = vb2_ops_wait_finish, | |
164 | .start_streaming = start_streaming, | |
165 | .stop_streaming = stop_streaming, | |
1da177e4 LT |
166 | }; |
167 | ||
168 | /* ------------------------------------------------------------------ */ | |
22f3f17d MK |
169 | |
170 | static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire) | |
171 | { | |
172 | struct cx8802_dev *dev= fe->dvb->priv; | |
173 | struct cx8802_driver *drv = NULL; | |
174 | int ret = 0; | |
363c35fc ST |
175 | int fe_id; |
176 | ||
0b6b6302 | 177 | fe_id = vb2_dvb_find_frontend(&dev->frontends, fe); |
363c35fc | 178 | if (!fe_id) { |
2af03eea | 179 | printk(KERN_ERR "%s() No frontend found\n", __func__); |
363c35fc ST |
180 | return -EINVAL; |
181 | } | |
182 | ||
8a317a87 | 183 | mutex_lock(&dev->core->lock); |
22f3f17d MK |
184 | drv = cx8802_get_driver(dev, CX88_MPEG_DVB); |
185 | if (drv) { | |
363c35fc ST |
186 | if (acquire){ |
187 | dev->frontends.active_fe_id = fe_id; | |
22f3f17d | 188 | ret = drv->request_acquire(drv); |
363c35fc | 189 | } else { |
22f3f17d | 190 | ret = drv->request_release(drv); |
363c35fc ST |
191 | dev->frontends.active_fe_id = 0; |
192 | } | |
22f3f17d | 193 | } |
1fe70e96 | 194 | mutex_unlock(&dev->core->lock); |
22f3f17d MK |
195 | |
196 | return ret; | |
197 | } | |
198 | ||
e32fadc4 MCC |
199 | static void cx88_dvb_gate_ctrl(struct cx88_core *core, int open) |
200 | { | |
0b6b6302 HV |
201 | struct vb2_dvb_frontends *f; |
202 | struct vb2_dvb_frontend *fe; | |
e32fadc4 MCC |
203 | |
204 | if (!core->dvbdev) | |
205 | return; | |
206 | ||
207 | f = &core->dvbdev->frontends; | |
208 | ||
209 | if (!f) | |
210 | return; | |
211 | ||
212 | if (f->gate <= 1) /* undefined or fe0 */ | |
0b6b6302 | 213 | fe = vb2_dvb_get_frontend(f, 1); |
e32fadc4 | 214 | else |
0b6b6302 | 215 | fe = vb2_dvb_get_frontend(f, f->gate); |
e32fadc4 MCC |
216 | |
217 | if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl) | |
218 | fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open); | |
219 | } | |
220 | ||
22f3f17d MK |
221 | /* ------------------------------------------------------------------ */ |
222 | ||
3d7d027a | 223 | static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe) |
1da177e4 | 224 | { |
2e4e98e7 | 225 | static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 }; |
226 | static const u8 reset [] = { RESET, 0x80 }; | |
227 | static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
228 | static const u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 }; | |
229 | static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; | |
230 | static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; | |
1da177e4 LT |
231 | |
232 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
233 | udelay(200); | |
234 | mt352_write(fe, reset, sizeof(reset)); | |
235 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
236 | ||
237 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
238 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
239 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
240 | return 0; | |
241 | } | |
242 | ||
43eabb4e CP |
243 | static int dvico_dual_demod_init(struct dvb_frontend *fe) |
244 | { | |
2e4e98e7 | 245 | static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 }; |
246 | static const u8 reset [] = { RESET, 0x80 }; | |
247 | static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | |
248 | static const u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 }; | |
249 | static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; | |
250 | static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; | |
43eabb4e CP |
251 | |
252 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
253 | udelay(200); | |
254 | mt352_write(fe, reset, sizeof(reset)); | |
255 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
256 | ||
257 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
258 | mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); | |
259 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
1da177e4 LT |
264 | static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe) |
265 | { | |
2e4e98e7 | 266 | static const u8 clock_config [] = { 0x89, 0x38, 0x39 }; |
267 | static const u8 reset [] = { 0x50, 0x80 }; | |
268 | static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 }; | |
269 | static const u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF, | |
f2421ca3 | 270 | 0x00, 0xFF, 0x00, 0x40, 0x40 }; |
2e4e98e7 | 271 | static const u8 dntv_extra[] = { 0xB5, 0x7A }; |
272 | static const u8 capt_range_cfg[] = { 0x75, 0x32 }; | |
1da177e4 LT |
273 | |
274 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
275 | udelay(2000); | |
276 | mt352_write(fe, reset, sizeof(reset)); | |
277 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
278 | ||
279 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
280 | udelay(2000); | |
281 | mt352_write(fe, dntv_extra, sizeof(dntv_extra)); | |
282 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
2e4e98e7 | 287 | static const struct mt352_config dvico_fusionhdtv = { |
f7b54b10 | 288 | .demod_address = 0x0f, |
3d7d027a | 289 | .demod_init = dvico_fusionhdtv_demod_init, |
1da177e4 LT |
290 | }; |
291 | ||
2e4e98e7 | 292 | static const struct mt352_config dntv_live_dvbt_config = { |
1da177e4 LT |
293 | .demod_address = 0x0f, |
294 | .demod_init = dntv_live_dvbt_demod_init, | |
1da177e4 | 295 | }; |
fc40b261 | 296 | |
2e4e98e7 | 297 | static const struct mt352_config dvico_fusionhdtv_dual = { |
f7b54b10 | 298 | .demod_address = 0x0f, |
43eabb4e | 299 | .demod_init = dvico_dual_demod_init, |
43eabb4e CP |
300 | }; |
301 | ||
2e4e98e7 | 302 | static const struct zl10353_config cx88_terratec_cinergy_ht_pci_mkii_config = { |
70101a27 SW |
303 | .demod_address = (0x1e >> 1), |
304 | .no_tuner = 1, | |
305 | .if2 = 45600, | |
306 | }; | |
307 | ||
111ac84a SI |
308 | static struct mb86a16_config twinhan_vp1027 = { |
309 | .demod_address = 0x08, | |
310 | }; | |
311 | ||
7b34be71 | 312 | #if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054) |
3d7d027a CP |
313 | static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe) |
314 | { | |
2e4e98e7 | 315 | static const u8 clock_config [] = { 0x89, 0x38, 0x38 }; |
316 | static const u8 reset [] = { 0x50, 0x80 }; | |
317 | static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 }; | |
318 | static const u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF, | |
3d7d027a | 319 | 0x00, 0xFF, 0x00, 0x40, 0x40 }; |
2e4e98e7 | 320 | static const u8 dntv_extra[] = { 0xB5, 0x7A }; |
321 | static const u8 capt_range_cfg[] = { 0x75, 0x32 }; | |
3d7d027a CP |
322 | |
323 | mt352_write(fe, clock_config, sizeof(clock_config)); | |
324 | udelay(2000); | |
325 | mt352_write(fe, reset, sizeof(reset)); | |
326 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | |
327 | ||
328 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | |
329 | udelay(2000); | |
330 | mt352_write(fe, dntv_extra, sizeof(dntv_extra)); | |
331 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
2e4e98e7 | 336 | static const struct mt352_config dntv_live_dvbt_pro_config = { |
fc40b261 CP |
337 | .demod_address = 0x0f, |
338 | .no_tuner = 1, | |
3d7d027a | 339 | .demod_init = dntv_live_dvbt_pro_demod_init, |
fc40b261 CP |
340 | }; |
341 | #endif | |
1da177e4 | 342 | |
2e4e98e7 | 343 | static const struct zl10353_config dvico_fusionhdtv_hybrid = { |
f7b54b10 | 344 | .demod_address = 0x0f, |
f54376e2 | 345 | .no_tuner = 1, |
780dfef3 CP |
346 | }; |
347 | ||
2e4e98e7 | 348 | static const struct zl10353_config dvico_fusionhdtv_xc3028 = { |
b3fb91d2 CP |
349 | .demod_address = 0x0f, |
350 | .if2 = 45600, | |
351 | .no_tuner = 1, | |
352 | }; | |
353 | ||
2e4e98e7 | 354 | static const struct mt352_config dvico_fusionhdtv_mt352_xc3028 = { |
b3fb91d2 CP |
355 | .demod_address = 0x0f, |
356 | .if2 = 4560, | |
357 | .no_tuner = 1, | |
358 | .demod_init = dvico_fusionhdtv_demod_init, | |
359 | }; | |
360 | ||
2e4e98e7 | 361 | static const struct zl10353_config dvico_fusionhdtv_plus_v1_1 = { |
f7b54b10 | 362 | .demod_address = 0x0f, |
780dfef3 | 363 | }; |
780dfef3 | 364 | |
2e4e98e7 | 365 | static const struct cx22702_config connexant_refboard_config = { |
1da177e4 | 366 | .demod_address = 0x43, |
38d84c3b | 367 | .output_mode = CX22702_SERIAL_OUTPUT, |
1da177e4 LT |
368 | }; |
369 | ||
2e4e98e7 | 370 | static const struct cx22702_config hauppauge_hvr_config = { |
aa481a65 ST |
371 | .demod_address = 0x63, |
372 | .output_mode = CX22702_SERIAL_OUTPUT, | |
373 | }; | |
1da177e4 | 374 | |
4a390558 | 375 | static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured) |
1da177e4 LT |
376 | { |
377 | struct cx8802_dev *dev= fe->dvb->priv; | |
378 | dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00; | |
379 | return 0; | |
380 | } | |
381 | ||
2e4e98e7 | 382 | static const struct or51132_config pchdtv_hd3000 = { |
f7b54b10 MK |
383 | .demod_address = 0x15, |
384 | .set_ts_params = or51132_set_ts_param, | |
1da177e4 | 385 | }; |
1da177e4 | 386 | |
6ddcc919 | 387 | static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index) |
0ccef6db MK |
388 | { |
389 | struct cx8802_dev *dev= fe->dvb->priv; | |
390 | struct cx88_core *core = dev->core; | |
391 | ||
32d83efc | 392 | dprintk(1, "%s: index = %d\n", __func__, index); |
0ccef6db MK |
393 | if (index == 0) |
394 | cx_clear(MO_GP0_IO, 8); | |
395 | else | |
396 | cx_set(MO_GP0_IO, 8); | |
397 | return 0; | |
398 | } | |
399 | ||
6ddcc919 | 400 | static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured) |
f1798495 MK |
401 | { |
402 | struct cx8802_dev *dev= fe->dvb->priv; | |
403 | if (is_punctured) | |
404 | dev->ts_gen_cntrl |= 0x04; | |
405 | else | |
406 | dev->ts_gen_cntrl &= ~0x04; | |
407 | return 0; | |
408 | } | |
409 | ||
6ddcc919 | 410 | static struct lgdt330x_config fusionhdtv_3_gold = { |
f7b54b10 MK |
411 | .demod_address = 0x0e, |
412 | .demod_chip = LGDT3302, | |
413 | .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */ | |
414 | .set_ts_params = lgdt330x_set_ts_param, | |
0d723c09 | 415 | }; |
e52e98a7 | 416 | |
2e4e98e7 | 417 | static const struct lgdt330x_config fusionhdtv_5_gold = { |
f7b54b10 MK |
418 | .demod_address = 0x0e, |
419 | .demod_chip = LGDT3303, | |
420 | .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */ | |
421 | .set_ts_params = lgdt330x_set_ts_param, | |
e52e98a7 | 422 | }; |
da215d22 | 423 | |
2e4e98e7 | 424 | static const struct lgdt330x_config pchdtv_hd5500 = { |
f7b54b10 MK |
425 | .demod_address = 0x59, |
426 | .demod_chip = LGDT3303, | |
427 | .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */ | |
428 | .set_ts_params = lgdt330x_set_ts_param, | |
da215d22 | 429 | }; |
f1798495 | 430 | |
4a390558 | 431 | static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured) |
fde6d31e KL |
432 | { |
433 | struct cx8802_dev *dev= fe->dvb->priv; | |
434 | dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00; | |
435 | return 0; | |
436 | } | |
437 | ||
2e4e98e7 | 438 | static const struct nxt200x_config ati_hdtvwonder = { |
f7b54b10 | 439 | .demod_address = 0x0a, |
f7b54b10 | 440 | .set_ts_params = nxt200x_set_ts_param, |
fde6d31e | 441 | }; |
fde6d31e | 442 | |
0fa14aa6 ST |
443 | static int cx24123_set_ts_param(struct dvb_frontend* fe, |
444 | int is_punctured) | |
445 | { | |
446 | struct cx8802_dev *dev= fe->dvb->priv; | |
f7b54b10 | 447 | dev->ts_gen_cntrl = 0x02; |
0fa14aa6 ST |
448 | return 0; |
449 | } | |
450 | ||
f7b54b10 | 451 | static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe, |
0df289a2 | 452 | enum fe_sec_voltage voltage) |
0e0351e3 VC |
453 | { |
454 | struct cx8802_dev *dev= fe->dvb->priv; | |
455 | struct cx88_core *core = dev->core; | |
456 | ||
4a390558 | 457 | if (voltage == SEC_VOLTAGE_OFF) |
f7b54b10 | 458 | cx_write(MO_GP0_IO, 0x000006fb); |
4a390558 | 459 | else |
cd20ca9f | 460 | cx_write(MO_GP0_IO, 0x000006f9); |
cd20ca9f AQ |
461 | |
462 | if (core->prev_set_voltage) | |
463 | return core->prev_set_voltage(fe, voltage); | |
464 | return 0; | |
0e0351e3 VC |
465 | } |
466 | ||
f7b54b10 | 467 | static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe, |
0df289a2 | 468 | enum fe_sec_voltage voltage) |
c02a34f4 SA |
469 | { |
470 | struct cx8802_dev *dev= fe->dvb->priv; | |
471 | struct cx88_core *core = dev->core; | |
472 | ||
473 | if (voltage == SEC_VOLTAGE_OFF) { | |
474 | dprintk(1,"LNB Voltage OFF\n"); | |
475 | cx_write(MO_GP0_IO, 0x0000efff); | |
476 | } | |
477 | ||
478 | if (core->prev_set_voltage) | |
479 | return core->prev_set_voltage(fe, voltage); | |
480 | return 0; | |
481 | } | |
482 | ||
af832623 | 483 | static int tevii_dvbs_set_voltage(struct dvb_frontend *fe, |
0df289a2 | 484 | enum fe_sec_voltage voltage) |
af832623 IL |
485 | { |
486 | struct cx8802_dev *dev= fe->dvb->priv; | |
487 | struct cx88_core *core = dev->core; | |
488 | ||
ad5f74c0 | 489 | cx_set(MO_GP0_IO, 0x6040); |
af832623 | 490 | switch (voltage) { |
111ac84a SI |
491 | case SEC_VOLTAGE_13: |
492 | cx_clear(MO_GP0_IO, 0x20); | |
493 | break; | |
494 | case SEC_VOLTAGE_18: | |
495 | cx_set(MO_GP0_IO, 0x20); | |
496 | break; | |
497 | case SEC_VOLTAGE_OFF: | |
498 | cx_clear(MO_GP0_IO, 0x20); | |
499 | break; | |
500 | } | |
501 | ||
502 | if (core->prev_set_voltage) | |
503 | return core->prev_set_voltage(fe, voltage); | |
504 | return 0; | |
505 | } | |
506 | ||
507 | static int vp1027_set_voltage(struct dvb_frontend *fe, | |
0df289a2 | 508 | enum fe_sec_voltage voltage) |
111ac84a SI |
509 | { |
510 | struct cx8802_dev *dev = fe->dvb->priv; | |
511 | struct cx88_core *core = dev->core; | |
512 | ||
513 | switch (voltage) { | |
514 | case SEC_VOLTAGE_13: | |
515 | dprintk(1, "LNB SEC Voltage=13\n"); | |
516 | cx_write(MO_GP0_IO, 0x00001220); | |
517 | break; | |
518 | case SEC_VOLTAGE_18: | |
519 | dprintk(1, "LNB SEC Voltage=18\n"); | |
520 | cx_write(MO_GP0_IO, 0x00001222); | |
521 | break; | |
522 | case SEC_VOLTAGE_OFF: | |
523 | dprintk(1, "LNB Voltage OFF\n"); | |
524 | cx_write(MO_GP0_IO, 0x00001230); | |
525 | break; | |
af832623 IL |
526 | } |
527 | ||
528 | if (core->prev_set_voltage) | |
529 | return core->prev_set_voltage(fe, voltage); | |
530 | return 0; | |
531 | } | |
532 | ||
2e4e98e7 | 533 | static const struct cx24123_config geniatech_dvbs_config = { |
f7b54b10 MK |
534 | .demod_address = 0x55, |
535 | .set_ts_params = cx24123_set_ts_param, | |
c02a34f4 SA |
536 | }; |
537 | ||
2e4e98e7 | 538 | static const struct cx24123_config hauppauge_novas_config = { |
f7b54b10 MK |
539 | .demod_address = 0x55, |
540 | .set_ts_params = cx24123_set_ts_param, | |
0e0351e3 VC |
541 | }; |
542 | ||
2e4e98e7 | 543 | static const struct cx24123_config kworld_dvbs_100_config = { |
f7b54b10 MK |
544 | .demod_address = 0x15, |
545 | .set_ts_params = cx24123_set_ts_param, | |
ef76856d | 546 | .lnb_polarity = 1, |
0fa14aa6 | 547 | }; |
0fa14aa6 | 548 | |
2e4e98e7 | 549 | static const struct s5h1409_config pinnacle_pctv_hd_800i_config = { |
60464da8 ST |
550 | .demod_address = 0x32 >> 1, |
551 | .output_mode = S5H1409_PARALLEL_OUTPUT, | |
552 | .gpio = S5H1409_GPIO_ON, | |
553 | .qam_if = 44000, | |
554 | .inversion = S5H1409_INVERSION_OFF, | |
555 | .status_mode = S5H1409_DEMODLOCKING, | |
4917019d | 556 | .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK, |
60464da8 ST |
557 | }; |
558 | ||
2e4e98e7 | 559 | static const struct s5h1409_config dvico_hdtv5_pci_nano_config = { |
5c00fac0 ST |
560 | .demod_address = 0x32 >> 1, |
561 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
562 | .gpio = S5H1409_GPIO_OFF, | |
563 | .inversion = S5H1409_INVERSION_OFF, | |
564 | .status_mode = S5H1409_DEMODLOCKING, | |
565 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
566 | }; | |
567 | ||
2e4e98e7 | 568 | static const struct s5h1409_config kworld_atsc_120_config = { |
99e09eac | 569 | .demod_address = 0x32 >> 1, |
99e09eac MCC |
570 | .output_mode = S5H1409_SERIAL_OUTPUT, |
571 | .gpio = S5H1409_GPIO_OFF, | |
572 | .inversion = S5H1409_INVERSION_OFF, | |
573 | .status_mode = S5H1409_DEMODLOCKING, | |
574 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
575 | }; | |
576 | ||
2e4e98e7 | 577 | static const struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = { |
60464da8 ST |
578 | .i2c_address = 0x64, |
579 | .if_khz = 5380, | |
60464da8 ST |
580 | }; |
581 | ||
2e4e98e7 | 582 | static const struct zl10353_config cx88_pinnacle_hybrid_pctv = { |
3f6014fc SV |
583 | .demod_address = (0x1e >> 1), |
584 | .no_tuner = 1, | |
585 | .if2 = 45600, | |
586 | }; | |
587 | ||
2e4e98e7 | 588 | static const struct zl10353_config cx88_geniatech_x8000_mt = { |
57069349 MCC |
589 | .demod_address = (0x1e >> 1), |
590 | .no_tuner = 1, | |
591 | .disable_i2c_gate_ctrl = 1, | |
9507901e MCC |
592 | }; |
593 | ||
2e4e98e7 | 594 | static const struct s5h1411_config dvico_fusionhdtv7_config = { |
d893d5dc ST |
595 | .output_mode = S5H1411_SERIAL_OUTPUT, |
596 | .gpio = S5H1411_GPIO_ON, | |
597 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
598 | .qam_if = S5H1411_IF_44000, | |
599 | .vsb_if = S5H1411_IF_44000, | |
600 | .inversion = S5H1411_INVERSION_OFF, | |
601 | .status_mode = S5H1411_DEMODLOCKING | |
602 | }; | |
603 | ||
2e4e98e7 | 604 | static const struct xc5000_config dvico_fusionhdtv7_tuner_config = { |
d893d5dc ST |
605 | .i2c_address = 0xc2 >> 1, |
606 | .if_khz = 5380, | |
d893d5dc ST |
607 | }; |
608 | ||
23fb348d MCC |
609 | static int attach_xc3028(u8 addr, struct cx8802_dev *dev) |
610 | { | |
611 | struct dvb_frontend *fe; | |
0b6b6302 | 612 | struct vb2_dvb_frontend *fe0 = NULL; |
99e09eac | 613 | struct xc2028_ctrl ctl; |
23fb348d MCC |
614 | struct xc2028_config cfg = { |
615 | .i2c_adap = &dev->core->i2c_adap, | |
616 | .i2c_addr = addr, | |
99e09eac | 617 | .ctrl = &ctl, |
23fb348d MCC |
618 | }; |
619 | ||
92abe9ee | 620 | /* Get the first frontend */ |
0b6b6302 | 621 | fe0 = vb2_dvb_get_frontend(&dev->frontends, 1); |
363c35fc ST |
622 | if (!fe0) |
623 | return -EINVAL; | |
624 | ||
625 | if (!fe0->dvb.frontend) { | |
ddd5441d MCC |
626 | printk(KERN_ERR "%s/2: dvb frontend not attached. " |
627 | "Can't attach xc3028\n", | |
628 | dev->core->name); | |
629 | return -EINVAL; | |
630 | } | |
631 | ||
99e09eac MCC |
632 | /* |
633 | * Some xc3028 devices may be hidden by an I2C gate. This is known | |
634 | * to happen with some s5h1409-based devices. | |
635 | * Now that I2C gate is open, sets up xc3028 configuration | |
636 | */ | |
637 | cx88_setup_xc3028(dev->core, &ctl); | |
638 | ||
363c35fc | 639 | fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg); |
23fb348d MCC |
640 | if (!fe) { |
641 | printk(KERN_ERR "%s/2: xc3028 attach failed\n", | |
642 | dev->core->name); | |
363c35fc ST |
643 | dvb_frontend_detach(fe0->dvb.frontend); |
644 | dvb_unregister_frontend(fe0->dvb.frontend); | |
645 | fe0->dvb.frontend = NULL; | |
23fb348d MCC |
646 | return -EINVAL; |
647 | } | |
648 | ||
649 | printk(KERN_INFO "%s/2: xc3028 attached\n", | |
650 | dev->core->name); | |
651 | ||
652 | return 0; | |
653 | } | |
9507901e | 654 | |
c21973e8 | 655 | static int attach_xc4000(struct cx8802_dev *dev, struct xc4000_config *cfg) |
656 | { | |
657 | struct dvb_frontend *fe; | |
0b6b6302 | 658 | struct vb2_dvb_frontend *fe0 = NULL; |
c21973e8 | 659 | |
660 | /* Get the first frontend */ | |
0b6b6302 | 661 | fe0 = vb2_dvb_get_frontend(&dev->frontends, 1); |
c21973e8 | 662 | if (!fe0) |
663 | return -EINVAL; | |
664 | ||
665 | if (!fe0->dvb.frontend) { | |
666 | printk(KERN_ERR "%s/2: dvb frontend not attached. " | |
667 | "Can't attach xc4000\n", | |
668 | dev->core->name); | |
669 | return -EINVAL; | |
670 | } | |
671 | ||
672 | fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, &dev->core->i2c_adap, | |
673 | cfg); | |
674 | if (!fe) { | |
675 | printk(KERN_ERR "%s/2: xc4000 attach failed\n", | |
676 | dev->core->name); | |
677 | dvb_frontend_detach(fe0->dvb.frontend); | |
678 | dvb_unregister_frontend(fe0->dvb.frontend); | |
679 | fe0->dvb.frontend = NULL; | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | printk(KERN_INFO "%s/2: xc4000 attached\n", dev->core->name); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
5bd1b663 ST |
688 | static int cx24116_set_ts_param(struct dvb_frontend *fe, |
689 | int is_punctured) | |
690 | { | |
691 | struct cx8802_dev *dev = fe->dvb->priv; | |
692 | dev->ts_gen_cntrl = 0x2; | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
b699c271 IL |
697 | static int stv0900_set_ts_param(struct dvb_frontend *fe, |
698 | int is_punctured) | |
699 | { | |
700 | struct cx8802_dev *dev = fe->dvb->priv; | |
701 | dev->ts_gen_cntrl = 0; | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
5bd1b663 ST |
706 | static int cx24116_reset_device(struct dvb_frontend *fe) |
707 | { | |
708 | struct cx8802_dev *dev = fe->dvb->priv; | |
709 | struct cx88_core *core = dev->core; | |
710 | ||
711 | /* Reset the part */ | |
363c35fc | 712 | /* Put the cx24116 into reset */ |
5bd1b663 ST |
713 | cx_write(MO_SRST_IO, 0); |
714 | msleep(10); | |
363c35fc | 715 | /* Take the cx24116 out of reset */ |
5bd1b663 ST |
716 | cx_write(MO_SRST_IO, 1); |
717 | msleep(10); | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
2e4e98e7 | 722 | static const struct cx24116_config hauppauge_hvr4000_config = { |
5bd1b663 ST |
723 | .demod_address = 0x05, |
724 | .set_ts_params = cx24116_set_ts_param, | |
725 | .reset_device = cx24116_reset_device, | |
726 | }; | |
727 | ||
2e4e98e7 | 728 | static const struct cx24116_config tevii_s460_config = { |
af832623 IL |
729 | .demod_address = 0x55, |
730 | .set_ts_params = cx24116_set_ts_param, | |
731 | .reset_device = cx24116_reset_device, | |
732 | }; | |
733 | ||
0cb73639 IL |
734 | static int ds3000_set_ts_param(struct dvb_frontend *fe, |
735 | int is_punctured) | |
736 | { | |
737 | struct cx8802_dev *dev = fe->dvb->priv; | |
738 | dev->ts_gen_cntrl = 4; | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
743 | static struct ds3000_config tevii_ds3000_config = { | |
744 | .demod_address = 0x68, | |
745 | .set_ts_params = ds3000_set_ts_param, | |
746 | }; | |
747 | ||
73f0af44 KD |
748 | static struct ts2020_config tevii_ts2020_config = { |
749 | .tuner_address = 0x60, | |
b858c331 | 750 | .clk_out_div = 1, |
73f0af44 KD |
751 | }; |
752 | ||
2e4e98e7 | 753 | static const struct stv0900_config prof_7301_stv0900_config = { |
b699c271 IL |
754 | .demod_address = 0x6a, |
755 | /* demod_mode = 0,*/ | |
756 | .xtal = 27000000, | |
757 | .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */ | |
758 | .diseqc_mode = 2,/* 2/3 PWM */ | |
759 | .tun1_maddress = 0,/* 0x60 */ | |
760 | .tun1_adc = 0,/* 2 Vpp */ | |
761 | .path1_mode = 3, | |
762 | .set_ts_params = stv0900_set_ts_param, | |
763 | }; | |
764 | ||
2e4e98e7 | 765 | static const struct stb6100_config prof_7301_stb6100_config = { |
b699c271 IL |
766 | .tuner_address = 0x60, |
767 | .refclock = 27000000, | |
768 | }; | |
769 | ||
2e4e98e7 | 770 | static const struct stv0299_config tevii_tuner_sharp_config = { |
e4aab64c | 771 | .demod_address = 0x68, |
d4305c68 | 772 | .inittab = sharp_z0194a_inittab, |
e4aab64c IL |
773 | .mclk = 88000000UL, |
774 | .invert = 1, | |
775 | .skip_reinit = 0, | |
776 | .lock_output = 1, | |
777 | .volt13_op0_op1 = STV0299_VOLT13_OP1, | |
778 | .min_delay_ms = 100, | |
d4305c68 | 779 | .set_symbol_rate = sharp_z0194a_set_symbol_rate, |
e4aab64c IL |
780 | .set_ts_params = cx24116_set_ts_param, |
781 | }; | |
782 | ||
2e4e98e7 | 783 | static const struct stv0288_config tevii_tuner_earda_config = { |
e4aab64c IL |
784 | .demod_address = 0x68, |
785 | .min_delay_ms = 100, | |
786 | .set_ts_params = cx24116_set_ts_param, | |
787 | }; | |
788 | ||
6e0e12f1 | 789 | static int cx8802_alloc_frontends(struct cx8802_dev *dev) |
1da177e4 | 790 | { |
0590d91c | 791 | struct cx88_core *core = dev->core; |
0b6b6302 | 792 | struct vb2_dvb_frontend *fe = NULL; |
e32fadc4 | 793 | int i; |
0590d91c | 794 | |
e32fadc4 MCC |
795 | mutex_init(&dev->frontends.lock); |
796 | INIT_LIST_HEAD(&dev->frontends.felist); | |
797 | ||
6e0e12f1 AW |
798 | if (!core->board.num_frontends) |
799 | return -ENODEV; | |
800 | ||
e32fadc4 MCC |
801 | printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, |
802 | core->board.num_frontends); | |
803 | for (i = 1; i <= core->board.num_frontends; i++) { | |
0b6b6302 | 804 | fe = vb2_dvb_alloc_frontend(&dev->frontends, i); |
6e0e12f1 | 805 | if (!fe) { |
e32fadc4 | 806 | printk(KERN_ERR "%s() failed to alloc\n", __func__); |
0b6b6302 | 807 | vb2_dvb_dealloc_frontends(&dev->frontends); |
6e0e12f1 | 808 | return -ENOMEM; |
e32fadc4 MCC |
809 | } |
810 | } | |
6e0e12f1 AW |
811 | return 0; |
812 | } | |
813 | ||
4f3ca2f1 DH |
814 | |
815 | ||
2e4e98e7 | 816 | static const u8 samsung_smt_7020_inittab[] = { |
4f3ca2f1 DH |
817 | 0x01, 0x15, |
818 | 0x02, 0x00, | |
819 | 0x03, 0x00, | |
820 | 0x04, 0x7D, | |
821 | 0x05, 0x0F, | |
822 | 0x06, 0x02, | |
823 | 0x07, 0x00, | |
824 | 0x08, 0x60, | |
825 | ||
826 | 0x0A, 0xC2, | |
827 | 0x0B, 0x00, | |
828 | 0x0C, 0x01, | |
829 | 0x0D, 0x81, | |
830 | 0x0E, 0x44, | |
831 | 0x0F, 0x09, | |
832 | 0x10, 0x3C, | |
833 | 0x11, 0x84, | |
834 | 0x12, 0xDA, | |
835 | 0x13, 0x99, | |
836 | 0x14, 0x8D, | |
837 | 0x15, 0xCE, | |
838 | 0x16, 0xE8, | |
839 | 0x17, 0x43, | |
840 | 0x18, 0x1C, | |
841 | 0x19, 0x1B, | |
842 | 0x1A, 0x1D, | |
843 | ||
844 | 0x1C, 0x12, | |
845 | 0x1D, 0x00, | |
846 | 0x1E, 0x00, | |
847 | 0x1F, 0x00, | |
848 | 0x20, 0x00, | |
849 | 0x21, 0x00, | |
850 | 0x22, 0x00, | |
851 | 0x23, 0x00, | |
852 | ||
853 | 0x28, 0x02, | |
854 | 0x29, 0x28, | |
855 | 0x2A, 0x14, | |
856 | 0x2B, 0x0F, | |
857 | 0x2C, 0x09, | |
858 | 0x2D, 0x05, | |
859 | ||
860 | 0x31, 0x1F, | |
861 | 0x32, 0x19, | |
862 | 0x33, 0xFC, | |
863 | 0x34, 0x13, | |
864 | 0xff, 0xff, | |
865 | }; | |
866 | ||
867 | ||
14d24d14 | 868 | static int samsung_smt_7020_tuner_set_params(struct dvb_frontend *fe) |
4f3ca2f1 | 869 | { |
b738ae16 | 870 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
4f3ca2f1 DH |
871 | struct cx8802_dev *dev = fe->dvb->priv; |
872 | u8 buf[4]; | |
873 | u32 div; | |
874 | struct i2c_msg msg = { | |
875 | .addr = 0x61, | |
876 | .flags = 0, | |
877 | .buf = buf, | |
878 | .len = sizeof(buf) }; | |
879 | ||
b738ae16 | 880 | div = c->frequency / 125; |
4f3ca2f1 DH |
881 | |
882 | buf[0] = (div >> 8) & 0x7f; | |
883 | buf[1] = div & 0xff; | |
884 | buf[2] = 0x84; /* 0xC4 */ | |
885 | buf[3] = 0x00; | |
886 | ||
b738ae16 | 887 | if (c->frequency < 1500000) |
4f3ca2f1 DH |
888 | buf[3] |= 0x10; |
889 | ||
890 | if (fe->ops.i2c_gate_ctrl) | |
891 | fe->ops.i2c_gate_ctrl(fe, 1); | |
892 | ||
893 | if (i2c_transfer(&dev->core->i2c_adap, &msg, 1) != 1) | |
894 | return -EIO; | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | static int samsung_smt_7020_set_tone(struct dvb_frontend *fe, | |
0df289a2 | 900 | enum fe_sec_tone_mode tone) |
4f3ca2f1 DH |
901 | { |
902 | struct cx8802_dev *dev = fe->dvb->priv; | |
903 | struct cx88_core *core = dev->core; | |
904 | ||
905 | cx_set(MO_GP0_IO, 0x0800); | |
906 | ||
907 | switch (tone) { | |
908 | case SEC_TONE_ON: | |
909 | cx_set(MO_GP0_IO, 0x08); | |
910 | break; | |
911 | case SEC_TONE_OFF: | |
912 | cx_clear(MO_GP0_IO, 0x08); | |
913 | break; | |
914 | default: | |
915 | return -EINVAL; | |
916 | } | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
921 | static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe, | |
0df289a2 | 922 | enum fe_sec_voltage voltage) |
4f3ca2f1 DH |
923 | { |
924 | struct cx8802_dev *dev = fe->dvb->priv; | |
925 | struct cx88_core *core = dev->core; | |
926 | ||
927 | u8 data; | |
928 | struct i2c_msg msg = { | |
929 | .addr = 8, | |
930 | .flags = 0, | |
931 | .buf = &data, | |
932 | .len = sizeof(data) }; | |
933 | ||
934 | cx_set(MO_GP0_IO, 0x8000); | |
935 | ||
936 | switch (voltage) { | |
937 | case SEC_VOLTAGE_OFF: | |
938 | break; | |
939 | case SEC_VOLTAGE_13: | |
940 | data = ISL6421_EN1 | ISL6421_LLC1; | |
941 | cx_clear(MO_GP0_IO, 0x80); | |
942 | break; | |
943 | case SEC_VOLTAGE_18: | |
944 | data = ISL6421_EN1 | ISL6421_LLC1 | ISL6421_VSEL1; | |
945 | cx_clear(MO_GP0_IO, 0x80); | |
946 | break; | |
947 | default: | |
948 | return -EINVAL; | |
c2c1b415 | 949 | } |
4f3ca2f1 DH |
950 | |
951 | return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO; | |
952 | } | |
953 | ||
954 | static int samsung_smt_7020_stv0299_set_symbol_rate(struct dvb_frontend *fe, | |
955 | u32 srate, u32 ratio) | |
956 | { | |
957 | u8 aclk = 0; | |
958 | u8 bclk = 0; | |
959 | ||
960 | if (srate < 1500000) { | |
961 | aclk = 0xb7; | |
962 | bclk = 0x47; | |
963 | } else if (srate < 3000000) { | |
964 | aclk = 0xb7; | |
965 | bclk = 0x4b; | |
966 | } else if (srate < 7000000) { | |
967 | aclk = 0xb7; | |
968 | bclk = 0x4f; | |
969 | } else if (srate < 14000000) { | |
970 | aclk = 0xb7; | |
971 | bclk = 0x53; | |
972 | } else if (srate < 30000000) { | |
973 | aclk = 0xb6; | |
974 | bclk = 0x53; | |
975 | } else if (srate < 45000000) { | |
976 | aclk = 0xb4; | |
977 | bclk = 0x51; | |
978 | } | |
979 | ||
980 | stv0299_writereg(fe, 0x13, aclk); | |
981 | stv0299_writereg(fe, 0x14, bclk); | |
982 | stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); | |
983 | stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); | |
984 | stv0299_writereg(fe, 0x21, ratio & 0xf0); | |
985 | ||
986 | return 0; | |
987 | } | |
988 | ||
989 | ||
2e4e98e7 | 990 | static const struct stv0299_config samsung_stv0299_config = { |
4f3ca2f1 DH |
991 | .demod_address = 0x68, |
992 | .inittab = samsung_smt_7020_inittab, | |
993 | .mclk = 88000000UL, | |
994 | .invert = 0, | |
995 | .skip_reinit = 0, | |
996 | .lock_output = STV0299_LOCKOUTPUT_LK, | |
997 | .volt13_op0_op1 = STV0299_VOLT13_OP1, | |
998 | .min_delay_ms = 100, | |
999 | .set_symbol_rate = samsung_smt_7020_stv0299_set_symbol_rate, | |
1000 | }; | |
1001 | ||
6e0e12f1 AW |
1002 | static int dvb_register(struct cx8802_dev *dev) |
1003 | { | |
1004 | struct cx88_core *core = dev->core; | |
0b6b6302 | 1005 | struct vb2_dvb_frontend *fe0, *fe1 = NULL; |
6e0e12f1 | 1006 | int mfe_shared = 0; /* bus not shared by default */ |
7b0962d3 | 1007 | int res = -EINVAL; |
6e0e12f1 AW |
1008 | |
1009 | if (0 != core->i2c_rc) { | |
1010 | printk(KERN_ERR "%s/2: no i2c-bus available, cannot attach dvb drivers\n", core->name); | |
1011 | goto frontend_detach; | |
1012 | } | |
e32fadc4 | 1013 | |
363c35fc | 1014 | /* Get the first frontend */ |
0b6b6302 | 1015 | fe0 = vb2_dvb_get_frontend(&dev->frontends, 1); |
363c35fc | 1016 | if (!fe0) |
60a5a927 | 1017 | goto frontend_detach; |
1da177e4 | 1018 | |
8e739090 DB |
1019 | /* multi-frontend gate control is undefined or defaults to fe0 */ |
1020 | dev->frontends.gate = 0; | |
1021 | ||
e32fadc4 MCC |
1022 | /* Sets the gate control callback to be used by i2c command calls */ |
1023 | core->gate_ctrl = cx88_dvb_gate_ctrl; | |
1024 | ||
8e739090 | 1025 | /* init frontend(s) */ |
0590d91c | 1026 | switch (core->boardnr) { |
1da177e4 | 1027 | case CX88_BOARD_HAUPPAUGE_DVB_T1: |
363c35fc | 1028 | fe0->dvb.frontend = dvb_attach(cx22702_attach, |
ed355260 | 1029 | &connexant_refboard_config, |
0590d91c | 1030 | &core->i2c_adap); |
363c35fc ST |
1031 | if (fe0->dvb.frontend != NULL) { |
1032 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1033 | 0x61, &core->i2c_adap, |
1034 | DVB_PLL_THOMSON_DTT759X)) | |
1035 | goto frontend_detach; | |
f54376e2 | 1036 | } |
1da177e4 | 1037 | break; |
e057ee11 | 1038 | case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1: |
1da177e4 | 1039 | case CX88_BOARD_CONEXANT_DVB_T1: |
f39624fd | 1040 | case CX88_BOARD_KWORLD_DVB_T_CX22702: |
2b5200a7 | 1041 | case CX88_BOARD_WINFAST_DTV1000: |
363c35fc | 1042 | fe0->dvb.frontend = dvb_attach(cx22702_attach, |
f7b54b10 | 1043 | &connexant_refboard_config, |
0590d91c | 1044 | &core->i2c_adap); |
363c35fc ST |
1045 | if (fe0->dvb.frontend != NULL) { |
1046 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1047 | 0x60, &core->i2c_adap, |
1048 | DVB_PLL_THOMSON_DTT7579)) | |
1049 | goto frontend_detach; | |
f54376e2 | 1050 | } |
1da177e4 | 1051 | break; |
4bd6e9d9 | 1052 | case CX88_BOARD_WINFAST_DTV2000H: |
611900c1 ST |
1053 | case CX88_BOARD_HAUPPAUGE_HVR1100: |
1054 | case CX88_BOARD_HAUPPAUGE_HVR1100LP: | |
a5a2ecfc | 1055 | case CX88_BOARD_HAUPPAUGE_HVR1300: |
363c35fc | 1056 | fe0->dvb.frontend = dvb_attach(cx22702_attach, |
ed355260 | 1057 | &hauppauge_hvr_config, |
0590d91c | 1058 | &core->i2c_adap); |
363c35fc ST |
1059 | if (fe0->dvb.frontend != NULL) { |
1060 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1061 | &core->i2c_adap, 0x61, |
1062 | TUNER_PHILIPS_FMD1216ME_MK3)) | |
1063 | goto frontend_detach; | |
f54376e2 | 1064 | } |
611900c1 | 1065 | break; |
27b93d8a MS |
1066 | case CX88_BOARD_WINFAST_DTV2000H_J: |
1067 | fe0->dvb.frontend = dvb_attach(cx22702_attach, | |
1068 | &hauppauge_hvr_config, | |
1069 | &core->i2c_adap); | |
1070 | if (fe0->dvb.frontend != NULL) { | |
1071 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
1072 | &core->i2c_adap, 0x61, | |
1073 | TUNER_PHILIPS_FMD1216MEX_MK3)) | |
1074 | goto frontend_detach; | |
1075 | } | |
1076 | break; | |
363c35fc | 1077 | case CX88_BOARD_HAUPPAUGE_HVR3000: |
60a5a927 DB |
1078 | /* MFE frontend 1 */ |
1079 | mfe_shared = 1; | |
1080 | dev->frontends.gate = 2; | |
363c35fc ST |
1081 | /* DVB-S init */ |
1082 | fe0->dvb.frontend = dvb_attach(cx24123_attach, | |
60a5a927 DB |
1083 | &hauppauge_novas_config, |
1084 | &dev->core->i2c_adap); | |
363c35fc | 1085 | if (fe0->dvb.frontend) { |
60a5a927 DB |
1086 | if (!dvb_attach(isl6421_attach, |
1087 | fe0->dvb.frontend, | |
1088 | &dev->core->i2c_adap, | |
48a8a03b | 1089 | 0x08, ISL6421_DCL, 0x00, false)) |
60a5a927 | 1090 | goto frontend_detach; |
363c35fc | 1091 | } |
60a5a927 | 1092 | /* MFE frontend 2 */ |
0b6b6302 | 1093 | fe1 = vb2_dvb_get_frontend(&dev->frontends, 2); |
60a5a927 DB |
1094 | if (!fe1) |
1095 | goto frontend_detach; | |
1096 | /* DVB-T init */ | |
1097 | fe1->dvb.frontend = dvb_attach(cx22702_attach, | |
1098 | &hauppauge_hvr_config, | |
1099 | &dev->core->i2c_adap); | |
1100 | if (fe1->dvb.frontend) { | |
1101 | fe1->dvb.frontend->id = 1; | |
1102 | if (!dvb_attach(simple_tuner_attach, | |
1103 | fe1->dvb.frontend, | |
1104 | &dev->core->i2c_adap, | |
1105 | 0x61, TUNER_PHILIPS_FMD1216ME_MK3)) | |
1106 | goto frontend_detach; | |
363c35fc ST |
1107 | } |
1108 | break; | |
780dfef3 | 1109 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS: |
363c35fc | 1110 | fe0->dvb.frontend = dvb_attach(mt352_attach, |
f7b54b10 | 1111 | &dvico_fusionhdtv, |
0590d91c | 1112 | &core->i2c_adap); |
363c35fc ST |
1113 | if (fe0->dvb.frontend != NULL) { |
1114 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1115 | 0x60, NULL, DVB_PLL_THOMSON_DTT7579)) |
1116 | goto frontend_detach; | |
780dfef3 | 1117 | break; |
f54376e2 | 1118 | } |
780dfef3 | 1119 | /* ZL10353 replaces MT352 on later cards */ |
363c35fc | 1120 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
f7b54b10 | 1121 | &dvico_fusionhdtv_plus_v1_1, |
0590d91c | 1122 | &core->i2c_adap); |
363c35fc ST |
1123 | if (fe0->dvb.frontend != NULL) { |
1124 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1125 | 0x60, NULL, DVB_PLL_THOMSON_DTT7579)) |
1126 | goto frontend_detach; | |
f54376e2 | 1127 | } |
c2af3cd6 MK |
1128 | break; |
1129 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL: | |
c2af3cd6 MK |
1130 | /* The tin box says DEE1601, but it seems to be DTT7579 |
1131 | * compatible, with a slightly different MT352 AGC gain. */ | |
363c35fc | 1132 | fe0->dvb.frontend = dvb_attach(mt352_attach, |
f7b54b10 | 1133 | &dvico_fusionhdtv_dual, |
0590d91c | 1134 | &core->i2c_adap); |
363c35fc ST |
1135 | if (fe0->dvb.frontend != NULL) { |
1136 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1137 | 0x61, NULL, DVB_PLL_THOMSON_DTT7579)) |
1138 | goto frontend_detach; | |
c2af3cd6 MK |
1139 | break; |
1140 | } | |
c2af3cd6 | 1141 | /* ZL10353 replaces MT352 on later cards */ |
363c35fc | 1142 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
f7b54b10 | 1143 | &dvico_fusionhdtv_plus_v1_1, |
0590d91c | 1144 | &core->i2c_adap); |
363c35fc ST |
1145 | if (fe0->dvb.frontend != NULL) { |
1146 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1147 | 0x61, NULL, DVB_PLL_THOMSON_DTT7579)) |
1148 | goto frontend_detach; | |
c2af3cd6 | 1149 | } |
1da177e4 | 1150 | break; |
780dfef3 | 1151 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1: |
363c35fc | 1152 | fe0->dvb.frontend = dvb_attach(mt352_attach, |
f7b54b10 | 1153 | &dvico_fusionhdtv, |
0590d91c | 1154 | &core->i2c_adap); |
363c35fc ST |
1155 | if (fe0->dvb.frontend != NULL) { |
1156 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1157 | 0x61, NULL, DVB_PLL_LG_Z201)) |
1158 | goto frontend_detach; | |
f54376e2 | 1159 | } |
1da177e4 LT |
1160 | break; |
1161 | case CX88_BOARD_KWORLD_DVB_T: | |
1162 | case CX88_BOARD_DNTV_LIVE_DVB_T: | |
a82decf6 | 1163 | case CX88_BOARD_ADSTECH_DVB_T_PCI: |
363c35fc | 1164 | fe0->dvb.frontend = dvb_attach(mt352_attach, |
f7b54b10 | 1165 | &dntv_live_dvbt_config, |
0590d91c | 1166 | &core->i2c_adap); |
363c35fc ST |
1167 | if (fe0->dvb.frontend != NULL) { |
1168 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1169 | 0x61, NULL, DVB_PLL_UNKNOWN_1)) |
1170 | goto frontend_detach; | |
f54376e2 | 1171 | } |
1da177e4 | 1172 | break; |
fc40b261 | 1173 | case CX88_BOARD_DNTV_LIVE_DVB_T_PRO: |
7b34be71 | 1174 | #if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054) |
f0ad9097 | 1175 | /* MT352 is on a secondary I2C bus made from some GPIO lines */ |
363c35fc | 1176 | fe0->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config, |
f0ad9097 | 1177 | &dev->vp3054->adap); |
363c35fc ST |
1178 | if (fe0->dvb.frontend != NULL) { |
1179 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1180 | &core->i2c_adap, 0x61, |
1181 | TUNER_PHILIPS_FMD1216ME_MK3)) | |
1182 | goto frontend_detach; | |
f54376e2 | 1183 | } |
fc40b261 | 1184 | #else |
0590d91c MCC |
1185 | printk(KERN_ERR "%s/2: built without vp3054 support\n", |
1186 | core->name); | |
fc40b261 CP |
1187 | #endif |
1188 | break; | |
780dfef3 | 1189 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID: |
363c35fc | 1190 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
f7b54b10 | 1191 | &dvico_fusionhdtv_hybrid, |
0590d91c | 1192 | &core->i2c_adap); |
363c35fc ST |
1193 | if (fe0->dvb.frontend != NULL) { |
1194 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1195 | &core->i2c_adap, 0x61, |
1196 | TUNER_THOMSON_FE6600)) | |
1197 | goto frontend_detach; | |
f54376e2 | 1198 | } |
780dfef3 | 1199 | break; |
b3fb91d2 | 1200 | case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO: |
363c35fc | 1201 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
b3fb91d2 | 1202 | &dvico_fusionhdtv_xc3028, |
0590d91c | 1203 | &core->i2c_adap); |
363c35fc ST |
1204 | if (fe0->dvb.frontend == NULL) |
1205 | fe0->dvb.frontend = dvb_attach(mt352_attach, | |
b3fb91d2 | 1206 | &dvico_fusionhdtv_mt352_xc3028, |
0590d91c | 1207 | &core->i2c_adap); |
8765561f CP |
1208 | /* |
1209 | * On this board, the demod provides the I2C bus pullup. | |
1210 | * We must not permit gate_ctrl to be performed, or | |
1211 | * the xc3028 cannot communicate on the bus. | |
1212 | */ | |
363c35fc ST |
1213 | if (fe0->dvb.frontend) |
1214 | fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL; | |
23fb348d | 1215 | if (attach_xc3028(0x61, dev) < 0) |
becd4305 | 1216 | goto frontend_detach; |
b3fb91d2 | 1217 | break; |
1da177e4 | 1218 | case CX88_BOARD_PCHDTV_HD3000: |
363c35fc | 1219 | fe0->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000, |
0590d91c | 1220 | &core->i2c_adap); |
363c35fc ST |
1221 | if (fe0->dvb.frontend != NULL) { |
1222 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1223 | &core->i2c_adap, 0x61, |
1224 | TUNER_THOMSON_DTT761X)) | |
1225 | goto frontend_detach; | |
f54376e2 | 1226 | } |
1da177e4 | 1227 | break; |
f1798495 MK |
1228 | case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q: |
1229 | dev->ts_gen_cntrl = 0x08; | |
f1798495 | 1230 | |
0590d91c | 1231 | /* Do a hardware reset of chip before using it. */ |
f1798495 MK |
1232 | cx_clear(MO_GP0_IO, 1); |
1233 | mdelay(100); | |
0ccef6db | 1234 | cx_set(MO_GP0_IO, 1); |
f1798495 | 1235 | mdelay(200); |
0ccef6db MK |
1236 | |
1237 | /* Select RF connector callback */ | |
6ddcc919 | 1238 | fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set; |
363c35fc | 1239 | fe0->dvb.frontend = dvb_attach(lgdt330x_attach, |
f7b54b10 | 1240 | &fusionhdtv_3_gold, |
0590d91c | 1241 | &core->i2c_adap); |
363c35fc ST |
1242 | if (fe0->dvb.frontend != NULL) { |
1243 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1244 | &core->i2c_adap, 0x61, |
1245 | TUNER_MICROTUNE_4042FI5)) | |
1246 | goto frontend_detach; | |
f1798495 MK |
1247 | } |
1248 | break; | |
0d723c09 MK |
1249 | case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T: |
1250 | dev->ts_gen_cntrl = 0x08; | |
0d723c09 | 1251 | |
0590d91c | 1252 | /* Do a hardware reset of chip before using it. */ |
0d723c09 MK |
1253 | cx_clear(MO_GP0_IO, 1); |
1254 | mdelay(100); | |
d975872c | 1255 | cx_set(MO_GP0_IO, 9); |
0d723c09 | 1256 | mdelay(200); |
363c35fc | 1257 | fe0->dvb.frontend = dvb_attach(lgdt330x_attach, |
f7b54b10 | 1258 | &fusionhdtv_3_gold, |
0590d91c | 1259 | &core->i2c_adap); |
363c35fc ST |
1260 | if (fe0->dvb.frontend != NULL) { |
1261 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1262 | &core->i2c_adap, 0x61, |
1263 | TUNER_THOMSON_DTT761X)) | |
1264 | goto frontend_detach; | |
0d723c09 MK |
1265 | } |
1266 | break; | |
e52e98a7 MCC |
1267 | case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: |
1268 | dev->ts_gen_cntrl = 0x08; | |
e52e98a7 | 1269 | |
0590d91c | 1270 | /* Do a hardware reset of chip before using it. */ |
e52e98a7 MCC |
1271 | cx_clear(MO_GP0_IO, 1); |
1272 | mdelay(100); | |
1273 | cx_set(MO_GP0_IO, 1); | |
1274 | mdelay(200); | |
363c35fc | 1275 | fe0->dvb.frontend = dvb_attach(lgdt330x_attach, |
f7b54b10 | 1276 | &fusionhdtv_5_gold, |
0590d91c | 1277 | &core->i2c_adap); |
363c35fc ST |
1278 | if (fe0->dvb.frontend != NULL) { |
1279 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1280 | &core->i2c_adap, 0x61, |
1281 | TUNER_LG_TDVS_H06XF)) | |
1282 | goto frontend_detach; | |
363c35fc | 1283 | if (!dvb_attach(tda9887_attach, fe0->dvb.frontend, |
0590d91c MCC |
1284 | &core->i2c_adap, 0x43)) |
1285 | goto frontend_detach; | |
e52e98a7 MCC |
1286 | } |
1287 | break; | |
da215d22 RS |
1288 | case CX88_BOARD_PCHDTV_HD5500: |
1289 | dev->ts_gen_cntrl = 0x08; | |
da215d22 | 1290 | |
0590d91c | 1291 | /* Do a hardware reset of chip before using it. */ |
da215d22 RS |
1292 | cx_clear(MO_GP0_IO, 1); |
1293 | mdelay(100); | |
1294 | cx_set(MO_GP0_IO, 1); | |
1295 | mdelay(200); | |
363c35fc | 1296 | fe0->dvb.frontend = dvb_attach(lgdt330x_attach, |
f7b54b10 | 1297 | &pchdtv_hd5500, |
0590d91c | 1298 | &core->i2c_adap); |
363c35fc ST |
1299 | if (fe0->dvb.frontend != NULL) { |
1300 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1301 | &core->i2c_adap, 0x61, |
1302 | TUNER_LG_TDVS_H06XF)) | |
1303 | goto frontend_detach; | |
363c35fc | 1304 | if (!dvb_attach(tda9887_attach, fe0->dvb.frontend, |
0590d91c MCC |
1305 | &core->i2c_adap, 0x43)) |
1306 | goto frontend_detach; | |
da215d22 RS |
1307 | } |
1308 | break; | |
fde6d31e | 1309 | case CX88_BOARD_ATI_HDTVWONDER: |
363c35fc | 1310 | fe0->dvb.frontend = dvb_attach(nxt200x_attach, |
f7b54b10 | 1311 | &ati_hdtvwonder, |
0590d91c | 1312 | &core->i2c_adap); |
363c35fc ST |
1313 | if (fe0->dvb.frontend != NULL) { |
1314 | if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
0590d91c MCC |
1315 | &core->i2c_adap, 0x61, |
1316 | TUNER_PHILIPS_TUV1236D)) | |
1317 | goto frontend_detach; | |
f54376e2 | 1318 | } |
0fa14aa6 | 1319 | break; |
0fa14aa6 ST |
1320 | case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1: |
1321 | case CX88_BOARD_HAUPPAUGE_NOVASE2_S1: | |
363c35fc | 1322 | fe0->dvb.frontend = dvb_attach(cx24123_attach, |
f7b54b10 | 1323 | &hauppauge_novas_config, |
0590d91c | 1324 | &core->i2c_adap); |
363c35fc | 1325 | if (fe0->dvb.frontend) { |
48a8a03b MCC |
1326 | bool override_tone; |
1327 | ||
1328 | if (core->model == 92001) | |
1329 | override_tone = true; | |
1330 | else | |
1331 | override_tone = false; | |
1332 | ||
363c35fc | 1333 | if (!dvb_attach(isl6421_attach, fe0->dvb.frontend, |
48a8a03b MCC |
1334 | &core->i2c_adap, 0x08, ISL6421_DCL, 0x00, |
1335 | override_tone)) | |
0590d91c | 1336 | goto frontend_detach; |
cd20ca9f | 1337 | } |
0e0351e3 VC |
1338 | break; |
1339 | case CX88_BOARD_KWORLD_DVBS_100: | |
363c35fc | 1340 | fe0->dvb.frontend = dvb_attach(cx24123_attach, |
f7b54b10 | 1341 | &kworld_dvbs_100_config, |
0590d91c | 1342 | &core->i2c_adap); |
363c35fc ST |
1343 | if (fe0->dvb.frontend) { |
1344 | core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage; | |
1345 | fe0->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage; | |
cd20ca9f | 1346 | } |
fde6d31e | 1347 | break; |
c02a34f4 | 1348 | case CX88_BOARD_GENIATECH_DVBS: |
363c35fc | 1349 | fe0->dvb.frontend = dvb_attach(cx24123_attach, |
f7b54b10 | 1350 | &geniatech_dvbs_config, |
0590d91c | 1351 | &core->i2c_adap); |
363c35fc ST |
1352 | if (fe0->dvb.frontend) { |
1353 | core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage; | |
1354 | fe0->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage; | |
c02a34f4 SA |
1355 | } |
1356 | break; | |
60464da8 | 1357 | case CX88_BOARD_PINNACLE_PCTV_HD_800i: |
363c35fc | 1358 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
60464da8 | 1359 | &pinnacle_pctv_hd_800i_config, |
0590d91c | 1360 | &core->i2c_adap); |
363c35fc ST |
1361 | if (fe0->dvb.frontend != NULL) { |
1362 | if (!dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
0590d91c | 1363 | &core->i2c_adap, |
30650961 | 1364 | &pinnacle_pctv_hd_800i_tuner_config)) |
0590d91c | 1365 | goto frontend_detach; |
60464da8 ST |
1366 | } |
1367 | break; | |
5c00fac0 | 1368 | case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO: |
363c35fc | 1369 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
5c00fac0 | 1370 | &dvico_hdtv5_pci_nano_config, |
0590d91c | 1371 | &core->i2c_adap); |
363c35fc | 1372 | if (fe0->dvb.frontend != NULL) { |
5c00fac0 ST |
1373 | struct dvb_frontend *fe; |
1374 | struct xc2028_config cfg = { | |
0590d91c | 1375 | .i2c_adap = &core->i2c_adap, |
5c00fac0 | 1376 | .i2c_addr = 0x61, |
5c00fac0 ST |
1377 | }; |
1378 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 1379 | .fname = XC2028_DEFAULT_FIRMWARE, |
5c00fac0 | 1380 | .max_len = 64, |
33e53161 | 1381 | .scode_table = XC3028_FE_OREN538, |
5c00fac0 ST |
1382 | }; |
1383 | ||
1384 | fe = dvb_attach(xc2028_attach, | |
363c35fc | 1385 | fe0->dvb.frontend, &cfg); |
5c00fac0 ST |
1386 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) |
1387 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
1388 | } | |
1389 | break; | |
d49f7a24 | 1390 | case CX88_BOARD_PINNACLE_HYBRID_PCTV: |
3047a176 | 1391 | case CX88_BOARD_WINFAST_DTV1800H: |
363c35fc | 1392 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
3f6014fc | 1393 | &cx88_pinnacle_hybrid_pctv, |
0590d91c | 1394 | &core->i2c_adap); |
363c35fc ST |
1395 | if (fe0->dvb.frontend) { |
1396 | fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL; | |
3f6014fc SV |
1397 | if (attach_xc3028(0x61, dev) < 0) |
1398 | goto frontend_detach; | |
1399 | } | |
9507901e | 1400 | break; |
8eb79c0b | 1401 | case CX88_BOARD_WINFAST_DTV1800H_XC4000: |
f271a3af | 1402 | case CX88_BOARD_WINFAST_DTV2000H_PLUS: |
1403 | fe0->dvb.frontend = dvb_attach(zl10353_attach, | |
1404 | &cx88_pinnacle_hybrid_pctv, | |
1405 | &core->i2c_adap); | |
1406 | if (fe0->dvb.frontend) { | |
1407 | struct xc4000_config cfg = { | |
1408 | .i2c_address = 0x61, | |
1409 | .default_pm = 0, | |
1410 | .dvb_amplitude = 134, | |
1411 | .set_smoothedcvbs = 1, | |
1412 | .if_khz = 4560 | |
1413 | }; | |
1414 | fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL; | |
1415 | if (attach_xc4000(dev, &cfg) < 0) | |
1416 | goto frontend_detach; | |
1417 | } | |
1418 | break; | |
1419 | case CX88_BOARD_GENIATECH_X8000_MT: | |
99e09eac | 1420 | dev->ts_gen_cntrl = 0x00; |
9507901e | 1421 | |
363c35fc | 1422 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
9507901e | 1423 | &cx88_geniatech_x8000_mt, |
0590d91c | 1424 | &core->i2c_adap); |
23fb348d | 1425 | if (attach_xc3028(0x61, dev) < 0) |
0590d91c | 1426 | goto frontend_detach; |
9507901e | 1427 | break; |
99e09eac | 1428 | case CX88_BOARD_KWORLD_ATSC_120: |
363c35fc | 1429 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
99e09eac | 1430 | &kworld_atsc_120_config, |
0590d91c | 1431 | &core->i2c_adap); |
99e09eac | 1432 | if (attach_xc3028(0x61, dev) < 0) |
0590d91c | 1433 | goto frontend_detach; |
99e09eac | 1434 | break; |
d893d5dc | 1435 | case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: |
363c35fc | 1436 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, |
d893d5dc | 1437 | &dvico_fusionhdtv7_config, |
0590d91c | 1438 | &core->i2c_adap); |
363c35fc ST |
1439 | if (fe0->dvb.frontend != NULL) { |
1440 | if (!dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
0590d91c | 1441 | &core->i2c_adap, |
30650961 | 1442 | &dvico_fusionhdtv7_tuner_config)) |
0590d91c | 1443 | goto frontend_detach; |
d893d5dc ST |
1444 | } |
1445 | break; | |
5bd1b663 | 1446 | case CX88_BOARD_HAUPPAUGE_HVR4000: |
60a5a927 DB |
1447 | /* MFE frontend 1 */ |
1448 | mfe_shared = 1; | |
1449 | dev->frontends.gate = 2; | |
363c35fc ST |
1450 | /* DVB-S/S2 Init */ |
1451 | fe0->dvb.frontend = dvb_attach(cx24116_attach, | |
60a5a927 DB |
1452 | &hauppauge_hvr4000_config, |
1453 | &dev->core->i2c_adap); | |
363c35fc | 1454 | if (fe0->dvb.frontend) { |
60a5a927 DB |
1455 | if (!dvb_attach(isl6421_attach, |
1456 | fe0->dvb.frontend, | |
1457 | &dev->core->i2c_adap, | |
48a8a03b | 1458 | 0x08, ISL6421_DCL, 0x00, false)) |
60a5a927 | 1459 | goto frontend_detach; |
363c35fc | 1460 | } |
60a5a927 | 1461 | /* MFE frontend 2 */ |
0b6b6302 | 1462 | fe1 = vb2_dvb_get_frontend(&dev->frontends, 2); |
60a5a927 DB |
1463 | if (!fe1) |
1464 | goto frontend_detach; | |
1465 | /* DVB-T Init */ | |
1466 | fe1->dvb.frontend = dvb_attach(cx22702_attach, | |
1467 | &hauppauge_hvr_config, | |
1468 | &dev->core->i2c_adap); | |
1469 | if (fe1->dvb.frontend) { | |
1470 | fe1->dvb.frontend->id = 1; | |
1471 | if (!dvb_attach(simple_tuner_attach, | |
1472 | fe1->dvb.frontend, | |
1473 | &dev->core->i2c_adap, | |
1474 | 0x61, TUNER_PHILIPS_FMD1216ME_MK3)) | |
1475 | goto frontend_detach; | |
363c35fc ST |
1476 | } |
1477 | break; | |
5bd1b663 | 1478 | case CX88_BOARD_HAUPPAUGE_HVR4000LITE: |
363c35fc | 1479 | fe0->dvb.frontend = dvb_attach(cx24116_attach, |
60a5a927 DB |
1480 | &hauppauge_hvr4000_config, |
1481 | &dev->core->i2c_adap); | |
363c35fc | 1482 | if (fe0->dvb.frontend) { |
60a5a927 DB |
1483 | if (!dvb_attach(isl6421_attach, |
1484 | fe0->dvb.frontend, | |
1485 | &dev->core->i2c_adap, | |
48a8a03b | 1486 | 0x08, ISL6421_DCL, 0x00, false)) |
60a5a927 | 1487 | goto frontend_detach; |
5bd1b663 ST |
1488 | } |
1489 | break; | |
cd3cde12 | 1490 | case CX88_BOARD_PROF_6200: |
4b29631d | 1491 | case CX88_BOARD_TBS_8910: |
e4aab64c | 1492 | case CX88_BOARD_TEVII_S420: |
363c35fc | 1493 | fe0->dvb.frontend = dvb_attach(stv0299_attach, |
e4aab64c IL |
1494 | &tevii_tuner_sharp_config, |
1495 | &core->i2c_adap); | |
363c35fc ST |
1496 | if (fe0->dvb.frontend != NULL) { |
1497 | if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60, | |
e4aab64c IL |
1498 | &core->i2c_adap, DVB_PLL_OPERA1)) |
1499 | goto frontend_detach; | |
363c35fc ST |
1500 | core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage; |
1501 | fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; | |
e4aab64c IL |
1502 | |
1503 | } else { | |
363c35fc | 1504 | fe0->dvb.frontend = dvb_attach(stv0288_attach, |
e4aab64c IL |
1505 | &tevii_tuner_earda_config, |
1506 | &core->i2c_adap); | |
86c330fa MCC |
1507 | if (fe0->dvb.frontend != NULL) { |
1508 | if (!dvb_attach(stb6000_attach, fe0->dvb.frontend, 0x61, | |
e4aab64c IL |
1509 | &core->i2c_adap)) |
1510 | goto frontend_detach; | |
363c35fc ST |
1511 | core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage; |
1512 | fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; | |
e4aab64c IL |
1513 | } |
1514 | } | |
1515 | break; | |
af832623 | 1516 | case CX88_BOARD_TEVII_S460: |
363c35fc | 1517 | fe0->dvb.frontend = dvb_attach(cx24116_attach, |
af832623 IL |
1518 | &tevii_s460_config, |
1519 | &core->i2c_adap); | |
93f26c14 | 1520 | if (fe0->dvb.frontend != NULL) |
363c35fc | 1521 | fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; |
4cd7fb87 | 1522 | break; |
0cb73639 IL |
1523 | case CX88_BOARD_TEVII_S464: |
1524 | fe0->dvb.frontend = dvb_attach(ds3000_attach, | |
1525 | &tevii_ds3000_config, | |
1526 | &core->i2c_adap); | |
73f0af44 KD |
1527 | if (fe0->dvb.frontend != NULL) { |
1528 | dvb_attach(ts2020_attach, fe0->dvb.frontend, | |
1529 | &tevii_ts2020_config, &core->i2c_adap); | |
0cb73639 IL |
1530 | fe0->dvb.frontend->ops.set_voltage = |
1531 | tevii_dvbs_set_voltage; | |
73f0af44 | 1532 | } |
0cb73639 | 1533 | break; |
4cd7fb87 | 1534 | case CX88_BOARD_OMICOM_SS4_PCI: |
ee73042c | 1535 | case CX88_BOARD_TBS_8920: |
57f51dbc | 1536 | case CX88_BOARD_PROF_7300: |
4b29631d | 1537 | case CX88_BOARD_SATTRADE_ST4200: |
363c35fc | 1538 | fe0->dvb.frontend = dvb_attach(cx24116_attach, |
ee73042c OR |
1539 | &hauppauge_hvr4000_config, |
1540 | &core->i2c_adap); | |
93f26c14 | 1541 | if (fe0->dvb.frontend != NULL) |
363c35fc | 1542 | fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage; |
af832623 | 1543 | break; |
70101a27 SW |
1544 | case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII: |
1545 | fe0->dvb.frontend = dvb_attach(zl10353_attach, | |
1546 | &cx88_terratec_cinergy_ht_pci_mkii_config, | |
1547 | &core->i2c_adap); | |
1548 | if (fe0->dvb.frontend) { | |
1549 | fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL; | |
1550 | if (attach_xc3028(0x61, dev) < 0) | |
1551 | goto frontend_detach; | |
1552 | } | |
1553 | break; | |
b699c271 IL |
1554 | case CX88_BOARD_PROF_7301:{ |
1555 | struct dvb_tuner_ops *tuner_ops = NULL; | |
1556 | ||
1557 | fe0->dvb.frontend = dvb_attach(stv0900_attach, | |
1558 | &prof_7301_stv0900_config, | |
1559 | &core->i2c_adap, 0); | |
1560 | if (fe0->dvb.frontend != NULL) { | |
1561 | if (!dvb_attach(stb6100_attach, fe0->dvb.frontend, | |
1562 | &prof_7301_stb6100_config, | |
1563 | &core->i2c_adap)) | |
1564 | goto frontend_detach; | |
1565 | ||
1566 | tuner_ops = &fe0->dvb.frontend->ops.tuner_ops; | |
1567 | tuner_ops->set_frequency = stb6100_set_freq; | |
1568 | tuner_ops->get_frequency = stb6100_get_freq; | |
1569 | tuner_ops->set_bandwidth = stb6100_set_bandw; | |
1570 | tuner_ops->get_bandwidth = stb6100_get_bandw; | |
1571 | ||
1572 | core->prev_set_voltage = | |
1573 | fe0->dvb.frontend->ops.set_voltage; | |
1574 | fe0->dvb.frontend->ops.set_voltage = | |
1575 | tevii_dvbs_set_voltage; | |
1576 | } | |
1577 | break; | |
1578 | } | |
4f3ca2f1 DH |
1579 | case CX88_BOARD_SAMSUNG_SMT_7020: |
1580 | dev->ts_gen_cntrl = 0x08; | |
1581 | ||
4f3ca2f1 DH |
1582 | cx_set(MO_GP0_IO, 0x0101); |
1583 | ||
1584 | cx_clear(MO_GP0_IO, 0x01); | |
1585 | mdelay(100); | |
1586 | cx_set(MO_GP0_IO, 0x01); | |
1587 | mdelay(200); | |
1588 | ||
1589 | fe0->dvb.frontend = dvb_attach(stv0299_attach, | |
1590 | &samsung_stv0299_config, | |
1591 | &dev->core->i2c_adap); | |
1592 | if (fe0->dvb.frontend) { | |
1593 | fe0->dvb.frontend->ops.tuner_ops.set_params = | |
1594 | samsung_smt_7020_tuner_set_params; | |
1595 | fe0->dvb.frontend->tuner_priv = | |
1596 | &dev->core->i2c_adap; | |
1597 | fe0->dvb.frontend->ops.set_voltage = | |
1598 | samsung_smt_7020_set_voltage; | |
1599 | fe0->dvb.frontend->ops.set_tone = | |
1600 | samsung_smt_7020_set_tone; | |
1601 | } | |
1602 | ||
1603 | break; | |
111ac84a SI |
1604 | case CX88_BOARD_TWINHAN_VP1027_DVBS: |
1605 | dev->ts_gen_cntrl = 0x00; | |
1606 | fe0->dvb.frontend = dvb_attach(mb86a16_attach, | |
1607 | &twinhan_vp1027, | |
1608 | &core->i2c_adap); | |
1609 | if (fe0->dvb.frontend) { | |
1610 | core->prev_set_voltage = | |
1611 | fe0->dvb.frontend->ops.set_voltage; | |
1612 | fe0->dvb.frontend->ops.set_voltage = | |
1613 | vp1027_set_voltage; | |
1614 | } | |
1615 | break; | |
4f3ca2f1 | 1616 | |
1da177e4 | 1617 | default: |
5772f813 | 1618 | printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n", |
0590d91c | 1619 | core->name); |
1da177e4 LT |
1620 | break; |
1621 | } | |
363c35fc | 1622 | |
2c9bcea1 | 1623 | if ( (NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend) ) { |
9507901e MCC |
1624 | printk(KERN_ERR |
1625 | "%s/2: frontend initialization failed\n", | |
0590d91c | 1626 | core->name); |
60a5a927 | 1627 | goto frontend_detach; |
9507901e | 1628 | } |
d7cba043 | 1629 | /* define general-purpose callback pointer */ |
363c35fc | 1630 | fe0->dvb.frontend->callback = cx88_tuner_callback; |
9507901e | 1631 | |
6c5be74c | 1632 | /* Ensure all frontends negotiate bus access */ |
363c35fc ST |
1633 | fe0->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl; |
1634 | if (fe1) | |
1635 | fe1->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl; | |
1da177e4 | 1636 | |
93352f5c | 1637 | /* Put the analog decoder in standby to keep it quiet */ |
622b828a | 1638 | call_all(core, core, s_power, 0); |
93352f5c | 1639 | |
1da177e4 | 1640 | /* register everything */ |
0b6b6302 | 1641 | res = vb2_dvb_register_bus(&dev->frontends, THIS_MODULE, dev, |
9adf6132 | 1642 | &dev->pci->dev, adapter_nr, mfe_shared); |
7b0962d3 DF |
1643 | if (res) |
1644 | goto frontend_detach; | |
1645 | return res; | |
0590d91c MCC |
1646 | |
1647 | frontend_detach: | |
e32fadc4 | 1648 | core->gate_ctrl = NULL; |
0b6b6302 | 1649 | vb2_dvb_dealloc_frontends(&dev->frontends); |
7b0962d3 | 1650 | return res; |
1da177e4 LT |
1651 | } |
1652 | ||
1653 | /* ----------------------------------------------------------- */ | |
1654 | ||
6c5be74c ST |
1655 | /* CX8802 MPEG -> mini driver - We have been given the hardware */ |
1656 | static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv) | |
1da177e4 | 1657 | { |
6c5be74c ST |
1658 | struct cx88_core *core = drv->core; |
1659 | int err = 0; | |
32d83efc | 1660 | dprintk( 1, "%s\n", __func__); |
6c5be74c | 1661 | |
6a59d64c | 1662 | switch (core->boardnr) { |
6c5be74c ST |
1663 | case CX88_BOARD_HAUPPAUGE_HVR1300: |
1664 | /* We arrive here with either the cx23416 or the cx22702 | |
1665 | * on the bus. Take the bus from the cx23416 and enable the | |
1666 | * cx22702 demod | |
1667 | */ | |
79392737 DB |
1668 | /* Toggle reset on cx22702 leaving i2c active */ |
1669 | cx_set(MO_GP0_IO, 0x00000080); | |
1670 | udelay(1000); | |
1671 | cx_clear(MO_GP0_IO, 0x00000080); | |
1672 | udelay(50); | |
1673 | cx_set(MO_GP0_IO, 0x00000080); | |
1674 | udelay(1000); | |
1675 | /* enable the cx22702 pins */ | |
6c5be74c ST |
1676 | cx_clear(MO_GP0_IO, 0x00000004); |
1677 | udelay(1000); | |
1678 | break; | |
363c35fc | 1679 | |
92abe9ee | 1680 | case CX88_BOARD_HAUPPAUGE_HVR3000: |
363c35fc | 1681 | case CX88_BOARD_HAUPPAUGE_HVR4000: |
79392737 DB |
1682 | /* Toggle reset on cx22702 leaving i2c active */ |
1683 | cx_set(MO_GP0_IO, 0x00000080); | |
1684 | udelay(1000); | |
1685 | cx_clear(MO_GP0_IO, 0x00000080); | |
1686 | udelay(50); | |
1687 | cx_set(MO_GP0_IO, 0x00000080); | |
1688 | udelay(1000); | |
1689 | switch (core->dvbdev->frontends.active_fe_id) { | |
1690 | case 1: /* DVB-S/S2 Enabled */ | |
1691 | /* tri-state the cx22702 pins */ | |
1692 | cx_set(MO_GP0_IO, 0x00000004); | |
1693 | /* Take the cx24116/cx24123 out of reset */ | |
1694 | cx_write(MO_SRST_IO, 1); | |
363c35fc | 1695 | core->dvbdev->ts_gen_cntrl = 0x02; /* Parallel IO */ |
79392737 DB |
1696 | break; |
1697 | case 2: /* DVB-T Enabled */ | |
363c35fc ST |
1698 | /* Put the cx24116/cx24123 into reset */ |
1699 | cx_write(MO_SRST_IO, 0); | |
79392737 | 1700 | /* enable the cx22702 pins */ |
363c35fc ST |
1701 | cx_clear(MO_GP0_IO, 0x00000004); |
1702 | core->dvbdev->ts_gen_cntrl = 0x0c; /* Serial IO */ | |
79392737 | 1703 | break; |
363c35fc | 1704 | } |
79392737 | 1705 | udelay(1000); |
363c35fc ST |
1706 | break; |
1707 | ||
f271a3af | 1708 | case CX88_BOARD_WINFAST_DTV2000H_PLUS: |
1709 | /* set RF input to AIR for DVB-T (GPIO 16) */ | |
1710 | cx_write(MO_GP2_IO, 0x0101); | |
1711 | break; | |
1712 | ||
6c5be74c ST |
1713 | default: |
1714 | err = -ENODEV; | |
1715 | } | |
1716 | return err; | |
1717 | } | |
1718 | ||
1719 | /* CX8802 MPEG -> mini driver - We no longer have the hardware */ | |
1720 | static int cx8802_dvb_advise_release(struct cx8802_driver *drv) | |
1721 | { | |
1722 | struct cx88_core *core = drv->core; | |
1723 | int err = 0; | |
32d83efc | 1724 | dprintk( 1, "%s\n", __func__); |
6c5be74c | 1725 | |
6a59d64c | 1726 | switch (core->boardnr) { |
6c5be74c ST |
1727 | case CX88_BOARD_HAUPPAUGE_HVR1300: |
1728 | /* Do Nothing, leave the cx22702 on the bus. */ | |
1729 | break; | |
363c35fc ST |
1730 | case CX88_BOARD_HAUPPAUGE_HVR3000: |
1731 | case CX88_BOARD_HAUPPAUGE_HVR4000: | |
1732 | break; | |
6c5be74c ST |
1733 | default: |
1734 | err = -ENODEV; | |
1735 | } | |
1736 | return err; | |
1737 | } | |
1738 | ||
1739 | static int cx8802_dvb_probe(struct cx8802_driver *drv) | |
1740 | { | |
1741 | struct cx88_core *core = drv->core; | |
1742 | struct cx8802_dev *dev = drv->core->dvbdev; | |
cbd82441 | 1743 | int err; |
0b6b6302 | 1744 | struct vb2_dvb_frontend *fe; |
6e0e12f1 | 1745 | int i; |
1da177e4 | 1746 | |
32d83efc | 1747 | dprintk( 1, "%s\n", __func__); |
6c5be74c | 1748 | dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n", |
6a59d64c | 1749 | core->boardnr, |
6c5be74c ST |
1750 | core->name, |
1751 | core->pci_bus, | |
1752 | core->pci_slot); | |
1da177e4 LT |
1753 | |
1754 | err = -ENODEV; | |
6a59d64c | 1755 | if (!(core->board.mpeg & CX88_MPEG_DVB)) |
1da177e4 LT |
1756 | goto fail_core; |
1757 | ||
ecf854df | 1758 | /* If vp3054 isn't enabled, a stub will just return 0 */ |
fc40b261 CP |
1759 | err = vp3054_i2c_probe(dev); |
1760 | if (0 != err) | |
6e0e12f1 | 1761 | goto fail_core; |
fc40b261 | 1762 | |
1da177e4 | 1763 | /* dvb stuff */ |
5772f813 | 1764 | printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name); |
363c35fc ST |
1765 | dev->ts_gen_cntrl = 0x0c; |
1766 | ||
6e0e12f1 AW |
1767 | err = cx8802_alloc_frontends(dev); |
1768 | if (err) | |
1769 | goto fail_core; | |
1770 | ||
cbd82441 | 1771 | err = -ENODEV; |
6e0e12f1 | 1772 | for (i = 1; i <= core->board.num_frontends; i++) { |
0b6b6302 HV |
1773 | struct vb2_queue *q; |
1774 | ||
1775 | fe = vb2_dvb_get_frontend(&core->dvbdev->frontends, i); | |
6e0e12f1 AW |
1776 | if (fe == NULL) { |
1777 | printk(KERN_ERR "%s() failed to get frontend(%d)\n", | |
cbd82441 | 1778 | __func__, i); |
6e0e12f1 AW |
1779 | goto fail_probe; |
1780 | } | |
0b6b6302 HV |
1781 | q = &fe->dvb.dvbq; |
1782 | q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
1783 | q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; | |
1784 | q->gfp_flags = GFP_DMA32; | |
1785 | q->min_buffers_needed = 2; | |
1786 | q->drv_priv = dev; | |
1787 | q->buf_struct_size = sizeof(struct cx88_buffer); | |
1788 | q->ops = &dvb_qops; | |
1789 | q->mem_ops = &vb2_dma_sg_memops; | |
1790 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
1791 | q->lock = &core->lock; | |
1792 | ||
1793 | err = vb2_queue_init(q); | |
1794 | if (err < 0) | |
1795 | goto fail_probe; | |
1796 | ||
1797 | /* init struct vb2_dvb */ | |
6e0e12f1 | 1798 | fe->dvb.name = dev->core->name; |
363c35fc | 1799 | } |
6e0e12f1 | 1800 | |
1da177e4 | 1801 | err = dvb_register(dev); |
cbd82441 DB |
1802 | if (err) |
1803 | /* frontends/adapter de-allocated in dvb_register */ | |
5772f813 TP |
1804 | printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n", |
1805 | core->name, err); | |
cbd82441 DB |
1806 | return err; |
1807 | fail_probe: | |
0b6b6302 | 1808 | vb2_dvb_dealloc_frontends(&core->dvbdev->frontends); |
92abe9ee | 1809 | fail_core: |
1da177e4 LT |
1810 | return err; |
1811 | } | |
1812 | ||
6c5be74c | 1813 | static int cx8802_dvb_remove(struct cx8802_driver *drv) |
1da177e4 | 1814 | { |
0fcd488d | 1815 | struct cx88_core *core = drv->core; |
6c5be74c | 1816 | struct cx8802_dev *dev = drv->core->dvbdev; |
611900c1 | 1817 | |
0fcd488d DB |
1818 | dprintk( 1, "%s\n", __func__); |
1819 | ||
0b6b6302 | 1820 | vb2_dvb_unregister_bus(&dev->frontends); |
1da177e4 | 1821 | |
fc40b261 | 1822 | vp3054_i2c_remove(dev); |
fc40b261 | 1823 | |
e32fadc4 MCC |
1824 | core->gate_ctrl = NULL; |
1825 | ||
6c5be74c | 1826 | return 0; |
1da177e4 LT |
1827 | } |
1828 | ||
6c5be74c ST |
1829 | static struct cx8802_driver cx8802_dvb_driver = { |
1830 | .type_id = CX88_MPEG_DVB, | |
1831 | .hw_access = CX8802_DRVCTL_SHARED, | |
1832 | .probe = cx8802_dvb_probe, | |
1833 | .remove = cx8802_dvb_remove, | |
1834 | .advise_acquire = cx8802_dvb_advise_acquire, | |
1835 | .advise_release = cx8802_dvb_advise_release, | |
1da177e4 LT |
1836 | }; |
1837 | ||
31d0f845 | 1838 | static int __init dvb_init(void) |
1da177e4 | 1839 | { |
1990d50b MCC |
1840 | printk(KERN_INFO "cx88/2: cx2388x dvb driver version %s loaded\n", |
1841 | CX88_VERSION); | |
6c5be74c | 1842 | return cx8802_register_driver(&cx8802_dvb_driver); |
1da177e4 LT |
1843 | } |
1844 | ||
31d0f845 | 1845 | static void __exit dvb_fini(void) |
1da177e4 | 1846 | { |
6c5be74c | 1847 | cx8802_unregister_driver(&cx8802_dvb_driver); |
1da177e4 LT |
1848 | } |
1849 | ||
1850 | module_init(dvb_init); | |
1851 | module_exit(dvb_fini); |