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1a9fc855 MCC |
1 | /* |
2 | * Driver for the Conexant CX25821 PCIe bridge | |
3 | * | |
4 | * Copyright (C) 2009 Conexant Systems Inc. | |
5 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * | |
16 | * GNU General Public License for more details. | |
1a9fc855 MCC |
17 | */ |
18 | ||
19 | #ifndef __ATHENA_SRAM_H__ | |
20 | #define __ATHENA_SRAM_H__ | |
21 | ||
1852a1bf MCC |
22 | /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */ |
23 | #define VID_CMDS_SIZE 80 /* Video CMDS size in bytes */ | |
24 | #define AUDIO_CMDS_SIZE 80 /* AUDIO CMDS size in bytes */ | |
25 | #define MBIF_CMDS_SIZE 80 /* MBIF CMDS size in bytes */ | |
1a9fc855 | 26 | |
16790554 | 27 | /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */ |
1852a1bf | 28 | #define VID_IQ_SIZE 64 /* VID instruction queue size in bytes */ |
1a9fc855 | 29 | #define MBIF_IQ_SIZE 64 |
1852a1bf | 30 | #define AUDIO_IQ_SIZE 64 /* AUD instruction queue size in bytes */ |
1a9fc855 | 31 | |
1852a1bf MCC |
32 | #define VID_CDT_SIZE 64 /* VID cluster descriptor table size in bytes */ |
33 | #define MBIF_CDT_SIZE 64 /* MBIF/HBI cluster descriptor table size in bytes */ | |
34 | #define AUDIO_CDT_SIZE 48 /* AUD cluster descriptor table size in bytes */ | |
1a9fc855 | 35 | |
1852a1bf MCC |
36 | /* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */ |
37 | /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */ | |
1a9fc855 | 38 | |
1852a1bf MCC |
39 | /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */ |
40 | /* #define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora */ | |
1a9fc855 | 41 | |
1852a1bf MCC |
42 | #define VID_CLUSTER_SIZE 1440 /* VID cluster data line */ |
43 | #define AUDIO_CLUSTER_SIZE 128 /* AUDIO cluster data line */ | |
44 | #define MBIF_CLUSTER_SIZE 1440 /* MBIF/HBI cluster data line */ | |
1a9fc855 | 45 | |
1852a1bf MCC |
46 | /* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */ |
47 | /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */ | |
1a9fc855 | 48 | |
1852a1bf | 49 | /* Receive SRAM */ |
1a9fc855 MCC |
50 | #define RX_SRAM_START 0x10000 |
51 | #define VID_A_DOWN_CMDS 0x10000 | |
52 | #define VID_B_DOWN_CMDS 0x10050 | |
53 | #define VID_C_DOWN_CMDS 0x100A0 | |
54 | #define VID_D_DOWN_CMDS 0x100F0 | |
55 | #define VID_E_DOWN_CMDS 0x10140 | |
56 | #define VID_F_DOWN_CMDS 0x10190 | |
57 | #define VID_G_DOWN_CMDS 0x101E0 | |
58 | #define VID_H_DOWN_CMDS 0x10230 | |
59 | #define VID_A_UP_CMDS 0x10280 | |
60 | #define VID_B_UP_CMDS 0x102D0 | |
61 | #define VID_C_UP_CMDS 0x10320 | |
62 | #define VID_D_UP_CMDS 0x10370 | |
63 | #define VID_E_UP_CMDS 0x103C0 | |
64 | #define VID_F_UP_CMDS 0x10410 | |
65 | #define VID_I_UP_CMDS 0x10460 | |
66 | #define VID_J_UP_CMDS 0x104B0 | |
67 | #define AUD_A_DOWN_CMDS 0x10500 | |
68 | #define AUD_B_DOWN_CMDS 0x10550 | |
69 | #define AUD_C_DOWN_CMDS 0x105A0 | |
70 | #define AUD_D_DOWN_CMDS 0x105F0 | |
71 | #define AUD_A_UP_CMDS 0x10640 | |
72 | #define AUD_B_UP_CMDS 0x10690 | |
73 | #define AUD_C_UP_CMDS 0x106E0 | |
74 | #define AUD_E_UP_CMDS 0x10730 | |
75 | #define MBIF_A_DOWN_CMDS 0x10780 | |
76 | #define MBIF_B_DOWN_CMDS 0x107D0 | |
1852a1bf | 77 | #define DMA_SCRATCH_PAD 0x10820 /* Scratch pad area from 0x10820 to 0x10B40 */ |
1a9fc855 | 78 | |
1852a1bf | 79 | /* #define RX_SRAM_POOL_START = 0x105B0; */ |
1a9fc855 MCC |
80 | |
81 | #define VID_A_IQ 0x11000 | |
82 | #define VID_B_IQ 0x11040 | |
83 | #define VID_C_IQ 0x11080 | |
84 | #define VID_D_IQ 0x110C0 | |
85 | #define VID_E_IQ 0x11100 | |
86 | #define VID_F_IQ 0x11140 | |
87 | #define VID_G_IQ 0x11180 | |
88 | #define VID_H_IQ 0x111C0 | |
89 | #define VID_I_IQ 0x11200 | |
90 | #define VID_J_IQ 0x11240 | |
91 | #define AUD_A_IQ 0x11280 | |
92 | #define AUD_B_IQ 0x112C0 | |
93 | #define AUD_C_IQ 0x11300 | |
94 | #define AUD_D_IQ 0x11340 | |
95 | #define AUD_E_IQ 0x11380 | |
96 | #define MBIF_A_IQ 0x11000 | |
97 | #define MBIF_B_IQ 0x110C0 | |
98 | ||
99 | #define VID_A_CDT 0x10C00 | |
100 | #define VID_B_CDT 0x10C40 | |
101 | #define VID_C_CDT 0x10C80 | |
102 | #define VID_D_CDT 0x10CC0 | |
103 | #define VID_E_CDT 0x10D00 | |
104 | #define VID_F_CDT 0x10D40 | |
105 | #define VID_G_CDT 0x10D80 | |
106 | #define VID_H_CDT 0x10DC0 | |
107 | #define VID_I_CDT 0x10E00 | |
108 | #define VID_J_CDT 0x10E40 | |
109 | #define AUD_A_CDT 0x10E80 | |
110 | #define AUD_B_CDT 0x10EB0 | |
111 | #define AUD_C_CDT 0x10EE0 | |
112 | #define AUD_D_CDT 0x10F10 | |
113 | #define AUD_E_CDT 0x10F40 | |
114 | #define MBIF_A_CDT 0x10C00 | |
115 | #define MBIF_B_CDT 0x10CC0 | |
116 | ||
1852a1bf | 117 | /* Cluster Buffer for RX */ |
1a9fc855 MCC |
118 | #define VID_A_UP_CLUSTER_1 0x11400 |
119 | #define VID_A_UP_CLUSTER_2 0x119A0 | |
120 | #define VID_A_UP_CLUSTER_3 0x11F40 | |
121 | #define VID_A_UP_CLUSTER_4 0x124E0 | |
122 | ||
123 | #define VID_B_UP_CLUSTER_1 0x12A80 | |
124 | #define VID_B_UP_CLUSTER_2 0x13020 | |
125 | #define VID_B_UP_CLUSTER_3 0x135C0 | |
126 | #define VID_B_UP_CLUSTER_4 0x13B60 | |
127 | ||
128 | #define VID_C_UP_CLUSTER_1 0x14100 | |
129 | #define VID_C_UP_CLUSTER_2 0x146A0 | |
130 | #define VID_C_UP_CLUSTER_3 0x14C40 | |
131 | #define VID_C_UP_CLUSTER_4 0x151E0 | |
132 | ||
133 | #define VID_D_UP_CLUSTER_1 0x15780 | |
134 | #define VID_D_UP_CLUSTER_2 0x15D20 | |
135 | #define VID_D_UP_CLUSTER_3 0x162C0 | |
136 | #define VID_D_UP_CLUSTER_4 0x16860 | |
137 | ||
138 | #define VID_E_UP_CLUSTER_1 0x16E00 | |
139 | #define VID_E_UP_CLUSTER_2 0x173A0 | |
140 | #define VID_E_UP_CLUSTER_3 0x17940 | |
141 | #define VID_E_UP_CLUSTER_4 0x17EE0 | |
142 | ||
143 | #define VID_F_UP_CLUSTER_1 0x18480 | |
144 | #define VID_F_UP_CLUSTER_2 0x18A20 | |
145 | #define VID_F_UP_CLUSTER_3 0x18FC0 | |
146 | #define VID_F_UP_CLUSTER_4 0x19560 | |
147 | ||
148 | #define VID_I_UP_CLUSTER_1 0x19B00 | |
149 | #define VID_I_UP_CLUSTER_2 0x1A0A0 | |
150 | #define VID_I_UP_CLUSTER_3 0x1A640 | |
151 | #define VID_I_UP_CLUSTER_4 0x1ABE0 | |
152 | ||
153 | #define VID_J_UP_CLUSTER_1 0x1B180 | |
154 | #define VID_J_UP_CLUSTER_2 0x1B720 | |
155 | #define VID_J_UP_CLUSTER_3 0x1BCC0 | |
156 | #define VID_J_UP_CLUSTER_4 0x1C260 | |
157 | ||
158 | #define AUD_A_UP_CLUSTER_1 0x1C800 | |
159 | #define AUD_A_UP_CLUSTER_2 0x1C880 | |
160 | #define AUD_A_UP_CLUSTER_3 0x1C900 | |
161 | ||
162 | #define AUD_B_UP_CLUSTER_1 0x1C980 | |
163 | #define AUD_B_UP_CLUSTER_2 0x1CA00 | |
164 | #define AUD_B_UP_CLUSTER_3 0x1CA80 | |
165 | ||
166 | #define AUD_C_UP_CLUSTER_1 0x1CB00 | |
167 | #define AUD_C_UP_CLUSTER_2 0x1CB80 | |
168 | #define AUD_C_UP_CLUSTER_3 0x1CC00 | |
169 | ||
170 | #define AUD_E_UP_CLUSTER_1 0x1CC80 | |
171 | #define AUD_E_UP_CLUSTER_2 0x1CD00 | |
172 | #define AUD_E_UP_CLUSTER_3 0x1CD80 | |
173 | ||
174 | #define RX_SRAM_POOL_FREE 0x1CE00 | |
175 | #define RX_SRAM_END 0x1D000 | |
176 | ||
1852a1bf | 177 | /* Free Receive SRAM 144 Bytes */ |
1a9fc855 | 178 | |
1852a1bf | 179 | /* Transmit SRAM */ |
1a9fc855 MCC |
180 | #define TX_SRAM_POOL_START 0x00000 |
181 | ||
182 | #define VID_A_DOWN_CLUSTER_1 0x00040 | |
183 | #define VID_A_DOWN_CLUSTER_2 0x005E0 | |
184 | #define VID_A_DOWN_CLUSTER_3 0x00B80 | |
185 | #define VID_A_DOWN_CLUSTER_4 0x01120 | |
186 | ||
187 | #define VID_B_DOWN_CLUSTER_1 0x016C0 | |
188 | #define VID_B_DOWN_CLUSTER_2 0x01C60 | |
189 | #define VID_B_DOWN_CLUSTER_3 0x02200 | |
190 | #define VID_B_DOWN_CLUSTER_4 0x027A0 | |
191 | ||
192 | #define VID_C_DOWN_CLUSTER_1 0x02D40 | |
193 | #define VID_C_DOWN_CLUSTER_2 0x032E0 | |
194 | #define VID_C_DOWN_CLUSTER_3 0x03880 | |
195 | #define VID_C_DOWN_CLUSTER_4 0x03E20 | |
196 | ||
197 | #define VID_D_DOWN_CLUSTER_1 0x043C0 | |
198 | #define VID_D_DOWN_CLUSTER_2 0x04960 | |
199 | #define VID_D_DOWN_CLUSTER_3 0x04F00 | |
200 | #define VID_D_DOWN_CLUSTER_4 0x054A0 | |
201 | ||
202 | #define VID_E_DOWN_CLUSTER_1 0x05a40 | |
203 | #define VID_E_DOWN_CLUSTER_2 0x05FE0 | |
204 | #define VID_E_DOWN_CLUSTER_3 0x06580 | |
205 | #define VID_E_DOWN_CLUSTER_4 0x06B20 | |
206 | ||
207 | #define VID_F_DOWN_CLUSTER_1 0x070C0 | |
208 | #define VID_F_DOWN_CLUSTER_2 0x07660 | |
209 | #define VID_F_DOWN_CLUSTER_3 0x07C00 | |
210 | #define VID_F_DOWN_CLUSTER_4 0x081A0 | |
211 | ||
212 | #define VID_G_DOWN_CLUSTER_1 0x08740 | |
213 | #define VID_G_DOWN_CLUSTER_2 0x08CE0 | |
214 | #define VID_G_DOWN_CLUSTER_3 0x09280 | |
215 | #define VID_G_DOWN_CLUSTER_4 0x09820 | |
216 | ||
217 | #define VID_H_DOWN_CLUSTER_1 0x09DC0 | |
218 | #define VID_H_DOWN_CLUSTER_2 0x0A360 | |
219 | #define VID_H_DOWN_CLUSTER_3 0x0A900 | |
220 | #define VID_H_DOWN_CLUSTER_4 0x0AEA0 | |
221 | ||
222 | #define AUD_A_DOWN_CLUSTER_1 0x0B500 | |
223 | #define AUD_A_DOWN_CLUSTER_2 0x0B580 | |
224 | #define AUD_A_DOWN_CLUSTER_3 0x0B600 | |
225 | ||
226 | #define AUD_B_DOWN_CLUSTER_1 0x0B680 | |
227 | #define AUD_B_DOWN_CLUSTER_2 0x0B700 | |
228 | #define AUD_B_DOWN_CLUSTER_3 0x0B780 | |
229 | ||
230 | #define AUD_C_DOWN_CLUSTER_1 0x0B800 | |
231 | #define AUD_C_DOWN_CLUSTER_2 0x0B880 | |
232 | #define AUD_C_DOWN_CLUSTER_3 0x0B900 | |
233 | ||
234 | #define AUD_D_DOWN_CLUSTER_1 0x0B980 | |
235 | #define AUD_D_DOWN_CLUSTER_2 0x0BA00 | |
236 | #define AUD_D_DOWN_CLUSTER_3 0x0BA80 | |
237 | ||
238 | #define TX_SRAM_POOL_FREE 0x0BB00 | |
239 | #define TX_SRAM_END 0x0C000 | |
240 | ||
241 | #define BYTES_TO_DWORDS(bcount) ((bcount) >> 2) | |
242 | #define BYTES_TO_QWORDS(bcount) ((bcount) >> 3) | |
243 | #define BYTES_TO_OWORDS(bcount) ((bcount) >> 4) | |
244 | ||
245 | #define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE) | |
246 | #define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE) | |
247 | #define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE) | |
248 | ||
249 | #define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE) | |
250 | #define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE) | |
251 | #define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE) | |
252 | ||
253 | #define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE) | |
254 | #define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE) | |
255 | #define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE) | |
256 | ||
257 | #endif |