Commit | Line | Data |
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02b20b0b MCC |
1 | /* |
2 | * Driver for the Conexant CX25821 PCIe bridge | |
3 | * | |
bb4c9a74 | 4 | * Copyright (C) 2009 Conexant Systems Inc. |
02b20b0b MCC |
5 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> |
6 | * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
36d89f7d JP |
24 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
25 | ||
02b20b0b | 26 | #include <linux/i2c.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
02b20b0b MCC |
28 | #include "cx25821.h" |
29 | #include "cx25821-sram.h" | |
30 | #include "cx25821-video.h" | |
31 | ||
32 | MODULE_DESCRIPTION("Driver for Athena cards"); | |
33 | MODULE_AUTHOR("Shu Lin - Hiep Huynh"); | |
34 | MODULE_LICENSE("GPL"); | |
35 | ||
02b20b0b MCC |
36 | static unsigned int debug; |
37 | module_param(debug, int, 0644); | |
38 | MODULE_PARM_DESC(debug, "enable debug messages"); | |
39 | ||
53e712d0 | 40 | static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; |
1a9fc855 | 41 | module_param_array(card, int, NULL, 0444); |
02b20b0b MCC |
42 | MODULE_PARM_DESC(card, "card type"); |
43 | ||
bfef0d35 | 44 | const struct sram_channel cx25821_sram_channels[] = { |
1a9fc855 | 45 | [SRAM_CH00] = { |
1c2b5520 LF |
46 | .i = SRAM_CH00, |
47 | .name = "VID A", | |
48 | .cmds_start = VID_A_DOWN_CMDS, | |
49 | .ctrl_start = VID_A_IQ, | |
50 | .cdt = VID_A_CDT, | |
51 | .fifo_start = VID_A_DOWN_CLUSTER_1, | |
52 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
53 | .ptr1_reg = DMA1_PTR1, | |
54 | .ptr2_reg = DMA1_PTR2, | |
55 | .cnt1_reg = DMA1_CNT1, | |
56 | .cnt2_reg = DMA1_CNT2, | |
57 | .int_msk = VID_A_INT_MSK, | |
58 | .int_stat = VID_A_INT_STAT, | |
59 | .int_mstat = VID_A_INT_MSTAT, | |
60 | .dma_ctl = VID_DST_A_DMA_CTL, | |
61 | .gpcnt_ctl = VID_DST_A_GPCNT_CTL, | |
62 | .gpcnt = VID_DST_A_GPCNT, | |
63 | .vip_ctl = VID_DST_A_VIP_CTL, | |
64 | .pix_frmt = VID_DST_A_PIX_FRMT, | |
65 | }, | |
1a9fc855 MCC |
66 | |
67 | [SRAM_CH01] = { | |
1c2b5520 LF |
68 | .i = SRAM_CH01, |
69 | .name = "VID B", | |
70 | .cmds_start = VID_B_DOWN_CMDS, | |
71 | .ctrl_start = VID_B_IQ, | |
72 | .cdt = VID_B_CDT, | |
73 | .fifo_start = VID_B_DOWN_CLUSTER_1, | |
74 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
75 | .ptr1_reg = DMA2_PTR1, | |
76 | .ptr2_reg = DMA2_PTR2, | |
77 | .cnt1_reg = DMA2_CNT1, | |
78 | .cnt2_reg = DMA2_CNT2, | |
79 | .int_msk = VID_B_INT_MSK, | |
80 | .int_stat = VID_B_INT_STAT, | |
81 | .int_mstat = VID_B_INT_MSTAT, | |
82 | .dma_ctl = VID_DST_B_DMA_CTL, | |
83 | .gpcnt_ctl = VID_DST_B_GPCNT_CTL, | |
84 | .gpcnt = VID_DST_B_GPCNT, | |
85 | .vip_ctl = VID_DST_B_VIP_CTL, | |
86 | .pix_frmt = VID_DST_B_PIX_FRMT, | |
87 | }, | |
1a9fc855 MCC |
88 | |
89 | [SRAM_CH02] = { | |
1c2b5520 LF |
90 | .i = SRAM_CH02, |
91 | .name = "VID C", | |
92 | .cmds_start = VID_C_DOWN_CMDS, | |
93 | .ctrl_start = VID_C_IQ, | |
94 | .cdt = VID_C_CDT, | |
95 | .fifo_start = VID_C_DOWN_CLUSTER_1, | |
96 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
97 | .ptr1_reg = DMA3_PTR1, | |
98 | .ptr2_reg = DMA3_PTR2, | |
99 | .cnt1_reg = DMA3_CNT1, | |
100 | .cnt2_reg = DMA3_CNT2, | |
101 | .int_msk = VID_C_INT_MSK, | |
102 | .int_stat = VID_C_INT_STAT, | |
103 | .int_mstat = VID_C_INT_MSTAT, | |
104 | .dma_ctl = VID_DST_C_DMA_CTL, | |
105 | .gpcnt_ctl = VID_DST_C_GPCNT_CTL, | |
106 | .gpcnt = VID_DST_C_GPCNT, | |
107 | .vip_ctl = VID_DST_C_VIP_CTL, | |
108 | .pix_frmt = VID_DST_C_PIX_FRMT, | |
109 | }, | |
1a9fc855 MCC |
110 | |
111 | [SRAM_CH03] = { | |
1c2b5520 LF |
112 | .i = SRAM_CH03, |
113 | .name = "VID D", | |
114 | .cmds_start = VID_D_DOWN_CMDS, | |
115 | .ctrl_start = VID_D_IQ, | |
116 | .cdt = VID_D_CDT, | |
117 | .fifo_start = VID_D_DOWN_CLUSTER_1, | |
118 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
119 | .ptr1_reg = DMA4_PTR1, | |
120 | .ptr2_reg = DMA4_PTR2, | |
121 | .cnt1_reg = DMA4_CNT1, | |
122 | .cnt2_reg = DMA4_CNT2, | |
123 | .int_msk = VID_D_INT_MSK, | |
124 | .int_stat = VID_D_INT_STAT, | |
125 | .int_mstat = VID_D_INT_MSTAT, | |
126 | .dma_ctl = VID_DST_D_DMA_CTL, | |
127 | .gpcnt_ctl = VID_DST_D_GPCNT_CTL, | |
128 | .gpcnt = VID_DST_D_GPCNT, | |
129 | .vip_ctl = VID_DST_D_VIP_CTL, | |
130 | .pix_frmt = VID_DST_D_PIX_FRMT, | |
131 | }, | |
1a9fc855 MCC |
132 | |
133 | [SRAM_CH04] = { | |
1c2b5520 LF |
134 | .i = SRAM_CH04, |
135 | .name = "VID E", | |
136 | .cmds_start = VID_E_DOWN_CMDS, | |
137 | .ctrl_start = VID_E_IQ, | |
138 | .cdt = VID_E_CDT, | |
139 | .fifo_start = VID_E_DOWN_CLUSTER_1, | |
140 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
141 | .ptr1_reg = DMA5_PTR1, | |
142 | .ptr2_reg = DMA5_PTR2, | |
143 | .cnt1_reg = DMA5_CNT1, | |
144 | .cnt2_reg = DMA5_CNT2, | |
145 | .int_msk = VID_E_INT_MSK, | |
146 | .int_stat = VID_E_INT_STAT, | |
147 | .int_mstat = VID_E_INT_MSTAT, | |
148 | .dma_ctl = VID_DST_E_DMA_CTL, | |
149 | .gpcnt_ctl = VID_DST_E_GPCNT_CTL, | |
150 | .gpcnt = VID_DST_E_GPCNT, | |
151 | .vip_ctl = VID_DST_E_VIP_CTL, | |
152 | .pix_frmt = VID_DST_E_PIX_FRMT, | |
153 | }, | |
1a9fc855 MCC |
154 | |
155 | [SRAM_CH05] = { | |
1c2b5520 LF |
156 | .i = SRAM_CH05, |
157 | .name = "VID F", | |
158 | .cmds_start = VID_F_DOWN_CMDS, | |
159 | .ctrl_start = VID_F_IQ, | |
160 | .cdt = VID_F_CDT, | |
161 | .fifo_start = VID_F_DOWN_CLUSTER_1, | |
162 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
163 | .ptr1_reg = DMA6_PTR1, | |
164 | .ptr2_reg = DMA6_PTR2, | |
165 | .cnt1_reg = DMA6_CNT1, | |
166 | .cnt2_reg = DMA6_CNT2, | |
167 | .int_msk = VID_F_INT_MSK, | |
168 | .int_stat = VID_F_INT_STAT, | |
169 | .int_mstat = VID_F_INT_MSTAT, | |
170 | .dma_ctl = VID_DST_F_DMA_CTL, | |
171 | .gpcnt_ctl = VID_DST_F_GPCNT_CTL, | |
172 | .gpcnt = VID_DST_F_GPCNT, | |
173 | .vip_ctl = VID_DST_F_VIP_CTL, | |
174 | .pix_frmt = VID_DST_F_PIX_FRMT, | |
175 | }, | |
1a9fc855 MCC |
176 | |
177 | [SRAM_CH06] = { | |
1c2b5520 LF |
178 | .i = SRAM_CH06, |
179 | .name = "VID G", | |
180 | .cmds_start = VID_G_DOWN_CMDS, | |
181 | .ctrl_start = VID_G_IQ, | |
182 | .cdt = VID_G_CDT, | |
183 | .fifo_start = VID_G_DOWN_CLUSTER_1, | |
184 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
185 | .ptr1_reg = DMA7_PTR1, | |
186 | .ptr2_reg = DMA7_PTR2, | |
187 | .cnt1_reg = DMA7_CNT1, | |
188 | .cnt2_reg = DMA7_CNT2, | |
189 | .int_msk = VID_G_INT_MSK, | |
190 | .int_stat = VID_G_INT_STAT, | |
191 | .int_mstat = VID_G_INT_MSTAT, | |
192 | .dma_ctl = VID_DST_G_DMA_CTL, | |
193 | .gpcnt_ctl = VID_DST_G_GPCNT_CTL, | |
194 | .gpcnt = VID_DST_G_GPCNT, | |
195 | .vip_ctl = VID_DST_G_VIP_CTL, | |
196 | .pix_frmt = VID_DST_G_PIX_FRMT, | |
197 | }, | |
1a9fc855 MCC |
198 | |
199 | [SRAM_CH07] = { | |
1c2b5520 LF |
200 | .i = SRAM_CH07, |
201 | .name = "VID H", | |
202 | .cmds_start = VID_H_DOWN_CMDS, | |
203 | .ctrl_start = VID_H_IQ, | |
204 | .cdt = VID_H_CDT, | |
205 | .fifo_start = VID_H_DOWN_CLUSTER_1, | |
206 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
207 | .ptr1_reg = DMA8_PTR1, | |
208 | .ptr2_reg = DMA8_PTR2, | |
209 | .cnt1_reg = DMA8_CNT1, | |
210 | .cnt2_reg = DMA8_CNT2, | |
211 | .int_msk = VID_H_INT_MSK, | |
212 | .int_stat = VID_H_INT_STAT, | |
213 | .int_mstat = VID_H_INT_MSTAT, | |
214 | .dma_ctl = VID_DST_H_DMA_CTL, | |
215 | .gpcnt_ctl = VID_DST_H_GPCNT_CTL, | |
216 | .gpcnt = VID_DST_H_GPCNT, | |
217 | .vip_ctl = VID_DST_H_VIP_CTL, | |
218 | .pix_frmt = VID_DST_H_PIX_FRMT, | |
219 | }, | |
1a9fc855 MCC |
220 | |
221 | [SRAM_CH08] = { | |
1c2b5520 LF |
222 | .name = "audio from", |
223 | .cmds_start = AUD_A_DOWN_CMDS, | |
224 | .ctrl_start = AUD_A_IQ, | |
225 | .cdt = AUD_A_CDT, | |
226 | .fifo_start = AUD_A_DOWN_CLUSTER_1, | |
227 | .fifo_size = AUDIO_CLUSTER_SIZE * 3, | |
228 | .ptr1_reg = DMA17_PTR1, | |
229 | .ptr2_reg = DMA17_PTR2, | |
230 | .cnt1_reg = DMA17_CNT1, | |
231 | .cnt2_reg = DMA17_CNT2, | |
232 | }, | |
1a9fc855 MCC |
233 | |
234 | [SRAM_CH09] = { | |
1c2b5520 LF |
235 | .i = SRAM_CH09, |
236 | .name = "VID Upstream I", | |
237 | .cmds_start = VID_I_UP_CMDS, | |
238 | .ctrl_start = VID_I_IQ, | |
239 | .cdt = VID_I_CDT, | |
240 | .fifo_start = VID_I_UP_CLUSTER_1, | |
241 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
242 | .ptr1_reg = DMA15_PTR1, | |
243 | .ptr2_reg = DMA15_PTR2, | |
244 | .cnt1_reg = DMA15_CNT1, | |
245 | .cnt2_reg = DMA15_CNT2, | |
246 | .int_msk = VID_I_INT_MSK, | |
247 | .int_stat = VID_I_INT_STAT, | |
248 | .int_mstat = VID_I_INT_MSTAT, | |
249 | .dma_ctl = VID_SRC_I_DMA_CTL, | |
250 | .gpcnt_ctl = VID_SRC_I_GPCNT_CTL, | |
251 | .gpcnt = VID_SRC_I_GPCNT, | |
252 | ||
253 | .vid_fmt_ctl = VID_SRC_I_FMT_CTL, | |
254 | .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1, | |
255 | .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2, | |
256 | .vid_cdt_size = VID_SRC_I_CDT_SZ, | |
257 | .irq_bit = 8, | |
258 | }, | |
1a9fc855 MCC |
259 | |
260 | [SRAM_CH10] = { | |
1c2b5520 LF |
261 | .i = SRAM_CH10, |
262 | .name = "VID Upstream J", | |
263 | .cmds_start = VID_J_UP_CMDS, | |
264 | .ctrl_start = VID_J_IQ, | |
265 | .cdt = VID_J_CDT, | |
266 | .fifo_start = VID_J_UP_CLUSTER_1, | |
267 | .fifo_size = (VID_CLUSTER_SIZE << 2), | |
268 | .ptr1_reg = DMA16_PTR1, | |
269 | .ptr2_reg = DMA16_PTR2, | |
270 | .cnt1_reg = DMA16_CNT1, | |
271 | .cnt2_reg = DMA16_CNT2, | |
272 | .int_msk = VID_J_INT_MSK, | |
273 | .int_stat = VID_J_INT_STAT, | |
274 | .int_mstat = VID_J_INT_MSTAT, | |
275 | .dma_ctl = VID_SRC_J_DMA_CTL, | |
276 | .gpcnt_ctl = VID_SRC_J_GPCNT_CTL, | |
277 | .gpcnt = VID_SRC_J_GPCNT, | |
278 | ||
279 | .vid_fmt_ctl = VID_SRC_J_FMT_CTL, | |
280 | .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1, | |
281 | .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2, | |
282 | .vid_cdt_size = VID_SRC_J_CDT_SZ, | |
283 | .irq_bit = 9, | |
284 | }, | |
1a9fc855 MCC |
285 | |
286 | [SRAM_CH11] = { | |
1c2b5520 LF |
287 | .i = SRAM_CH11, |
288 | .name = "Audio Upstream Channel B", | |
289 | .cmds_start = AUD_B_UP_CMDS, | |
290 | .ctrl_start = AUD_B_IQ, | |
291 | .cdt = AUD_B_CDT, | |
292 | .fifo_start = AUD_B_UP_CLUSTER_1, | |
293 | .fifo_size = (AUDIO_CLUSTER_SIZE * 3), | |
294 | .ptr1_reg = DMA22_PTR1, | |
295 | .ptr2_reg = DMA22_PTR2, | |
296 | .cnt1_reg = DMA22_CNT1, | |
297 | .cnt2_reg = DMA22_CNT2, | |
298 | .int_msk = AUD_B_INT_MSK, | |
299 | .int_stat = AUD_B_INT_STAT, | |
300 | .int_mstat = AUD_B_INT_MSTAT, | |
301 | .dma_ctl = AUD_INT_DMA_CTL, | |
302 | .gpcnt_ctl = AUD_B_GPCNT_CTL, | |
303 | .gpcnt = AUD_B_GPCNT, | |
304 | .aud_length = AUD_B_LNGTH, | |
305 | .aud_cfg = AUD_B_CFG, | |
306 | .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN, | |
307 | .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN, | |
308 | .irq_bit = 11, | |
309 | }, | |
02b20b0b | 310 | }; |
de2c4349 | 311 | EXPORT_SYMBOL(cx25821_sram_channels); |
02b20b0b | 312 | |
02b20b0b MCC |
313 | static int cx25821_risc_decode(u32 risc) |
314 | { | |
36d89f7d | 315 | static const char * const instr[16] = { |
1a9fc855 MCC |
316 | [RISC_SYNC >> 28] = "sync", |
317 | [RISC_WRITE >> 28] = "write", | |
318 | [RISC_WRITEC >> 28] = "writec", | |
319 | [RISC_READ >> 28] = "read", | |
320 | [RISC_READC >> 28] = "readc", | |
321 | [RISC_JUMP >> 28] = "jump", | |
322 | [RISC_SKIP >> 28] = "skip", | |
323 | [RISC_WRITERM >> 28] = "writerm", | |
324 | [RISC_WRITECM >> 28] = "writecm", | |
325 | [RISC_WRITECR >> 28] = "writecr", | |
326 | }; | |
36d89f7d | 327 | static const int incr[16] = { |
1a9fc855 MCC |
328 | [RISC_WRITE >> 28] = 3, |
329 | [RISC_JUMP >> 28] = 3, | |
330 | [RISC_SKIP >> 28] = 1, | |
331 | [RISC_SYNC >> 28] = 1, | |
332 | [RISC_WRITERM >> 28] = 3, | |
333 | [RISC_WRITECM >> 28] = 3, | |
334 | [RISC_WRITECR >> 28] = 4, | |
335 | }; | |
36d89f7d | 336 | static const char * const bits[] = { |
1a9fc855 MCC |
337 | "12", "13", "14", "resync", |
338 | "cnt0", "cnt1", "18", "19", | |
339 | "20", "21", "22", "23", | |
340 | "irq1", "irq2", "eol", "sol", | |
341 | }; | |
342 | int i; | |
343 | ||
36d89f7d JP |
344 | pr_cont("0x%08x [ %s", |
345 | risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); | |
1a9fc855 MCC |
346 | for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { |
347 | if (risc & (1 << (i + 12))) | |
36d89f7d | 348 | pr_cont(" %s", bits[i]); |
bb4c9a74 | 349 | } |
36d89f7d | 350 | pr_cont(" count=%d ]\n", risc & 0xfff); |
1a9fc855 | 351 | return incr[risc >> 28] ? incr[risc >> 28] : 1; |
02b20b0b MCC |
352 | } |
353 | ||
354 | static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap) | |
355 | { | |
1a9fc855 MCC |
356 | struct cx25821_i2c *bus = i2c_adap->algo_data; |
357 | struct cx25821_dev *dev = bus->dev; | |
358 | return cx_read(bus->reg_stat) & 0x01; | |
02b20b0b MCC |
359 | } |
360 | ||
02b20b0b MCC |
361 | static void cx25821_registers_init(struct cx25821_dev *dev) |
362 | { | |
1a9fc855 | 363 | u32 tmp; |
bb4c9a74 | 364 | |
de2c4349 | 365 | /* enable RUN_RISC in Pecos */ |
1a9fc855 | 366 | cx_write(DEV_CNTRL2, 0x20); |
bb4c9a74 | 367 | |
de2c4349 OP |
368 | /* Set the master PCI interrupt masks to enable video, audio, MBIF, |
369 | * and GPIO interrupts | |
370 | * I2C interrupt masking is handled by the I2C objects themselves. */ | |
1a9fc855 | 371 | cx_write(PCI_INT_MSK, 0x2001FFFF); |
02b20b0b | 372 | |
1a9fc855 | 373 | tmp = cx_read(RDR_TLCTL0); |
de2c4349 | 374 | tmp &= ~FLD_CFG_RCB_CK_EN; /* Clear the RCB_CK_EN bit */ |
1a9fc855 | 375 | cx_write(RDR_TLCTL0, tmp); |
02b20b0b | 376 | |
de2c4349 | 377 | /* PLL-A setting for the Audio Master Clock */ |
1a9fc855 | 378 | cx_write(PLL_A_INT_FRAC, 0x9807A58B); |
02b20b0b | 379 | |
de2c4349 | 380 | /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */ |
1a9fc855 | 381 | cx_write(PLL_A_POST_STAT_BIST, 0x8000019C); |
bb4c9a74 | 382 | |
de2c4349 | 383 | /* clear reset bit [31] */ |
1a9fc855 MCC |
384 | tmp = cx_read(PLL_A_INT_FRAC); |
385 | cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF); | |
02b20b0b | 386 | |
de2c4349 | 387 | /* PLL-B setting for Mobilygen Host Bus Interface */ |
1a9fc855 | 388 | cx_write(PLL_B_INT_FRAC, 0x9883A86F); |
02b20b0b | 389 | |
de2c4349 | 390 | /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */ |
1a9fc855 | 391 | cx_write(PLL_B_POST_STAT_BIST, 0x8000018D); |
02b20b0b | 392 | |
de2c4349 | 393 | /* clear reset bit [31] */ |
1a9fc855 MCC |
394 | tmp = cx_read(PLL_B_INT_FRAC); |
395 | cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF); | |
02b20b0b | 396 | |
de2c4349 | 397 | /* PLL-C setting for video upstream channel */ |
1a9fc855 | 398 | cx_write(PLL_C_INT_FRAC, 0x96A0EA3F); |
02b20b0b | 399 | |
de2c4349 | 400 | /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */ |
1a9fc855 | 401 | cx_write(PLL_C_POST_STAT_BIST, 0x80000103); |
02b20b0b | 402 | |
de2c4349 | 403 | /* clear reset bit [31] */ |
1a9fc855 MCC |
404 | tmp = cx_read(PLL_C_INT_FRAC); |
405 | cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF); | |
02b20b0b | 406 | |
de2c4349 | 407 | /* PLL-D setting for audio upstream channel */ |
1a9fc855 | 408 | cx_write(PLL_D_INT_FRAC, 0x98757F5B); |
02b20b0b | 409 | |
de2c4349 | 410 | /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */ |
1a9fc855 | 411 | cx_write(PLL_D_POST_STAT_BIST, 0x80000113); |
02b20b0b | 412 | |
de2c4349 | 413 | /* clear reset bit [31] */ |
1a9fc855 MCC |
414 | tmp = cx_read(PLL_D_INT_FRAC); |
415 | cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF); | |
02b20b0b | 416 | |
de2c4349 OP |
417 | /* This selects the PLL C clock source for the video upstream channel |
418 | * I and J */ | |
1a9fc855 MCC |
419 | tmp = cx_read(VID_CH_CLK_SEL); |
420 | cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000); | |
bb4c9a74 | 421 | |
de2c4349 OP |
422 | /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for |
423 | * channel A-C | |
424 | * select 656/VIP DST for downstream Channel A - C */ | |
1a9fc855 | 425 | tmp = cx_read(VID_CH_MODE_SEL); |
de2c4349 | 426 | /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */ |
1a9fc855 | 427 | cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); |
02b20b0b | 428 | |
de2c4349 | 429 | /* enables 656 port I and J as output */ |
1a9fc855 | 430 | tmp = cx_read(CLK_RST); |
de2c4349 OP |
431 | /* use external ALT_PLL_REF pin as its reference clock instead */ |
432 | tmp |= FLD_USE_ALT_PLL_REF; | |
1a9fc855 | 433 | cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE)); |
bb4c9a74 | 434 | |
1a9fc855 MCC |
435 | mdelay(100); |
436 | } | |
02b20b0b | 437 | |
1a9fc855 | 438 | int cx25821_sram_channel_setup(struct cx25821_dev *dev, |
bfef0d35 | 439 | const struct sram_channel *ch, |
1a9fc855 MCC |
440 | unsigned int bpl, u32 risc) |
441 | { | |
442 | unsigned int i, lines; | |
443 | u32 cdt; | |
444 | ||
445 | if (ch->cmds_start == 0) { | |
446 | cx_write(ch->ptr1_reg, 0); | |
447 | cx_write(ch->ptr2_reg, 0); | |
448 | cx_write(ch->cnt2_reg, 0); | |
449 | cx_write(ch->cnt1_reg, 0); | |
450 | return 0; | |
451 | } | |
bb4c9a74 | 452 | |
1a9fc855 MCC |
453 | bpl = (bpl + 7) & ~7; /* alignment */ |
454 | cdt = ch->cdt; | |
455 | lines = ch->fifo_size / bpl; | |
bb4c9a74 | 456 | |
de2c4349 | 457 | if (lines > 4) |
1a9fc855 | 458 | lines = 4; |
02b20b0b | 459 | |
1a9fc855 MCC |
460 | BUG_ON(lines < 2); |
461 | ||
462 | cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); | |
463 | cx_write(8 + 4, 8); | |
464 | cx_write(8 + 8, 0); | |
465 | ||
466 | /* write CDT */ | |
467 | for (i = 0; i < lines; i++) { | |
468 | cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); | |
469 | cx_write(cdt + 16 * i + 4, 0); | |
470 | cx_write(cdt + 16 * i + 8, 0); | |
471 | cx_write(cdt + 16 * i + 12, 0); | |
472 | } | |
473 | ||
de2c4349 | 474 | /* init the first cdt buffer */ |
1a9fc855 MCC |
475 | for (i = 0; i < 128; i++) |
476 | cx_write(ch->fifo_start + 4 * i, i); | |
477 | ||
478 | /* write CMDS */ | |
de2c4349 | 479 | if (ch->jumponly) |
1a9fc855 | 480 | cx_write(ch->cmds_start + 0, 8); |
de2c4349 | 481 | else |
1a9fc855 | 482 | cx_write(ch->cmds_start + 0, risc); |
1a9fc855 MCC |
483 | |
484 | cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ | |
485 | cx_write(ch->cmds_start + 8, cdt); | |
486 | cx_write(ch->cmds_start + 12, (lines * 16) >> 3); | |
487 | cx_write(ch->cmds_start + 16, ch->ctrl_start); | |
488 | ||
489 | if (ch->jumponly) | |
490 | cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); | |
491 | else | |
492 | cx_write(ch->cmds_start + 20, 64 >> 2); | |
493 | ||
494 | for (i = 24; i < 80; i += 4) | |
495 | cx_write(ch->cmds_start + i, 0); | |
496 | ||
497 | /* fill registers */ | |
498 | cx_write(ch->ptr1_reg, ch->fifo_start); | |
499 | cx_write(ch->ptr2_reg, cdt); | |
500 | cx_write(ch->cnt2_reg, (lines * 16) >> 3); | |
501 | cx_write(ch->cnt1_reg, (bpl >> 3) - 1); | |
02b20b0b | 502 | |
bb4c9a74 | 503 | return 0; |
02b20b0b MCC |
504 | } |
505 | ||
506 | int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev, | |
bfef0d35 | 507 | const struct sram_channel *ch, |
1a9fc855 | 508 | unsigned int bpl, u32 risc) |
02b20b0b | 509 | { |
1a9fc855 MCC |
510 | unsigned int i, lines; |
511 | u32 cdt; | |
512 | ||
513 | if (ch->cmds_start == 0) { | |
514 | cx_write(ch->ptr1_reg, 0); | |
515 | cx_write(ch->ptr2_reg, 0); | |
516 | cx_write(ch->cnt2_reg, 0); | |
517 | cx_write(ch->cnt1_reg, 0); | |
518 | return 0; | |
519 | } | |
520 | ||
521 | bpl = (bpl + 7) & ~7; /* alignment */ | |
522 | cdt = ch->cdt; | |
523 | lines = ch->fifo_size / bpl; | |
524 | ||
de2c4349 OP |
525 | if (lines > 3) |
526 | lines = 3; /* for AUDIO */ | |
02b20b0b | 527 | |
1a9fc855 MCC |
528 | BUG_ON(lines < 2); |
529 | ||
530 | cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC); | |
531 | cx_write(8 + 4, 8); | |
532 | cx_write(8 + 8, 0); | |
533 | ||
534 | /* write CDT */ | |
535 | for (i = 0; i < lines; i++) { | |
536 | cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); | |
537 | cx_write(cdt + 16 * i + 4, 0); | |
538 | cx_write(cdt + 16 * i + 8, 0); | |
539 | cx_write(cdt + 16 * i + 12, 0); | |
540 | } | |
541 | ||
542 | /* write CMDS */ | |
de2c4349 | 543 | if (ch->jumponly) |
1a9fc855 | 544 | cx_write(ch->cmds_start + 0, 8); |
de2c4349 | 545 | else |
1a9fc855 | 546 | cx_write(ch->cmds_start + 0, risc); |
1a9fc855 MCC |
547 | |
548 | cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ | |
549 | cx_write(ch->cmds_start + 8, cdt); | |
550 | cx_write(ch->cmds_start + 12, (lines * 16) >> 3); | |
551 | cx_write(ch->cmds_start + 16, ch->ctrl_start); | |
552 | ||
de2c4349 OP |
553 | /* IQ size */ |
554 | if (ch->jumponly) | |
1a9fc855 | 555 | cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); |
de2c4349 | 556 | else |
1a9fc855 | 557 | cx_write(ch->cmds_start + 20, 64 >> 2); |
1a9fc855 | 558 | |
de2c4349 | 559 | /* zero out */ |
1a9fc855 MCC |
560 | for (i = 24; i < 80; i += 4) |
561 | cx_write(ch->cmds_start + i, 0); | |
562 | ||
563 | /* fill registers */ | |
564 | cx_write(ch->ptr1_reg, ch->fifo_start); | |
565 | cx_write(ch->ptr2_reg, cdt); | |
566 | cx_write(ch->cnt2_reg, (lines * 16) >> 3); | |
567 | cx_write(ch->cnt1_reg, (bpl >> 3) - 1); | |
02b20b0b | 568 | |
bb4c9a74 | 569 | return 0; |
02b20b0b | 570 | } |
de2c4349 | 571 | EXPORT_SYMBOL(cx25821_sram_channel_setup_audio); |
02b20b0b | 572 | |
bfef0d35 | 573 | void cx25821_sram_channel_dump(struct cx25821_dev *dev, const struct sram_channel *ch) |
02b20b0b | 574 | { |
1a9fc855 MCC |
575 | static char *name[] = { |
576 | "init risc lo", | |
577 | "init risc hi", | |
578 | "cdt base", | |
579 | "cdt size", | |
580 | "iq base", | |
581 | "iq size", | |
582 | "risc pc lo", | |
583 | "risc pc hi", | |
584 | "iq wr ptr", | |
585 | "iq rd ptr", | |
586 | "cdt current", | |
587 | "pci target lo", | |
588 | "pci target hi", | |
589 | "line / byte", | |
590 | }; | |
591 | u32 risc; | |
592 | unsigned int i, j, n; | |
593 | ||
36d89f7d | 594 | pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name); |
1a9fc855 | 595 | for (i = 0; i < ARRAY_SIZE(name); i++) |
36d89f7d JP |
596 | pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n", |
597 | i * 4, name[i], cx_read(ch->cmds_start + 4 * i)); | |
1a9fc855 MCC |
598 | |
599 | j = i * 4; | |
600 | for (i = 0; i < 4;) { | |
601 | risc = cx_read(ch->cmds_start + 4 * (i + 14)); | |
36d89f7d | 602 | pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i); |
1a9fc855 MCC |
603 | i += cx25821_risc_decode(risc); |
604 | } | |
605 | ||
606 | for (i = 0; i < (64 >> 2); i += n) { | |
607 | risc = cx_read(ch->ctrl_start + 4 * i); | |
608 | /* No consideration for bits 63-32 */ | |
609 | ||
36d89f7d JP |
610 | pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ", |
611 | i * 4, ch->ctrl_start + 4 * i, i); | |
1a9fc855 MCC |
612 | n = cx25821_risc_decode(risc); |
613 | for (j = 1; j < n; j++) { | |
614 | risc = cx_read(ch->ctrl_start + 4 * (i + j)); | |
36d89f7d JP |
615 | pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", |
616 | 4 * (i + j), i + j, risc, j); | |
1a9fc855 | 617 | } |
bb4c9a74 | 618 | } |
1a9fc855 | 619 | |
36d89f7d JP |
620 | pr_warn(" : fifo: 0x%08x -> 0x%x\n", |
621 | ch->fifo_start, ch->fifo_start + ch->fifo_size); | |
622 | pr_warn(" : ctrl: 0x%08x -> 0x%x\n", | |
623 | ch->ctrl_start, ch->ctrl_start + 6 * 16); | |
624 | pr_warn(" : ptr1_reg: 0x%08x\n", | |
625 | cx_read(ch->ptr1_reg)); | |
626 | pr_warn(" : ptr2_reg: 0x%08x\n", | |
627 | cx_read(ch->ptr2_reg)); | |
628 | pr_warn(" : cnt1_reg: 0x%08x\n", | |
629 | cx_read(ch->cnt1_reg)); | |
630 | pr_warn(" : cnt2_reg: 0x%08x\n", | |
631 | cx_read(ch->cnt2_reg)); | |
02b20b0b MCC |
632 | } |
633 | ||
1a9fc855 | 634 | void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev, |
bfef0d35 | 635 | const struct sram_channel *ch) |
02b20b0b | 636 | { |
36d89f7d | 637 | static const char * const name[] = { |
1a9fc855 MCC |
638 | "init risc lo", |
639 | "init risc hi", | |
640 | "cdt base", | |
641 | "cdt size", | |
642 | "iq base", | |
643 | "iq size", | |
644 | "risc pc lo", | |
645 | "risc pc hi", | |
646 | "iq wr ptr", | |
647 | "iq rd ptr", | |
648 | "cdt current", | |
649 | "pci target lo", | |
650 | "pci target hi", | |
651 | "line / byte", | |
652 | }; | |
bb4c9a74 MCC |
653 | |
654 | u32 risc, value, tmp; | |
1a9fc855 | 655 | unsigned int i, j, n; |
02b20b0b | 656 | |
36d89f7d JP |
657 | pr_info("\n%s: %s - dma Audio channel status dump\n", |
658 | dev->name, ch->name); | |
02b20b0b | 659 | |
1a9fc855 | 660 | for (i = 0; i < ARRAY_SIZE(name); i++) |
36d89f7d JP |
661 | pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n", |
662 | dev->name, i * 4, name[i], | |
663 | cx_read(ch->cmds_start + 4 * i)); | |
bb4c9a74 | 664 | |
1a9fc855 MCC |
665 | j = i * 4; |
666 | for (i = 0; i < 4;) { | |
667 | risc = cx_read(ch->cmds_start + 4 * (i + 14)); | |
36d89f7d | 668 | pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i); |
1a9fc855 MCC |
669 | i += cx25821_risc_decode(risc); |
670 | } | |
02b20b0b | 671 | |
1a9fc855 MCC |
672 | for (i = 0; i < (64 >> 2); i += n) { |
673 | risc = cx_read(ch->ctrl_start + 4 * i); | |
674 | /* No consideration for bits 63-32 */ | |
02b20b0b | 675 | |
36d89f7d JP |
676 | pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ", |
677 | i * 4, ch->ctrl_start + 4 * i, i); | |
1a9fc855 | 678 | n = cx25821_risc_decode(risc); |
bb4c9a74 | 679 | |
1a9fc855 MCC |
680 | for (j = 1; j < n; j++) { |
681 | risc = cx_read(ch->ctrl_start + 4 * (i + j)); | |
36d89f7d JP |
682 | pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n", |
683 | 4 * (i + j), i + j, risc, j); | |
1a9fc855 MCC |
684 | } |
685 | } | |
bb4c9a74 | 686 | |
36d89f7d JP |
687 | pr_warn(" : fifo: 0x%08x -> 0x%x\n", |
688 | ch->fifo_start, ch->fifo_start + ch->fifo_size); | |
689 | pr_warn(" : ctrl: 0x%08x -> 0x%x\n", | |
690 | ch->ctrl_start, ch->ctrl_start + 6 * 16); | |
691 | pr_warn(" : ptr1_reg: 0x%08x\n", | |
692 | cx_read(ch->ptr1_reg)); | |
693 | pr_warn(" : ptr2_reg: 0x%08x\n", | |
694 | cx_read(ch->ptr2_reg)); | |
695 | pr_warn(" : cnt1_reg: 0x%08x\n", | |
696 | cx_read(ch->cnt1_reg)); | |
697 | pr_warn(" : cnt2_reg: 0x%08x\n", | |
698 | cx_read(ch->cnt2_reg)); | |
1a9fc855 MCC |
699 | |
700 | for (i = 0; i < 4; i++) { | |
701 | risc = cx_read(ch->cmds_start + 56 + (i * 4)); | |
36d89f7d | 702 | pr_warn("instruction %d = 0x%x\n", i, risc); |
1a9fc855 | 703 | } |
bb4c9a74 | 704 | |
de2c4349 | 705 | /* read data from the first cdt buffer */ |
1a9fc855 | 706 | risc = cx_read(AUD_A_CDT); |
36d89f7d | 707 | pr_warn("\nread cdt loc=0x%x\n", risc); |
1a9fc855 MCC |
708 | for (i = 0; i < 8; i++) { |
709 | n = cx_read(risc + i * 4); | |
36d89f7d | 710 | pr_cont("0x%x ", n); |
bb4c9a74 | 711 | } |
36d89f7d | 712 | pr_cont("\n\n"); |
1a9fc855 MCC |
713 | |
714 | value = cx_read(CLK_RST); | |
de2c4349 | 715 | CX25821_INFO(" CLK_RST = 0x%x\n\n", value); |
1a9fc855 MCC |
716 | |
717 | value = cx_read(PLL_A_POST_STAT_BIST); | |
de2c4349 | 718 | CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value); |
1a9fc855 | 719 | value = cx_read(PLL_A_INT_FRAC); |
de2c4349 | 720 | CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value); |
1a9fc855 MCC |
721 | |
722 | value = cx_read(PLL_B_POST_STAT_BIST); | |
de2c4349 | 723 | CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value); |
1a9fc855 | 724 | value = cx_read(PLL_B_INT_FRAC); |
de2c4349 | 725 | CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value); |
1a9fc855 MCC |
726 | |
727 | value = cx_read(PLL_C_POST_STAT_BIST); | |
de2c4349 | 728 | CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value); |
1a9fc855 | 729 | value = cx_read(PLL_C_INT_FRAC); |
de2c4349 | 730 | CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value); |
1a9fc855 MCC |
731 | |
732 | value = cx_read(PLL_D_POST_STAT_BIST); | |
de2c4349 | 733 | CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value); |
1a9fc855 | 734 | value = cx_read(PLL_D_INT_FRAC); |
de2c4349 | 735 | CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value); |
1a9fc855 MCC |
736 | |
737 | value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp); | |
de2c4349 | 738 | CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value); |
02b20b0b | 739 | } |
de2c4349 | 740 | EXPORT_SYMBOL(cx25821_sram_channel_dump_audio); |
02b20b0b MCC |
741 | |
742 | static void cx25821_shutdown(struct cx25821_dev *dev) | |
743 | { | |
1a9fc855 | 744 | int i; |
02b20b0b | 745 | |
1a9fc855 MCC |
746 | /* disable RISC controller */ |
747 | cx_write(DEV_CNTRL2, 0); | |
02b20b0b | 748 | |
1a9fc855 MCC |
749 | /* Disable Video A/B activity */ |
750 | for (i = 0; i < VID_CHANNEL_NUM; i++) { | |
e4115bb2 RP |
751 | cx_write(dev->channels[i].sram_channels->dma_ctl, 0); |
752 | cx_write(dev->channels[i].sram_channels->int_msk, 0); | |
1a9fc855 | 753 | } |
02b20b0b | 754 | |
e4115bb2 RP |
755 | for (i = VID_UPSTREAM_SRAM_CHANNEL_I; |
756 | i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) { | |
757 | cx_write(dev->channels[i].sram_channels->dma_ctl, 0); | |
758 | cx_write(dev->channels[i].sram_channels->int_msk, 0); | |
1a9fc855 | 759 | } |
bb4c9a74 | 760 | |
1a9fc855 MCC |
761 | /* Disable Audio activity */ |
762 | cx_write(AUD_INT_DMA_CTL, 0); | |
02b20b0b | 763 | |
1a9fc855 MCC |
764 | /* Disable Serial port */ |
765 | cx_write(UART_CTL, 0); | |
02b20b0b | 766 | |
1a9fc855 MCC |
767 | /* Disable Interrupts */ |
768 | cx_write(PCI_INT_MSK, 0); | |
769 | cx_write(AUD_A_INT_MSK, 0); | |
02b20b0b MCC |
770 | } |
771 | ||
1a9fc855 MCC |
772 | void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select, |
773 | u32 format) | |
bb4c9a74 | 774 | { |
1a9fc855 | 775 | if (channel_select <= 7 && channel_select >= 0) { |
3f0bfe5b LF |
776 | cx_write(dev->channels[channel_select].sram_channels->pix_frmt, |
777 | format); | |
1a9fc855 | 778 | } |
ea3f7ac6 | 779 | dev->channels[channel_select].pixel_formats = format; |
02b20b0b MCC |
780 | } |
781 | ||
1a9fc855 | 782 | static void cx25821_set_vip_mode(struct cx25821_dev *dev, |
bfef0d35 | 783 | const struct sram_channel *ch) |
02b20b0b | 784 | { |
1a9fc855 MCC |
785 | cx_write(ch->pix_frmt, PIXEL_FRMT_422); |
786 | cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1); | |
02b20b0b MCC |
787 | } |
788 | ||
789 | static void cx25821_initialize(struct cx25821_dev *dev) | |
790 | { | |
1a9fc855 | 791 | int i; |
bb4c9a74 | 792 | |
1a9fc855 | 793 | dprintk(1, "%s()\n", __func__); |
bb4c9a74 | 794 | |
1a9fc855 MCC |
795 | cx25821_shutdown(dev); |
796 | cx_write(PCI_INT_STAT, 0xffffffff); | |
02b20b0b | 797 | |
1a9fc855 | 798 | for (i = 0; i < VID_CHANNEL_NUM; i++) |
e4115bb2 | 799 | cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff); |
02b20b0b | 800 | |
1a9fc855 MCC |
801 | cx_write(AUD_A_INT_STAT, 0xffffffff); |
802 | cx_write(AUD_B_INT_STAT, 0xffffffff); | |
803 | cx_write(AUD_C_INT_STAT, 0xffffffff); | |
804 | cx_write(AUD_D_INT_STAT, 0xffffffff); | |
805 | cx_write(AUD_E_INT_STAT, 0xffffffff); | |
02b20b0b | 806 | |
1a9fc855 | 807 | cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000); |
de2c4349 OP |
808 | cx_write(PAD_CTRL, 0x12); /* for I2C */ |
809 | cx25821_registers_init(dev); /* init Pecos registers */ | |
1a9fc855 | 810 | mdelay(100); |
bb4c9a74 | 811 | |
1a9fc855 | 812 | for (i = 0; i < VID_CHANNEL_NUM; i++) { |
e4115bb2 RP |
813 | cx25821_set_vip_mode(dev, dev->channels[i].sram_channels); |
814 | cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels, | |
815 | 1440, 0); | |
816 | dev->channels[i].pixel_formats = PIXEL_FRMT_422; | |
bad1f29d | 817 | dev->channels[i].use_cif_resolution = 0; |
1a9fc855 | 818 | } |
bb4c9a74 | 819 | |
de2c4349 | 820 | /* Probably only affect Downstream */ |
e4115bb2 RP |
821 | for (i = VID_UPSTREAM_SRAM_CHANNEL_I; |
822 | i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) { | |
ea3f7ac6 | 823 | dev->channels[i].pixel_formats = PIXEL_FRMT_422; |
e4115bb2 | 824 | cx25821_set_vip_mode(dev, dev->channels[i].sram_channels); |
1a9fc855 | 825 | } |
bb4c9a74 | 826 | |
e4115bb2 | 827 | cx25821_sram_channel_setup_audio(dev, |
3f0bfe5b | 828 | dev->channels[SRAM_CH08].sram_channels, 128, 0); |
02b20b0b | 829 | |
1a9fc855 | 830 | cx25821_gpio_init(dev); |
02b20b0b MCC |
831 | } |
832 | ||
f2466d63 | 833 | static int cx25821_get_resources(struct cx25821_dev *dev) |
02b20b0b | 834 | { |
3f0bfe5b LF |
835 | if (request_mem_region(pci_resource_start(dev->pci, 0), |
836 | pci_resource_len(dev->pci, 0), dev->name)) | |
1a9fc855 | 837 | return 0; |
02b20b0b | 838 | |
36d89f7d | 839 | pr_err("%s: can't get MMIO memory @ 0x%llx\n", |
c14ea5e5 | 840 | dev->name, (unsigned long long)pci_resource_start(dev->pci, 0)); |
02b20b0b | 841 | |
1a9fc855 | 842 | return -EBUSY; |
02b20b0b MCC |
843 | } |
844 | ||
02b20b0b MCC |
845 | static void cx25821_dev_checkrevision(struct cx25821_dev *dev) |
846 | { | |
1a9fc855 | 847 | dev->hwrevision = cx_read(RDR_CFG2) & 0xff; |
02b20b0b | 848 | |
467870ca | 849 | pr_info("Hardware revision = 0x%02x\n", dev->hwrevision); |
02b20b0b MCC |
850 | } |
851 | ||
852 | static void cx25821_iounmap(struct cx25821_dev *dev) | |
853 | { | |
1a9fc855 MCC |
854 | if (dev == NULL) |
855 | return; | |
856 | ||
857 | /* Releasing IO memory */ | |
858 | if (dev->lmmio != NULL) { | |
1a9fc855 MCC |
859 | iounmap(dev->lmmio); |
860 | dev->lmmio = NULL; | |
861 | } | |
02b20b0b MCC |
862 | } |
863 | ||
02b20b0b | 864 | static int cx25821_dev_setup(struct cx25821_dev *dev) |
bb4c9a74 | 865 | { |
a8f35ce3 | 866 | static unsigned int cx25821_devcount; |
30fdf035 | 867 | int i; |
1a9fc855 | 868 | |
1a9fc855 MCC |
869 | mutex_init(&dev->lock); |
870 | ||
1a9fc855 MCC |
871 | dev->nr = ++cx25821_devcount; |
872 | sprintf(dev->name, "cx25821[%d]", dev->nr); | |
873 | ||
1a9fc855 | 874 | if (dev->pci->device != 0x8210) { |
36d89f7d JP |
875 | pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n", |
876 | __func__, dev->pci->device); | |
b671ae6b | 877 | return -ENODEV; |
1a9fc855 | 878 | } |
b671ae6b | 879 | pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device); |
02b20b0b | 880 | |
1a9fc855 MCC |
881 | /* Apply a sensible clock frequency for the PCIe bridge */ |
882 | dev->clk_freq = 28000000; | |
f8d7ee70 HV |
883 | for (i = 0; i < MAX_VID_CHANNEL_NUM; i++) { |
884 | dev->channels[i].dev = dev; | |
885 | dev->channels[i].id = i; | |
e4115bb2 | 886 | dev->channels[i].sram_channels = &cx25821_sram_channels[i]; |
f8d7ee70 | 887 | } |
02b20b0b | 888 | |
de2c4349 | 889 | if (dev->nr > 1) |
1a9fc855 | 890 | CX25821_INFO("dev->nr > 1!"); |
bb4c9a74 | 891 | |
1a9fc855 | 892 | /* board config */ |
de2c4349 | 893 | dev->board = 1; /* card[dev->nr]; */ |
1a9fc855 MCC |
894 | dev->_max_num_decoders = MAX_DECODERS; |
895 | ||
896 | dev->pci_bus = dev->pci->bus->number; | |
897 | dev->pci_slot = PCI_SLOT(dev->pci->devfn); | |
898 | dev->pci_irqmask = 0x001f00; | |
899 | ||
900 | /* External Master 1 Bus */ | |
901 | dev->i2c_bus[0].nr = 0; | |
902 | dev->i2c_bus[0].dev = dev; | |
903 | dev->i2c_bus[0].reg_stat = I2C1_STAT; | |
904 | dev->i2c_bus[0].reg_ctrl = I2C1_CTRL; | |
905 | dev->i2c_bus[0].reg_addr = I2C1_ADDR; | |
906 | dev->i2c_bus[0].reg_rdata = I2C1_RDATA; | |
907 | dev->i2c_bus[0].reg_wdata = I2C1_WDATA; | |
908 | dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */ | |
909 | ||
f2466d63 | 910 | if (cx25821_get_resources(dev) < 0) { |
36d89f7d | 911 | pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n", |
1a9fc855 MCC |
912 | dev->name, dev->pci->subsystem_vendor, |
913 | dev->pci->subsystem_device); | |
914 | ||
915 | cx25821_devcount--; | |
c37c6d21 | 916 | return -EBUSY; |
1a9fc855 | 917 | } |
bb4c9a74 | 918 | |
1a9fc855 MCC |
919 | /* PCIe stuff */ |
920 | dev->base_io_addr = pci_resource_start(dev->pci, 0); | |
02b20b0b | 921 | |
1a9fc855 MCC |
922 | if (!dev->base_io_addr) { |
923 | CX25821_ERR("No PCI Memory resources, exiting!\n"); | |
924 | return -ENODEV; | |
925 | } | |
bb4c9a74 | 926 | |
1a9fc855 | 927 | dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0)); |
02b20b0b | 928 | |
1a9fc855 | 929 | if (!dev->lmmio) { |
3f0bfe5b | 930 | CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n"); |
1a9fc855 MCC |
931 | cx25821_iounmap(dev); |
932 | return -ENOMEM; | |
933 | } | |
934 | ||
935 | dev->bmmio = (u8 __iomem *) dev->lmmio; | |
02b20b0b | 936 | |
36d89f7d JP |
937 | pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", |
938 | dev->name, dev->pci->subsystem_vendor, | |
939 | dev->pci->subsystem_device, cx25821_boards[dev->board].name, | |
940 | dev->board, card[dev->nr] == dev->board ? | |
941 | "insmod option" : "autodetected"); | |
02b20b0b | 942 | |
1a9fc855 MCC |
943 | /* init hardware */ |
944 | cx25821_initialize(dev); | |
bb4c9a74 | 945 | |
1a9fc855 | 946 | cx25821_i2c_register(&dev->i2c_bus[0]); |
de2c4349 OP |
947 | /* cx25821_i2c_register(&dev->i2c_bus[1]); |
948 | * cx25821_i2c_register(&dev->i2c_bus[2]); */ | |
02b20b0b | 949 | |
e4115bb2 | 950 | if (medusa_video_init(dev) < 0) |
36d89f7d | 951 | CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__); |
bb4c9a74 | 952 | |
e4115bb2 | 953 | cx25821_video_register(dev); |
bb4c9a74 | 954 | |
1a9fc855 | 955 | cx25821_dev_checkrevision(dev); |
1a9fc855 | 956 | return 0; |
bb4c9a74 | 957 | } |
02b20b0b | 958 | |
02b20b0b MCC |
959 | void cx25821_dev_unregister(struct cx25821_dev *dev) |
960 | { | |
1a9fc855 | 961 | int i; |
bb4c9a74 | 962 | |
1a9fc855 MCC |
963 | if (!dev->base_io_addr) |
964 | return; | |
bb4c9a74 | 965 | |
1a9fc855 | 966 | release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0)); |
02b20b0b | 967 | |
b6f21dc3 | 968 | for (i = 0; i < MAX_VID_CAP_CHANNEL_NUM - 1; i++) { |
31b32073 HV |
969 | if (i == SRAM_CH08) /* audio channel */ |
970 | continue; | |
b6f21dc3 HV |
971 | /* |
972 | * TODO: enable when video output is properly | |
973 | * supported. | |
7087d31b HV |
974 | if (i == SRAM_CH09 || i == SRAM_CH10) |
975 | cx25821_free_mem_upstream(&dev->channels[i]); | |
b6f21dc3 | 976 | */ |
1a9fc855 MCC |
977 | cx25821_video_unregister(dev, i); |
978 | } | |
bb4c9a74 | 979 | |
1a9fc855 MCC |
980 | cx25821_i2c_unregister(&dev->i2c_bus[0]); |
981 | cx25821_iounmap(dev); | |
02b20b0b | 982 | } |
de2c4349 | 983 | EXPORT_SYMBOL(cx25821_dev_unregister); |
02b20b0b | 984 | |
5ede94c7 HV |
985 | int cx25821_riscmem_alloc(struct pci_dev *pci, |
986 | struct cx25821_riscmem *risc, | |
987 | unsigned int size) | |
988 | { | |
989 | __le32 *cpu; | |
990 | dma_addr_t dma = 0; | |
991 | ||
992 | if (NULL != risc->cpu && risc->size < size) | |
993 | pci_free_consistent(pci, risc->size, risc->cpu, risc->dma); | |
994 | if (NULL == risc->cpu) { | |
995 | cpu = pci_zalloc_consistent(pci, size, &dma); | |
996 | if (NULL == cpu) | |
997 | return -ENOMEM; | |
998 | risc->cpu = cpu; | |
999 | risc->dma = dma; | |
1000 | risc->size = size; | |
1001 | } | |
1002 | return 0; | |
1003 | } | |
1004 | EXPORT_SYMBOL(cx25821_riscmem_alloc); | |
1005 | ||
1a9fc855 MCC |
1006 | static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist, |
1007 | unsigned int offset, u32 sync_line, | |
1008 | unsigned int bpl, unsigned int padding, | |
b671ae6b | 1009 | unsigned int lines, bool jump) |
02b20b0b | 1010 | { |
1a9fc855 MCC |
1011 | struct scatterlist *sg; |
1012 | unsigned int line, todo; | |
1013 | ||
b671ae6b HV |
1014 | if (jump) { |
1015 | *(rp++) = cpu_to_le32(RISC_JUMP); | |
1016 | *(rp++) = cpu_to_le32(0); | |
1017 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1018 | } | |
1019 | ||
1a9fc855 | 1020 | /* sync instruction */ |
de2c4349 | 1021 | if (sync_line != NO_SYNC_LINE) |
1a9fc855 | 1022 | *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); |
bb4c9a74 | 1023 | |
1a9fc855 MCC |
1024 | /* scan lines */ |
1025 | sg = sglist; | |
1026 | for (line = 0; line < lines; line++) { | |
1027 | while (offset && offset >= sg_dma_len(sg)) { | |
1028 | offset -= sg_dma_len(sg); | |
872dfcfe | 1029 | sg = sg_next(sg); |
1a9fc855 MCC |
1030 | } |
1031 | if (bpl <= sg_dma_len(sg) - offset) { | |
1032 | /* fits into current chunk */ | |
3f0bfe5b LF |
1033 | *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | |
1034 | bpl); | |
1a9fc855 MCC |
1035 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); |
1036 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1037 | offset += bpl; | |
1038 | } else { | |
1039 | /* scanline needs to be split */ | |
1040 | todo = bpl; | |
3f0bfe5b | 1041 | *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | |
1a9fc855 MCC |
1042 | (sg_dma_len(sg) - offset)); |
1043 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); | |
1044 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1045 | todo -= (sg_dma_len(sg) - offset); | |
1046 | offset = 0; | |
872dfcfe | 1047 | sg = sg_next(sg); |
1a9fc855 | 1048 | while (todo > sg_dma_len(sg)) { |
3f0bfe5b LF |
1049 | *(rp++) = cpu_to_le32(RISC_WRITE | |
1050 | sg_dma_len(sg)); | |
1a9fc855 MCC |
1051 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); |
1052 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1053 | todo -= sg_dma_len(sg); | |
872dfcfe | 1054 | sg = sg_next(sg); |
1a9fc855 MCC |
1055 | } |
1056 | *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); | |
1057 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); | |
1058 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1059 | offset += todo; | |
1060 | } | |
1061 | ||
1062 | offset += padding; | |
1063 | } | |
02b20b0b | 1064 | |
1a9fc855 | 1065 | return rp; |
02b20b0b MCC |
1066 | } |
1067 | ||
5ede94c7 | 1068 | int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc, |
1a9fc855 MCC |
1069 | struct scatterlist *sglist, unsigned int top_offset, |
1070 | unsigned int bottom_offset, unsigned int bpl, | |
1071 | unsigned int padding, unsigned int lines) | |
02b20b0b | 1072 | { |
1a9fc855 MCC |
1073 | u32 instructions; |
1074 | u32 fields; | |
1075 | __le32 *rp; | |
1076 | int rc; | |
1077 | ||
1078 | fields = 0; | |
1079 | if (UNSET != top_offset) | |
1080 | fields++; | |
1081 | if (UNSET != bottom_offset) | |
1082 | fields++; | |
1083 | ||
1084 | /* estimate risc mem: worst case is one write per page border + | |
b671ae6b | 1085 | one write per scan line + syncs + jump (all 3 dwords). Padding |
1a9fc855 MCC |
1086 | can cause next bpl to start close to a page border. First DMA |
1087 | region may be smaller than PAGE_SIZE */ | |
1088 | /* write and jump need and extra dword */ | |
3f0bfe5b LF |
1089 | instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + |
1090 | lines); | |
b671ae6b | 1091 | instructions += 5; |
5ede94c7 | 1092 | rc = cx25821_riscmem_alloc(pci, risc, instructions * 12); |
1a9fc855 MCC |
1093 | |
1094 | if (rc < 0) | |
1095 | return rc; | |
1096 | ||
1097 | /* write risc instructions */ | |
1098 | rp = risc->cpu; | |
1099 | ||
1100 | if (UNSET != top_offset) { | |
1101 | rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding, | |
b671ae6b | 1102 | lines, true); |
1a9fc855 | 1103 | } |
02b20b0b | 1104 | |
1a9fc855 MCC |
1105 | if (UNSET != bottom_offset) { |
1106 | rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl, | |
b671ae6b | 1107 | padding, lines, UNSET == top_offset); |
bb4c9a74 MCC |
1108 | } |
1109 | ||
1a9fc855 MCC |
1110 | /* save pointer to jmp instruction address */ |
1111 | risc->jmp = rp; | |
b671ae6b | 1112 | BUG_ON((risc->jmp - risc->cpu + 3) * sizeof(*risc->cpu) > risc->size); |
1a9fc855 MCC |
1113 | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist, | |
1118 | unsigned int offset, u32 sync_line, | |
1119 | unsigned int bpl, unsigned int padding, | |
1120 | unsigned int lines, unsigned int lpi) | |
1121 | { | |
1122 | struct scatterlist *sg; | |
1123 | unsigned int line, todo, sol; | |
1124 | ||
1125 | /* sync instruction */ | |
1126 | if (sync_line != NO_SYNC_LINE) | |
1127 | *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); | |
1128 | ||
1129 | /* scan lines */ | |
1130 | sg = sglist; | |
1131 | for (line = 0; line < lines; line++) { | |
1132 | while (offset && offset >= sg_dma_len(sg)) { | |
1133 | offset -= sg_dma_len(sg); | |
872dfcfe | 1134 | sg = sg_next(sg); |
1a9fc855 MCC |
1135 | } |
1136 | ||
1137 | if (lpi && line > 0 && !(line % lpi)) | |
1138 | sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; | |
1139 | else | |
1140 | sol = RISC_SOL; | |
1141 | ||
1142 | if (bpl <= sg_dma_len(sg) - offset) { | |
1143 | /* fits into current chunk */ | |
3f0bfe5b LF |
1144 | *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL | |
1145 | bpl); | |
1a9fc855 MCC |
1146 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); |
1147 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1148 | offset += bpl; | |
1149 | } else { | |
1150 | /* scanline needs to be split */ | |
1151 | todo = bpl; | |
1152 | *(rp++) = cpu_to_le32(RISC_WRITE | sol | | |
c14ea5e5 | 1153 | (sg_dma_len(sg) - offset)); |
1a9fc855 MCC |
1154 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); |
1155 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1156 | todo -= (sg_dma_len(sg) - offset); | |
1157 | offset = 0; | |
872dfcfe | 1158 | sg = sg_next(sg); |
1a9fc855 MCC |
1159 | while (todo > sg_dma_len(sg)) { |
1160 | *(rp++) = cpu_to_le32(RISC_WRITE | | |
c14ea5e5 | 1161 | sg_dma_len(sg)); |
1a9fc855 MCC |
1162 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); |
1163 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1164 | todo -= sg_dma_len(sg); | |
872dfcfe | 1165 | sg = sg_next(sg); |
1a9fc855 MCC |
1166 | } |
1167 | *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); | |
1168 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); | |
1169 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */ | |
1170 | offset += todo; | |
1171 | } | |
1172 | offset += padding; | |
bb4c9a74 | 1173 | } |
02b20b0b | 1174 | |
1a9fc855 | 1175 | return rp; |
02b20b0b MCC |
1176 | } |
1177 | ||
1178 | int cx25821_risc_databuffer_audio(struct pci_dev *pci, | |
5ede94c7 | 1179 | struct cx25821_riscmem *risc, |
1a9fc855 MCC |
1180 | struct scatterlist *sglist, |
1181 | unsigned int bpl, | |
1182 | unsigned int lines, unsigned int lpi) | |
02b20b0b | 1183 | { |
1a9fc855 MCC |
1184 | u32 instructions; |
1185 | __le32 *rp; | |
1186 | int rc; | |
1187 | ||
1188 | /* estimate risc mem: worst case is one write per page border + | |
1189 | one write per scan line + syncs + jump (all 2 dwords). Here | |
1190 | there is no padding and no sync. First DMA region may be smaller | |
1191 | than PAGE_SIZE */ | |
1192 | /* Jump and write need an extra dword */ | |
1193 | instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; | |
1194 | instructions += 1; | |
1195 | ||
5ede94c7 | 1196 | rc = cx25821_riscmem_alloc(pci, risc, instructions * 12); |
de2c4349 | 1197 | if (rc < 0) |
1a9fc855 MCC |
1198 | return rc; |
1199 | ||
1200 | /* write risc instructions */ | |
1201 | rp = risc->cpu; | |
1202 | rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, | |
1203 | lines, lpi); | |
1204 | ||
1205 | /* save pointer to jmp instruction address */ | |
1206 | risc->jmp = rp; | |
1207 | BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); | |
1208 | return 0; | |
02b20b0b | 1209 | } |
de2c4349 | 1210 | EXPORT_SYMBOL(cx25821_risc_databuffer_audio); |
02b20b0b | 1211 | |
b671ae6b | 1212 | void cx25821_free_buffer(struct cx25821_dev *dev, struct cx25821_buffer *buf) |
02b20b0b | 1213 | { |
1a9fc855 | 1214 | BUG_ON(in_interrupt()); |
b671ae6b HV |
1215 | if (WARN_ON(buf->risc.size == 0)) |
1216 | return; | |
1217 | pci_free_consistent(dev->pci, | |
5ede94c7 | 1218 | buf->risc.size, buf->risc.cpu, buf->risc.dma); |
b671ae6b | 1219 | memset(&buf->risc, 0, sizeof(buf->risc)); |
02b20b0b MCC |
1220 | } |
1221 | ||
02b20b0b MCC |
1222 | static irqreturn_t cx25821_irq(int irq, void *dev_id) |
1223 | { | |
1a9fc855 | 1224 | struct cx25821_dev *dev = dev_id; |
30fdf035 | 1225 | u32 pci_status; |
1a9fc855 MCC |
1226 | u32 vid_status; |
1227 | int i, handled = 0; | |
1228 | u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; | |
02b20b0b | 1229 | |
1a9fc855 | 1230 | pci_status = cx_read(PCI_INT_STAT); |
02b20b0b | 1231 | |
1a9fc855 MCC |
1232 | if (pci_status == 0) |
1233 | goto out; | |
bb4c9a74 | 1234 | |
1a9fc855 MCC |
1235 | for (i = 0; i < VID_CHANNEL_NUM; i++) { |
1236 | if (pci_status & mask[i]) { | |
e4115bb2 RP |
1237 | vid_status = cx_read(dev->channels[i]. |
1238 | sram_channels->int_stat); | |
02b20b0b | 1239 | |
1a9fc855 | 1240 | if (vid_status) |
3f0bfe5b LF |
1241 | handled += cx25821_video_irq(dev, i, |
1242 | vid_status); | |
02b20b0b | 1243 | |
1a9fc855 MCC |
1244 | cx_write(PCI_INT_STAT, mask[i]); |
1245 | } | |
bb4c9a74 | 1246 | } |
bb4c9a74 | 1247 | |
de2c4349 | 1248 | out: |
1a9fc855 | 1249 | return IRQ_RETVAL(handled); |
02b20b0b MCC |
1250 | } |
1251 | ||
1252 | void cx25821_print_irqbits(char *name, char *tag, char **strings, | |
bb4c9a74 | 1253 | int len, u32 bits, u32 mask) |
02b20b0b | 1254 | { |
1a9fc855 MCC |
1255 | unsigned int i; |
1256 | ||
36d89f7d | 1257 | printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits); |
1a9fc855 MCC |
1258 | |
1259 | for (i = 0; i < len; i++) { | |
1260 | if (!(bits & (1 << i))) | |
1261 | continue; | |
1262 | if (strings[i]) | |
36d89f7d | 1263 | pr_cont(" %s", strings[i]); |
1a9fc855 | 1264 | else |
36d89f7d | 1265 | pr_cont(" %d", i); |
1a9fc855 MCC |
1266 | if (!(mask & (1 << i))) |
1267 | continue; | |
36d89f7d | 1268 | pr_cont("*"); |
1a9fc855 | 1269 | } |
36d89f7d | 1270 | pr_cont("\n"); |
02b20b0b | 1271 | } |
de2c4349 | 1272 | EXPORT_SYMBOL(cx25821_print_irqbits); |
02b20b0b | 1273 | |
1a9fc855 | 1274 | struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci) |
02b20b0b | 1275 | { |
1a9fc855 MCC |
1276 | struct cx25821_dev *dev = pci_get_drvdata(pci); |
1277 | return dev; | |
02b20b0b | 1278 | } |
de2c4349 | 1279 | EXPORT_SYMBOL(cx25821_dev_get); |
02b20b0b | 1280 | |
4c62e976 GKH |
1281 | static int cx25821_initdev(struct pci_dev *pci_dev, |
1282 | const struct pci_device_id *pci_id) | |
02b20b0b | 1283 | { |
1a9fc855 MCC |
1284 | struct cx25821_dev *dev; |
1285 | int err = 0; | |
bb4c9a74 | 1286 | |
1a9fc855 MCC |
1287 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
1288 | if (NULL == dev) | |
1289 | return -ENOMEM; | |
bb4c9a74 | 1290 | |
1a9fc855 MCC |
1291 | err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); |
1292 | if (err < 0) | |
1293 | goto fail_free; | |
02b20b0b | 1294 | |
1a9fc855 MCC |
1295 | /* pci init */ |
1296 | dev->pci = pci_dev; | |
1297 | if (pci_enable_device(pci_dev)) { | |
1298 | err = -EIO; | |
02b20b0b | 1299 | |
36d89f7d | 1300 | pr_info("pci enable failed!\n"); |
02b20b0b | 1301 | |
1a9fc855 MCC |
1302 | goto fail_unregister_device; |
1303 | } | |
b671ae6b HV |
1304 | dev->alloc_ctx = vb2_dma_sg_init_ctx(&pci_dev->dev); |
1305 | if (IS_ERR(dev->alloc_ctx)) { | |
1306 | err = PTR_ERR(dev->alloc_ctx); | |
1307 | goto fail_unregister_pci; | |
1308 | } | |
02b20b0b | 1309 | |
c37c6d21 | 1310 | err = cx25821_dev_setup(dev); |
b671ae6b HV |
1311 | if (err) |
1312 | goto fail_free_ctx; | |
02b20b0b | 1313 | |
1a9fc855 MCC |
1314 | /* print pci info */ |
1315 | pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); | |
1316 | pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); | |
36d89f7d JP |
1317 | pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n", |
1318 | dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq, | |
1319 | dev->pci_lat, (unsigned long long)dev->base_io_addr); | |
1a9fc855 MCC |
1320 | |
1321 | pci_set_master(pci_dev); | |
251c5912 | 1322 | if (!pci_set_dma_mask(pci_dev, 0xffffffff)) { |
36d89f7d | 1323 | pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); |
1a9fc855 MCC |
1324 | err = -EIO; |
1325 | goto fail_irq; | |
1326 | } | |
02b20b0b | 1327 | |
3f0bfe5b LF |
1328 | err = request_irq(pci_dev->irq, cx25821_irq, |
1329 | IRQF_SHARED, dev->name, dev); | |
02b20b0b | 1330 | |
1a9fc855 | 1331 | if (err < 0) { |
36d89f7d | 1332 | pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq); |
1a9fc855 MCC |
1333 | goto fail_irq; |
1334 | } | |
02b20b0b | 1335 | |
1a9fc855 | 1336 | return 0; |
02b20b0b | 1337 | |
de2c4349 | 1338 | fail_irq: |
36d89f7d | 1339 | pr_info("cx25821_initdev() can't get IRQ !\n"); |
1a9fc855 | 1340 | cx25821_dev_unregister(dev); |
bb4c9a74 | 1341 | |
b671ae6b HV |
1342 | fail_free_ctx: |
1343 | vb2_dma_sg_cleanup_ctx(dev->alloc_ctx); | |
c37c6d21 KV |
1344 | fail_unregister_pci: |
1345 | pci_disable_device(pci_dev); | |
de2c4349 | 1346 | fail_unregister_device: |
1a9fc855 | 1347 | v4l2_device_unregister(&dev->v4l2_dev); |
bb4c9a74 | 1348 | |
de2c4349 | 1349 | fail_free: |
1a9fc855 MCC |
1350 | kfree(dev); |
1351 | return err; | |
02b20b0b MCC |
1352 | } |
1353 | ||
4c62e976 | 1354 | static void cx25821_finidev(struct pci_dev *pci_dev) |
02b20b0b | 1355 | { |
1a9fc855 MCC |
1356 | struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); |
1357 | struct cx25821_dev *dev = get_cx25821(v4l2_dev); | |
bb4c9a74 | 1358 | |
1a9fc855 MCC |
1359 | cx25821_shutdown(dev); |
1360 | pci_disable_device(pci_dev); | |
02b20b0b | 1361 | |
1a9fc855 MCC |
1362 | /* unregister stuff */ |
1363 | if (pci_dev->irq) | |
1364 | free_irq(pci_dev->irq, dev); | |
bb4c9a74 | 1365 | |
1a9fc855 | 1366 | cx25821_dev_unregister(dev); |
b671ae6b | 1367 | vb2_dma_sg_cleanup_ctx(dev->alloc_ctx); |
1a9fc855 MCC |
1368 | v4l2_device_unregister(v4l2_dev); |
1369 | kfree(dev); | |
02b20b0b MCC |
1370 | } |
1371 | ||
f1b84d36 | 1372 | static const struct pci_device_id cx25821_pci_tbl[] = { |
1a9fc855 | 1373 | { |
1c2b5520 LF |
1374 | /* CX25821 Athena */ |
1375 | .vendor = 0x14f1, | |
1376 | .device = 0x8210, | |
1377 | .subvendor = 0x14f1, | |
1378 | .subdevice = 0x0920, | |
632fba4d SE |
1379 | }, { |
1380 | /* CX25821 No Brand */ | |
1381 | .vendor = 0x14f1, | |
1382 | .device = 0x8210, | |
1383 | .subvendor = 0x0000, | |
1384 | .subdevice = 0x0000, | |
1385 | }, { | |
1c2b5520 LF |
1386 | /* --- end of list --- */ |
1387 | } | |
02b20b0b MCC |
1388 | }; |
1389 | ||
1390 | MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl); | |
1391 | ||
1a9fc855 MCC |
1392 | static struct pci_driver cx25821_pci_driver = { |
1393 | .name = "cx25821", | |
1394 | .id_table = cx25821_pci_tbl, | |
1395 | .probe = cx25821_initdev, | |
4c62e976 | 1396 | .remove = cx25821_finidev, |
1a9fc855 MCC |
1397 | /* TODO */ |
1398 | .suspend = NULL, | |
1399 | .resume = NULL, | |
02b20b0b MCC |
1400 | }; |
1401 | ||
64ed2016 | 1402 | static int __init cx25821_init(void) |
02b20b0b | 1403 | { |
36d89f7d JP |
1404 | pr_info("driver version %d.%d.%d loaded\n", |
1405 | (CX25821_VERSION_CODE >> 16) & 0xff, | |
1406 | (CX25821_VERSION_CODE >> 8) & 0xff, | |
1407 | CX25821_VERSION_CODE & 0xff); | |
1a9fc855 | 1408 | return pci_register_driver(&cx25821_pci_driver); |
02b20b0b MCC |
1409 | } |
1410 | ||
64ed2016 | 1411 | static void __exit cx25821_fini(void) |
02b20b0b | 1412 | { |
1a9fc855 | 1413 | pci_unregister_driver(&cx25821_pci_driver); |
02b20b0b MCC |
1414 | } |
1415 | ||
02b20b0b MCC |
1416 | module_init(cx25821_init); |
1417 | module_exit(cx25821_fini); |