Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1c1e45d1 HV |
2 | /* |
3 | * cx18 init/start/stop/exit stream functions | |
4 | * | |
5 | * Derived from ivtv-streams.c | |
6 | * | |
7 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6afdeaf8 | 8 | * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> |
1c1e45d1 HV |
9 | */ |
10 | ||
11 | #include "cx18-driver.h" | |
b1526421 | 12 | #include "cx18-io.h" |
1c1e45d1 HV |
13 | #include "cx18-fileops.h" |
14 | #include "cx18-mailbox.h" | |
15 | #include "cx18-i2c.h" | |
16 | #include "cx18-queue.h" | |
17 | #include "cx18-ioctl.h" | |
18 | #include "cx18-streams.h" | |
19 | #include "cx18-cards.h" | |
20 | #include "cx18-scb.h" | |
1c1e45d1 HV |
21 | #include "cx18-dvb.h" |
22 | ||
6e6a8b5a | 23 | #define CX18_DSP0_INTERRUPT_MASK 0xd0004C |
1c1e45d1 | 24 | |
e66fb184 | 25 | static const struct v4l2_file_operations cx18_v4l2_enc_fops = { |
daf20d95 HV |
26 | .owner = THIS_MODULE, |
27 | .read = cx18_v4l2_read, | |
28 | .open = cx18_v4l2_open, | |
dcaded7e | 29 | .unlocked_ioctl = video_ioctl2, |
daf20d95 HV |
30 | .release = cx18_v4l2_close, |
31 | .poll = cx18_v4l2_enc_poll, | |
b7101de3 | 32 | .mmap = cx18_v4l2_mmap, |
1c1e45d1 HV |
33 | }; |
34 | ||
35 | /* offset from 0 to register ts v4l2 minors on */ | |
36 | #define CX18_V4L2_ENC_TS_OFFSET 16 | |
37 | /* offset from 0 to register pcm v4l2 minors on */ | |
38 | #define CX18_V4L2_ENC_PCM_OFFSET 24 | |
39 | /* offset from 0 to register yuv v4l2 minors on */ | |
40 | #define CX18_V4L2_ENC_YUV_OFFSET 32 | |
41 | ||
42 | static struct { | |
43 | const char *name; | |
44 | int vfl_type; | |
dd89601d | 45 | int num_offset; |
1c1e45d1 | 46 | int dma; |
dfdf780b | 47 | u32 caps; |
1c1e45d1 HV |
48 | } cx18_stream_info[] = { |
49 | { /* CX18_ENC_STREAM_TYPE_MPG */ | |
50 | "encoder MPEG", | |
51 | VFL_TYPE_GRABBER, 0, | |
ff82b211 | 52 | PCI_DMA_FROMDEVICE, |
dfdf780b HV |
53 | V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | |
54 | V4L2_CAP_AUDIO | V4L2_CAP_TUNER | |
1c1e45d1 HV |
55 | }, |
56 | { /* CX18_ENC_STREAM_TYPE_TS */ | |
57 | "TS", | |
58 | VFL_TYPE_GRABBER, -1, | |
ff82b211 | 59 | PCI_DMA_FROMDEVICE, |
1c1e45d1 HV |
60 | }, |
61 | { /* CX18_ENC_STREAM_TYPE_YUV */ | |
62 | "encoder YUV", | |
63 | VFL_TYPE_GRABBER, CX18_V4L2_ENC_YUV_OFFSET, | |
ff82b211 | 64 | PCI_DMA_FROMDEVICE, |
dfdf780b HV |
65 | V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | |
66 | V4L2_CAP_STREAMING | V4L2_CAP_AUDIO | V4L2_CAP_TUNER | |
1c1e45d1 HV |
67 | }, |
68 | { /* CX18_ENC_STREAM_TYPE_VBI */ | |
69 | "encoder VBI", | |
70 | VFL_TYPE_VBI, 0, | |
ff82b211 | 71 | PCI_DMA_FROMDEVICE, |
dfdf780b HV |
72 | V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE | |
73 | V4L2_CAP_READWRITE | V4L2_CAP_TUNER | |
1c1e45d1 HV |
74 | }, |
75 | { /* CX18_ENC_STREAM_TYPE_PCM */ | |
76 | "encoder PCM audio", | |
77 | VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET, | |
ff82b211 | 78 | PCI_DMA_FROMDEVICE, |
2b4fd3ed | 79 | V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, |
1c1e45d1 HV |
80 | }, |
81 | { /* CX18_ENC_STREAM_TYPE_IDX */ | |
82 | "encoder IDX", | |
83 | VFL_TYPE_GRABBER, -1, | |
ff82b211 | 84 | PCI_DMA_FROMDEVICE, |
1c1e45d1 HV |
85 | }, |
86 | { /* CX18_ENC_STREAM_TYPE_RAD */ | |
87 | "encoder radio", | |
88 | VFL_TYPE_RADIO, 0, | |
ff82b211 | 89 | PCI_DMA_NONE, |
dfdf780b | 90 | V4L2_CAP_RADIO | V4L2_CAP_TUNER |
1c1e45d1 HV |
91 | }, |
92 | }; | |
93 | ||
1bf5842f | 94 | |
5e6e81b2 | 95 | static void cx18_dma_free(struct videobuf_queue *q, |
1bf5842f SF |
96 | struct cx18_stream *s, struct cx18_videobuf_buffer *buf) |
97 | { | |
98 | videobuf_waiton(q, &buf->vb, 0, 0); | |
99 | videobuf_vmalloc_free(&buf->vb); | |
100 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
101 | } | |
102 | ||
103 | static int cx18_prepare_buffer(struct videobuf_queue *q, | |
104 | struct cx18_stream *s, | |
105 | struct cx18_videobuf_buffer *buf, | |
106 | u32 pixelformat, | |
107 | unsigned int width, unsigned int height, | |
108 | enum v4l2_field field) | |
109 | { | |
4a3fad70 | 110 | struct cx18 *cx = s->cx; |
1bf5842f SF |
111 | int rc = 0; |
112 | ||
113 | /* check settings */ | |
114 | buf->bytes_used = 0; | |
115 | ||
116 | if ((width < 48) || (height < 32)) | |
117 | return -EINVAL; | |
118 | ||
119 | buf->vb.size = (width * height * 2); | |
120 | if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size)) | |
121 | return -EINVAL; | |
122 | ||
123 | /* alloc + fill struct (if changed) */ | |
124 | if (buf->vb.width != width || buf->vb.height != height || | |
125 | buf->vb.field != field || s->pixelformat != pixelformat || | |
126 | buf->tvnorm != cx->std) { | |
127 | ||
128 | buf->vb.width = width; | |
129 | buf->vb.height = height; | |
130 | buf->vb.field = field; | |
131 | buf->tvnorm = cx->std; | |
132 | s->pixelformat = pixelformat; | |
133 | ||
09fc9802 SF |
134 | /* HM12 YUV size is (Y=(h*720) + UV=(h*(720/2))) |
135 | UYUV YUV size is (Y=(h*720) + UV=(h*(720))) */ | |
136 | if (s->pixelformat == V4L2_PIX_FMT_HM12) | |
137 | s->vb_bytes_per_frame = height * 720 * 3 / 2; | |
138 | else | |
139 | s->vb_bytes_per_frame = height * 720 * 2; | |
1bf5842f SF |
140 | cx18_dma_free(q, s, buf); |
141 | } | |
142 | ||
143 | if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size)) | |
144 | return -EINVAL; | |
145 | ||
146 | if (buf->vb.field == 0) | |
147 | buf->vb.field = V4L2_FIELD_INTERLACED; | |
148 | ||
149 | if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { | |
150 | buf->vb.width = width; | |
151 | buf->vb.height = height; | |
152 | buf->vb.field = field; | |
153 | buf->tvnorm = cx->std; | |
154 | s->pixelformat = pixelformat; | |
155 | ||
09fc9802 SF |
156 | /* HM12 YUV size is (Y=(h*720) + UV=(h*(720/2))) |
157 | UYUV YUV size is (Y=(h*720) + UV=(h*(720))) */ | |
158 | if (s->pixelformat == V4L2_PIX_FMT_HM12) | |
159 | s->vb_bytes_per_frame = height * 720 * 3 / 2; | |
160 | else | |
161 | s->vb_bytes_per_frame = height * 720 * 2; | |
1bf5842f SF |
162 | rc = videobuf_iolock(q, &buf->vb, NULL); |
163 | if (rc != 0) | |
164 | goto fail; | |
165 | } | |
166 | buf->vb.state = VIDEOBUF_PREPARED; | |
167 | return 0; | |
168 | ||
169 | fail: | |
170 | cx18_dma_free(q, s, buf); | |
171 | return rc; | |
172 | ||
173 | } | |
174 | ||
175 | /* VB_MIN_BUFSIZE is lcm(1440 * 480, 1440 * 576) | |
176 | 1440 is a single line of 4:2:2 YUV at 720 luma samples wide | |
177 | */ | |
178 | #define VB_MIN_BUFFERS 32 | |
179 | #define VB_MIN_BUFSIZE 4147200 | |
180 | ||
181 | static int buffer_setup(struct videobuf_queue *q, | |
182 | unsigned int *count, unsigned int *size) | |
183 | { | |
184 | struct cx18_stream *s = q->priv_data; | |
185 | struct cx18 *cx = s->cx; | |
186 | ||
187 | *size = 2 * cx->cxhdl.width * cx->cxhdl.height; | |
188 | if (*count == 0) | |
189 | *count = VB_MIN_BUFFERS; | |
190 | ||
191 | while (*size * *count > VB_MIN_BUFFERS * VB_MIN_BUFSIZE) | |
192 | (*count)--; | |
193 | ||
194 | q->field = V4L2_FIELD_INTERLACED; | |
195 | q->last = V4L2_FIELD_INTERLACED; | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | static int buffer_prepare(struct videobuf_queue *q, | |
201 | struct videobuf_buffer *vb, | |
202 | enum v4l2_field field) | |
203 | { | |
204 | struct cx18_videobuf_buffer *buf = | |
205 | container_of(vb, struct cx18_videobuf_buffer, vb); | |
206 | struct cx18_stream *s = q->priv_data; | |
207 | struct cx18 *cx = s->cx; | |
208 | ||
209 | return cx18_prepare_buffer(q, s, buf, s->pixelformat, | |
210 | cx->cxhdl.width, cx->cxhdl.height, field); | |
211 | } | |
212 | ||
213 | static void buffer_release(struct videobuf_queue *q, | |
214 | struct videobuf_buffer *vb) | |
215 | { | |
216 | struct cx18_videobuf_buffer *buf = | |
217 | container_of(vb, struct cx18_videobuf_buffer, vb); | |
218 | struct cx18_stream *s = q->priv_data; | |
219 | ||
220 | cx18_dma_free(q, s, buf); | |
221 | } | |
222 | ||
223 | static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
224 | { | |
225 | struct cx18_videobuf_buffer *buf = | |
226 | container_of(vb, struct cx18_videobuf_buffer, vb); | |
227 | struct cx18_stream *s = q->priv_data; | |
228 | ||
229 | buf->vb.state = VIDEOBUF_QUEUED; | |
230 | ||
231 | list_add_tail(&buf->vb.queue, &s->vb_capture); | |
232 | } | |
233 | ||
66883248 | 234 | static const struct videobuf_queue_ops cx18_videobuf_qops = { |
1bf5842f SF |
235 | .buf_setup = buffer_setup, |
236 | .buf_prepare = buffer_prepare, | |
237 | .buf_queue = buffer_queue, | |
238 | .buf_release = buffer_release, | |
239 | }; | |
240 | ||
1c1e45d1 HV |
241 | static void cx18_stream_init(struct cx18 *cx, int type) |
242 | { | |
243 | struct cx18_stream *s = &cx->streams[type]; | |
1c1e45d1 | 244 | |
1c1e45d1 | 245 | memset(s, 0, sizeof(*s)); |
1c1e45d1 HV |
246 | |
247 | /* initialize cx18_stream fields */ | |
754f9969 | 248 | s->dvb = NULL; |
1c1e45d1 HV |
249 | s->cx = cx; |
250 | s->type = type; | |
251 | s->name = cx18_stream_info[type].name; | |
d3c5e707 | 252 | s->handle = CX18_INVALID_TASK_HANDLE; |
1c1e45d1 HV |
253 | |
254 | s->dma = cx18_stream_info[type].dma; | |
dfdf780b | 255 | s->v4l2_dev_caps = cx18_stream_info[type].caps; |
6ecd86dc | 256 | s->buffers = cx->stream_buffers[type]; |
1c1e45d1 | 257 | s->buf_size = cx->stream_buf_size[type]; |
52fcb3ec AW |
258 | INIT_LIST_HEAD(&s->buf_pool); |
259 | s->bufs_per_mdl = 1; | |
260 | s->mdl_size = s->buf_size * s->bufs_per_mdl; | |
6ecd86dc | 261 | |
1c1e45d1 HV |
262 | init_waitqueue_head(&s->waitq); |
263 | s->id = -1; | |
40c5520f | 264 | spin_lock_init(&s->q_free.lock); |
1c1e45d1 | 265 | cx18_queue_init(&s->q_free); |
40c5520f | 266 | spin_lock_init(&s->q_busy.lock); |
66c2a6b0 | 267 | cx18_queue_init(&s->q_busy); |
40c5520f | 268 | spin_lock_init(&s->q_full.lock); |
1c1e45d1 | 269 | cx18_queue_init(&s->q_full); |
52fcb3ec AW |
270 | spin_lock_init(&s->q_idle.lock); |
271 | cx18_queue_init(&s->q_idle); | |
21a278b8 AW |
272 | |
273 | INIT_WORK(&s->out_work_order, cx18_out_work_handler); | |
b7101de3 ST |
274 | |
275 | INIT_LIST_HEAD(&s->vb_capture); | |
162e6376 | 276 | timer_setup(&s->vb_timeout, cx18_vb_timeout, 0); |
b7101de3 | 277 | spin_lock_init(&s->vb_lock); |
1bf5842f | 278 | if (type == CX18_ENC_STREAM_TYPE_YUV) { |
612031c0 SF |
279 | spin_lock_init(&s->vbuf_q_lock); |
280 | ||
1bf5842f SF |
281 | s->vb_type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
282 | videobuf_queue_vmalloc_init(&s->vbuf_q, &cx18_videobuf_qops, | |
283 | &cx->pci_dev->dev, &s->vbuf_q_lock, | |
284 | V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
285 | V4L2_FIELD_INTERLACED, | |
286 | sizeof(struct cx18_videobuf_buffer), | |
287 | s, &cx->serialize_lock); | |
288 | ||
289 | /* Assume the previous pixel default */ | |
290 | s->pixelformat = V4L2_PIX_FMT_HM12; | |
09fc9802 | 291 | s->vb_bytes_per_frame = cx->cxhdl.height * 720 * 3 / 2; |
3a29a4f1 | 292 | s->vb_bytes_per_line = 720; |
1bf5842f | 293 | } |
1c1e45d1 HV |
294 | } |
295 | ||
296 | static int cx18_prep_dev(struct cx18 *cx, int type) | |
297 | { | |
298 | struct cx18_stream *s = &cx->streams[type]; | |
299 | u32 cap = cx->v4l2_cap; | |
dd89601d | 300 | int num_offset = cx18_stream_info[type].num_offset; |
5811cf99 | 301 | int num = cx->instance + cx18_first_minor + num_offset; |
1c1e45d1 | 302 | |
754f9969 AW |
303 | /* |
304 | * These five fields are always initialized. | |
08569d64 | 305 | * For analog capture related streams, if video_dev.v4l2_dev == NULL then the |
754f9969 AW |
306 | * stream is not in use. |
307 | * For the TS stream, if dvb == NULL then the stream is not in use. | |
308 | * In those cases no other fields but these four can be used. | |
309 | */ | |
08569d64 | 310 | s->video_dev.v4l2_dev = NULL; |
754f9969 | 311 | s->dvb = NULL; |
1c1e45d1 HV |
312 | s->cx = cx; |
313 | s->type = type; | |
314 | s->name = cx18_stream_info[type].name; | |
315 | ||
316 | /* Check whether the radio is supported */ | |
317 | if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO)) | |
318 | return 0; | |
319 | ||
320 | /* Check whether VBI is supported */ | |
321 | if (type == CX18_ENC_STREAM_TYPE_VBI && | |
322 | !(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE))) | |
323 | return 0; | |
324 | ||
1c1e45d1 HV |
325 | /* User explicitly selected 0 buffers for these streams, so don't |
326 | create them. */ | |
327 | if (cx18_stream_info[type].dma != PCI_DMA_NONE && | |
6ecd86dc | 328 | cx->stream_buffers[type] == 0) { |
1c1e45d1 HV |
329 | CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name); |
330 | return 0; | |
331 | } | |
332 | ||
333 | cx18_stream_init(cx, type); | |
334 | ||
754f9969 AW |
335 | /* Allocate the cx18_dvb struct only for the TS on cards with DTV */ |
336 | if (type == CX18_ENC_STREAM_TYPE_TS) { | |
337 | if (cx->card->hw_all & CX18_HW_DVB) { | |
338 | s->dvb = kzalloc(sizeof(struct cx18_dvb), GFP_KERNEL); | |
339 | if (s->dvb == NULL) { | |
6beb1388 MCC |
340 | CX18_ERR("Couldn't allocate cx18_dvb structure for %s\n", |
341 | s->name); | |
754f9969 AW |
342 | return -ENOMEM; |
343 | } | |
344 | } else { | |
345 | /* Don't need buffers for the TS, if there is no DVB */ | |
346 | s->buffers = 0; | |
347 | } | |
348 | } | |
349 | ||
dd89601d | 350 | if (num_offset == -1) |
1c1e45d1 HV |
351 | return 0; |
352 | ||
08569d64 HV |
353 | /* initialize the v4l2 video device structure */ |
354 | snprintf(s->video_dev.name, sizeof(s->video_dev.name), "%s %s", | |
5811cf99 | 355 | cx->v4l2_dev.name, s->name); |
1c1e45d1 | 356 | |
08569d64 HV |
357 | s->video_dev.num = num; |
358 | s->video_dev.v4l2_dev = &cx->v4l2_dev; | |
359 | s->video_dev.fops = &cx18_v4l2_enc_fops; | |
360 | s->video_dev.release = video_device_release_empty; | |
3a29a4f1 HV |
361 | if (cx->card->video_inputs->video_type == CX18_CARD_INPUT_VID_TUNER) |
362 | s->video_dev.tvnorms = cx->tuner_std; | |
363 | else | |
364 | s->video_dev.tvnorms = V4L2_STD_ALL; | |
08569d64 HV |
365 | s->video_dev.lock = &cx->serialize_lock; |
366 | cx18_set_funcs(&s->video_dev); | |
1c1e45d1 HV |
367 | return 0; |
368 | } | |
369 | ||
370 | /* Initialize v4l2 variables and register v4l2 devices */ | |
371 | int cx18_streams_setup(struct cx18 *cx) | |
372 | { | |
9b4a7c8a | 373 | int type, ret; |
1c1e45d1 HV |
374 | |
375 | /* Setup V4L2 Devices */ | |
376 | for (type = 0; type < CX18_MAX_STREAMS; type++) { | |
377 | /* Prepare device */ | |
9b4a7c8a AW |
378 | ret = cx18_prep_dev(cx, type); |
379 | if (ret < 0) | |
1c1e45d1 HV |
380 | break; |
381 | ||
382 | /* Allocate Stream */ | |
9b4a7c8a AW |
383 | ret = cx18_stream_alloc(&cx->streams[type]); |
384 | if (ret < 0) | |
1c1e45d1 HV |
385 | break; |
386 | } | |
387 | if (type == CX18_MAX_STREAMS) | |
388 | return 0; | |
389 | ||
390 | /* One or more streams could not be initialized. Clean 'em all up. */ | |
3f98387e | 391 | cx18_streams_cleanup(cx, 0); |
9b4a7c8a | 392 | return ret; |
1c1e45d1 HV |
393 | } |
394 | ||
395 | static int cx18_reg_dev(struct cx18 *cx, int type) | |
396 | { | |
397 | struct cx18_stream *s = &cx->streams[type]; | |
398 | int vfl_type = cx18_stream_info[type].vfl_type; | |
38c7c036 | 399 | const char *name; |
9b4a7c8a | 400 | int num, ret; |
1c1e45d1 | 401 | |
754f9969 | 402 | if (type == CX18_ENC_STREAM_TYPE_TS && s->dvb != NULL) { |
9b4a7c8a AW |
403 | ret = cx18_dvb_register(s); |
404 | if (ret < 0) { | |
1c1e45d1 | 405 | CX18_ERR("DVB failed to register\n"); |
9b4a7c8a | 406 | return ret; |
1c1e45d1 HV |
407 | } |
408 | } | |
409 | ||
08569d64 | 410 | if (s->video_dev.v4l2_dev == NULL) |
1c1e45d1 HV |
411 | return 0; |
412 | ||
08569d64 | 413 | num = s->video_dev.num; |
dd89601d HV |
414 | /* card number + user defined offset + device offset */ |
415 | if (type != CX18_ENC_STREAM_TYPE_MPG) { | |
416 | struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG]; | |
417 | ||
08569d64 HV |
418 | if (s_mpg->video_dev.v4l2_dev) |
419 | num = s_mpg->video_dev.num | |
3d05913d | 420 | + cx18_stream_info[type].num_offset; |
dd89601d | 421 | } |
08569d64 | 422 | video_set_drvdata(&s->video_dev, s); |
1c1e45d1 HV |
423 | |
424 | /* Register device. First try the desired minor, then any free one. */ | |
08569d64 | 425 | ret = video_register_device_no_warn(&s->video_dev, vfl_type, num); |
9b4a7c8a | 426 | if (ret < 0) { |
581644d9 | 427 | CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n", |
dd89601d | 428 | s->name, num); |
08569d64 | 429 | s->video_dev.v4l2_dev = NULL; |
9b4a7c8a | 430 | return ret; |
1c1e45d1 | 431 | } |
38c7c036 | 432 | |
08569d64 | 433 | name = video_device_node_name(&s->video_dev); |
1c1e45d1 HV |
434 | |
435 | switch (vfl_type) { | |
436 | case VFL_TYPE_GRABBER: | |
38c7c036 LP |
437 | CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n", |
438 | name, s->name, cx->stream_buffers[type], | |
22dce188 AW |
439 | cx->stream_buf_size[type] / 1024, |
440 | (cx->stream_buf_size[type] * 100 / 1024) % 100); | |
1c1e45d1 HV |
441 | break; |
442 | ||
443 | case VFL_TYPE_RADIO: | |
38c7c036 | 444 | CX18_INFO("Registered device %s for %s\n", name, s->name); |
1c1e45d1 HV |
445 | break; |
446 | ||
447 | case VFL_TYPE_VBI: | |
6ecd86dc | 448 | if (cx->stream_buffers[type]) |
6beb1388 | 449 | CX18_INFO("Registered device %s for %s (%d x %d bytes)\n", |
38c7c036 | 450 | name, s->name, cx->stream_buffers[type], |
6ecd86dc | 451 | cx->stream_buf_size[type]); |
1c1e45d1 | 452 | else |
38c7c036 LP |
453 | CX18_INFO("Registered device %s for %s\n", |
454 | name, s->name); | |
1c1e45d1 HV |
455 | break; |
456 | } | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | /* Register v4l2 devices */ | |
462 | int cx18_streams_register(struct cx18 *cx) | |
463 | { | |
464 | int type; | |
9b4a7c8a AW |
465 | int err; |
466 | int ret = 0; | |
1c1e45d1 HV |
467 | |
468 | /* Register V4L2 devices */ | |
9b4a7c8a AW |
469 | for (type = 0; type < CX18_MAX_STREAMS; type++) { |
470 | err = cx18_reg_dev(cx, type); | |
471 | if (err && ret == 0) | |
472 | ret = err; | |
473 | } | |
1c1e45d1 | 474 | |
9b4a7c8a | 475 | if (ret == 0) |
1c1e45d1 HV |
476 | return 0; |
477 | ||
478 | /* One or more streams could not be initialized. Clean 'em all up. */ | |
3f98387e | 479 | cx18_streams_cleanup(cx, 1); |
9b4a7c8a | 480 | return ret; |
1c1e45d1 HV |
481 | } |
482 | ||
483 | /* Unregister v4l2 devices */ | |
3f98387e | 484 | void cx18_streams_cleanup(struct cx18 *cx, int unregister) |
1c1e45d1 HV |
485 | { |
486 | struct video_device *vdev; | |
487 | int type; | |
488 | ||
489 | /* Teardown all streams */ | |
490 | for (type = 0; type < CX18_MAX_STREAMS; type++) { | |
7b1dde03 | 491 | |
754f9969 | 492 | /* The TS has a cx18_dvb structure, not a video_device */ |
7b1dde03 | 493 | if (type == CX18_ENC_STREAM_TYPE_TS) { |
754f9969 AW |
494 | if (cx->streams[type].dvb != NULL) { |
495 | if (unregister) | |
496 | cx18_dvb_unregister(&cx->streams[type]); | |
497 | kfree(cx->streams[type].dvb); | |
498 | cx->streams[type].dvb = NULL; | |
7b1dde03 AW |
499 | cx18_stream_free(&cx->streams[type]); |
500 | } | |
501 | continue; | |
502 | } | |
503 | ||
504 | /* No struct video_device, but can have buffers allocated */ | |
505 | if (type == CX18_ENC_STREAM_TYPE_IDX) { | |
0f890ab1 | 506 | /* If the module params didn't inhibit IDX ... */ |
7b1dde03 AW |
507 | if (cx->stream_buffers[type] != 0) { |
508 | cx->stream_buffers[type] = 0; | |
0f890ab1 AW |
509 | /* |
510 | * Before calling cx18_stream_free(), | |
511 | * check if the IDX stream was actually set up. | |
512 | * Needed, since the cx18_probe() error path | |
513 | * exits through here as well as normal clean up | |
514 | */ | |
515 | if (cx->streams[type].buffers != 0) | |
516 | cx18_stream_free(&cx->streams[type]); | |
7b1dde03 AW |
517 | } |
518 | continue; | |
fac3639d | 519 | } |
1c1e45d1 | 520 | |
7b1dde03 | 521 | /* If struct video_device exists, can have buffers allocated */ |
08569d64 | 522 | vdev = &cx->streams[type].video_dev; |
1c1e45d1 | 523 | |
08569d64 | 524 | if (vdev->v4l2_dev == NULL) |
1c1e45d1 HV |
525 | continue; |
526 | ||
1bf5842f SF |
527 | if (type == CX18_ENC_STREAM_TYPE_YUV) |
528 | videobuf_mmap_free(&cx->streams[type].vbuf_q); | |
529 | ||
1c1e45d1 HV |
530 | cx18_stream_free(&cx->streams[type]); |
531 | ||
08569d64 | 532 | video_unregister_device(vdev); |
1c1e45d1 HV |
533 | } |
534 | } | |
535 | ||
536 | static void cx18_vbi_setup(struct cx18_stream *s) | |
537 | { | |
538 | struct cx18 *cx = s->cx; | |
dd073434 | 539 | int raw = cx18_raw_vbi(cx); |
1c1e45d1 HV |
540 | u32 data[CX2341X_MBOX_MAX_DATA]; |
541 | int lines; | |
542 | ||
543 | if (cx->is_60hz) { | |
544 | cx->vbi.count = 12; | |
545 | cx->vbi.start[0] = 10; | |
546 | cx->vbi.start[1] = 273; | |
547 | } else { /* PAL/SECAM */ | |
548 | cx->vbi.count = 18; | |
549 | cx->vbi.start[0] = 6; | |
550 | cx->vbi.start[1] = 318; | |
551 | } | |
552 | ||
553 | /* setup VBI registers */ | |
add632cd HV |
554 | if (raw) |
555 | v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &cx->vbi.in.fmt.vbi); | |
556 | else | |
557 | v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &cx->vbi.in.fmt.sliced); | |
1c1e45d1 | 558 | |
dcc0ef88 AW |
559 | /* |
560 | * Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw | |
561 | * VBI when the first analog capture channel starts, as once it starts | |
562 | * (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup | |
563 | * (i.e. for the VBI capture channels). We also send it for each | |
564 | * analog capture channel anyway just to make sure we get the proper | |
565 | * behavior | |
566 | */ | |
1c1e45d1 HV |
567 | if (raw) { |
568 | lines = cx->vbi.count * 2; | |
569 | } else { | |
812b1f9d AW |
570 | /* |
571 | * For 525/60 systems, according to the VIP 2 & BT.656 std: | |
572 | * The EAV RP code's Field bit toggles on line 4, a few lines | |
573 | * after the Vertcal Blank bit has already toggled. | |
574 | * Tell the encoder to capture 21-4+1=18 lines per field, | |
575 | * since we want lines 10 through 21. | |
576 | * | |
5ab74052 AW |
577 | * For 625/50 systems, according to the VIP 2 & BT.656 std: |
578 | * The EAV RP code's Field bit toggles on line 1, a few lines | |
579 | * after the Vertcal Blank bit has already toggled. | |
929a3ad1 AW |
580 | * (We've actually set the digitizer so that the Field bit |
581 | * toggles on line 2.) Tell the encoder to capture 23-2+1=22 | |
582 | * lines per field, since we want lines 6 through 23. | |
812b1f9d | 583 | */ |
929a3ad1 | 584 | lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2; |
1c1e45d1 HV |
585 | } |
586 | ||
1c1e45d1 HV |
587 | data[0] = s->handle; |
588 | /* Lines per field */ | |
589 | data[1] = (lines / 2) | ((lines / 2) << 16); | |
590 | /* bytes per line */ | |
318de791 MCC |
591 | data[2] = (raw ? VBI_ACTIVE_SAMPLES |
592 | : (cx->is_60hz ? VBI_HBLANK_SAMPLES_60HZ | |
593 | : VBI_HBLANK_SAMPLES_50HZ)); | |
1c1e45d1 HV |
594 | /* Every X number of frames a VBI interrupt arrives |
595 | (frames as in 25 or 30 fps) */ | |
596 | data[3] = 1; | |
302df970 AW |
597 | /* |
598 | * Set the SAV/EAV RP codes to look for as start/stop points | |
599 | * when in VIP-1.1 mode | |
600 | */ | |
1c1e45d1 | 601 | if (raw) { |
302df970 AW |
602 | /* |
603 | * Start codes for beginning of "active" line in vertical blank | |
604 | * 0x20 ( VerticalBlank ) | |
605 | * 0x60 ( EvenField VerticalBlank ) | |
606 | */ | |
1c1e45d1 | 607 | data[4] = 0x20602060; |
302df970 AW |
608 | /* |
609 | * End codes for end of "active" raw lines and regular lines | |
610 | * 0x30 ( VerticalBlank HorizontalBlank) | |
611 | * 0x70 ( EvenField VerticalBlank HorizontalBlank) | |
612 | * 0x90 (Task HorizontalBlank) | |
613 | * 0xd0 (Task EvenField HorizontalBlank) | |
614 | */ | |
af009cf6 | 615 | data[5] = 0x307090d0; |
1c1e45d1 | 616 | } else { |
302df970 AW |
617 | /* |
618 | * End codes for active video, we want data in the hblank region | |
619 | * 0xb0 (Task 0 VerticalBlank HorizontalBlank) | |
620 | * 0xf0 (Task EvenField VerticalBlank HorizontalBlank) | |
621 | * | |
622 | * Since the V bit is only allowed to toggle in the EAV RP code, | |
623 | * just before the first active region line, these two | |
812b1f9d | 624 | * are problematic: |
302df970 AW |
625 | * 0x90 (Task HorizontalBlank) |
626 | * 0xd0 (Task EvenField HorizontalBlank) | |
812b1f9d | 627 | * |
af7c58b1 AW |
628 | * We have set the digitzer such that we don't have to worry |
629 | * about these problem codes. | |
302df970 | 630 | */ |
1c1e45d1 | 631 | data[4] = 0xB0F0B0F0; |
302df970 AW |
632 | /* |
633 | * Start codes for beginning of active line in vertical blank | |
634 | * 0xa0 (Task VerticalBlank ) | |
635 | * 0xe0 (Task EvenField VerticalBlank ) | |
636 | */ | |
1c1e45d1 HV |
637 | data[5] = 0xA0E0A0E0; |
638 | } | |
639 | ||
640 | CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n", | |
641 | data[0], data[1], data[2], data[3], data[4], data[5]); | |
642 | ||
dcc0ef88 | 643 | cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data); |
1c1e45d1 HV |
644 | } |
645 | ||
ef991797 AW |
646 | void cx18_stream_rotate_idx_mdls(struct cx18 *cx) |
647 | { | |
648 | struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX]; | |
649 | struct cx18_mdl *mdl; | |
650 | ||
651 | if (!cx18_stream_enabled(s)) | |
652 | return; | |
653 | ||
654 | /* Return if the firmware is not running low on MDLs */ | |
655 | if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >= | |
656 | CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN) | |
657 | return; | |
658 | ||
659 | /* Return if there are no MDLs to rotate back to the firmware */ | |
660 | if (atomic_read(&s->q_full.depth) < 2) | |
661 | return; | |
662 | ||
663 | /* | |
664 | * Take the oldest IDX MDL still holding data, and discard its index | |
665 | * entries by scheduling the MDL to go back to the firmware | |
666 | */ | |
667 | mdl = cx18_dequeue(s, &s->q_full); | |
668 | if (mdl != NULL) | |
669 | cx18_enqueue(s, mdl, &s->q_free); | |
670 | } | |
671 | ||
87116159 | 672 | static |
52fcb3ec AW |
673 | struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s, |
674 | struct cx18_mdl *mdl) | |
66c2a6b0 AW |
675 | { |
676 | struct cx18 *cx = s->cx; | |
677 | struct cx18_queue *q; | |
678 | ||
679 | /* Don't give it to the firmware, if we're not running a capture */ | |
680 | if (s->handle == CX18_INVALID_TASK_HANDLE || | |
87116159 | 681 | test_bit(CX18_F_S_STOPPING, &s->s_flags) || |
66c2a6b0 | 682 | !test_bit(CX18_F_S_STREAMING, &s->s_flags)) |
52fcb3ec | 683 | return cx18_enqueue(s, mdl, &s->q_free); |
66c2a6b0 | 684 | |
52fcb3ec | 685 | q = cx18_enqueue(s, mdl, &s->q_busy); |
66c2a6b0 | 686 | if (q != &s->q_busy) |
52fcb3ec | 687 | return q; /* The firmware has the max MDLs it can handle */ |
66c2a6b0 | 688 | |
52fcb3ec | 689 | cx18_mdl_sync_for_device(s, mdl); |
66c2a6b0 | 690 | cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle, |
52fcb3ec AW |
691 | (void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem, |
692 | s->bufs_per_mdl, mdl->id, s->mdl_size); | |
66c2a6b0 AW |
693 | return q; |
694 | } | |
695 | ||
87116159 AW |
696 | static |
697 | void _cx18_stream_load_fw_queue(struct cx18_stream *s) | |
66c2a6b0 | 698 | { |
abb096de | 699 | struct cx18_queue *q; |
52fcb3ec | 700 | struct cx18_mdl *mdl; |
66c2a6b0 | 701 | |
c37b11bf AW |
702 | if (atomic_read(&s->q_free.depth) == 0 || |
703 | atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM) | |
abb096de AW |
704 | return; |
705 | ||
706 | /* Move from q_free to q_busy notifying the firmware, until the limit */ | |
707 | do { | |
52fcb3ec AW |
708 | mdl = cx18_dequeue(s, &s->q_free); |
709 | if (mdl == NULL) | |
abb096de | 710 | break; |
52fcb3ec | 711 | q = _cx18_stream_put_mdl_fw(s, mdl); |
c37b11bf | 712 | } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM |
0ef02892 | 713 | && q == &s->q_busy); |
66c2a6b0 AW |
714 | } |
715 | ||
87116159 AW |
716 | void cx18_out_work_handler(struct work_struct *work) |
717 | { | |
21a278b8 AW |
718 | struct cx18_stream *s = |
719 | container_of(work, struct cx18_stream, out_work_order); | |
87116159 | 720 | |
21a278b8 | 721 | _cx18_stream_load_fw_queue(s); |
87116159 AW |
722 | } |
723 | ||
52fcb3ec AW |
724 | static void cx18_stream_configure_mdls(struct cx18_stream *s) |
725 | { | |
726 | cx18_unload_queues(s); | |
727 | ||
22dce188 AW |
728 | switch (s->type) { |
729 | case CX18_ENC_STREAM_TYPE_YUV: | |
730 | /* | |
731 | * Height should be a multiple of 32 lines. | |
732 | * Set the MDL size to the exact size needed for one frame. | |
733 | * Use enough buffers per MDL to cover the MDL size | |
734 | */ | |
1bf5842f SF |
735 | if (s->pixelformat == V4L2_PIX_FMT_HM12) |
736 | s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2; | |
737 | else | |
738 | s->mdl_size = 720 * s->cx->cxhdl.height * 2; | |
22dce188 AW |
739 | s->bufs_per_mdl = s->mdl_size / s->buf_size; |
740 | if (s->mdl_size % s->buf_size) | |
741 | s->bufs_per_mdl++; | |
742 | break; | |
127ce5f0 AW |
743 | case CX18_ENC_STREAM_TYPE_VBI: |
744 | s->bufs_per_mdl = 1; | |
745 | if (cx18_raw_vbi(s->cx)) { | |
746 | s->mdl_size = (s->cx->is_60hz ? 12 : 18) | |
318de791 | 747 | * 2 * VBI_ACTIVE_SAMPLES; |
127ce5f0 AW |
748 | } else { |
749 | /* | |
750 | * See comment in cx18_vbi_setup() below about the | |
751 | * extra lines we capture in sliced VBI mode due to | |
752 | * the lines on which EAV RP codes toggle. | |
753 | */ | |
754 | s->mdl_size = s->cx->is_60hz | |
318de791 MCC |
755 | ? (21 - 4 + 1) * 2 * VBI_HBLANK_SAMPLES_60HZ |
756 | : (23 - 2 + 1) * 2 * VBI_HBLANK_SAMPLES_50HZ; | |
127ce5f0 AW |
757 | } |
758 | break; | |
22dce188 AW |
759 | default: |
760 | s->bufs_per_mdl = 1; | |
761 | s->mdl_size = s->buf_size * s->bufs_per_mdl; | |
762 | break; | |
763 | } | |
52fcb3ec AW |
764 | |
765 | cx18_load_queues(s); | |
766 | } | |
767 | ||
1c1e45d1 HV |
768 | int cx18_start_v4l2_encode_stream(struct cx18_stream *s) |
769 | { | |
770 | u32 data[MAX_MB_ARGUMENTS]; | |
771 | struct cx18 *cx = s->cx; | |
1c1e45d1 | 772 | int captype = 0; |
e46c54a8 | 773 | struct cx18_stream *s_idx; |
1c1e45d1 | 774 | |
540bab93 | 775 | if (!cx18_stream_enabled(s)) |
1c1e45d1 HV |
776 | return -EINVAL; |
777 | ||
778 | CX18_DEBUG_INFO("Start encoder stream %s\n", s->name); | |
779 | ||
780 | switch (s->type) { | |
781 | case CX18_ENC_STREAM_TYPE_MPG: | |
782 | captype = CAPTURE_CHANNEL_TYPE_MPEG; | |
783 | cx->mpg_data_received = cx->vbi_data_inserted = 0; | |
784 | cx->dualwatch_jiffies = jiffies; | |
a75b9be1 | 785 | cx->dualwatch_stereo_mode = v4l2_ctrl_g_ctrl(cx->cxhdl.audio_mode); |
1c1e45d1 HV |
786 | cx->search_pack_header = 0; |
787 | break; | |
788 | ||
e46c54a8 AW |
789 | case CX18_ENC_STREAM_TYPE_IDX: |
790 | captype = CAPTURE_CHANNEL_TYPE_INDEX; | |
791 | break; | |
1c1e45d1 HV |
792 | case CX18_ENC_STREAM_TYPE_TS: |
793 | captype = CAPTURE_CHANNEL_TYPE_TS; | |
1c1e45d1 HV |
794 | break; |
795 | case CX18_ENC_STREAM_TYPE_YUV: | |
796 | captype = CAPTURE_CHANNEL_TYPE_YUV; | |
797 | break; | |
798 | case CX18_ENC_STREAM_TYPE_PCM: | |
799 | captype = CAPTURE_CHANNEL_TYPE_PCM; | |
800 | break; | |
801 | case CX18_ENC_STREAM_TYPE_VBI: | |
dcc0ef88 | 802 | #ifdef CX18_ENCODER_PARSES_SLICED |
dd073434 AW |
803 | captype = cx18_raw_vbi(cx) ? |
804 | CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI; | |
dcc0ef88 AW |
805 | #else |
806 | /* | |
807 | * Currently we set things up so that Sliced VBI from the | |
808 | * digitizer is handled as Raw VBI by the encoder | |
809 | */ | |
810 | captype = CAPTURE_CHANNEL_TYPE_VBI; | |
811 | #endif | |
1c1e45d1 HV |
812 | cx->vbi.frame = 0; |
813 | cx->vbi.inserted_frame = 0; | |
814 | memset(cx->vbi.sliced_mpeg_size, | |
815 | 0, sizeof(cx->vbi.sliced_mpeg_size)); | |
816 | break; | |
817 | default: | |
818 | return -EINVAL; | |
819 | } | |
1c1e45d1 | 820 | |
1c1e45d1 HV |
821 | /* Clear Streamoff flags in case left from last capture */ |
822 | clear_bit(CX18_F_S_STREAMOFF, &s->s_flags); | |
823 | ||
824 | cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE); | |
825 | s->handle = data[0]; | |
826 | cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype); | |
827 | ||
dcc0ef88 AW |
828 | /* |
829 | * For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and | |
830 | * set up all the parameters, as it is not obvious which parameters the | |
831 | * firmware shares across capture channel types and which it does not. | |
832 | * | |
833 | * Some of the cx18_vapi() calls below apply to only certain capture | |
834 | * channel types. We're hoping there's no harm in calling most of them | |
835 | * anyway, as long as the values are all consistent. Setting some | |
836 | * shared parameters will have no effect once an analog capture channel | |
837 | * has started streaming. | |
838 | */ | |
839 | if (captype != CAPTURE_CHANNEL_TYPE_TS) { | |
1c1e45d1 HV |
840 | cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0); |
841 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1); | |
842 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0); | |
843 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1); | |
1c1e45d1 | 844 | |
dcc0ef88 AW |
845 | /* |
846 | * Audio related reset according to | |
2ebe0bb3 | 847 | * Documentation/media/v4l-drivers/cx2341x.rst |
dcc0ef88 AW |
848 | */ |
849 | if (atomic_read(&cx->ana_capturing) == 0) | |
850 | cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2, | |
851 | s->handle, 12); | |
852 | ||
853 | /* | |
854 | * Number of lines for Field 1 & Field 2 according to | |
2ebe0bb3 | 855 | * Documentation/media/v4l-drivers/cx2341x.rst |
f37aa511 AW |
856 | * Field 1 is 312 for 625 line systems in BT.656 |
857 | * Field 2 is 313 for 625 line systems in BT.656 | |
dcc0ef88 | 858 | */ |
1c1e45d1 | 859 | cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3, |
f37aa511 | 860 | s->handle, 312, 313); |
1c1e45d1 | 861 | |
1c1e45d1 HV |
862 | if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE) |
863 | cx18_vbi_setup(s); | |
864 | ||
dcc0ef88 | 865 | /* |
e46c54a8 AW |
866 | * Select to receive I, P, and B frame index entries, if the |
867 | * index stream is enabled. Otherwise disable index entry | |
868 | * generation. | |
dcc0ef88 | 869 | */ |
e46c54a8 | 870 | s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX]; |
5ada5773 AW |
871 | cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2, |
872 | s->handle, cx18_stream_enabled(s_idx) ? 7 : 0); | |
1c1e45d1 | 873 | |
dcc0ef88 | 874 | /* Call out to the common CX2341x API setup for user controls */ |
a75b9be1 HV |
875 | cx->cxhdl.priv = s; |
876 | cx2341x_handler_setup(&cx->cxhdl); | |
dcc0ef88 AW |
877 | |
878 | /* | |
879 | * When starting a capture and we're set for radio, | |
880 | * ensure the video is muted, despite the user control. | |
881 | */ | |
a75b9be1 | 882 | if (!cx->cxhdl.video_mute && |
dcc0ef88 AW |
883 | test_bit(CX18_F_I_RADIO_USER, &cx->i_flags)) |
884 | cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle, | |
a75b9be1 | 885 | (v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8) | 1); |
b7101de3 ST |
886 | |
887 | /* Enable the Video Format Converter for UYVY 4:2:2 support, | |
888 | * rather than the default HM12 Macroblovk 4:2:0 support. | |
889 | */ | |
890 | if (captype == CAPTURE_CHANNEL_TYPE_YUV) { | |
1bf5842f | 891 | if (s->pixelformat == V4L2_PIX_FMT_UYVY) |
b7101de3 ST |
892 | cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2, |
893 | s->handle, 1); | |
894 | else | |
895 | /* If in doubt, default to HM12 */ | |
896 | cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2, | |
897 | s->handle, 0); | |
898 | } | |
1c1e45d1 HV |
899 | } |
900 | ||
31554ae5 | 901 | if (atomic_read(&cx->tot_capturing) == 0) { |
a75b9be1 | 902 | cx2341x_handler_set_busy(&cx->cxhdl, 1); |
1c1e45d1 | 903 | clear_bit(CX18_F_I_EOS, &cx->i_flags); |
b1526421 | 904 | cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK); |
1c1e45d1 HV |
905 | } |
906 | ||
907 | cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle, | |
990c81c8 AV |
908 | (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem, |
909 | (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem); | |
1c1e45d1 | 910 | |
66c2a6b0 | 911 | /* Init all the cpu_mdls for this stream */ |
52fcb3ec | 912 | cx18_stream_configure_mdls(s); |
87116159 | 913 | _cx18_stream_load_fw_queue(s); |
66c2a6b0 | 914 | |
1c1e45d1 HV |
915 | /* begin_capture */ |
916 | if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) { | |
917 | CX18_DEBUG_WARN("Error starting capture!\n"); | |
3b5df8ea | 918 | /* Ensure we're really not capturing before releasing MDLs */ |
87116159 | 919 | set_bit(CX18_F_S_STOPPING, &s->s_flags); |
3b5df8ea AW |
920 | if (s->type == CX18_ENC_STREAM_TYPE_MPG) |
921 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1); | |
922 | else | |
923 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle); | |
66c2a6b0 AW |
924 | clear_bit(CX18_F_S_STREAMING, &s->s_flags); |
925 | /* FIXME - CX18_F_S_STREAMOFF as well? */ | |
3b5df8ea | 926 | cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle); |
1c1e45d1 | 927 | cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle); |
66c2a6b0 | 928 | s->handle = CX18_INVALID_TASK_HANDLE; |
87116159 | 929 | clear_bit(CX18_F_S_STOPPING, &s->s_flags); |
66c2a6b0 AW |
930 | if (atomic_read(&cx->tot_capturing) == 0) { |
931 | set_bit(CX18_F_I_EOS, &cx->i_flags); | |
932 | cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK); | |
933 | } | |
1c1e45d1 HV |
934 | return -EINVAL; |
935 | } | |
936 | ||
937 | /* you're live! sit back and await interrupts :) */ | |
dcc0ef88 | 938 | if (captype != CAPTURE_CHANNEL_TYPE_TS) |
31554ae5 HV |
939 | atomic_inc(&cx->ana_capturing); |
940 | atomic_inc(&cx->tot_capturing); | |
1c1e45d1 HV |
941 | return 0; |
942 | } | |
0f4cf676 | 943 | EXPORT_SYMBOL(cx18_start_v4l2_encode_stream); |
1c1e45d1 HV |
944 | |
945 | void cx18_stop_all_captures(struct cx18 *cx) | |
946 | { | |
947 | int i; | |
948 | ||
949 | for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) { | |
950 | struct cx18_stream *s = &cx->streams[i]; | |
951 | ||
540bab93 | 952 | if (!cx18_stream_enabled(s)) |
1c1e45d1 HV |
953 | continue; |
954 | if (test_bit(CX18_F_S_STREAMING, &s->s_flags)) | |
955 | cx18_stop_v4l2_encode_stream(s, 0); | |
956 | } | |
957 | } | |
958 | ||
959 | int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end) | |
960 | { | |
961 | struct cx18 *cx = s->cx; | |
1c1e45d1 | 962 | |
540bab93 | 963 | if (!cx18_stream_enabled(s)) |
1c1e45d1 HV |
964 | return -EINVAL; |
965 | ||
966 | /* This function assumes that you are allowed to stop the capture | |
967 | and that we are actually capturing */ | |
968 | ||
969 | CX18_DEBUG_INFO("Stop Capture\n"); | |
970 | ||
31554ae5 | 971 | if (atomic_read(&cx->tot_capturing) == 0) |
1c1e45d1 HV |
972 | return 0; |
973 | ||
87116159 | 974 | set_bit(CX18_F_S_STOPPING, &s->s_flags); |
1c1e45d1 HV |
975 | if (s->type == CX18_ENC_STREAM_TYPE_MPG) |
976 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end); | |
977 | else | |
978 | cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle); | |
979 | ||
1c1e45d1 HV |
980 | if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) { |
981 | CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n"); | |
982 | } | |
983 | ||
31554ae5 HV |
984 | if (s->type != CX18_ENC_STREAM_TYPE_TS) |
985 | atomic_dec(&cx->ana_capturing); | |
986 | atomic_dec(&cx->tot_capturing); | |
1c1e45d1 HV |
987 | |
988 | /* Clear capture and no-read bits */ | |
989 | clear_bit(CX18_F_S_STREAMING, &s->s_flags); | |
990 | ||
f68d0cf5 AW |
991 | /* Tell the CX23418 it can't use our buffers anymore */ |
992 | cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle); | |
993 | ||
1c1e45d1 | 994 | cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle); |
d3c5e707 | 995 | s->handle = CX18_INVALID_TASK_HANDLE; |
87116159 | 996 | clear_bit(CX18_F_S_STOPPING, &s->s_flags); |
1c1e45d1 | 997 | |
31554ae5 | 998 | if (atomic_read(&cx->tot_capturing) > 0) |
1c1e45d1 HV |
999 | return 0; |
1000 | ||
a75b9be1 | 1001 | cx2341x_handler_set_busy(&cx->cxhdl, 0); |
b1526421 | 1002 | cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK); |
1c1e45d1 HV |
1003 | wake_up(&s->waitq); |
1004 | ||
1005 | return 0; | |
1006 | } | |
0f4cf676 | 1007 | EXPORT_SYMBOL(cx18_stop_v4l2_encode_stream); |
1c1e45d1 HV |
1008 | |
1009 | u32 cx18_find_handle(struct cx18 *cx) | |
1010 | { | |
1011 | int i; | |
1012 | ||
1013 | /* find first available handle to be used for global settings */ | |
1014 | for (i = 0; i < CX18_MAX_STREAMS; i++) { | |
1015 | struct cx18_stream *s = &cx->streams[i]; | |
1016 | ||
08569d64 | 1017 | if (s->video_dev.v4l2_dev && (s->handle != CX18_INVALID_TASK_HANDLE)) |
1c1e45d1 HV |
1018 | return s->handle; |
1019 | } | |
d3c5e707 | 1020 | return CX18_INVALID_TASK_HANDLE; |
1c1e45d1 | 1021 | } |
ee2d64f5 AW |
1022 | |
1023 | struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle) | |
1024 | { | |
1025 | int i; | |
1026 | struct cx18_stream *s; | |
1027 | ||
1028 | if (handle == CX18_INVALID_TASK_HANDLE) | |
1029 | return NULL; | |
1030 | ||
1031 | for (i = 0; i < CX18_MAX_STREAMS; i++) { | |
1032 | s = &cx->streams[i]; | |
1033 | if (s->handle != handle) | |
1034 | continue; | |
540bab93 | 1035 | if (cx18_stream_enabled(s)) |
ee2d64f5 AW |
1036 | return s; |
1037 | } | |
1038 | return NULL; | |
1039 | } |